X86RecognizableInstr.cpp revision 226890 
1//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the implementation of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13//  X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
17#include "X86DisassemblerShared.h"
18#include "X86RecognizableInstr.h"
19#include "X86ModRMFilters.h"
20
21#include "llvm/Support/ErrorHandling.h"
22
23#include <string>
24
25using namespace llvm;
26
27#define MRM_MAPPING     \
28  MAP(C1, 33)           \
29  MAP(C2, 34)           \
30  MAP(C3, 35)           \
31  MAP(C4, 36)           \
32  MAP(C8, 37)           \
33  MAP(C9, 38)           \
34  MAP(E8, 39)           \
35  MAP(F0, 40)           \
36  MAP(F8, 41)           \
37  MAP(F9, 42)           \
38  MAP(D0, 45)           \
39  MAP(D1, 46)
40
41// A clone of X86 since we can't depend on something that is generated.
42namespace X86Local {
43  enum {
44    Pseudo      = 0,
45    RawFrm      = 1,
46    AddRegFrm   = 2,
47    MRMDestReg  = 3,
48    MRMDestMem  = 4,
49    MRMSrcReg   = 5,
50    MRMSrcMem   = 6,
51    MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52    MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53    MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54    MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
55    MRMInitReg  = 32,
56#define MAP(from, to) MRM_##from = to,
57    MRM_MAPPING
58#undef MAP
59    RawFrmImm8  = 43,
60    RawFrmImm16 = 44,
61    lastMRM
62  };
63
64  enum {
65    TB  = 1,
66    REP = 2,
67    D8 = 3, D9 = 4, DA = 5, DB = 6,
68    DC = 7, DD = 8, DE = 9, DF = 10,
69    XD = 11,  XS = 12,
70    T8 = 13,  P_TA = 14,
71    A6 = 15,  A7 = 16, TF = 17
72  };
73}
74
75// If rows are added to the opcode extension tables, then corresponding entries
76// must be added here.
77//
78// If the row corresponds to a single byte (i.e., 8f), then add an entry for
79// that byte to ONE_BYTE_EXTENSION_TABLES.
80//
81// If the row corresponds to two bytes where the first is 0f, add an entry for
82// the second byte to TWO_BYTE_EXTENSION_TABLES.
83//
84// If the row corresponds to some other set of bytes, you will need to modify
85// the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86// to the X86 TD files, except in two cases: if the first two bytes of such a
87// new combination are 0f 38 or 0f 3a, you just have to add maps called
88// THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89// switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90// in RecognizableInstr::emitDecodePath().
91
92#define ONE_BYTE_EXTENSION_TABLES \
93  EXTENSION_TABLE(80)             \
94  EXTENSION_TABLE(81)             \
95  EXTENSION_TABLE(82)             \
96  EXTENSION_TABLE(83)             \
97  EXTENSION_TABLE(8f)             \
98  EXTENSION_TABLE(c0)             \
99  EXTENSION_TABLE(c1)             \
100  EXTENSION_TABLE(c6)             \
101  EXTENSION_TABLE(c7)             \
102  EXTENSION_TABLE(d0)             \
103  EXTENSION_TABLE(d1)             \
104  EXTENSION_TABLE(d2)             \
105  EXTENSION_TABLE(d3)             \
106  EXTENSION_TABLE(f6)             \
107  EXTENSION_TABLE(f7)             \
108  EXTENSION_TABLE(fe)             \
109  EXTENSION_TABLE(ff)
110
111#define TWO_BYTE_EXTENSION_TABLES \
112  EXTENSION_TABLE(00)             \
113  EXTENSION_TABLE(01)             \
114  EXTENSION_TABLE(18)             \
115  EXTENSION_TABLE(71)             \
116  EXTENSION_TABLE(72)             \
117  EXTENSION_TABLE(73)             \
118  EXTENSION_TABLE(ae)             \
119  EXTENSION_TABLE(ba)             \
120  EXTENSION_TABLE(c7)
121
122using namespace X86Disassembler;
123
124/// needsModRMForDecode - Indicates whether a particular instruction requires a
125///   ModR/M byte for the instruction to be properly decoded.  For example, a
126///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
127///   0b11.
128///
129/// @param form - The form of the instruction.
130/// @return     - true if the form implies that a ModR/M byte is required, false
131///               otherwise.
132static bool needsModRMForDecode(uint8_t form) {
133  if (form == X86Local::MRMDestReg    ||
134     form == X86Local::MRMDestMem    ||
135     form == X86Local::MRMSrcReg     ||
136     form == X86Local::MRMSrcMem     ||
137     (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
138     (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
139    return true;
140  else
141    return false;
142}
143
144/// isRegFormat - Indicates whether a particular form requires the Mod field of
145///   the ModR/M byte to be 0b11.
146///
147/// @param form - The form of the instruction.
148/// @return     - true if the form implies that Mod must be 0b11, false
149///               otherwise.
150static bool isRegFormat(uint8_t form) {
151  if (form == X86Local::MRMDestReg ||
152     form == X86Local::MRMSrcReg  ||
153     (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
154    return true;
155  else
156    return false;
157}
158
159/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
160///   Useful for switch statements and the like.
161///
162/// @param init - A reference to the BitsInit to be decoded.
163/// @return     - The field, with the first bit in the BitsInit as the lowest
164///               order bit.
165static uint8_t byteFromBitsInit(BitsInit &init) {
166  int width = init.getNumBits();
167
168  assert(width <= 8 && "Field is too large for uint8_t!");
169
170  int     index;
171  uint8_t mask = 0x01;
172
173  uint8_t ret = 0;
174
175  for (index = 0; index < width; index++) {
176    if (static_cast<BitInit*>(init.getBit(index))->getValue())
177      ret |= mask;
178
179    mask <<= 1;
180  }
181
182  return ret;
183}
184
185/// byteFromRec - Extract a value at most 8 bits in with from a Record given the
186///   name of the field.
187///
188/// @param rec  - The record from which to extract the value.
189/// @param name - The name of the field in the record.
190/// @return     - The field, as translated by byteFromBitsInit().
191static uint8_t byteFromRec(const Record* rec, const std::string &name) {
192  BitsInit* bits = rec->getValueAsBitsInit(name);
193  return byteFromBitsInit(*bits);
194}
195
196RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
197                                     const CodeGenInstruction &insn,
198                                     InstrUID uid) {
199  UID = uid;
200
201  Rec = insn.TheDef;
202  Name = Rec->getName();
203  Spec = &tables.specForUID(UID);
204
205  if (!Rec->isSubClassOf("X86Inst")) {
206    ShouldBeEmitted = false;
207    return;
208  }
209
210  Prefix   = byteFromRec(Rec, "Prefix");
211  Opcode   = byteFromRec(Rec, "Opcode");
212  Form     = byteFromRec(Rec, "FormBits");
213  SegOvr   = byteFromRec(Rec, "SegOvrBits");
214
215  HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
216  HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
217  HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
218  HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
219  HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
220  IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
221  HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
222  IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
223
224  Name      = Rec->getName();
225  AsmString = Rec->getValueAsString("AsmString");
226
227  Operands = &insn.Operands.OperandList;
228
229  IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
230                     (Name.find("CRC32") != Name.npos);
231  HasFROperands    = hasFROperands();
232  HasVEX_LPrefix   = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
233
234  // Check for 64-bit inst which does not require REX
235  Is32Bit = false;
236  Is64Bit = false;
237  // FIXME: Is there some better way to check for In64BitMode?
238  std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
239  for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
240    if (Predicates[i]->getName().find("32Bit") != Name.npos) {
241      Is32Bit = true;
242      break;
243    }
244    if (Predicates[i]->getName().find("64Bit") != Name.npos) {
245      Is64Bit = true;
246      break;
247    }
248  }
249  // FIXME: These instructions aren't marked as 64-bit in any way
250  Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
251             Rec->getName() == "MASKMOVDQU64" ||
252             Rec->getName() == "POPFS64" ||
253             Rec->getName() == "POPGS64" ||
254             Rec->getName() == "PUSHFS64" ||
255             Rec->getName() == "PUSHGS64" ||
256             Rec->getName() == "REX64_PREFIX" ||
257             Rec->getName().find("VMREAD64") != Name.npos ||
258             Rec->getName().find("VMWRITE64") != Name.npos ||
259             Rec->getName().find("INVEPT64") != Name.npos ||
260             Rec->getName().find("INVVPID64") != Name.npos ||
261             Rec->getName().find("MOV64") != Name.npos ||
262             Rec->getName().find("PUSH64") != Name.npos ||
263             Rec->getName().find("POP64") != Name.npos;
264
265  ShouldBeEmitted  = true;
266}
267
268void RecognizableInstr::processInstr(DisassemblerTables &tables,
269	const CodeGenInstruction &insn,
270                                   InstrUID uid)
271{
272  // Ignore "asm parser only" instructions.
273  if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
274    return;
275
276  RecognizableInstr recogInstr(tables, insn, uid);
277
278  recogInstr.emitInstructionSpecifier(tables);
279
280  if (recogInstr.shouldBeEmitted())
281    recogInstr.emitDecodePath(tables);
282}
283
284InstructionContext RecognizableInstr::insnContext() const {
285  InstructionContext insnContext;
286
287  if (HasVEX_4VPrefix || HasVEXPrefix) {
288    if (HasVEX_LPrefix && HasVEX_WPrefix)
289      llvm_unreachable("Don't support VEX.L and VEX.W together");
290    else if (HasOpSizePrefix && HasVEX_LPrefix)
291      insnContext = IC_VEX_L_OPSIZE;
292    else if (HasOpSizePrefix && HasVEX_WPrefix)
293      insnContext = IC_VEX_W_OPSIZE;
294    else if (HasOpSizePrefix)
295      insnContext = IC_VEX_OPSIZE;
296    else if (HasVEX_LPrefix && Prefix == X86Local::XS)
297      insnContext = IC_VEX_L_XS;
298    else if (HasVEX_LPrefix && Prefix == X86Local::XD)
299      insnContext = IC_VEX_L_XD;
300    else if (HasVEX_WPrefix && Prefix == X86Local::XS)
301      insnContext = IC_VEX_W_XS;
302    else if (HasVEX_WPrefix && Prefix == X86Local::XD)
303      insnContext = IC_VEX_W_XD;
304    else if (HasVEX_WPrefix)
305      insnContext = IC_VEX_W;
306    else if (HasVEX_LPrefix)
307      insnContext = IC_VEX_L;
308    else if (Prefix == X86Local::XD)
309      insnContext = IC_VEX_XD;
310    else if (Prefix == X86Local::XS)
311      insnContext = IC_VEX_XS;
312    else
313      insnContext = IC_VEX;
314  } else if (Is64Bit || HasREX_WPrefix) {
315    if (HasREX_WPrefix && HasOpSizePrefix)
316      insnContext = IC_64BIT_REXW_OPSIZE;
317    else if (HasOpSizePrefix &&
318             (Prefix == X86Local::XD || Prefix == X86Local::TF))
319      insnContext = IC_64BIT_XD_OPSIZE;
320    else if (HasOpSizePrefix && Prefix == X86Local::XS)
321      insnContext = IC_64BIT_XS_OPSIZE;
322    else if (HasOpSizePrefix)
323      insnContext = IC_64BIT_OPSIZE;
324    else if (HasREX_WPrefix && Prefix == X86Local::XS)
325      insnContext = IC_64BIT_REXW_XS;
326    else if (HasREX_WPrefix &&
327             (Prefix == X86Local::XD || Prefix == X86Local::TF))
328      insnContext = IC_64BIT_REXW_XD;
329    else if (Prefix == X86Local::XD || Prefix == X86Local::TF)
330      insnContext = IC_64BIT_XD;
331    else if (Prefix == X86Local::XS)
332      insnContext = IC_64BIT_XS;
333    else if (HasREX_WPrefix)
334      insnContext = IC_64BIT_REXW;
335    else
336      insnContext = IC_64BIT;
337  } else {
338    if (HasOpSizePrefix &&
339        (Prefix == X86Local::XD || Prefix == X86Local::TF))
340      insnContext = IC_XD_OPSIZE;
341    else if (HasOpSizePrefix && Prefix == X86Local::XS)
342      insnContext = IC_XS_OPSIZE;
343    else if (HasOpSizePrefix)
344      insnContext = IC_OPSIZE;
345    else if (Prefix == X86Local::XD || Prefix == X86Local::TF)
346      insnContext = IC_XD;
347    else if (Prefix == X86Local::XS || Prefix == X86Local::REP)
348      insnContext = IC_XS;
349    else
350      insnContext = IC;
351  }
352
353  return insnContext;
354}
355
356RecognizableInstr::filter_ret RecognizableInstr::filter() const {
357  ///////////////////
358  // FILTER_STRONG
359  //
360
361  // Filter out intrinsics
362
363  if (!Rec->isSubClassOf("X86Inst"))
364    return FILTER_STRONG;
365
366  if (Form == X86Local::Pseudo ||
367      (IsCodeGenOnly && Name.find("_REV") == Name.npos))
368    return FILTER_STRONG;
369
370  if (Form == X86Local::MRMInitReg)
371    return FILTER_STRONG;
372
373
374  // Filter out artificial instructions
375
376  if (Name.find("TAILJMP") != Name.npos    ||
377      Name.find("_Int") != Name.npos       ||
378      Name.find("_int") != Name.npos       ||
379      Name.find("Int_") != Name.npos       ||
380      Name.find("_NOREX") != Name.npos     ||
381      Name.find("_TC") != Name.npos        ||
382      Name.find("EH_RETURN") != Name.npos  ||
383      Name.find("V_SET") != Name.npos      ||
384      Name.find("LOCK_") != Name.npos      ||
385      Name.find("WIN") != Name.npos        ||
386      Name.find("_AVX") != Name.npos       ||
387      Name.find("2SDL") != Name.npos)
388    return FILTER_STRONG;
389
390  // Filter out instructions with segment override prefixes.
391  // They're too messy to handle now and we'll special case them if needed.
392
393  if (SegOvr)
394    return FILTER_STRONG;
395
396  // Filter out instructions that can't be printed.
397
398  if (AsmString.size() == 0)
399    return FILTER_STRONG;
400
401  // Filter out instructions with subreg operands.
402
403  if (AsmString.find("subreg") != AsmString.npos)
404    return FILTER_STRONG;
405
406  /////////////////
407  // FILTER_WEAK
408  //
409
410
411  // Filter out instructions with a LOCK prefix;
412  //   prefer forms that do not have the prefix
413  if (HasLockPrefix)
414    return FILTER_WEAK;
415
416  // Filter out alternate forms of AVX instructions
417  if (Name.find("_alt") != Name.npos ||
418      Name.find("XrYr") != Name.npos ||
419      (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
420      Name.find("_64mr") != Name.npos ||
421      Name.find("Xrr") != Name.npos ||
422      Name.find("rr64") != Name.npos)
423    return FILTER_WEAK;
424
425  if (Name == "VMASKMOVDQU64"  ||
426      Name == "VEXTRACTPSrr64" ||
427      Name == "VMOVQd64rr"     ||
428      Name == "VMOVQs64rr")
429    return FILTER_WEAK;
430
431  // Special cases.
432
433  if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
434    return FILTER_WEAK;
435  if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
436    return FILTER_WEAK;
437
438  if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
439    return FILTER_WEAK;
440  if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
441    return FILTER_WEAK;
442  if (Name.find("Fs") != Name.npos)
443    return FILTER_WEAK;
444  if (Name == "MOVLPDrr"          ||
445      Name == "MOVLPSrr"          ||
446      Name == "PUSHFQ"            ||
447      Name == "BSF16rr"           ||
448      Name == "BSF16rm"           ||
449      Name == "BSR16rr"           ||
450      Name == "BSR16rm"           ||
451      Name == "MOVSX16rm8"        ||
452      Name == "MOVSX16rr8"        ||
453      Name == "MOVZX16rm8"        ||
454      Name == "MOVZX16rr8"        ||
455      Name == "PUSH32i16"         ||
456      Name == "PUSH64i16"         ||
457      Name == "MOVPQI2QImr"       ||
458      Name == "VMOVPQI2QImr"      ||
459      Name == "MOVSDmr"           ||
460      Name == "MOVSDrm"           ||
461      Name == "MOVSSmr"           ||
462      Name == "MOVSSrm"           ||
463      Name == "MMX_MOVD64rrv164"  ||
464      Name == "CRC32m16"          ||
465      Name == "MOV64ri64i32"      ||
466      Name == "CRC32r16")
467    return FILTER_WEAK;
468
469  if (HasFROperands && Name.find("MOV") != Name.npos &&
470     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
471      (Name.find("to") != Name.npos)))
472    return FILTER_WEAK;
473
474  return FILTER_NORMAL;
475}
476
477bool RecognizableInstr::hasFROperands() const {
478  const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
479  unsigned numOperands = OperandList.size();
480
481  for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
482    const std::string &recName = OperandList[operandIndex].Rec->getName();
483
484    if (recName.find("FR") != recName.npos)
485      return true;
486  }
487  return false;
488}
489
490bool RecognizableInstr::has256BitOperands() const {
491  const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
492  unsigned numOperands = OperandList.size();
493
494  for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
495    const std::string &recName = OperandList[operandIndex].Rec->getName();
496
497    if (!recName.compare("VR256") || !recName.compare("f256mem")) {
498      return true;
499    }
500  }
501  return false;
502}
503
504void RecognizableInstr::handleOperand(
505  bool optional,
506  unsigned &operandIndex,
507  unsigned &physicalOperandIndex,
508  unsigned &numPhysicalOperands,
509  unsigned *operandMapping,
510  OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
511  if (optional) {
512    if (physicalOperandIndex >= numPhysicalOperands)
513      return;
514  } else {
515    assert(physicalOperandIndex < numPhysicalOperands);
516  }
517
518  while (operandMapping[operandIndex] != operandIndex) {
519    Spec->operands[operandIndex].encoding = ENCODING_DUP;
520    Spec->operands[operandIndex].type =
521      (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
522    ++operandIndex;
523  }
524
525  const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
526
527  Spec->operands[operandIndex].encoding = encodingFromString(typeName,
528                                                              HasOpSizePrefix);
529  Spec->operands[operandIndex].type = typeFromString(typeName,
530                                                     IsSSE,
531                                                     HasREX_WPrefix,
532                                                     HasOpSizePrefix);
533
534  ++operandIndex;
535  ++physicalOperandIndex;
536}
537
538void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
539  Spec->name       = Name;
540
541  if (!Rec->isSubClassOf("X86Inst"))
542    return;
543
544  switch (filter()) {
545  case FILTER_WEAK:
546    Spec->filtered = true;
547    break;
548  case FILTER_STRONG:
549    ShouldBeEmitted = false;
550    return;
551  case FILTER_NORMAL:
552    break;
553  }
554
555  Spec->insnContext = insnContext();
556
557  const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
558
559  unsigned operandIndex;
560  unsigned numOperands = OperandList.size();
561  unsigned numPhysicalOperands = 0;
562
563  // operandMapping maps from operands in OperandList to their originals.
564  // If operandMapping[i] != i, then the entry is a duplicate.
565  unsigned operandMapping[X86_MAX_OPERANDS];
566
567  bool hasFROperands = false;
568
569  assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
570
571  for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
572    if (OperandList[operandIndex].Constraints.size()) {
573      const CGIOperandList::ConstraintInfo &Constraint =
574        OperandList[operandIndex].Constraints[0];
575      if (Constraint.isTied()) {
576        operandMapping[operandIndex] = Constraint.getTiedOperand();
577      } else {
578        ++numPhysicalOperands;
579        operandMapping[operandIndex] = operandIndex;
580      }
581    } else {
582      ++numPhysicalOperands;
583      operandMapping[operandIndex] = operandIndex;
584    }
585
586    const std::string &recName = OperandList[operandIndex].Rec->getName();
587
588    if (recName.find("FR") != recName.npos)
589      hasFROperands = true;
590  }
591
592  if (hasFROperands && Name.find("MOV") != Name.npos &&
593     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
594      (Name.find("to") != Name.npos)))
595    ShouldBeEmitted = false;
596
597  if (!ShouldBeEmitted)
598    return;
599
600#define HANDLE_OPERAND(class)               \
601  handleOperand(false,                      \
602                operandIndex,               \
603                physicalOperandIndex,       \
604                numPhysicalOperands,        \
605                operandMapping,             \
606                class##EncodingFromString);
607
608#define HANDLE_OPTIONAL(class)              \
609  handleOperand(true,                       \
610                operandIndex,               \
611                physicalOperandIndex,       \
612                numPhysicalOperands,        \
613                operandMapping,             \
614                class##EncodingFromString);
615
616  // operandIndex should always be < numOperands
617  operandIndex = 0;
618  // physicalOperandIndex should always be < numPhysicalOperands
619  unsigned physicalOperandIndex = 0;
620
621  switch (Form) {
622  case X86Local::RawFrm:
623    // Operand 1 (optional) is an address or immediate.
624    // Operand 2 (optional) is an immediate.
625    assert(numPhysicalOperands <= 2 &&
626           "Unexpected number of operands for RawFrm");
627    HANDLE_OPTIONAL(relocation)
628    HANDLE_OPTIONAL(immediate)
629    break;
630  case X86Local::AddRegFrm:
631    // Operand 1 is added to the opcode.
632    // Operand 2 (optional) is an address.
633    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
634           "Unexpected number of operands for AddRegFrm");
635    HANDLE_OPERAND(opcodeModifier)
636    HANDLE_OPTIONAL(relocation)
637    break;
638  case X86Local::MRMDestReg:
639    // Operand 1 is a register operand in the R/M field.
640    // Operand 2 is a register operand in the Reg/Opcode field.
641    // - In AVX, there is a register operand in the VEX.vvvv field here -
642    // Operand 3 (optional) is an immediate.
643    if (HasVEX_4VPrefix)
644      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
645             "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
646    else
647      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
648             "Unexpected number of operands for MRMDestRegFrm");
649
650    HANDLE_OPERAND(rmRegister)
651
652    if (HasVEX_4VPrefix)
653      // FIXME: In AVX, the register below becomes the one encoded
654      // in ModRMVEX and the one above the one in the VEX.VVVV field
655      HANDLE_OPERAND(vvvvRegister)
656
657    HANDLE_OPERAND(roRegister)
658    HANDLE_OPTIONAL(immediate)
659    break;
660  case X86Local::MRMDestMem:
661    // Operand 1 is a memory operand (possibly SIB-extended)
662    // Operand 2 is a register operand in the Reg/Opcode field.
663    // - In AVX, there is a register operand in the VEX.vvvv field here -
664    // Operand 3 (optional) is an immediate.
665    if (HasVEX_4VPrefix)
666      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
667             "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
668    else
669      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
670             "Unexpected number of operands for MRMDestMemFrm");
671    HANDLE_OPERAND(memory)
672
673    if (HasVEX_4VPrefix)
674      // FIXME: In AVX, the register below becomes the one encoded
675      // in ModRMVEX and the one above the one in the VEX.VVVV field
676      HANDLE_OPERAND(vvvvRegister)
677
678    HANDLE_OPERAND(roRegister)
679    HANDLE_OPTIONAL(immediate)
680    break;
681  case X86Local::MRMSrcReg:
682    // Operand 1 is a register operand in the Reg/Opcode field.
683    // Operand 2 is a register operand in the R/M field.
684    // - In AVX, there is a register operand in the VEX.vvvv field here -
685    // Operand 3 (optional) is an immediate.
686
687    if (HasVEX_4VPrefix)
688      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
689             "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
690    else
691      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
692             "Unexpected number of operands for MRMSrcRegFrm");
693
694    HANDLE_OPERAND(roRegister)
695
696    if (HasVEX_4VPrefix)
697      // FIXME: In AVX, the register below becomes the one encoded
698      // in ModRMVEX and the one above the one in the VEX.VVVV field
699      HANDLE_OPERAND(vvvvRegister)
700
701    HANDLE_OPERAND(rmRegister)
702    HANDLE_OPTIONAL(immediate)
703    break;
704  case X86Local::MRMSrcMem:
705    // Operand 1 is a register operand in the Reg/Opcode field.
706    // Operand 2 is a memory operand (possibly SIB-extended)
707    // - In AVX, there is a register operand in the VEX.vvvv field here -
708    // Operand 3 (optional) is an immediate.
709
710    if (HasVEX_4VPrefix)
711      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
712             "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
713    else
714      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
715             "Unexpected number of operands for MRMSrcMemFrm");
716
717    HANDLE_OPERAND(roRegister)
718
719    if (HasVEX_4VPrefix)
720      // FIXME: In AVX, the register below becomes the one encoded
721      // in ModRMVEX and the one above the one in the VEX.VVVV field
722      HANDLE_OPERAND(vvvvRegister)
723
724    HANDLE_OPERAND(memory)
725    HANDLE_OPTIONAL(immediate)
726    break;
727  case X86Local::MRM0r:
728  case X86Local::MRM1r:
729  case X86Local::MRM2r:
730  case X86Local::MRM3r:
731  case X86Local::MRM4r:
732  case X86Local::MRM5r:
733  case X86Local::MRM6r:
734  case X86Local::MRM7r:
735    // Operand 1 is a register operand in the R/M field.
736    // Operand 2 (optional) is an immediate or relocation.
737    if (HasVEX_4VPrefix)
738      assert(numPhysicalOperands <= 3 &&
739             "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
740    else
741      assert(numPhysicalOperands <= 2 &&
742             "Unexpected number of operands for MRMnRFrm");
743    if (HasVEX_4VPrefix)
744      HANDLE_OPERAND(vvvvRegister);
745    HANDLE_OPTIONAL(rmRegister)
746    HANDLE_OPTIONAL(relocation)
747    break;
748  case X86Local::MRM0m:
749  case X86Local::MRM1m:
750  case X86Local::MRM2m:
751  case X86Local::MRM3m:
752  case X86Local::MRM4m:
753  case X86Local::MRM5m:
754  case X86Local::MRM6m:
755  case X86Local::MRM7m:
756    // Operand 1 is a memory operand (possibly SIB-extended)
757    // Operand 2 (optional) is an immediate or relocation.
758    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
759           "Unexpected number of operands for MRMnMFrm");
760    HANDLE_OPERAND(memory)
761    HANDLE_OPTIONAL(relocation)
762    break;
763  case X86Local::RawFrmImm8:
764    // operand 1 is a 16-bit immediate
765    // operand 2 is an 8-bit immediate
766    assert(numPhysicalOperands == 2 &&
767           "Unexpected number of operands for X86Local::RawFrmImm8");
768    HANDLE_OPERAND(immediate)
769    HANDLE_OPERAND(immediate)
770    break;
771  case X86Local::RawFrmImm16:
772    // operand 1 is a 16-bit immediate
773    // operand 2 is a 16-bit immediate
774    HANDLE_OPERAND(immediate)
775    HANDLE_OPERAND(immediate)
776    break;
777  case X86Local::MRMInitReg:
778    // Ignored.
779    break;
780  }
781
782  #undef HANDLE_OPERAND
783  #undef HANDLE_OPTIONAL
784}
785
786void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
787  // Special cases where the LLVM tables are not complete
788
789#define MAP(from, to)                     \
790  case X86Local::MRM_##from:              \
791    filter = new ExactFilter(0x##from);   \
792    break;
793
794  OpcodeType    opcodeType  = (OpcodeType)-1;
795
796  ModRMFilter*  filter      = NULL;
797  uint8_t       opcodeToSet = 0;
798
799  switch (Prefix) {
800  // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
801  case X86Local::XD:
802  case X86Local::XS:
803  case X86Local::TB:
804    opcodeType = TWOBYTE;
805
806    switch (Opcode) {
807    default:
808      if (needsModRMForDecode(Form))
809        filter = new ModFilter(isRegFormat(Form));
810      else
811        filter = new DumbFilter();
812      break;
813#define EXTENSION_TABLE(n) case 0x##n:
814    TWO_BYTE_EXTENSION_TABLES
815#undef EXTENSION_TABLE
816      switch (Form) {
817      default:
818        llvm_unreachable("Unhandled two-byte extended opcode");
819      case X86Local::MRM0r:
820      case X86Local::MRM1r:
821      case X86Local::MRM2r:
822      case X86Local::MRM3r:
823      case X86Local::MRM4r:
824      case X86Local::MRM5r:
825      case X86Local::MRM6r:
826      case X86Local::MRM7r:
827        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
828        break;
829      case X86Local::MRM0m:
830      case X86Local::MRM1m:
831      case X86Local::MRM2m:
832      case X86Local::MRM3m:
833      case X86Local::MRM4m:
834      case X86Local::MRM5m:
835      case X86Local::MRM6m:
836      case X86Local::MRM7m:
837        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
838        break;
839      MRM_MAPPING
840      } // switch (Form)
841      break;
842    } // switch (Opcode)
843    opcodeToSet = Opcode;
844    break;
845  case X86Local::T8:
846  case X86Local::TF:
847    opcodeType = THREEBYTE_38;
848    if (needsModRMForDecode(Form))
849      filter = new ModFilter(isRegFormat(Form));
850    else
851      filter = new DumbFilter();
852    opcodeToSet = Opcode;
853    break;
854  case X86Local::P_TA:
855    opcodeType = THREEBYTE_3A;
856    if (needsModRMForDecode(Form))
857      filter = new ModFilter(isRegFormat(Form));
858    else
859      filter = new DumbFilter();
860    opcodeToSet = Opcode;
861    break;
862  case X86Local::A6:
863    opcodeType = THREEBYTE_A6;
864    if (needsModRMForDecode(Form))
865      filter = new ModFilter(isRegFormat(Form));
866    else
867      filter = new DumbFilter();
868    opcodeToSet = Opcode;
869    break;
870  case X86Local::A7:
871    opcodeType = THREEBYTE_A7;
872    if (needsModRMForDecode(Form))
873      filter = new ModFilter(isRegFormat(Form));
874    else
875      filter = new DumbFilter();
876    opcodeToSet = Opcode;
877    break;
878  case X86Local::D8:
879  case X86Local::D9:
880  case X86Local::DA:
881  case X86Local::DB:
882  case X86Local::DC:
883  case X86Local::DD:
884  case X86Local::DE:
885  case X86Local::DF:
886    assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
887    opcodeType = ONEBYTE;
888    if (Form == X86Local::AddRegFrm) {
889      Spec->modifierType = MODIFIER_MODRM;
890      Spec->modifierBase = Opcode;
891      filter = new AddRegEscapeFilter(Opcode);
892    } else {
893      filter = new EscapeFilter(true, Opcode);
894    }
895    opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
896    break;
897  case X86Local::REP:
898  default:
899    opcodeType = ONEBYTE;
900    switch (Opcode) {
901#define EXTENSION_TABLE(n) case 0x##n:
902    ONE_BYTE_EXTENSION_TABLES
903#undef EXTENSION_TABLE
904      switch (Form) {
905      default:
906        llvm_unreachable("Fell through the cracks of a single-byte "
907                         "extended opcode");
908      case X86Local::MRM0r:
909      case X86Local::MRM1r:
910      case X86Local::MRM2r:
911      case X86Local::MRM3r:
912      case X86Local::MRM4r:
913      case X86Local::MRM5r:
914      case X86Local::MRM6r:
915      case X86Local::MRM7r:
916        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
917        break;
918      case X86Local::MRM0m:
919      case X86Local::MRM1m:
920      case X86Local::MRM2m:
921      case X86Local::MRM3m:
922      case X86Local::MRM4m:
923      case X86Local::MRM5m:
924      case X86Local::MRM6m:
925      case X86Local::MRM7m:
926        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
927        break;
928      MRM_MAPPING
929      } // switch (Form)
930      break;
931    case 0xd8:
932    case 0xd9:
933    case 0xda:
934    case 0xdb:
935    case 0xdc:
936    case 0xdd:
937    case 0xde:
938    case 0xdf:
939      filter = new EscapeFilter(false, Form - X86Local::MRM0m);
940      break;
941    default:
942      if (needsModRMForDecode(Form))
943        filter = new ModFilter(isRegFormat(Form));
944      else
945        filter = new DumbFilter();
946      break;
947    } // switch (Opcode)
948    opcodeToSet = Opcode;
949  } // switch (Prefix)
950
951  assert(opcodeType != (OpcodeType)-1 &&
952         "Opcode type not set");
953  assert(filter && "Filter not set");
954
955  if (Form == X86Local::AddRegFrm) {
956    if(Spec->modifierType != MODIFIER_MODRM) {
957      assert(opcodeToSet < 0xf9 &&
958             "Not enough room for all ADDREG_FRM operands");
959
960      uint8_t currentOpcode;
961
962      for (currentOpcode = opcodeToSet;
963           currentOpcode < opcodeToSet + 8;
964           ++currentOpcode)
965        tables.setTableFields(opcodeType,
966                              insnContext(),
967                              currentOpcode,
968                              *filter,
969                              UID, Is32Bit, IgnoresVEX_L);
970
971      Spec->modifierType = MODIFIER_OPCODE;
972      Spec->modifierBase = opcodeToSet;
973    } else {
974      // modifierBase was set where MODIFIER_MODRM was set
975      tables.setTableFields(opcodeType,
976                            insnContext(),
977                            opcodeToSet,
978                            *filter,
979                            UID, Is32Bit, IgnoresVEX_L);
980    }
981  } else {
982    tables.setTableFields(opcodeType,
983                          insnContext(),
984                          opcodeToSet,
985                          *filter,
986                          UID, Is32Bit, IgnoresVEX_L);
987
988    Spec->modifierType = MODIFIER_NONE;
989    Spec->modifierBase = opcodeToSet;
990  }
991
992  delete filter;
993
994#undef MAP
995}
996
997#define TYPE(str, type) if (s == str) return type;
998OperandType RecognizableInstr::typeFromString(const std::string &s,
999                                              bool isSSE,
1000                                              bool hasREX_WPrefix,
1001                                              bool hasOpSizePrefix) {
1002  if (isSSE) {
1003    // For SSE instructions, we ignore the OpSize prefix and force operand
1004    // sizes.
1005    TYPE("GR16",              TYPE_R16)
1006    TYPE("GR32",              TYPE_R32)
1007    TYPE("GR64",              TYPE_R64)
1008  }
1009  if(hasREX_WPrefix) {
1010    // For instructions with a REX_W prefix, a declared 32-bit register encoding
1011    // is special.
1012    TYPE("GR32",              TYPE_R32)
1013  }
1014  if(!hasOpSizePrefix) {
1015    // For instructions without an OpSize prefix, a declared 16-bit register or
1016    // immediate encoding is special.
1017    TYPE("GR16",              TYPE_R16)
1018    TYPE("i16imm",            TYPE_IMM16)
1019  }
1020  TYPE("i16mem",              TYPE_Mv)
1021  TYPE("i16imm",              TYPE_IMMv)
1022  TYPE("i16i8imm",            TYPE_IMMv)
1023  TYPE("GR16",                TYPE_Rv)
1024  TYPE("i32mem",              TYPE_Mv)
1025  TYPE("i32imm",              TYPE_IMMv)
1026  TYPE("i32i8imm",            TYPE_IMM32)
1027  TYPE("u32u8imm",            TYPE_IMM32)
1028  TYPE("GR32",                TYPE_Rv)
1029  TYPE("i64mem",              TYPE_Mv)
1030  TYPE("i64i32imm",           TYPE_IMM64)
1031  TYPE("i64i8imm",            TYPE_IMM64)
1032  TYPE("GR64",                TYPE_R64)
1033  TYPE("i8mem",               TYPE_M8)
1034  TYPE("i8imm",               TYPE_IMM8)
1035  TYPE("GR8",                 TYPE_R8)
1036  TYPE("VR128",               TYPE_XMM128)
1037  TYPE("f128mem",             TYPE_M128)
1038  TYPE("f256mem",             TYPE_M256)
1039  TYPE("FR64",                TYPE_XMM64)
1040  TYPE("f64mem",              TYPE_M64FP)
1041  TYPE("sdmem",               TYPE_M64FP)
1042  TYPE("FR32",                TYPE_XMM32)
1043  TYPE("f32mem",              TYPE_M32FP)
1044  TYPE("ssmem",               TYPE_M32FP)
1045  TYPE("RST",                 TYPE_ST)
1046  TYPE("i128mem",             TYPE_M128)
1047  TYPE("i256mem",             TYPE_M256)
1048  TYPE("i64i32imm_pcrel",     TYPE_REL64)
1049  TYPE("i16imm_pcrel",        TYPE_REL16)
1050  TYPE("i32imm_pcrel",        TYPE_REL32)
1051  TYPE("SSECC",               TYPE_IMM3)
1052  TYPE("brtarget",            TYPE_RELv)
1053  TYPE("uncondbrtarget",      TYPE_RELv)
1054  TYPE("brtarget8",           TYPE_REL8)
1055  TYPE("f80mem",              TYPE_M80FP)
1056  TYPE("lea32mem",            TYPE_LEA)
1057  TYPE("lea64_32mem",         TYPE_LEA)
1058  TYPE("lea64mem",            TYPE_LEA)
1059  TYPE("VR64",                TYPE_MM64)
1060  TYPE("i64imm",              TYPE_IMMv)
1061  TYPE("opaque32mem",         TYPE_M1616)
1062  TYPE("opaque48mem",         TYPE_M1632)
1063  TYPE("opaque80mem",         TYPE_M1664)
1064  TYPE("opaque512mem",        TYPE_M512)
1065  TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1066  TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1067  TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1068  TYPE("offset8",             TYPE_MOFFS8)
1069  TYPE("offset16",            TYPE_MOFFS16)
1070  TYPE("offset32",            TYPE_MOFFS32)
1071  TYPE("offset64",            TYPE_MOFFS64)
1072  TYPE("VR256",               TYPE_XMM256)
1073  TYPE("GR16_NOAX",           TYPE_Rv)
1074  TYPE("GR32_NOAX",           TYPE_Rv)
1075  TYPE("GR64_NOAX",           TYPE_R64)
1076  errs() << "Unhandled type string " << s << "\n";
1077  llvm_unreachable("Unhandled type string");
1078}
1079#undef TYPE
1080
1081#define ENCODING(str, encoding) if (s == str) return encoding;
1082OperandEncoding RecognizableInstr::immediateEncodingFromString
1083  (const std::string &s,
1084   bool hasOpSizePrefix) {
1085  if(!hasOpSizePrefix) {
1086    // For instructions without an OpSize prefix, a declared 16-bit register or
1087    // immediate encoding is special.
1088    ENCODING("i16imm",        ENCODING_IW)
1089  }
1090  ENCODING("i32i8imm",        ENCODING_IB)
1091  ENCODING("u32u8imm",        ENCODING_IB)
1092  ENCODING("SSECC",           ENCODING_IB)
1093  ENCODING("i16imm",          ENCODING_Iv)
1094  ENCODING("i16i8imm",        ENCODING_IB)
1095  ENCODING("i32imm",          ENCODING_Iv)
1096  ENCODING("i64i32imm",       ENCODING_ID)
1097  ENCODING("i64i8imm",        ENCODING_IB)
1098  ENCODING("i8imm",           ENCODING_IB)
1099  // This is not a typo.  Instructions like BLENDVPD put
1100  // register IDs in 8-bit immediates nowadays.
1101  ENCODING("VR256",           ENCODING_IB)
1102  ENCODING("VR128",           ENCODING_IB)
1103  errs() << "Unhandled immediate encoding " << s << "\n";
1104  llvm_unreachable("Unhandled immediate encoding");
1105}
1106
1107OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1108  (const std::string &s,
1109   bool hasOpSizePrefix) {
1110  ENCODING("GR16",            ENCODING_RM)
1111  ENCODING("GR32",            ENCODING_RM)
1112  ENCODING("GR64",            ENCODING_RM)
1113  ENCODING("GR8",             ENCODING_RM)
1114  ENCODING("VR128",           ENCODING_RM)
1115  ENCODING("FR64",            ENCODING_RM)
1116  ENCODING("FR32",            ENCODING_RM)
1117  ENCODING("VR64",            ENCODING_RM)
1118  ENCODING("VR256",           ENCODING_RM)
1119  errs() << "Unhandled R/M register encoding " << s << "\n";
1120  llvm_unreachable("Unhandled R/M register encoding");
1121}
1122
1123OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1124  (const std::string &s,
1125   bool hasOpSizePrefix) {
1126  ENCODING("GR16",            ENCODING_REG)
1127  ENCODING("GR32",            ENCODING_REG)
1128  ENCODING("GR64",            ENCODING_REG)
1129  ENCODING("GR8",             ENCODING_REG)
1130  ENCODING("VR128",           ENCODING_REG)
1131  ENCODING("FR64",            ENCODING_REG)
1132  ENCODING("FR32",            ENCODING_REG)
1133  ENCODING("VR64",            ENCODING_REG)
1134  ENCODING("SEGMENT_REG",     ENCODING_REG)
1135  ENCODING("DEBUG_REG",       ENCODING_REG)
1136  ENCODING("CONTROL_REG",     ENCODING_REG)
1137  ENCODING("VR256",           ENCODING_REG)
1138  errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1139  llvm_unreachable("Unhandled reg/opcode register encoding");
1140}
1141
1142OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1143  (const std::string &s,
1144   bool hasOpSizePrefix) {
1145  ENCODING("GR32",            ENCODING_VVVV)
1146  ENCODING("GR64",            ENCODING_VVVV)
1147  ENCODING("FR32",            ENCODING_VVVV)
1148  ENCODING("FR64",            ENCODING_VVVV)
1149  ENCODING("VR128",           ENCODING_VVVV)
1150  ENCODING("VR256",           ENCODING_VVVV)
1151  errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1152  llvm_unreachable("Unhandled VEX.vvvv register encoding");
1153}
1154
1155OperandEncoding RecognizableInstr::memoryEncodingFromString
1156  (const std::string &s,
1157   bool hasOpSizePrefix) {
1158  ENCODING("i16mem",          ENCODING_RM)
1159  ENCODING("i32mem",          ENCODING_RM)
1160  ENCODING("i64mem",          ENCODING_RM)
1161  ENCODING("i8mem",           ENCODING_RM)
1162  ENCODING("ssmem",           ENCODING_RM)
1163  ENCODING("sdmem",           ENCODING_RM)
1164  ENCODING("f128mem",         ENCODING_RM)
1165  ENCODING("f256mem",         ENCODING_RM)
1166  ENCODING("f64mem",          ENCODING_RM)
1167  ENCODING("f32mem",          ENCODING_RM)
1168  ENCODING("i128mem",         ENCODING_RM)
1169  ENCODING("i256mem",         ENCODING_RM)
1170  ENCODING("f80mem",          ENCODING_RM)
1171  ENCODING("lea32mem",        ENCODING_RM)
1172  ENCODING("lea64_32mem",     ENCODING_RM)
1173  ENCODING("lea64mem",        ENCODING_RM)
1174  ENCODING("opaque32mem",     ENCODING_RM)
1175  ENCODING("opaque48mem",     ENCODING_RM)
1176  ENCODING("opaque80mem",     ENCODING_RM)
1177  ENCODING("opaque512mem",    ENCODING_RM)
1178  errs() << "Unhandled memory encoding " << s << "\n";
1179  llvm_unreachable("Unhandled memory encoding");
1180}
1181
1182OperandEncoding RecognizableInstr::relocationEncodingFromString
1183  (const std::string &s,
1184   bool hasOpSizePrefix) {
1185  if(!hasOpSizePrefix) {
1186    // For instructions without an OpSize prefix, a declared 16-bit register or
1187    // immediate encoding is special.
1188    ENCODING("i16imm",        ENCODING_IW)
1189  }
1190  ENCODING("i16imm",          ENCODING_Iv)
1191  ENCODING("i16i8imm",        ENCODING_IB)
1192  ENCODING("i32imm",          ENCODING_Iv)
1193  ENCODING("i32i8imm",        ENCODING_IB)
1194  ENCODING("i64i32imm",       ENCODING_ID)
1195  ENCODING("i64i8imm",        ENCODING_IB)
1196  ENCODING("i8imm",           ENCODING_IB)
1197  ENCODING("i64i32imm_pcrel", ENCODING_ID)
1198  ENCODING("i16imm_pcrel",    ENCODING_IW)
1199  ENCODING("i32imm_pcrel",    ENCODING_ID)
1200  ENCODING("brtarget",        ENCODING_Iv)
1201  ENCODING("brtarget8",       ENCODING_IB)
1202  ENCODING("i64imm",          ENCODING_IO)
1203  ENCODING("offset8",         ENCODING_Ia)
1204  ENCODING("offset16",        ENCODING_Ia)
1205  ENCODING("offset32",        ENCODING_Ia)
1206  ENCODING("offset64",        ENCODING_Ia)
1207  errs() << "Unhandled relocation encoding " << s << "\n";
1208  llvm_unreachable("Unhandled relocation encoding");
1209}
1210
1211OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1212  (const std::string &s,
1213   bool hasOpSizePrefix) {
1214  ENCODING("RST",             ENCODING_I)
1215  ENCODING("GR32",            ENCODING_Rv)
1216  ENCODING("GR64",            ENCODING_RO)
1217  ENCODING("GR16",            ENCODING_Rv)
1218  ENCODING("GR8",             ENCODING_RB)
1219  ENCODING("GR16_NOAX",       ENCODING_Rv)
1220  ENCODING("GR32_NOAX",       ENCODING_Rv)
1221  ENCODING("GR64_NOAX",       ENCODING_RO)
1222  errs() << "Unhandled opcode modifier encoding " << s << "\n";
1223  llvm_unreachable("Unhandled opcode modifier encoding");
1224}
1225#undef ENCODING
1226