PseudoLoweringEmitter.cpp revision 245431
197403Sobrien//===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===// 297403Sobrien// 397403Sobrien// The LLVM Compiler Infrastructure 497403Sobrien// 597403Sobrien// This file is distributed under the University of Illinois Open Source 697403Sobrien// License. See LICENSE.TXT for details. 797403Sobrien// 897403Sobrien//===----------------------------------------------------------------------===// 997403Sobrien 1097403Sobrien#define DEBUG_TYPE "pseudo-lowering" 1197403Sobrien#include "CodeGenInstruction.h" 1297403Sobrien#include "CodeGenTarget.h" 1397403Sobrien#include "llvm/ADT/IndexedMap.h" 1497403Sobrien#include "llvm/ADT/SmallVector.h" 1597403Sobrien#include "llvm/ADT/StringMap.h" 1697403Sobrien#include "llvm/Support/Debug.h" 1797403Sobrien#include "llvm/Support/ErrorHandling.h" 1897403Sobrien#include "llvm/TableGen/Error.h" 1997403Sobrien#include "llvm/TableGen/Record.h" 2097403Sobrien#include "llvm/TableGen/TableGenBackend.h" 2197403Sobrien#include <vector> 2297403Sobrienusing namespace llvm; 2397403Sobrien 2497403Sobriennamespace { 2597403Sobrienclass PseudoLoweringEmitter { 2697403Sobrien struct OpData { 2797403Sobrien enum MapKind { Operand, Imm, Reg }; 2897403Sobrien MapKind Kind; 2997403Sobrien union { 3097403Sobrien unsigned Operand; // Operand number mapped to. 3197403Sobrien uint64_t Imm; // Integer immedate value. 3297403Sobrien Record *Reg; // Physical register. 3397403Sobrien } Data; 3497403Sobrien }; 3597403Sobrien struct PseudoExpansion { 3697403Sobrien CodeGenInstruction Source; // The source pseudo instruction definition. 3797403Sobrien CodeGenInstruction Dest; // The destination instruction to lower to. 3897403Sobrien IndexedMap<OpData> OperandMap; 3997403Sobrien 4097403Sobrien PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d, 4197403Sobrien IndexedMap<OpData> &m) : 4297403Sobrien Source(s), Dest(d), OperandMap(m) {} 4397403Sobrien }; 4497403Sobrien 4597403Sobrien RecordKeeper &Records; 4697403Sobrien 4797403Sobrien // It's overkill to have an instance of the full CodeGenTarget object, 4897403Sobrien // but it loads everything on demand, not in the constructor, so it's 4997403Sobrien // lightweight in performance, so it works out OK. 5097403Sobrien CodeGenTarget Target; 5197403Sobrien 5297403Sobrien SmallVector<PseudoExpansion, 64> Expansions; 5397403Sobrien 5497403Sobrien unsigned addDagOperandMapping(Record *Rec, DagInit *Dag, 5597403Sobrien CodeGenInstruction &Insn, 5697403Sobrien IndexedMap<OpData> &OperandMap, 5797403Sobrien unsigned BaseIdx); 5897403Sobrien void evaluateExpansion(Record *Pseudo); 5997403Sobrien void emitLoweringEmitter(raw_ostream &o); 6097403Sobrienpublic: 6197403Sobrien PseudoLoweringEmitter(RecordKeeper &R) : Records(R), Target(R) {} 6297403Sobrien 6397403Sobrien /// run - Output the pseudo-lowerings. 6497403Sobrien void run(raw_ostream &o); 6597403Sobrien}; 6697403Sobrien} // End anonymous namespace 6797403Sobrien 6897403Sobrien// FIXME: This pass currently can only expand a pseudo to a single instruction. 6997403Sobrien// The pseudo expansion really should take a list of dags, not just 7097403Sobrien// a single dag, so we can do fancier things. 7197403Sobrien 7297403Sobrienunsigned PseudoLoweringEmitter:: 7397403SobrienaddDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, 7497403Sobrien IndexedMap<OpData> &OperandMap, unsigned BaseIdx) { 7597403Sobrien unsigned OpsAdded = 0; 7697403Sobrien for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) { 7797403Sobrien if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) { 7897403Sobrien // Physical register reference. Explicit check for the special case 7997403Sobrien // "zero_reg" definition. 8097403Sobrien if (DI->getDef()->isSubClassOf("Register") || 8197403Sobrien DI->getDef()->getName() == "zero_reg") { 8297403Sobrien OperandMap[BaseIdx + i].Kind = OpData::Reg; 8397403Sobrien OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); 8497403Sobrien ++OpsAdded; 8597403Sobrien continue; 8697403Sobrien } 8797403Sobrien 8897403Sobrien // Normal operands should always have the same type, or we have a 8997403Sobrien // problem. 9097403Sobrien // FIXME: We probably shouldn't ever get a non-zero BaseIdx here. 9197403Sobrien assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!"); 9297403Sobrien if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) 9397403Sobrien PrintFatalError(Rec->getLoc(), 9497403Sobrien "Pseudo operand type '" + DI->getDef()->getName() + 9597403Sobrien "' does not match expansion operand type '" + 9697403Sobrien Insn.Operands[BaseIdx + i].Rec->getName() + "'"); 9797403Sobrien // Source operand maps to destination operand. The Data element 9897403Sobrien // will be filled in later, just set the Kind for now. Do it 9997403Sobrien // for each corresponding MachineInstr operand, not just the first. 10097403Sobrien for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) 10197403Sobrien OperandMap[BaseIdx + i + I].Kind = OpData::Operand; 10297403Sobrien OpsAdded += Insn.Operands[i].MINumOperands; 10397403Sobrien } else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) { 10497403Sobrien OperandMap[BaseIdx + i].Kind = OpData::Imm; 10597403Sobrien OperandMap[BaseIdx + i].Data.Imm = II->getValue(); 10697403Sobrien ++OpsAdded; 10797403Sobrien } else if (DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) { 10897403Sobrien // Just add the operands recursively. This is almost certainly 10997403Sobrien // a constant value for a complex operand (> 1 MI operand). 11097403Sobrien unsigned NewOps = 11197403Sobrien addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i); 11297403Sobrien OpsAdded += NewOps; 11397403Sobrien // Since we added more than one, we also need to adjust the base. 11497403Sobrien BaseIdx += NewOps - 1; 11597403Sobrien } else 11697403Sobrien llvm_unreachable("Unhandled pseudo-expansion argument type!"); 11797403Sobrien } 11897403Sobrien return OpsAdded; 11997403Sobrien} 12097403Sobrien 12197403Sobrienvoid PseudoLoweringEmitter::evaluateExpansion(Record *Rec) { 12297403Sobrien DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n"); 12397403Sobrien 12497403Sobrien // Validate that the result pattern has the corrent number and types 12597403Sobrien // of arguments for the instruction it references. 12697403Sobrien DagInit *Dag = Rec->getValueAsDag("ResultInst"); 12797403Sobrien assert(Dag && "Missing result instruction in pseudo expansion!"); 12897403Sobrien DEBUG(dbgs() << " Result: " << *Dag << "\n"); 12997403Sobrien 13097403Sobrien DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator()); 13197403Sobrien if (!OpDef) 13297403Sobrien PrintFatalError(Rec->getLoc(), Rec->getName() + 13397403Sobrien " has unexpected operator type!"); 13497403Sobrien Record *Operator = OpDef->getDef(); 13597403Sobrien if (!Operator->isSubClassOf("Instruction")) 13697403Sobrien PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + 13797403Sobrien "' is not an instruction!"); 13897403Sobrien 13997403Sobrien CodeGenInstruction Insn(Operator); 14097403Sobrien 14197403Sobrien if (Insn.isCodeGenOnly || Insn.isPseudo) 14297403Sobrien PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + 14397403Sobrien "' cannot be another pseudo instruction!"); 14497403Sobrien 14597403Sobrien if (Insn.Operands.size() != Dag->getNumArgs()) 14697403Sobrien PrintFatalError(Rec->getLoc(), "Pseudo result '" + Operator->getName() + 14797403Sobrien "' operand count mismatch"); 14897403Sobrien 14997403Sobrien unsigned NumMIOperands = 0; 15097403Sobrien for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) 15197403Sobrien NumMIOperands += Insn.Operands[i].MINumOperands; 15297403Sobrien IndexedMap<OpData> OperandMap; 15397403Sobrien OperandMap.grow(NumMIOperands); 15497403Sobrien 15597403Sobrien addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0); 15697403Sobrien 15797403Sobrien // If there are more operands that weren't in the DAG, they have to 15897403Sobrien // be operands that have default values, or we have an error. Currently, 15997403Sobrien // Operands that are a sublass of OperandWithDefaultOp have default values. 16097403Sobrien 16197403Sobrien 16297403Sobrien // Validate that each result pattern argument has a matching (by name) 16397403Sobrien // argument in the source instruction, in either the (outs) or (ins) list. 16497403Sobrien // Also check that the type of the arguments match. 16597403Sobrien // 16697403Sobrien // Record the mapping of the source to result arguments for use by 16797403Sobrien // the lowering emitter. 16897403Sobrien CodeGenInstruction SourceInsn(Rec); 16997403Sobrien StringMap<unsigned> SourceOperands; 17097403Sobrien for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i) 17197403Sobrien SourceOperands[SourceInsn.Operands[i].Name] = i; 17297403Sobrien 17397403Sobrien DEBUG(dbgs() << " Operand mapping:\n"); 17497403Sobrien for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) { 17597403Sobrien // We've already handled constant values. Just map instruction operands 17697403Sobrien // here. 17797403Sobrien if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand) 17897403Sobrien continue; 17997403Sobrien StringMap<unsigned>::iterator SourceOp = 18097403Sobrien SourceOperands.find(Dag->getArgName(i)); 18197403Sobrien if (SourceOp == SourceOperands.end()) 18297403Sobrien PrintFatalError(Rec->getLoc(), 18397403Sobrien "Pseudo output operand '" + Dag->getArgName(i) + 18497403Sobrien "' has no matching source operand."); 18597403Sobrien // Map the source operand to the destination operand index for each 18697403Sobrien // MachineInstr operand. 18797403Sobrien for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) 18897403Sobrien OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand = 18997403Sobrien SourceOp->getValue(); 19097403Sobrien 19197403Sobrien DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << i << "\n"); 19297403Sobrien } 19397403Sobrien 19497403Sobrien Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap)); 19597403Sobrien} 19697403Sobrien 19797403Sobrienvoid PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) { 19897403Sobrien // Emit file header. 19997403Sobrien emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o); 20097403Sobrien 20197403Sobrien o << "bool " << Target.getName() + "AsmPrinter" << "::\n" 20297403Sobrien << "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n" 20397403Sobrien << " const MachineInstr *MI) {\n" 20497403Sobrien << " switch (MI->getOpcode()) {\n" 20597403Sobrien << " default: return false;\n"; 20697403Sobrien for (unsigned i = 0, e = Expansions.size(); i != e; ++i) { 20797403Sobrien PseudoExpansion &Expansion = Expansions[i]; 20897403Sobrien CodeGenInstruction &Source = Expansion.Source; 20997403Sobrien CodeGenInstruction &Dest = Expansion.Dest; 21097403Sobrien o << " case " << Source.Namespace << "::" 21197403Sobrien << Source.TheDef->getName() << ": {\n" 21297403Sobrien << " MCInst TmpInst;\n" 21397403Sobrien << " MCOperand MCOp;\n" 21497403Sobrien << " TmpInst.setOpcode(" << Dest.Namespace << "::" 21597403Sobrien << Dest.TheDef->getName() << ");\n"; 21697403Sobrien 21797403Sobrien // Copy the operands from the source instruction. 21897403Sobrien // FIXME: Instruction operands with defaults values (predicates and cc_out 21997403Sobrien // in ARM, for example shouldn't need explicit values in the 22097403Sobrien // expansion DAG. 22197403Sobrien unsigned MIOpNo = 0; 22297403Sobrien for (unsigned OpNo = 0, E = Dest.Operands.size(); OpNo != E; 22397403Sobrien ++OpNo) { 22497403Sobrien o << " // Operand: " << Dest.Operands[OpNo].Name << "\n"; 22597403Sobrien for (unsigned i = 0, e = Dest.Operands[OpNo].MINumOperands; 22697403Sobrien i != e; ++i) { 22797403Sobrien switch (Expansion.OperandMap[MIOpNo + i].Kind) { 22897403Sobrien case OpData::Operand: 22997403Sobrien o << " lowerOperand(MI->getOperand(" 23097403Sobrien << Source.Operands[Expansion.OperandMap[MIOpNo].Data 23197403Sobrien .Operand].MIOperandNo + i 23297403Sobrien << "), MCOp);\n" 23397403Sobrien << " TmpInst.addOperand(MCOp);\n"; 23497403Sobrien break; 23597403Sobrien case OpData::Imm: 23697403Sobrien o << " TmpInst.addOperand(MCOperand::CreateImm(" 23797403Sobrien << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n"; 23897403Sobrien break; 23997403Sobrien case OpData::Reg: { 24097403Sobrien Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg; 24197403Sobrien o << " TmpInst.addOperand(MCOperand::CreateReg("; 24297403Sobrien // "zero_reg" is special. 24397403Sobrien if (Reg->getName() == "zero_reg") 24497403Sobrien o << "0"; 24597403Sobrien else 24697403Sobrien o << Reg->getValueAsString("Namespace") << "::" << Reg->getName(); 24797403Sobrien o << "));\n"; 24897403Sobrien break; 24997403Sobrien } 25097403Sobrien } 25197403Sobrien } 25297403Sobrien MIOpNo += Dest.Operands[OpNo].MINumOperands; 25397403Sobrien } 25497403Sobrien if (Dest.Operands.isVariadic) { 25597403Sobrien o << " // variable_ops\n"; 25697403Sobrien o << " for (unsigned i = " << MIOpNo 25797403Sobrien << ", e = MI->getNumOperands(); i != e; ++i)\n" 25897403Sobrien << " if (lowerOperand(MI->getOperand(i), MCOp))\n" 25997403Sobrien << " TmpInst.addOperand(MCOp);\n"; 26097403Sobrien } 26197403Sobrien o << " OutStreamer.EmitInstruction(TmpInst);\n" 26297403Sobrien << " break;\n" 26397403Sobrien << " }\n"; 26497403Sobrien } 26597403Sobrien o << " }\n return true;\n}\n\n"; 26697403Sobrien} 26797403Sobrien 26897403Sobrienvoid PseudoLoweringEmitter::run(raw_ostream &o) { 26997403Sobrien Record *ExpansionClass = Records.getClass("PseudoInstExpansion"); 27097403Sobrien Record *InstructionClass = Records.getClass("Instruction"); 27197403Sobrien assert(ExpansionClass && "PseudoInstExpansion class definition missing!"); 27297403Sobrien assert(InstructionClass && "Instruction class definition missing!"); 27397403Sobrien 27497403Sobrien std::vector<Record*> Insts; 27597403Sobrien for (std::map<std::string, Record*>::const_iterator I = 27697403Sobrien Records.getDefs().begin(), E = Records.getDefs().end(); I != E; ++I) { 27797403Sobrien if (I->second->isSubClassOf(ExpansionClass) && 27897403Sobrien I->second->isSubClassOf(InstructionClass)) 27997403Sobrien Insts.push_back(I->second); 28097403Sobrien } 28197403Sobrien 28297403Sobrien // Process the pseudo expansion definitions, validating them as we do so. 28397403Sobrien for (unsigned i = 0, e = Insts.size(); i != e; ++i) 28497403Sobrien evaluateExpansion(Insts[i]); 28597403Sobrien 28697403Sobrien // Generate expansion code to lower the pseudo to an MCInst of the real 28797403Sobrien // instruction. 28897403Sobrien emitLoweringEmitter(o); 28997403Sobrien} 29097403Sobrien 29197403Sobriennamespace llvm { 29297403Sobrien 29397403Sobrienvoid EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS) { 29497403Sobrien PseudoLoweringEmitter(RK).run(OS); 29597403Sobrien} 29697403Sobrien 29797403Sobrien} // End llvm namespace 29897403Sobrien