AsmWriterEmitter.cpp revision 208954
156293Sjkh//===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===// 256293Sjkh// 356293Sjkh// The LLVM Compiler Infrastructure 456293Sjkh// 556293Sjkh// This file is distributed under the University of Illinois Open Source 656293Sjkh// License. See LICENSE.TXT for details. 756293Sjkh// 856293Sjkh//===----------------------------------------------------------------------===// 956293Sjkh// 1056293Sjkh// This tablegen backend is emits an assembly printer for the current target. 1156293Sjkh// Note that this is currently fairly skeletal, but will grow over time. 1256293Sjkh// 1356293Sjkh//===----------------------------------------------------------------------===// 1456293Sjkh 1556293Sjkh#include "AsmWriterEmitter.h" 1677837Sphk#include "AsmWriterInst.h" 1756293Sjkh#include "CodeGenTarget.h" 1856293Sjkh#include "Record.h" 1956293Sjkh#include "StringToOffsetTable.h" 2056293Sjkh#include "llvm/Support/Debug.h" 2156293Sjkh#include "llvm/Support/MathExtras.h" 2256293Sjkh#include <algorithm> 2356293Sjkhusing namespace llvm; 2456293Sjkh 2556293Sjkhstatic void PrintCases(std::vector<std::pair<std::string, 2656293Sjkh AsmWriterOperand> > &OpsToPrint, raw_ostream &O) { 2756293Sjkh O << " case " << OpsToPrint.back().first << ": "; 2856293Sjkh AsmWriterOperand TheOp = OpsToPrint.back().second; 2956293Sjkh OpsToPrint.pop_back(); 3056293Sjkh 3156293Sjkh // Check to see if any other operands are identical in this list, and if so, 3256293Sjkh // emit a case label for them. 3356293Sjkh for (unsigned i = OpsToPrint.size(); i != 0; --i) 3456293Sjkh if (OpsToPrint[i-1].second == TheOp) { 3556293Sjkh O << "\n case " << OpsToPrint[i-1].first << ": "; 3656293Sjkh OpsToPrint.erase(OpsToPrint.begin()+i-1); 3756293Sjkh } 3856293Sjkh 3956293Sjkh // Finally, emit the code. 4056293Sjkh O << TheOp.getCode(); 4156293Sjkh O << "break;\n"; 4256293Sjkh} 4356293Sjkh 4456293Sjkh 4556293Sjkh/// EmitInstructions - Emit the last instruction in the vector and any other 4656293Sjkh/// instructions that are suitably similar to it. 4756293Sjkhstatic void EmitInstructions(std::vector<AsmWriterInst> &Insts, 4856293Sjkh raw_ostream &O) { 4956293Sjkh AsmWriterInst FirstInst = Insts.back(); 5056293Sjkh Insts.pop_back(); 5156293Sjkh 5256293Sjkh std::vector<AsmWriterInst> SimilarInsts; 5356293Sjkh unsigned DifferingOperand = ~0; 5456293Sjkh for (unsigned i = Insts.size(); i != 0; --i) { 5556293Sjkh unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst); 5656293Sjkh if (DiffOp != ~1U) { 5756293Sjkh if (DifferingOperand == ~0U) // First match! 5856293Sjkh DifferingOperand = DiffOp; 5956293Sjkh 6056293Sjkh // If this differs in the same operand as the rest of the instructions in 6156293Sjkh // this class, move it to the SimilarInsts list. 6256293Sjkh if (DifferingOperand == DiffOp || DiffOp == ~0U) { 6356293Sjkh SimilarInsts.push_back(Insts[i-1]); 6456293Sjkh Insts.erase(Insts.begin()+i-1); 6556293Sjkh } 6656293Sjkh } 6756293Sjkh } 6856293Sjkh 6956293Sjkh O << " case " << FirstInst.CGI->Namespace << "::" 7056293Sjkh << FirstInst.CGI->TheDef->getName() << ":\n"; 7156293Sjkh for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i) 7256293Sjkh O << " case " << SimilarInsts[i].CGI->Namespace << "::" 7356293Sjkh << SimilarInsts[i].CGI->TheDef->getName() << ":\n"; 7456293Sjkh for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) { 7556293Sjkh if (i != DifferingOperand) { 7656293Sjkh // If the operand is the same for all instructions, just print it. 7756293Sjkh O << " " << FirstInst.Operands[i].getCode(); 7856293Sjkh } else { 7956293Sjkh // If this is the operand that varies between all of the instructions, 8056293Sjkh // emit a switch for just this operand now. 8156293Sjkh O << " switch (MI->getOpcode()) {\n"; 8256293Sjkh std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint; 8356293Sjkh OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" + 8456293Sjkh FirstInst.CGI->TheDef->getName(), 8556293Sjkh FirstInst.Operands[i])); 8656293Sjkh 8756293Sjkh for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) { 8856293Sjkh AsmWriterInst &AWI = SimilarInsts[si]; 8956293Sjkh OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+ 9056293Sjkh AWI.CGI->TheDef->getName(), 9156293Sjkh AWI.Operands[i])); 9256293Sjkh } 9356293Sjkh std::reverse(OpsToPrint.begin(), OpsToPrint.end()); 9456293Sjkh while (!OpsToPrint.empty()) 9556293Sjkh PrintCases(OpsToPrint, O); 9656293Sjkh O << " }"; 9756293Sjkh } 9856293Sjkh O << "\n"; 9956293Sjkh } 10056293Sjkh O << " break;\n"; 10156293Sjkh} 10256293Sjkh 10356293Sjkhvoid AsmWriterEmitter:: 10456293SjkhFindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands, 10556293Sjkh std::vector<unsigned> &InstIdxs, 10656293Sjkh std::vector<unsigned> &InstOpsUsed) const { 10756293Sjkh InstIdxs.assign(NumberedInstructions.size(), ~0U); 10856293Sjkh 10956293Sjkh // This vector parallels UniqueOperandCommands, keeping track of which 11056293Sjkh // instructions each case are used for. It is a comma separated string of 11156293Sjkh // enums. 11256293Sjkh std::vector<std::string> InstrsForCase; 11356293Sjkh InstrsForCase.resize(UniqueOperandCommands.size()); 11456293Sjkh InstOpsUsed.assign(UniqueOperandCommands.size(), 0); 11556293Sjkh 11656293Sjkh for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 11756293Sjkh const AsmWriterInst *Inst = getAsmWriterInstByID(i); 11856293Sjkh if (Inst == 0) continue; // PHI, INLINEASM, DBG_LABEL, etc. 11956293Sjkh 12056293Sjkh std::string Command; 12156293Sjkh if (Inst->Operands.empty()) 12256455Speter continue; // Instruction already done. 12356455Speter 12456455Speter Command = " " + Inst->Operands[0].getCode() + "\n"; 12556455Speter 12656455Speter // Check to see if we already have 'Command' in UniqueOperandCommands. 12756455Speter // If not, add it. 12856455Speter bool FoundIt = false; 12956293Sjkh for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx) 13056293Sjkh if (UniqueOperandCommands[idx] == Command) { 13156293Sjkh InstIdxs[i] = idx; 13256293Sjkh InstrsForCase[idx] += ", "; 13356293Sjkh InstrsForCase[idx] += Inst->CGI->TheDef->getName(); 13456293Sjkh FoundIt = true; 13556293Sjkh break; 13656293Sjkh } 13756293Sjkh if (!FoundIt) { 13856293Sjkh InstIdxs[i] = UniqueOperandCommands.size(); 13956293Sjkh UniqueOperandCommands.push_back(Command); 14056293Sjkh InstrsForCase.push_back(Inst->CGI->TheDef->getName()); 14156293Sjkh 14256293Sjkh // This command matches one operand so far. 14356293Sjkh InstOpsUsed.push_back(1); 14456293Sjkh } 14556293Sjkh } 14656293Sjkh 14756293Sjkh // For each entry of UniqueOperandCommands, there is a set of instructions 14856293Sjkh // that uses it. If the next command of all instructions in the set are 14956293Sjkh // identical, fold it into the command. 15056293Sjkh for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size(); 15156293Sjkh CommandIdx != e; ++CommandIdx) { 15256293Sjkh 15356293Sjkh for (unsigned Op = 1; ; ++Op) { 15456293Sjkh // Scan for the first instruction in the set. 15556293Sjkh std::vector<unsigned>::iterator NIT = 15656293Sjkh std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx); 15756293Sjkh if (NIT == InstIdxs.end()) break; // No commonality. 15856293Sjkh 15956293Sjkh // If this instruction has no more operands, we isn't anything to merge 16056293Sjkh // into this command. 16156293Sjkh const AsmWriterInst *FirstInst = 16256293Sjkh getAsmWriterInstByID(NIT-InstIdxs.begin()); 16356293Sjkh if (!FirstInst || FirstInst->Operands.size() == Op) 16456293Sjkh break; 16556293Sjkh 16656293Sjkh // Otherwise, scan to see if all of the other instructions in this command 16756293Sjkh // set share the operand. 16856293Sjkh bool AllSame = true; 16956293Sjkh // Keep track of the maximum, number of operands or any 17056293Sjkh // instruction we see in the group. 17156293Sjkh size_t MaxSize = FirstInst->Operands.size(); 17256293Sjkh 17356293Sjkh for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx); 17456293Sjkh NIT != InstIdxs.end(); 17556293Sjkh NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) { 17656293Sjkh // Okay, found another instruction in this command set. If the operand 17756293Sjkh // matches, we're ok, otherwise bail out. 17856293Sjkh const AsmWriterInst *OtherInst = 17956293Sjkh getAsmWriterInstByID(NIT-InstIdxs.begin()); 18056293Sjkh 18156293Sjkh if (OtherInst && 18256293Sjkh OtherInst->Operands.size() > FirstInst->Operands.size()) 18356293Sjkh MaxSize = std::max(MaxSize, OtherInst->Operands.size()); 18456293Sjkh 18577837Sphk if (!OtherInst || OtherInst->Operands.size() == Op || 18656293Sjkh OtherInst->Operands[Op] != FirstInst->Operands[Op]) { 18756293Sjkh AllSame = false; 18856293Sjkh break; 18956293Sjkh } 19056293Sjkh } 19156293Sjkh if (!AllSame) break; 19256293Sjkh 19356293Sjkh // Okay, everything in this command set has the same next operand. Add it 19456293Sjkh // to UniqueOperandCommands and remember that it was consumed. 19556293Sjkh std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n"; 19656293Sjkh 19756293Sjkh UniqueOperandCommands[CommandIdx] += Command; 19856293Sjkh InstOpsUsed[CommandIdx]++; 19956293Sjkh } 20056293Sjkh } 20156293Sjkh 20256293Sjkh // Prepend some of the instructions each case is used for onto the case val. 20356293Sjkh for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) { 20456293Sjkh std::string Instrs = InstrsForCase[i]; 20556293Sjkh if (Instrs.size() > 70) { 20656293Sjkh Instrs.erase(Instrs.begin()+70, Instrs.end()); 20756293Sjkh Instrs += "..."; 20856293Sjkh } 20956293Sjkh 21056293Sjkh if (!Instrs.empty()) 21156293Sjkh UniqueOperandCommands[i] = " // " + Instrs + "\n" + 21256293Sjkh UniqueOperandCommands[i]; 21356293Sjkh } 21456293Sjkh} 21556293Sjkh 21656293Sjkh 21756293Sjkhstatic void UnescapeString(std::string &Str) { 21856293Sjkh for (unsigned i = 0; i != Str.size(); ++i) { 21956293Sjkh if (Str[i] == '\\' && i != Str.size()-1) { 22056293Sjkh switch (Str[i+1]) { 22177837Sphk default: continue; // Don't execute the code after the switch. 22256293Sjkh case 'a': Str[i] = '\a'; break; 22356293Sjkh case 'b': Str[i] = '\b'; break; 22456293Sjkh case 'e': Str[i] = 27; break; 22556293Sjkh case 'f': Str[i] = '\f'; break; 22656293Sjkh case 'n': Str[i] = '\n'; break; 22756293Sjkh case 'r': Str[i] = '\r'; break; 22856293Sjkh case 't': Str[i] = '\t'; break; 22956293Sjkh case 'v': Str[i] = '\v'; break; 23056293Sjkh case '"': Str[i] = '\"'; break; 23156293Sjkh case '\'': Str[i] = '\''; break; 23256293Sjkh case '\\': Str[i] = '\\'; break; 23356293Sjkh } 23456293Sjkh // Nuke the second character. 23556293Sjkh Str.erase(Str.begin()+i+1); 23656293Sjkh } 23756293Sjkh } 23856293Sjkh} 23956293Sjkh 24056293Sjkh/// EmitPrintInstruction - Generate the code for the "printInstruction" method 24156293Sjkh/// implementation. 24256293Sjkhvoid AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { 24356293Sjkh CodeGenTarget Target; 24456293Sjkh Record *AsmWriter = Target.getAsmWriter(); 24556293Sjkh std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 24656293Sjkh 24756293Sjkh O << 24856293Sjkh "/// printInstruction - This method is automatically generated by tablegen\n" 24956293Sjkh "/// from the instruction set description.\n" 25056293Sjkh "void " << Target.getName() << ClassName 25156293Sjkh << "::printInstruction(const MachineInstr *MI, raw_ostream &O) {\n"; 25256293Sjkh 25356293Sjkh std::vector<AsmWriterInst> Instructions; 25456293Sjkh 25556293Sjkh for (CodeGenTarget::inst_iterator I = Target.inst_begin(), 25656293Sjkh E = Target.inst_end(); I != E; ++I) 25756293Sjkh if (!(*I)->AsmString.empty() && 25856293Sjkh (*I)->TheDef->getName() != "PHI") 25956293Sjkh Instructions.push_back( 26056293Sjkh AsmWriterInst(**I, 26156293Sjkh AsmWriter->getValueAsInt("Variant"), 26256293Sjkh AsmWriter->getValueAsInt("FirstOperandColumn"), 26356293Sjkh AsmWriter->getValueAsInt("OperandSpacing"))); 26456293Sjkh 26556293Sjkh // Get the instruction numbering. 26656293Sjkh NumberedInstructions = Target.getInstructionsByEnumValue(); 26756293Sjkh 26856293Sjkh // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not 26956293Sjkh // all machine instructions are necessarily being printed, so there may be 27056293Sjkh // target instructions not in this map. 27156293Sjkh for (unsigned i = 0, e = Instructions.size(); i != e; ++i) 27256293Sjkh CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i])); 27356293Sjkh 27456293Sjkh // Build an aggregate string, and build a table of offsets into it. 27556293Sjkh StringToOffsetTable StringTable; 27656293Sjkh 27756293Sjkh /// OpcodeInfo - This encodes the index of the string to use for the first 27856293Sjkh /// chunk of the output as well as indices used for operand printing. 27956293Sjkh std::vector<unsigned> OpcodeInfo; 28056293Sjkh 28156293Sjkh unsigned MaxStringIdx = 0; 28256293Sjkh for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 28356293Sjkh AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]]; 28456293Sjkh unsigned Idx; 28556293Sjkh if (AWI == 0) { 28656293Sjkh // Something not handled by the asmwriter printer. 28756293Sjkh Idx = ~0U; 28856293Sjkh } else if (AWI->Operands[0].OperandType != 28956293Sjkh AsmWriterOperand::isLiteralTextOperand || 29056293Sjkh AWI->Operands[0].Str.empty()) { 29156293Sjkh // Something handled by the asmwriter printer, but with no leading string. 29256293Sjkh Idx = StringTable.GetOrAddStringOffset(""); 29356293Sjkh } else { 29456293Sjkh std::string Str = AWI->Operands[0].Str; 29556293Sjkh UnescapeString(Str); 29656293Sjkh Idx = StringTable.GetOrAddStringOffset(Str); 29756293Sjkh MaxStringIdx = std::max(MaxStringIdx, Idx); 29856293Sjkh 29956293Sjkh // Nuke the string from the operand list. It is now handled! 30056293Sjkh AWI->Operands.erase(AWI->Operands.begin()); 30156293Sjkh } 30256293Sjkh 30356293Sjkh // Bias offset by one since we want 0 as a sentinel. 30456293Sjkh OpcodeInfo.push_back(Idx+1); 30556293Sjkh } 30656293Sjkh 30756293Sjkh // Figure out how many bits we used for the string index. 30856293Sjkh unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2); 30956293Sjkh 31056293Sjkh // To reduce code size, we compactify common instructions into a few bits 31157352Ssheldonh // in the opcode-indexed table. 31257352Ssheldonh unsigned BitsLeft = 32-AsmStrBits; 31357352Ssheldonh 31456293Sjkh std::vector<std::vector<std::string> > TableDrivenOperandPrinters; 31556293Sjkh 31656293Sjkh while (1) { 31756293Sjkh std::vector<std::string> UniqueOperandCommands; 31856293Sjkh std::vector<unsigned> InstIdxs; 31956293Sjkh std::vector<unsigned> NumInstOpsHandled; 32056293Sjkh FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs, 32156293Sjkh NumInstOpsHandled); 32256293Sjkh 32356293Sjkh // If we ran out of operands to print, we're done. 32456293Sjkh if (UniqueOperandCommands.empty()) break; 32556293Sjkh 32656293Sjkh // Compute the number of bits we need to represent these cases, this is 32756455Speter // ceil(log2(numentries)). 32856455Speter unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size()); 32956455Speter 33056455Speter // If we don't have enough bits for this operand, don't include it. 33156455Speter if (NumBits > BitsLeft) { 33256455Speter DEBUG(errs() << "Not enough bits to densely encode " << NumBits 33356455Speter << " more bits\n"); 33456455Speter break; 33556455Speter } 33656455Speter 33756455Speter // Otherwise, we can include this in the initial lookup table. Add it in. 33856455Speter BitsLeft -= NumBits; 33956455Speter for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i) 34056455Speter if (InstIdxs[i] != ~0U) 34156455Speter OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits); 34256293Sjkh 343 // Remove the info about this operand. 344 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 345 if (AsmWriterInst *Inst = getAsmWriterInstByID(i)) 346 if (!Inst->Operands.empty()) { 347 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]]; 348 assert(NumOps <= Inst->Operands.size() && 349 "Can't remove this many ops!"); 350 Inst->Operands.erase(Inst->Operands.begin(), 351 Inst->Operands.begin()+NumOps); 352 } 353 } 354 355 // Remember the handlers for this set of operands. 356 TableDrivenOperandPrinters.push_back(UniqueOperandCommands); 357 } 358 359 360 361 O<<" static const unsigned OpInfo[] = {\n"; 362 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 363 O << " " << OpcodeInfo[i] << "U,\t// " 364 << NumberedInstructions[i]->TheDef->getName() << "\n"; 365 } 366 // Add a dummy entry so the array init doesn't end with a comma. 367 O << " 0U\n"; 368 O << " };\n\n"; 369 370 // Emit the string itself. 371 O << " const char *AsmStrs = \n"; 372 StringTable.EmitString(O); 373 O << ";\n\n"; 374 375 O << " O << \"\\t\";\n\n"; 376 377 O << " // Emit the opcode for the instruction.\n" 378 << " unsigned Bits = OpInfo[MI->getOpcode()];\n" 379 << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" 380 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n"; 381 382 // Output the table driven operand information. 383 BitsLeft = 32-AsmStrBits; 384 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) { 385 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i]; 386 387 // Compute the number of bits we need to represent these cases, this is 388 // ceil(log2(numentries)). 389 unsigned NumBits = Log2_32_Ceil(Commands.size()); 390 assert(NumBits <= BitsLeft && "consistency error"); 391 392 // Emit code to extract this field from Bits. 393 BitsLeft -= NumBits; 394 395 O << "\n // Fragment " << i << " encoded into " << NumBits 396 << " bits for " << Commands.size() << " unique commands.\n"; 397 398 if (Commands.size() == 2) { 399 // Emit two possibilitys with if/else. 400 O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & " 401 << ((1 << NumBits)-1) << ") {\n" 402 << Commands[1] 403 << " } else {\n" 404 << Commands[0] 405 << " }\n\n"; 406 } else { 407 O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & " 408 << ((1 << NumBits)-1) << ") {\n" 409 << " default: // unreachable.\n"; 410 411 // Print out all the cases. 412 for (unsigned i = 0, e = Commands.size(); i != e; ++i) { 413 O << " case " << i << ":\n"; 414 O << Commands[i]; 415 O << " break;\n"; 416 } 417 O << " }\n\n"; 418 } 419 } 420 421 // Okay, delete instructions with no operand info left. 422 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) { 423 // Entire instruction has been emitted? 424 AsmWriterInst &Inst = Instructions[i]; 425 if (Inst.Operands.empty()) { 426 Instructions.erase(Instructions.begin()+i); 427 --i; --e; 428 } 429 } 430 431 432 // Because this is a vector, we want to emit from the end. Reverse all of the 433 // elements in the vector. 434 std::reverse(Instructions.begin(), Instructions.end()); 435 436 437 // Now that we've emitted all of the operand info that fit into 32 bits, emit 438 // information for those instructions that are left. This is a less dense 439 // encoding, but we expect the main 32-bit table to handle the majority of 440 // instructions. 441 if (!Instructions.empty()) { 442 // Find the opcode # of inline asm. 443 O << " switch (MI->getOpcode()) {\n"; 444 while (!Instructions.empty()) 445 EmitInstructions(Instructions, O); 446 447 O << " }\n"; 448 O << " return;\n"; 449 } 450 451 O << "}\n"; 452} 453 454 455void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { 456 CodeGenTarget Target; 457 Record *AsmWriter = Target.getAsmWriter(); 458 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 459 const std::vector<CodeGenRegister> &Registers = Target.getRegisters(); 460 461 StringToOffsetTable StringTable; 462 O << 463 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n" 464 "/// from the register set description. This returns the assembler name\n" 465 "/// for the specified register.\n" 466 "const char *" << Target.getName() << ClassName 467 << "::getRegisterName(unsigned RegNo) {\n" 468 << " assert(RegNo && RegNo < " << (Registers.size()+1) 469 << " && \"Invalid register number!\");\n" 470 << "\n" 471 << " static const unsigned RegAsmOffset[] = {"; 472 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 473 const CodeGenRegister &Reg = Registers[i]; 474 475 std::string AsmName = Reg.TheDef->getValueAsString("AsmName"); 476 if (AsmName.empty()) 477 AsmName = Reg.getName(); 478 479 480 if ((i % 14) == 0) 481 O << "\n "; 482 483 O << StringTable.GetOrAddStringOffset(AsmName) << ", "; 484 } 485 O << "0\n" 486 << " };\n" 487 << "\n"; 488 489 O << " const char *AsmStrs =\n"; 490 StringTable.EmitString(O); 491 O << ";\n"; 492 493 O << " return AsmStrs+RegAsmOffset[RegNo-1];\n" 494 << "}\n"; 495} 496 497void AsmWriterEmitter::EmitGetInstructionName(raw_ostream &O) { 498 CodeGenTarget Target; 499 Record *AsmWriter = Target.getAsmWriter(); 500 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 501 502 const std::vector<const CodeGenInstruction*> &NumberedInstructions = 503 Target.getInstructionsByEnumValue(); 504 505 StringToOffsetTable StringTable; 506 O << 507"\n\n#ifdef GET_INSTRUCTION_NAME\n" 508"#undef GET_INSTRUCTION_NAME\n\n" 509"/// getInstructionName: This method is automatically generated by tblgen\n" 510"/// from the instruction set description. This returns the enum name of the\n" 511"/// specified instruction.\n" 512 "const char *" << Target.getName() << ClassName 513 << "::getInstructionName(unsigned Opcode) {\n" 514 << " assert(Opcode < " << NumberedInstructions.size() 515 << " && \"Invalid instruction number!\");\n" 516 << "\n" 517 << " static const unsigned InstAsmOffset[] = {"; 518 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 519 const CodeGenInstruction &Inst = *NumberedInstructions[i]; 520 521 std::string AsmName = Inst.TheDef->getName(); 522 if ((i % 14) == 0) 523 O << "\n "; 524 525 O << StringTable.GetOrAddStringOffset(AsmName) << ", "; 526 } 527 O << "0\n" 528 << " };\n" 529 << "\n"; 530 531 O << " const char *Strs =\n"; 532 StringTable.EmitString(O); 533 O << ";\n"; 534 535 O << " return Strs+InstAsmOffset[Opcode];\n" 536 << "}\n\n#endif\n"; 537} 538 539 540 541void AsmWriterEmitter::run(raw_ostream &O) { 542 EmitSourceFileHeader("Assembly Writer Source Fragment", O); 543 544 EmitPrintInstruction(O); 545 EmitGetRegisterName(O); 546 EmitGetInstructionName(O); 547} 548 549