patch-r262261-llvm-r199187-sparc.diff revision 267654 
1Pull in r199187 from upstream llvm trunk (by Jakob Stoklund Olesen):
2
3  Always let value types influence register classes.
4
5  When creating a virtual register for a def, the value type should be
6  used to pick the register class. If we only use the register class
7  constraint on the instruction, we might pick a too large register class.
8
9  Some registers can store values of different sizes. For example, the x86
10  xmm registers can hold f32, f64, and 128-bit vectors. The three
11  different value sizes are represented by register classes with identical
12  register sets: FR32, FR64, and VR128. These register classes have
13  different spill slot sizes, so it is important to use the right one.
14
15  The register class constraint on an instruction doesn't necessarily care
16  about the size of the value its defining. The value type determines
17  that.
18
19  This fixes a problem where InstrEmitter was picking 32-bit register
20  classes for 64-bit values on SPARC.
21
22Introduced here: http://svn.freebsd.org/changeset/base/262261
23
24Index: test/CodeGen/SPARC/spillsize.ll
25===================================================================
26--- test/CodeGen/SPARC/spillsize.ll
27+++ test/CodeGen/SPARC/spillsize.ll
28@@ -0,0 +1,25 @@
29+; RUN: llc < %s -verify-machineinstrs | FileCheck %s
30+target datalayout = "E-m:e-i64:64-n32:64-S128"
31+target triple = "sparcv9"
32+
33+; CHECK-LABEL: spill4
34+; This function spills two values: %p and the materialized large constant.
35+; Both must use 8-byte spill and fill instructions.
36+; CHECK: stx %{{..}}, [%fp+
37+; CHECK: stx %{{..}}, [%fp+
38+; CHECK: ldx [%fp+
39+; CHECK: ldx [%fp+
40+define void @spill4(i64* nocapture %p) {
41+entry:
42+  %val0 = load i64* %p
43+  %cmp0 = icmp ult i64 %val0, 385672958347594845
44+  %cm80 = zext i1 %cmp0 to i64
45+  store i64 %cm80, i64* %p, align 8
46+  tail call void asm sideeffect "", "~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{g2},~{g3},~{g4},~{g5},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o7}"()
47+  %arrayidx1 = getelementptr inbounds i64* %p, i64 1
48+  %val = load i64* %arrayidx1
49+  %cmp = icmp ult i64 %val, 385672958347594845
50+  %cm8 = select i1 %cmp, i64 10, i64 20
51+  store i64 %cm8, i64* %arrayidx1, align 8
52+  ret void
53+}
54Index: lib/CodeGen/SelectionDAG/InstrEmitter.cpp
55===================================================================
56--- lib/CodeGen/SelectionDAG/InstrEmitter.cpp
57+++ lib/CodeGen/SelectionDAG/InstrEmitter.cpp
58@@ -220,10 +220,19 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *
59     unsigned VRBase = 0;
60     const TargetRegisterClass *RC =
61       TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
62-    // If the register class is unknown for the given definition, then try to
63-    // infer one from the value type.
64-    if (!RC && i < NumResults)
65-      RC = TLI->getRegClassFor(Node->getSimpleValueType(i));
66+    // Always let the value type influence the used register class. The
67+    // constraints on the instruction may be too lax to represent the value
68+    // type correctly. For example, a 64-bit float (X86::FR64) can't live in
69+    // the 32-bit float super-class (X86::FR32).
70+    if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
71+      const TargetRegisterClass *VTRC =
72+        TLI->getRegClassFor(Node->getSimpleValueType(i));
73+      if (RC)
74+        VTRC = TRI->getCommonSubClass(RC, VTRC);
75+      if (VTRC)
76+        RC = VTRC;
77+    }
78+
79     if (II.OpInfo[i].isOptionalDef()) {
80       // Optional def must be a physical register.
81       unsigned NumResults = CountResults(Node);
82