XCoreInstrInfo.td revision 208954
1//===- XCoreInstrInfo.td - Target Description for XCore ----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the XCore instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14// Uses of CP, DP are not currently reflected in the patterns, since 15// having a physical register as an operand prevents loop hoisting and 16// since the value of these registers never changes during the life of the 17// function. 18 19//===----------------------------------------------------------------------===// 20// Instruction format superclass. 21//===----------------------------------------------------------------------===// 22 23include "XCoreInstrFormats.td" 24 25//===----------------------------------------------------------------------===// 26// XCore specific DAG Nodes. 27// 28 29// Call 30def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 31def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, 32 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, 33 SDNPVariadic]>; 34 35def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, 36 [SDNPHasChain, SDNPOptInFlag]>; 37 38def SDT_XCoreBR_JT : SDTypeProfile<0, 2, 39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 40 41def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT, 42 [SDNPHasChain]>; 43 44def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT, 45 [SDNPHasChain]>; 46 47def SDT_XCoreAddress : SDTypeProfile<1, 1, 48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 49 50def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, 51 []>; 52 53def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, 54 []>; 55 56def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, 57 []>; 58 59def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; 60def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, 61 [SDNPHasChain]>; 62 63// These are target-independent nodes, but have target-specific formats. 64def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 65def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 66 SDTCisVT<1, i32> ]>; 67 68def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart, 69 [SDNPHasChain, SDNPOutFlag]>; 70def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd, 71 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 72 73//===----------------------------------------------------------------------===// 74// Instruction Pattern Stuff 75//===----------------------------------------------------------------------===// 76 77def div4_xform : SDNodeXForm<imm, [{ 78 // Transformation function: imm/4 79 assert(N->getZExtValue() % 4 == 0); 80 return getI32Imm(N->getZExtValue()/4); 81}]>; 82 83def msksize_xform : SDNodeXForm<imm, [{ 84 // Transformation function: get the size of a mask 85 assert(isMask_32(N->getZExtValue())); 86 // look for the first non-zero bit 87 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue())); 88}]>; 89 90def neg_xform : SDNodeXForm<imm, [{ 91 // Transformation function: -imm 92 uint32_t value = N->getZExtValue(); 93 return getI32Imm(-value); 94}]>; 95 96def bpwsub_xform : SDNodeXForm<imm, [{ 97 // Transformation function: 32-imm 98 uint32_t value = N->getZExtValue(); 99 return getI32Imm(32-value); 100}]>; 101 102def div4neg_xform : SDNodeXForm<imm, [{ 103 // Transformation function: -imm/4 104 uint32_t value = N->getZExtValue(); 105 assert(-value % 4 == 0); 106 return getI32Imm(-value/4); 107}]>; 108 109def immUs4Neg : PatLeaf<(imm), [{ 110 uint32_t value = (uint32_t)N->getZExtValue(); 111 return (-value)%4 == 0 && (-value)/4 <= 11; 112}]>; 113 114def immUs4 : PatLeaf<(imm), [{ 115 uint32_t value = (uint32_t)N->getZExtValue(); 116 return value%4 == 0 && value/4 <= 11; 117}]>; 118 119def immUsNeg : PatLeaf<(imm), [{ 120 return -((uint32_t)N->getZExtValue()) <= 11; 121}]>; 122 123def immUs : PatLeaf<(imm), [{ 124 return (uint32_t)N->getZExtValue() <= 11; 125}]>; 126 127def immU6 : PatLeaf<(imm), [{ 128 return (uint32_t)N->getZExtValue() < (1 << 6); 129}]>; 130 131def immU10 : PatLeaf<(imm), [{ 132 return (uint32_t)N->getZExtValue() < (1 << 10); 133}]>; 134 135def immU16 : PatLeaf<(imm), [{ 136 return (uint32_t)N->getZExtValue() < (1 << 16); 137}]>; 138 139def immU20 : PatLeaf<(imm), [{ 140 return (uint32_t)N->getZExtValue() < (1 << 20); 141}]>; 142 143def immMskBitp : PatLeaf<(imm), [{ 144 uint32_t value = (uint32_t)N->getZExtValue(); 145 if (!isMask_32(value)) { 146 return false; 147 } 148 int msksize = 32 - CountLeadingZeros_32(value); 149 return (msksize >= 1 && msksize <= 8) 150 || msksize == 16 151 || msksize == 24 152 || msksize == 32; 153}]>; 154 155def immBitp : PatLeaf<(imm), [{ 156 uint32_t value = (uint32_t)N->getZExtValue(); 157 return (value >= 1 && value <= 8) 158 || value == 16 159 || value == 24 160 || value == 32; 161}]>; 162 163def immBpwSubBitp : PatLeaf<(imm), [{ 164 uint32_t value = (uint32_t)N->getZExtValue(); 165 return (value >= 24 && value <= 31) 166 || value == 16 167 || value == 8 168 || value == 0; 169}]>; 170 171def lda16f : PatFrag<(ops node:$addr, node:$offset), 172 (add node:$addr, (shl node:$offset, 1))>; 173def lda16b : PatFrag<(ops node:$addr, node:$offset), 174 (sub node:$addr, (shl node:$offset, 1))>; 175def ldawf : PatFrag<(ops node:$addr, node:$offset), 176 (add node:$addr, (shl node:$offset, 2))>; 177def ldawb : PatFrag<(ops node:$addr, node:$offset), 178 (sub node:$addr, (shl node:$offset, 2))>; 179 180// Instruction operand types 181def calltarget : Operand<i32>; 182def brtarget : Operand<OtherVT>; 183def pclabel : Operand<i32>; 184 185// Addressing modes 186def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; 187def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper], 188 []>; 189def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper], 190 []>; 191 192// Address operands 193def MEMii : Operand<i32> { 194 let PrintMethod = "printMemOperand"; 195 let MIOperandInfo = (ops i32imm, i32imm); 196} 197 198// Jump tables. 199def InlineJT : Operand<i32> { 200 let PrintMethod = "printInlineJT"; 201} 202 203def InlineJT32 : Operand<i32> { 204 let PrintMethod = "printInlineJT32"; 205} 206 207//===----------------------------------------------------------------------===// 208// Instruction Class Templates 209//===----------------------------------------------------------------------===// 210 211// Three operand short 212 213multiclass F3R_2RUS<string OpcStr, SDNode OpNode> { 214 def _3r: _F3R< 215 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 216 !strconcat(OpcStr, " $dst, $b, $c"), 217 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 218 def _2rus : _F2RUS< 219 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 220 !strconcat(OpcStr, " $dst, $b, $c"), 221 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 222} 223 224multiclass F3R_2RUS_np<string OpcStr> { 225 def _3r: _F3R< 226 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 227 !strconcat(OpcStr, " $dst, $b, $c"), 228 []>; 229 def _2rus : _F2RUS< 230 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 231 !strconcat(OpcStr, " $dst, $b, $c"), 232 []>; 233} 234 235multiclass F3R_2RBITP<string OpcStr, SDNode OpNode> { 236 def _3r: _F3R< 237 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 238 !strconcat(OpcStr, " $dst, $b, $c"), 239 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 240 def _2rus : _F2RUS< 241 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 242 !strconcat(OpcStr, " $dst, $b, $c"), 243 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 244} 245 246class F3R<string OpcStr, SDNode OpNode> : _F3R< 247 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 248 !strconcat(OpcStr, " $dst, $b, $c"), 249 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 250 251class F3R_np<string OpcStr> : _F3R< 252 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 253 !strconcat(OpcStr, " $dst, $b, $c"), 254 []>; 255// Three operand long 256 257/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 258multiclass FL3R_L2RUS<string OpcStr, SDNode OpNode> { 259 def _l3r: _FL3R< 260 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 261 !strconcat(OpcStr, " $dst, $b, $c"), 262 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 263 def _l2rus : _FL2RUS< 264 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 265 !strconcat(OpcStr, " $dst, $b, $c"), 266 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 267} 268 269/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 270multiclass FL3R_L2RBITP<string OpcStr, SDNode OpNode> { 271 def _l3r: _FL3R< 272 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 273 !strconcat(OpcStr, " $dst, $b, $c"), 274 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 275 def _l2rus : _FL2RUS< 276 (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 277 !strconcat(OpcStr, " $dst, $b, $c"), 278 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 279} 280 281class FL3R<string OpcStr, SDNode OpNode> : _FL3R< 282 (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 283 !strconcat(OpcStr, " $dst, $b, $c"), 284 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 285 286// Register - U6 287// Operand register - U6 288multiclass FRU6_LRU6_branch<string OpcStr> { 289 def _ru6: _FRU6< 290 (outs), (ins GRRegs:$cond, brtarget:$dest), 291 !strconcat(OpcStr, " $cond, $dest"), 292 []>; 293 def _lru6: _FLRU6< 294 (outs), (ins GRRegs:$cond, brtarget:$dest), 295 !strconcat(OpcStr, " $cond, $dest"), 296 []>; 297} 298 299multiclass FRU6_LRU6_cp<string OpcStr> { 300 def _ru6: _FRU6< 301 (outs GRRegs:$dst), (ins i32imm:$a), 302 !strconcat(OpcStr, " $dst, cp[$a]"), 303 []>; 304 def _lru6: _FLRU6< 305 (outs GRRegs:$dst), (ins i32imm:$a), 306 !strconcat(OpcStr, " $dst, cp[$a]"), 307 []>; 308} 309 310// U6 311multiclass FU6_LU6<string OpcStr, SDNode OpNode> { 312 def _u6: _FU6< 313 (outs), (ins i32imm:$b), 314 !strconcat(OpcStr, " $b"), 315 [(OpNode immU6:$b)]>; 316 def _lu6: _FLU6< 317 (outs), (ins i32imm:$b), 318 !strconcat(OpcStr, " $b"), 319 [(OpNode immU16:$b)]>; 320} 321 322multiclass FU6_LU6_np<string OpcStr> { 323 def _u6: _FU6< 324 (outs), (ins i32imm:$b), 325 !strconcat(OpcStr, " $b"), 326 []>; 327 def _lu6: _FLU6< 328 (outs), (ins i32imm:$b), 329 !strconcat(OpcStr, " $b"), 330 []>; 331} 332 333// U10 334multiclass FU10_LU10_np<string OpcStr> { 335 def _u10: _FU10< 336 (outs), (ins i32imm:$b), 337 !strconcat(OpcStr, " $b"), 338 []>; 339 def _lu10: _FLU10< 340 (outs), (ins i32imm:$b), 341 !strconcat(OpcStr, " $b"), 342 []>; 343} 344 345// Two operand short 346 347class F2R_np<string OpcStr> : _F2R< 348 (outs GRRegs:$dst), (ins GRRegs:$b), 349 !strconcat(OpcStr, " $dst, $b"), 350 []>; 351 352// Two operand long 353 354//===----------------------------------------------------------------------===// 355// Pseudo Instructions 356//===----------------------------------------------------------------------===// 357 358let Defs = [SP], Uses = [SP] in { 359def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt), 360 "${:comment} ADJCALLSTACKDOWN $amt", 361 [(callseq_start timm:$amt)]>; 362def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), 363 "${:comment} ADJCALLSTACKUP $amt1", 364 [(callseq_end timm:$amt1, timm:$amt2)]>; 365} 366 367def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 368 "${:comment} LDWFI $dst, $addr", 369 [(set GRRegs:$dst, (load ADDRspii:$addr))]>; 370 371def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 372 "${:comment} LDAWFI $dst, $addr", 373 [(set GRRegs:$dst, ADDRspii:$addr)]>; 374 375def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), 376 "${:comment} STWFI $src, $addr", 377 [(store GRRegs:$src, ADDRspii:$addr)]>; 378 379// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 380// instruction selection into a branch sequence. 381let usesCustomInserter = 1 in { 382 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), 383 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), 384 "${:comment} SELECT_CC PSEUDO!", 385 [(set GRRegs:$dst, 386 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; 387} 388 389//===----------------------------------------------------------------------===// 390// Instructions 391//===----------------------------------------------------------------------===// 392 393// Three operand short 394defm ADD : F3R_2RUS<"add", add>; 395defm SUB : F3R_2RUS<"sub", sub>; 396let neverHasSideEffects = 1 in { 397defm EQ : F3R_2RUS_np<"eq">; 398def LSS_3r : F3R_np<"lss">; 399def LSU_3r : F3R_np<"lsu">; 400} 401def AND_3r : F3R<"and", and>; 402def OR_3r : F3R<"or", or>; 403 404let mayLoad=1 in { 405def LDW_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 406 "ldw $dst, $addr[$offset]", 407 []>; 408 409def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset), 410 "ldw $dst, $addr[$offset]", 411 []>; 412 413def LD16S_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 414 "ld16s $dst, $addr[$offset]", 415 []>; 416 417def LD8U_3r : _F3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 418 "ld8u $dst, $addr[$offset]", 419 []>; 420} 421 422let mayStore=1 in { 423def STW_3r : _F3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 424 "stw $val, $addr[$offset]", 425 []>; 426 427def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), 428 "stw $val, $addr[$offset]", 429 []>; 430} 431 432defm SHL : F3R_2RBITP<"shl", shl>; 433defm SHR : F3R_2RBITP<"shr", srl>; 434// TODO tsetr 435 436// Three operand long 437def LDAWF_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 438 "ldaw $dst, $addr[$offset]", 439 [(set GRRegs:$dst, (ldawf GRRegs:$addr, GRRegs:$offset))]>; 440 441let neverHasSideEffects = 1 in 442def LDAWF_l2rus : _FL2RUS<(outs GRRegs:$dst), 443 (ins GRRegs:$addr, i32imm:$offset), 444 "ldaw $dst, $addr[$offset]", 445 []>; 446 447def LDAWB_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 448 "ldaw $dst, $addr[-$offset]", 449 [(set GRRegs:$dst, (ldawb GRRegs:$addr, GRRegs:$offset))]>; 450 451let neverHasSideEffects = 1 in 452def LDAWB_l2rus : _FL2RUS<(outs GRRegs:$dst), 453 (ins GRRegs:$addr, i32imm:$offset), 454 "ldaw $dst, $addr[-$offset]", 455 []>; 456 457def LDA16F_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 458 "lda16 $dst, $addr[$offset]", 459 [(set GRRegs:$dst, (lda16f GRRegs:$addr, GRRegs:$offset))]>; 460 461def LDA16B_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$addr, GRRegs:$offset), 462 "lda16 $dst, $addr[-$offset]", 463 [(set GRRegs:$dst, (lda16b GRRegs:$addr, GRRegs:$offset))]>; 464 465def MUL_l3r : FL3R<"mul", mul>; 466// Instructions which may trap are marked as side effecting. 467let hasSideEffects = 1 in { 468def DIVS_l3r : FL3R<"divs", sdiv>; 469def DIVU_l3r : FL3R<"divu", udiv>; 470def REMS_l3r : FL3R<"rems", srem>; 471def REMU_l3r : FL3R<"remu", urem>; 472} 473def XOR_l3r : FL3R<"xor", xor>; 474defm ASHR : FL3R_L2RBITP<"ashr", sra>; 475// TODO crc32, crc8, inpw, outpw 476let mayStore=1 in { 477def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 478 "st16 $val, $addr[$offset]", 479 []>; 480 481def ST8_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 482 "st8 $val, $addr[$offset]", 483 []>; 484} 485 486// Four operand long 487let Constraints = "$src1 = $dst1,$src2 = $dst2" in { 488def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 489 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 490 GRRegs:$src4), 491 "maccu $dst1, $dst2, $src3, $src4", 492 []>; 493 494def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), 495 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 496 GRRegs:$src4), 497 "maccs $dst1, $dst2, $src3, $src4", 498 []>; 499} 500 501// Five operand long 502 503def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 504 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 505 "ladd $dst1, $dst2, $src1, $src2, $src3", 506 []>; 507 508def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 509 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 510 "lsub $dst1, $dst2, $src1, $src2, $src3", 511 []>; 512 513def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), 514 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 515 "ldiv $dst1, $dst2, $src1, $src2, $src3", 516 []>; 517 518// Six operand long 519 520def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2), 521 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 522 GRRegs:$src4), 523 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", 524 []>; 525 526// Register - U6 527 528//let Uses = [DP] in ... 529let neverHasSideEffects = 1, isReMaterializable = 1 in 530def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), 531 "ldaw $dst, dp[$a]", 532 []>; 533 534let isReMaterializable = 1 in 535def LDAWDP_lru6: _FLRU6< 536 (outs GRRegs:$dst), (ins MEMii:$a), 537 "ldaw $dst, dp[$a]", 538 [(set GRRegs:$dst, ADDRdpii:$a)]>; 539 540let mayLoad=1 in 541def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), 542 "ldw $dst, dp[$a]", 543 []>; 544 545def LDWDP_lru6: _FLRU6< 546 (outs GRRegs:$dst), (ins MEMii:$a), 547 "ldw $dst, dp[$a]", 548 [(set GRRegs:$dst, (load ADDRdpii:$a))]>; 549 550let mayStore=1 in 551def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr), 552 "stw $val, dp[$addr]", 553 []>; 554 555def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr), 556 "stw $val, dp[$addr]", 557 [(store GRRegs:$val, ADDRdpii:$addr)]>; 558 559//let Uses = [CP] in .. 560let mayLoad = 1, isReMaterializable = 1 in 561defm LDWCP : FRU6_LRU6_cp<"ldw">; 562 563let Uses = [SP] in { 564let mayStore=1 in { 565def STWSP_ru6 : _FRU6< 566 (outs), (ins GRRegs:$val, i32imm:$index), 567 "stw $val, sp[$index]", 568 [(XCoreStwsp GRRegs:$val, immU6:$index)]>; 569 570def STWSP_lru6 : _FLRU6< 571 (outs), (ins GRRegs:$val, i32imm:$index), 572 "stw $val, sp[$index]", 573 [(XCoreStwsp GRRegs:$val, immU16:$index)]>; 574} 575 576let mayLoad=1 in { 577def LDWSP_ru6 : _FRU6< 578 (outs GRRegs:$dst), (ins i32imm:$b), 579 "ldw $dst, sp[$b]", 580 []>; 581 582def LDWSP_lru6 : _FLRU6< 583 (outs GRRegs:$dst), (ins i32imm:$b), 584 "ldw $dst, sp[$b]", 585 []>; 586} 587 588let neverHasSideEffects = 1 in { 589def LDAWSP_ru6 : _FRU6< 590 (outs GRRegs:$dst), (ins i32imm:$b), 591 "ldaw $dst, sp[$b]", 592 []>; 593 594def LDAWSP_lru6 : _FLRU6< 595 (outs GRRegs:$dst), (ins i32imm:$b), 596 "ldaw $dst, sp[$b]", 597 []>; 598 599def LDAWSP_ru6_RRegs : _FRU6< 600 (outs RRegs:$dst), (ins i32imm:$b), 601 "ldaw $dst, sp[$b]", 602 []>; 603 604def LDAWSP_lru6_RRegs : _FLRU6< 605 (outs RRegs:$dst), (ins i32imm:$b), 606 "ldaw $dst, sp[$b]", 607 []>; 608} 609} 610 611let isReMaterializable = 1 in { 612def LDC_ru6 : _FRU6< 613 (outs GRRegs:$dst), (ins i32imm:$b), 614 "ldc $dst, $b", 615 [(set GRRegs:$dst, immU6:$b)]>; 616 617def LDC_lru6 : _FLRU6< 618 (outs GRRegs:$dst), (ins i32imm:$b), 619 "ldc $dst, $b", 620 [(set GRRegs:$dst, immU16:$b)]>; 621} 622 623// Operand register - U6 624// TODO setc 625let isBranch = 1, isTerminator = 1 in { 626defm BRFT: FRU6_LRU6_branch<"bt">; 627defm BRBT: FRU6_LRU6_branch<"bt">; 628defm BRFF: FRU6_LRU6_branch<"bf">; 629defm BRBF: FRU6_LRU6_branch<"bf">; 630} 631 632// U6 633let Defs = [SP], Uses = [SP] in { 634let neverHasSideEffects = 1 in 635defm EXTSP : FU6_LU6_np<"extsp">; 636let mayStore = 1 in 637defm ENTSP : FU6_LU6_np<"entsp">; 638 639let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 640defm RETSP : FU6_LU6<"retsp", XCoreRetsp>; 641} 642} 643 644// TODO extdp, kentsp, krestsp, blat, setsr 645// clrsr, getsr, kalli 646let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 647def BRBU_u6 : _FU6< 648 (outs), 649 (ins brtarget:$target), 650 "bu $target", 651 []>; 652 653def BRBU_lu6 : _FLU6< 654 (outs), 655 (ins brtarget:$target), 656 "bu $target", 657 []>; 658 659def BRFU_u6 : _FU6< 660 (outs), 661 (ins brtarget:$target), 662 "bu $target", 663 []>; 664 665def BRFU_lu6 : _FLU6< 666 (outs), 667 (ins brtarget:$target), 668 "bu $target", 669 []>; 670} 671 672//let Uses = [CP] in ... 673let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in 674def LDAWCP_u6: _FRU6<(outs), (ins MEMii:$a), 675 "ldaw r11, cp[$a]", 676 []>; 677 678let Defs = [R11], isReMaterializable = 1 in 679def LDAWCP_lu6: _FLRU6< 680 (outs), (ins MEMii:$a), 681 "ldaw r11, cp[$a]", 682 [(set R11, ADDRcpii:$a)]>; 683 684// U10 685// TODO ldwcpl, blacp 686 687let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in 688def LDAP_u10 : _FU10< 689 (outs), 690 (ins i32imm:$addr), 691 "ldap r11, $addr", 692 []>; 693 694let Defs = [R11], isReMaterializable = 1 in 695def LDAP_lu10 : _FLU10< 696 (outs), 697 (ins i32imm:$addr), 698 "ldap r11, $addr", 699 [(set R11, (pcrelwrapper tglobaladdr:$addr))]>; 700 701let Defs = [R11], isReMaterializable = 1 in 702def LDAP_lu10_ba : _FLU10<(outs), 703 (ins i32imm:$addr), 704 "ldap r11, $addr", 705 [(set R11, (pcrelwrapper tblockaddress:$addr))]>; 706 707let isCall=1, 708// All calls clobber the link register and the non-callee-saved registers: 709Defs = [R0, R1, R2, R3, R11, LR] in { 710def BL_u10 : _FU10< 711 (outs), 712 (ins calltarget:$target, variable_ops), 713 "bl $target", 714 [(XCoreBranchLink immU10:$target)]>; 715 716def BL_lu10 : _FLU10< 717 (outs), 718 (ins calltarget:$target, variable_ops), 719 "bl $target", 720 [(XCoreBranchLink immU20:$target)]>; 721} 722 723// Two operand short 724// TODO getr, getst 725def NOT : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), 726 "not $dst, $b", 727 [(set GRRegs:$dst, (not GRRegs:$b))]>; 728 729def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), 730 "neg $dst, $b", 731 [(set GRRegs:$dst, (ineg GRRegs:$b))]>; 732 733// TODO setd, eet, eef, getts, setpt, outct, inct, chkct, outt, intt, out, 734// in, outshr, inshr, testct, testwct, tinitpc, tinitdp, tinitsp, tinitcp, 735// tsetmr, sext (reg), zext (reg) 736let isTwoAddress = 1 in { 737let neverHasSideEffects = 1 in 738def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 739 "sext $dst, $src2", 740 []>; 741 742let neverHasSideEffects = 1 in 743def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 744 "zext $dst, $src2", 745 []>; 746 747def ANDNOT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 748 "andnot $dst, $src2", 749 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; 750} 751 752let isReMaterializable = 1, neverHasSideEffects = 1 in 753def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size), 754 "mkmsk $dst, $size", 755 []>; 756 757def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size), 758 "mkmsk $dst, $size", 759 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>; 760 761// Two operand long 762// TODO settw, setclk, setrdy, setpsc, endin, peek, 763// getd, testlcl, tinitlr, getps, setps 764def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 765 "bitrev $dst, $src", 766 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; 767 768def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 769 "byterev $dst, $src", 770 [(set GRRegs:$dst, (bswap GRRegs:$src))]>; 771 772def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), 773 "clz $dst, $src", 774 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; 775 776// One operand short 777// TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp 778// setdp, setcp, setv, setev, kcall 779// dgetreg 780let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 781def BAU_1r : _F1R<(outs), (ins GRRegs:$addr), 782 "bau $addr", 783 [(brind GRRegs:$addr)]>; 784 785let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 786def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i), 787 "bru $i\n$t", 788 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>; 789 790let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 791def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), 792 "bru $i\n$t", 793 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; 794 795let Defs=[SP], neverHasSideEffects=1 in 796def SETSP_1r : _F1R<(outs), (ins GRRegs:$src), 797 "set sp, $src", 798 []>; 799 800let hasCtrlDep = 1 in 801def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src), 802 "ecallt $src", 803 []>; 804 805let hasCtrlDep = 1 in 806def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src), 807 "ecallf $src", 808 []>; 809 810let isCall=1, 811// All calls clobber the link register and the non-callee-saved registers: 812Defs = [R0, R1, R2, R3, R11, LR] in { 813def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops), 814 "bla $addr", 815 [(XCoreBranchLink GRRegs:$addr)]>; 816} 817 818// Zero operand short 819// TODO waiteu, clre, ssync, freet, ldspc, stspc, ldssr, stssr, ldsed, stsed, 820// stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret, 821// dentsp, drestsp 822 823let Defs = [R11] in 824def GETID_0R : _F0R<(outs), (ins), 825 "get r11, id", 826 [(set R11, (int_xcore_getid))]>; 827 828//===----------------------------------------------------------------------===// 829// Non-Instruction Patterns 830//===----------------------------------------------------------------------===// 831 832def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>; 833def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>; 834 835/// sext_inreg 836def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; 837def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>; 838def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>; 839 840/// loads 841def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)), 842 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 843def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 844 845def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 846 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 847def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 848 849def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)), 850 (LDW_3r GRRegs:$addr, GRRegs:$offset)>; 851def : Pat<(load (add GRRegs:$addr, immUs4:$offset)), 852 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 853def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>; 854 855/// anyext 856def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)), 857 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 858def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 859def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 860 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 861def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 862 863/// stores 864def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), 865 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 866def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), 867 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 868 869def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), 870 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 871def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), 872 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 873 874def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), 875 (STW_3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 876def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), 877 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; 878def : Pat<(store GRRegs:$val, GRRegs:$addr), 879 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; 880 881/// cttz 882def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; 883 884/// trap 885def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; 886 887/// 888/// branch patterns 889/// 890 891// unconditional branch 892def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>; 893 894// direct match equal/notequal zero brcond 895def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst), 896 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>; 897def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst), 898 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>; 899 900def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 901 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 902def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 903 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 904def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 905 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 906def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 907 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 908def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 909 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 910def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst), 911 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>; 912 913// generic brcond pattern 914def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>; 915 916 917/// 918/// Select patterns 919/// 920 921// direct match equal/notequal zero select 922def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 923 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>; 924 925def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 926 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>; 927 928def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 929 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 930def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 931 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 932def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 933 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 934def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 935 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 936def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 937 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 938def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F), 939 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>; 940 941/// 942/// setcc patterns, only matched when none of the above brcond 943/// patterns match 944/// 945 946// setcc 2 register operands 947def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs), 948 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 949def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs), 950 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 951 952def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 953 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>; 954def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs), 955 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>; 956 957def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs), 958 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 959def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs), 960 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 961 962def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 963 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>; 964def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs), 965 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>; 966 967def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs), 968 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 969 970def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs), 971 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>; 972 973// setcc reg/imm operands 974def : Pat<(seteq GRRegs:$lhs, immUs:$rhs), 975 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>; 976def : Pat<(setne GRRegs:$lhs, immUs:$rhs), 977 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>; 978 979// misc 980def : Pat<(add GRRegs:$addr, immUs4:$offset), 981 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 982 983def : Pat<(sub GRRegs:$addr, immUs4:$offset), 984 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 985 986def : Pat<(and GRRegs:$val, immMskBitp:$mask), 987 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>; 988 989// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 990def : Pat<(add GRRegs:$src1, immUsNeg:$src2), 991 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>; 992 993def : Pat<(add GRRegs:$src1, immUs4Neg:$src2), 994 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>; 995 996/// 997/// Some peepholes 998/// 999 1000def : Pat<(mul GRRegs:$src, 3), 1001 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>; 1002 1003def : Pat<(mul GRRegs:$src, 5), 1004 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>; 1005 1006def : Pat<(mul GRRegs:$src, -3), 1007 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>; 1008 1009// ashr X, 32 is equivalent to ashr X, 31 on the XCore. 1010def : Pat<(sra GRRegs:$src, 31), 1011 (ASHR_l2rus GRRegs:$src, 32)>; 1012 1013def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1014 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1015 1016// setge X, 0 is canonicalized to setgt X, -1 1017def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1018 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1019 1020def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1021 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; 1022 1023def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1024 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; 1025 1026def : Pat<(setgt GRRegs:$lhs, -1), 1027 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; 1028 1029def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), 1030 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; 1031