1226584Sdim//===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// 2226584Sdim// 3226584Sdim// The LLVM Compiler Infrastructure 4226584Sdim// 5226584Sdim// This file is distributed under the University of Illinois Open Source 6226584Sdim// License. See LICENSE.TXT for details. 7226584Sdim// 8226584Sdim//===----------------------------------------------------------------------===// 9226584Sdim// 10226584Sdim// This file contains small standalone helper functions and enum definitions for 11226584Sdim// the X86 target useful for the compiler back-end and the MC libraries. 12226584Sdim// As such, it deliberately does not include references to LLVM core 13226584Sdim// code gen types, passes, etc.. 14226584Sdim// 15226584Sdim//===----------------------------------------------------------------------===// 16226584Sdim 17226584Sdim#ifndef X86BASEINFO_H 18226584Sdim#define X86BASEINFO_H 19226584Sdim 20226584Sdim#include "X86MCTargetDesc.h" 21226584Sdim#include "llvm/Support/DataTypes.h" 22235633Sdim#include "llvm/Support/ErrorHandling.h" 23252723Sdim#include "llvm/MC/MCInstrInfo.h" 24226584Sdim 25226584Sdimnamespace llvm { 26226584Sdim 27226584Sdimnamespace X86 { 28226584Sdim // Enums for memory operand decoding. Each memory operand is represented with 29226584Sdim // a 5 operand sequence in the form: 30226584Sdim // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] 31226584Sdim // These enums help decode this. 32226584Sdim enum { 33226584Sdim AddrBaseReg = 0, 34226584Sdim AddrScaleAmt = 1, 35226584Sdim AddrIndexReg = 2, 36226584Sdim AddrDisp = 3, 37226584Sdim 38226584Sdim /// AddrSegmentReg - The operand # of the segment in the memory operand. 39226584Sdim AddrSegmentReg = 4, 40226584Sdim 41226584Sdim /// AddrNumOperands - Total number of operands in a memory reference. 42226584Sdim AddrNumOperands = 5 43226584Sdim }; 44226584Sdim} // end namespace X86; 45226584Sdim 46226584Sdim/// X86II - This namespace holds all of the target specific flags that 47226584Sdim/// instruction info tracks. 48226584Sdim/// 49226584Sdimnamespace X86II { 50226584Sdim /// Target Operand Flag enum. 51226584Sdim enum TOF { 52226584Sdim //===------------------------------------------------------------------===// 53226584Sdim // X86 Specific MachineOperand flags. 54226584Sdim 55226584Sdim MO_NO_FLAG, 56226584Sdim 57226584Sdim /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 58226584Sdim /// relocation of: 59226584Sdim /// SYMBOL_LABEL + [. - PICBASELABEL] 60226584Sdim MO_GOT_ABSOLUTE_ADDRESS, 61226584Sdim 62226584Sdim /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 63226584Sdim /// immediate should get the value of the symbol minus the PIC base label: 64226584Sdim /// SYMBOL_LABEL - PICBASELABEL 65226584Sdim MO_PIC_BASE_OFFSET, 66226584Sdim 67226584Sdim /// MO_GOT - On a symbol operand this indicates that the immediate is the 68226584Sdim /// offset to the GOT entry for the symbol name from the base of the GOT. 69226584Sdim /// 70226584Sdim /// See the X86-64 ELF ABI supplement for more details. 71226584Sdim /// SYMBOL_LABEL @GOT 72226584Sdim MO_GOT, 73226584Sdim 74226584Sdim /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 75226584Sdim /// the offset to the location of the symbol name from the base of the GOT. 76226584Sdim /// 77226584Sdim /// See the X86-64 ELF ABI supplement for more details. 78226584Sdim /// SYMBOL_LABEL @GOTOFF 79226584Sdim MO_GOTOFF, 80226584Sdim 81226584Sdim /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 82226584Sdim /// offset to the GOT entry for the symbol name from the current code 83226584Sdim /// location. 84226584Sdim /// 85226584Sdim /// See the X86-64 ELF ABI supplement for more details. 86226584Sdim /// SYMBOL_LABEL @GOTPCREL 87226584Sdim MO_GOTPCREL, 88226584Sdim 89226584Sdim /// MO_PLT - On a symbol operand this indicates that the immediate is 90226584Sdim /// offset to the PLT entry of symbol name from the current code location. 91226584Sdim /// 92226584Sdim /// See the X86-64 ELF ABI supplement for more details. 93226584Sdim /// SYMBOL_LABEL @PLT 94226584Sdim MO_PLT, 95226584Sdim 96226584Sdim /// MO_TLSGD - On a symbol operand this indicates that the immediate is 97245431Sdim /// the offset of the GOT entry with the TLS index structure that contains 98245431Sdim /// the module number and variable offset for the symbol. Used in the 99245431Sdim /// general dynamic TLS access model. 100226584Sdim /// 101226584Sdim /// See 'ELF Handling for Thread-Local Storage' for more details. 102226584Sdim /// SYMBOL_LABEL @TLSGD 103226584Sdim MO_TLSGD, 104226584Sdim 105245431Sdim /// MO_TLSLD - On a symbol operand this indicates that the immediate is 106245431Sdim /// the offset of the GOT entry with the TLS index for the module that 107252723Sdim /// contains the symbol. When this index is passed to a call to 108245431Sdim /// __tls_get_addr, the function will return the base address of the TLS 109245431Sdim /// block for the symbol. Used in the x86-64 local dynamic TLS access model. 110245431Sdim /// 111245431Sdim /// See 'ELF Handling for Thread-Local Storage' for more details. 112245431Sdim /// SYMBOL_LABEL @TLSLD 113245431Sdim MO_TLSLD, 114245431Sdim 115245431Sdim /// MO_TLSLDM - On a symbol operand this indicates that the immediate is 116245431Sdim /// the offset of the GOT entry with the TLS index for the module that 117252723Sdim /// contains the symbol. When this index is passed to a call to 118245431Sdim /// ___tls_get_addr, the function will return the base address of the TLS 119245431Sdim /// block for the symbol. Used in the IA32 local dynamic TLS access model. 120245431Sdim /// 121245431Sdim /// See 'ELF Handling for Thread-Local Storage' for more details. 122245431Sdim /// SYMBOL_LABEL @TLSLDM 123245431Sdim MO_TLSLDM, 124245431Sdim 125226584Sdim /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 126245431Sdim /// the offset of the GOT entry with the thread-pointer offset for the 127245431Sdim /// symbol. Used in the x86-64 initial exec TLS access model. 128226584Sdim /// 129226584Sdim /// See 'ELF Handling for Thread-Local Storage' for more details. 130226584Sdim /// SYMBOL_LABEL @GOTTPOFF 131226584Sdim MO_GOTTPOFF, 132226584Sdim 133226584Sdim /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 134245431Sdim /// the absolute address of the GOT entry with the negative thread-pointer 135245431Sdim /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access 136245431Sdim /// model. 137226584Sdim /// 138226584Sdim /// See 'ELF Handling for Thread-Local Storage' for more details. 139226584Sdim /// SYMBOL_LABEL @INDNTPOFF 140226584Sdim MO_INDNTPOFF, 141226584Sdim 142226584Sdim /// MO_TPOFF - On a symbol operand this indicates that the immediate is 143245431Sdim /// the thread-pointer offset for the symbol. Used in the x86-64 local 144245431Sdim /// exec TLS access model. 145226584Sdim /// 146226584Sdim /// See 'ELF Handling for Thread-Local Storage' for more details. 147226584Sdim /// SYMBOL_LABEL @TPOFF 148226584Sdim MO_TPOFF, 149226584Sdim 150245431Sdim /// MO_DTPOFF - On a symbol operand this indicates that the immediate is 151245431Sdim /// the offset of the GOT entry with the TLS offset of the symbol. Used 152245431Sdim /// in the local dynamic TLS access model. 153245431Sdim /// 154245431Sdim /// See 'ELF Handling for Thread-Local Storage' for more details. 155245431Sdim /// SYMBOL_LABEL @DTPOFF 156245431Sdim MO_DTPOFF, 157245431Sdim 158226584Sdim /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 159245431Sdim /// the negative thread-pointer offset for the symbol. Used in the IA32 160245431Sdim /// local exec TLS access model. 161226584Sdim /// 162226584Sdim /// See 'ELF Handling for Thread-Local Storage' for more details. 163226584Sdim /// SYMBOL_LABEL @NTPOFF 164226584Sdim MO_NTPOFF, 165226584Sdim 166245431Sdim /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is 167245431Sdim /// the offset of the GOT entry with the negative thread-pointer offset for 168245431Sdim /// the symbol. Used in the PIC IA32 initial exec TLS access model. 169245431Sdim /// 170245431Sdim /// See 'ELF Handling for Thread-Local Storage' for more details. 171245431Sdim /// SYMBOL_LABEL @GOTNTPOFF 172245431Sdim MO_GOTNTPOFF, 173245431Sdim 174226584Sdim /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 175226584Sdim /// reference is actually to the "__imp_FOO" symbol. This is used for 176226584Sdim /// dllimport linkage on windows. 177226584Sdim MO_DLLIMPORT, 178226584Sdim 179226584Sdim /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the 180226584Sdim /// reference is actually to the "FOO$stub" symbol. This is used for calls 181226584Sdim /// and jumps to external functions on Tiger and earlier. 182226584Sdim MO_DARWIN_STUB, 183226584Sdim 184226584Sdim /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 185226584Sdim /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 186226584Sdim /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 187226584Sdim MO_DARWIN_NONLAZY, 188226584Sdim 189226584Sdim /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 190226584Sdim /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 191226584Sdim /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 192226584Sdim MO_DARWIN_NONLAZY_PIC_BASE, 193226584Sdim 194226584Sdim /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this 195226584Sdim /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE", 196226584Sdim /// which is a PIC-base-relative reference to a hidden dyld lazy pointer 197226584Sdim /// stub. 198226584Sdim MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, 199226584Sdim 200226584Sdim /// MO_TLVP - On a symbol operand this indicates that the immediate is 201226584Sdim /// some TLS offset. 202226584Sdim /// 203226584Sdim /// This is the TLS offset for the Darwin TLS mechanism. 204226584Sdim MO_TLVP, 205226584Sdim 206226584Sdim /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 207226584Sdim /// is some TLS offset from the picbase. 208226584Sdim /// 209226584Sdim /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 210235633Sdim MO_TLVP_PIC_BASE, 211235633Sdim 212235633Sdim /// MO_SECREL - On a symbol operand this indicates that the immediate is 213235633Sdim /// the offset from beginning of section. 214235633Sdim /// 215235633Sdim /// This is the TLS offset for the COFF/Windows TLS mechanism. 216235633Sdim MO_SECREL 217226584Sdim }; 218226584Sdim 219226584Sdim enum { 220226584Sdim //===------------------------------------------------------------------===// 221226584Sdim // Instruction encodings. These are the standard/most common forms for X86 222226584Sdim // instructions. 223226584Sdim // 224226584Sdim 225226584Sdim // PseudoFrm - This represents an instruction that is a pseudo instruction 226226584Sdim // or one that has not been implemented yet. It is illegal to code generate 227226584Sdim // it, but tolerated for intermediate implementation stages. 228226584Sdim Pseudo = 0, 229226584Sdim 230226584Sdim /// Raw - This form is for instructions that don't have any operands, so 231226584Sdim /// they are just a fixed opcode value, like 'leave'. 232226584Sdim RawFrm = 1, 233226584Sdim 234226584Sdim /// AddRegFrm - This form is used for instructions like 'push r32' that have 235226584Sdim /// their one register operand added to their opcode. 236226584Sdim AddRegFrm = 2, 237226584Sdim 238226584Sdim /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 239226584Sdim /// to specify a destination, which in this case is a register. 240226584Sdim /// 241226584Sdim MRMDestReg = 3, 242226584Sdim 243226584Sdim /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 244226584Sdim /// to specify a destination, which in this case is memory. 245226584Sdim /// 246226584Sdim MRMDestMem = 4, 247226584Sdim 248226584Sdim /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 249226584Sdim /// to specify a source, which in this case is a register. 250226584Sdim /// 251226584Sdim MRMSrcReg = 5, 252226584Sdim 253226584Sdim /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 254226584Sdim /// to specify a source, which in this case is memory. 255226584Sdim /// 256226584Sdim MRMSrcMem = 6, 257226584Sdim 258226584Sdim /// MRM[0-7][rm] - These forms are used to represent instructions that use 259226584Sdim /// a Mod/RM byte, and use the middle field to hold extended opcode 260226584Sdim /// information. In the intel manual these are represented as /0, /1, ... 261226584Sdim /// 262226584Sdim 263226584Sdim // First, instructions that operate on a register r/m operand... 264226584Sdim MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 265226584Sdim MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 266226584Sdim 267226584Sdim // Next, instructions that operate on a memory r/m operand... 268226584Sdim MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 269226584Sdim MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 270226584Sdim 271226584Sdim // MRMInitReg - This form is used for instructions whose source and 272226584Sdim // destinations are the same register. 273226584Sdim MRMInitReg = 32, 274226584Sdim 275235633Sdim //// MRM_XX - A mod/rm byte of exactly 0xXX. 276235633Sdim MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35, MRM_C4 = 36, 277252723Sdim MRM_C8 = 37, MRM_C9 = 38, MRM_CA = 39, MRM_CB = 40, 278252723Sdim MRM_E8 = 41, MRM_F0 = 42, MRM_F8 = 45, MRM_F9 = 46, 279252723Sdim MRM_D0 = 47, MRM_D1 = 48, MRM_D4 = 49, MRM_D5 = 50, 280252723Sdim MRM_D6 = 51, MRM_D8 = 52, MRM_D9 = 53, MRM_DA = 54, 281252723Sdim MRM_DB = 55, MRM_DC = 56, MRM_DD = 57, MRM_DE = 58, 282252723Sdim MRM_DF = 59, 283226584Sdim 284226584Sdim /// RawFrmImm8 - This is used for the ENTER instruction, which has two 285226584Sdim /// immediates, the first of which is a 16-bit immediate (specified by 286226584Sdim /// the imm encoding) and the second is a 8-bit fixed value. 287226584Sdim RawFrmImm8 = 43, 288226584Sdim 289226584Sdim /// RawFrmImm16 - This is used for CALL FAR instructions, which have two 290226584Sdim /// immediates, the first of which is a 16 or 32-bit immediate (specified by 291226584Sdim /// the imm encoding) and the second is a 16-bit fixed value. In the AMD 292226584Sdim /// manual, this operand is described as pntr16:32 and pntr16:16 293226584Sdim RawFrmImm16 = 44, 294226584Sdim 295226584Sdim FormMask = 63, 296226584Sdim 297226584Sdim //===------------------------------------------------------------------===// 298226584Sdim // Actual flags... 299226584Sdim 300226584Sdim // OpSize - Set if this instruction requires an operand size prefix (0x66), 301226584Sdim // which most often indicates that the instruction operates on 16 bit data 302226584Sdim // instead of 32 bit data. 303226584Sdim OpSize = 1 << 6, 304226584Sdim 305226584Sdim // AsSize - Set if this instruction requires an operand size prefix (0x67), 306226584Sdim // which most often indicates that the instruction address 16 bit address 307226584Sdim // instead of 32 bit address (or 32 bit address in 64 bit mode). 308226584Sdim AdSize = 1 << 7, 309226584Sdim 310226584Sdim //===------------------------------------------------------------------===// 311226584Sdim // Op0Mask - There are several prefix bytes that are used to form two byte 312226584Sdim // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is 313226584Sdim // used to obtain the setting of this field. If no bits in this field is 314226584Sdim // set, there is no prefix byte for obtaining a multibyte opcode. 315226584Sdim // 316226584Sdim Op0Shift = 8, 317226584Sdim Op0Mask = 0x1F << Op0Shift, 318226584Sdim 319226584Sdim // TB - TwoByte - Set if this instruction has a two byte opcode, which 320226584Sdim // starts with a 0x0F byte before the real opcode. 321226584Sdim TB = 1 << Op0Shift, 322226584Sdim 323226584Sdim // REP - The 0xF3 prefix byte indicating repetition of the following 324226584Sdim // instruction. 325226584Sdim REP = 2 << Op0Shift, 326226584Sdim 327226584Sdim // D8-DF - These escape opcodes are used by the floating point unit. These 328226584Sdim // values must remain sequential. 329226584Sdim D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, 330226584Sdim DA = 5 << Op0Shift, DB = 6 << Op0Shift, 331226584Sdim DC = 7 << Op0Shift, DD = 8 << Op0Shift, 332226584Sdim DE = 9 << Op0Shift, DF = 10 << Op0Shift, 333226584Sdim 334226584Sdim // XS, XD - These prefix codes are for single and double precision scalar 335226584Sdim // floating point operations performed in the SSE registers. 336226584Sdim XD = 11 << Op0Shift, XS = 12 << Op0Shift, 337226584Sdim 338226584Sdim // T8, TA, A6, A7 - Prefix after the 0x0F prefix. 339226584Sdim T8 = 13 << Op0Shift, TA = 14 << Op0Shift, 340226584Sdim A6 = 15 << Op0Shift, A7 = 16 << Op0Shift, 341226584Sdim 342235633Sdim // T8XD - Prefix before and after 0x0F. Combination of T8 and XD. 343235633Sdim T8XD = 17 << Op0Shift, 344226584Sdim 345235633Sdim // T8XS - Prefix before and after 0x0F. Combination of T8 and XS. 346235633Sdim T8XS = 18 << Op0Shift, 347235633Sdim 348235633Sdim // TAXD - Prefix before and after 0x0F. Combination of TA and XD. 349235633Sdim TAXD = 19 << Op0Shift, 350235633Sdim 351235633Sdim // XOP8 - Prefix to include use of imm byte. 352235633Sdim XOP8 = 20 << Op0Shift, 353235633Sdim 354235633Sdim // XOP9 - Prefix to exclude use of imm byte. 355235633Sdim XOP9 = 21 << Op0Shift, 356235633Sdim 357263509Sdim // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions. 358263509Sdim XOPA = 22 << Op0Shift, 359263509Sdim 360226584Sdim //===------------------------------------------------------------------===// 361226584Sdim // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 362226584Sdim // They are used to specify GPRs and SSE registers, 64-bit operand size, 363226584Sdim // etc. We only cares about REX.W and REX.R bits and only the former is 364226584Sdim // statically determined. 365226584Sdim // 366226584Sdim REXShift = Op0Shift + 5, 367226584Sdim REX_W = 1 << REXShift, 368226584Sdim 369226584Sdim //===------------------------------------------------------------------===// 370226584Sdim // This three-bit field describes the size of an immediate operand. Zero is 371226584Sdim // unused so that we can tell if we forgot to set a value. 372226584Sdim ImmShift = REXShift + 1, 373226584Sdim ImmMask = 7 << ImmShift, 374226584Sdim Imm8 = 1 << ImmShift, 375226584Sdim Imm8PCRel = 2 << ImmShift, 376226584Sdim Imm16 = 3 << ImmShift, 377226584Sdim Imm16PCRel = 4 << ImmShift, 378226584Sdim Imm32 = 5 << ImmShift, 379226584Sdim Imm32PCRel = 6 << ImmShift, 380226584Sdim Imm64 = 7 << ImmShift, 381226584Sdim 382226584Sdim //===------------------------------------------------------------------===// 383226584Sdim // FP Instruction Classification... Zero is non-fp instruction. 384226584Sdim 385226584Sdim // FPTypeMask - Mask for all of the FP types... 386226584Sdim FPTypeShift = ImmShift + 3, 387226584Sdim FPTypeMask = 7 << FPTypeShift, 388226584Sdim 389226584Sdim // NotFP - The default, set for instructions that do not use FP registers. 390226584Sdim NotFP = 0 << FPTypeShift, 391226584Sdim 392226584Sdim // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 393226584Sdim ZeroArgFP = 1 << FPTypeShift, 394226584Sdim 395226584Sdim // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 396226584Sdim OneArgFP = 2 << FPTypeShift, 397226584Sdim 398226584Sdim // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 399226584Sdim // result back to ST(0). For example, fcos, fsqrt, etc. 400226584Sdim // 401226584Sdim OneArgFPRW = 3 << FPTypeShift, 402226584Sdim 403226584Sdim // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 404226584Sdim // explicit argument, storing the result to either ST(0) or the implicit 405226584Sdim // argument. For example: fadd, fsub, fmul, etc... 406226584Sdim TwoArgFP = 4 << FPTypeShift, 407226584Sdim 408226584Sdim // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 409226584Sdim // explicit argument, but have no destination. Example: fucom, fucomi, ... 410226584Sdim CompareFP = 5 << FPTypeShift, 411226584Sdim 412226584Sdim // CondMovFP - "2 operand" floating point conditional move instructions. 413226584Sdim CondMovFP = 6 << FPTypeShift, 414226584Sdim 415226584Sdim // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 416226584Sdim SpecialFP = 7 << FPTypeShift, 417226584Sdim 418226584Sdim // Lock prefix 419226584Sdim LOCKShift = FPTypeShift + 3, 420226584Sdim LOCK = 1 << LOCKShift, 421226584Sdim 422226584Sdim // Segment override prefixes. Currently we just need ability to address 423226584Sdim // stuff in gs and fs segments. 424226584Sdim SegOvrShift = LOCKShift + 1, 425226584Sdim SegOvrMask = 3 << SegOvrShift, 426226584Sdim FS = 1 << SegOvrShift, 427226584Sdim GS = 2 << SegOvrShift, 428226584Sdim 429226584Sdim // Execution domain for SSE instructions in bits 23, 24. 430226584Sdim // 0 in bits 23-24 means normal, non-SSE instruction. 431226584Sdim SSEDomainShift = SegOvrShift + 2, 432226584Sdim 433226584Sdim OpcodeShift = SSEDomainShift + 2, 434226584Sdim 435226584Sdim //===------------------------------------------------------------------===// 436226584Sdim /// VEX - The opcode prefix used by AVX instructions 437226584Sdim VEXShift = OpcodeShift + 8, 438226584Sdim VEX = 1U << 0, 439226584Sdim 440226584Sdim /// VEX_W - Has a opcode specific functionality, but is used in the same 441226584Sdim /// way as REX_W is for regular SSE instructions. 442226584Sdim VEX_W = 1U << 1, 443226584Sdim 444226584Sdim /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 445226584Sdim /// address instructions in SSE are represented as 3 address ones in AVX 446226584Sdim /// and the additional register is encoded in VEX_VVVV prefix. 447226584Sdim VEX_4V = 1U << 2, 448226584Sdim 449235633Sdim /// VEX_4VOp3 - Similar to VEX_4V, but used on instructions that encode 450235633Sdim /// operand 3 with VEX.vvvv. 451235633Sdim VEX_4VOp3 = 1U << 3, 452235633Sdim 453226584Sdim /// VEX_I8IMM - Specifies that the last register used in a AVX instruction, 454226584Sdim /// must be encoded in the i8 immediate field. This usually happens in 455226584Sdim /// instructions with 4 operands. 456235633Sdim VEX_I8IMM = 1U << 4, 457226584Sdim 458226584Sdim /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current 459226584Sdim /// instruction uses 256-bit wide registers. This is usually auto detected 460226584Sdim /// if a VR256 register is used, but some AVX instructions also have this 461226584Sdim /// field marked when using a f256 memory references. 462235633Sdim VEX_L = 1U << 5, 463226584Sdim 464226584Sdim // VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX 465226584Sdim // prefix. Usually used for scalar instructions. Needed by disassembler. 466235633Sdim VEX_LIG = 1U << 6, 467226584Sdim 468263509Sdim // TODO: we should combine VEX_L and VEX_LIG together to form a 2-bit field 469263509Sdim // with following encoding: 470263509Sdim // - 00 V128 471263509Sdim // - 01 V256 472263509Sdim // - 10 V512 473263509Sdim // - 11 LIG (but, in insn encoding, leave VEX.L and EVEX.L in zeros. 474263509Sdim // this will save 1 tsflag bit 475263509Sdim 476263509Sdim // VEX_EVEX - Specifies that this instruction use EVEX form which provides 477263509Sdim // syntax support up to 32 512-bit register operands and up to 7 16-bit 478263509Sdim // mask operands as well as source operand data swizzling/memory operand 479263509Sdim // conversion, eviction hint, and rounding mode. 480263509Sdim EVEX = 1U << 7, 481263509Sdim 482263509Sdim // EVEX_K - Set if this instruction requires masking 483263509Sdim EVEX_K = 1U << 8, 484263509Sdim 485263509Sdim // EVEX_Z - Set if this instruction has EVEX.Z field set. 486263509Sdim EVEX_Z = 1U << 9, 487263509Sdim 488263509Sdim // EVEX_L2 - Set if this instruction has EVEX.L' field set. 489263509Sdim EVEX_L2 = 1U << 10, 490263509Sdim 491263509Sdim // EVEX_B - Set if this instruction has EVEX.B field set. 492263509Sdim EVEX_B = 1U << 11, 493263509Sdim 494263509Sdim // EVEX_CD8E - compressed disp8 form, element-size 495263509Sdim EVEX_CD8EShift = VEXShift + 12, 496263509Sdim EVEX_CD8EMask = 3, 497263509Sdim 498263509Sdim // EVEX_CD8V - compressed disp8 form, vector-width 499263509Sdim EVEX_CD8VShift = EVEX_CD8EShift + 2, 500263509Sdim EVEX_CD8VMask = 7, 501263509Sdim 502226584Sdim /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the 503226584Sdim /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents 504226584Sdim /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction 505226584Sdim /// storing a classifier in the imm8 field. To simplify our implementation, 506226584Sdim /// we handle this by storeing the classifier in the opcode field and using 507226584Sdim /// this flag to indicate that the encoder should do the wacky 3DNow! thing. 508263509Sdim Has3DNow0F0FOpcode = 1U << 17, 509235633Sdim 510235633Sdim /// MemOp4 - Used to indicate swapping of operand 3 and 4 to be encoded in 511235633Sdim /// ModRM or I8IMM. This is used for FMA4 and XOP instructions. 512263509Sdim MemOp4 = 1U << 18, 513235633Sdim 514235633Sdim /// XOP - Opcode prefix used by XOP instructions. 515263509Sdim XOP = 1U << 19 516235633Sdim 517226584Sdim }; 518226584Sdim 519226584Sdim // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 520226584Sdim // specified machine instruction. 521226584Sdim // 522245431Sdim inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { 523226584Sdim return TSFlags >> X86II::OpcodeShift; 524226584Sdim } 525226584Sdim 526245431Sdim inline bool hasImm(uint64_t TSFlags) { 527226584Sdim return (TSFlags & X86II::ImmMask) != 0; 528226584Sdim } 529226584Sdim 530226584Sdim /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field 531226584Sdim /// of the specified instruction. 532245431Sdim inline unsigned getSizeOfImm(uint64_t TSFlags) { 533226584Sdim switch (TSFlags & X86II::ImmMask) { 534235633Sdim default: llvm_unreachable("Unknown immediate size"); 535226584Sdim case X86II::Imm8: 536226584Sdim case X86II::Imm8PCRel: return 1; 537226584Sdim case X86II::Imm16: 538226584Sdim case X86II::Imm16PCRel: return 2; 539226584Sdim case X86II::Imm32: 540226584Sdim case X86II::Imm32PCRel: return 4; 541226584Sdim case X86II::Imm64: return 8; 542226584Sdim } 543226584Sdim } 544226584Sdim 545226584Sdim /// isImmPCRel - Return true if the immediate of the specified instruction's 546226584Sdim /// TSFlags indicates that it is pc relative. 547245431Sdim inline unsigned isImmPCRel(uint64_t TSFlags) { 548226584Sdim switch (TSFlags & X86II::ImmMask) { 549235633Sdim default: llvm_unreachable("Unknown immediate size"); 550226584Sdim case X86II::Imm8PCRel: 551226584Sdim case X86II::Imm16PCRel: 552226584Sdim case X86II::Imm32PCRel: 553226584Sdim return true; 554226584Sdim case X86II::Imm8: 555226584Sdim case X86II::Imm16: 556226584Sdim case X86II::Imm32: 557226584Sdim case X86II::Imm64: 558226584Sdim return false; 559226584Sdim } 560226584Sdim } 561226584Sdim 562252723Sdim /// getOperandBias - compute any additional adjustment needed to 563252723Sdim /// the offset to the start of the memory operand 564252723Sdim /// in this instruction. 565252723Sdim /// If this is a two-address instruction,skip one of the register operands. 566252723Sdim /// FIXME: This should be handled during MCInst lowering. 567252723Sdim inline int getOperandBias(const MCInstrDesc& Desc) 568252723Sdim { 569252723Sdim unsigned NumOps = Desc.getNumOperands(); 570252723Sdim unsigned CurOp = 0; 571252723Sdim if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) 572252723Sdim ++CurOp; 573263509Sdim else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 574263509Sdim Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) 575263509Sdim // Special case for AVX-512 GATHER with 2 TIED_TO operands 576263509Sdim // Skip the first 2 operands: dst, mask_wb 577263509Sdim CurOp += 2; 578263509Sdim else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 579263509Sdim Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1) 580252723Sdim // Special case for GATHER with 2 TIED_TO operands 581252723Sdim // Skip the first 2 operands: dst, mask_wb 582252723Sdim CurOp += 2; 583263509Sdim else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0) 584263509Sdim // SCATTER 585263509Sdim ++CurOp; 586252723Sdim return CurOp; 587252723Sdim } 588252723Sdim 589226584Sdim /// getMemoryOperandNo - The function returns the MCInst operand # for the 590226584Sdim /// first field of the memory operand. If the instruction doesn't have a 591226584Sdim /// memory operand, this returns -1. 592226584Sdim /// 593226584Sdim /// Note that this ignores tied operands. If there is a tied register which 594226584Sdim /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only 595226584Sdim /// counted as one operand. 596226584Sdim /// 597245431Sdim inline int getMemoryOperandNo(uint64_t TSFlags, unsigned Opcode) { 598226584Sdim switch (TSFlags & X86II::FormMask) { 599245431Sdim case X86II::MRMInitReg: 600245431Sdim // FIXME: Remove this form. 601245431Sdim return -1; 602235633Sdim default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!"); 603226584Sdim case X86II::Pseudo: 604226584Sdim case X86II::RawFrm: 605226584Sdim case X86II::AddRegFrm: 606226584Sdim case X86II::MRMDestReg: 607226584Sdim case X86II::MRMSrcReg: 608226584Sdim case X86II::RawFrmImm8: 609226584Sdim case X86II::RawFrmImm16: 610226584Sdim return -1; 611226584Sdim case X86II::MRMDestMem: 612226584Sdim return 0; 613226584Sdim case X86II::MRMSrcMem: { 614226584Sdim bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 615235633Sdim bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 616263509Sdim bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX; 617263509Sdim bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K); 618226584Sdim unsigned FirstMemOp = 1; 619226584Sdim if (HasVEX_4V) 620226584Sdim ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV). 621235633Sdim if (HasMemOp4) 622235633Sdim ++FirstMemOp;// Skip the register source (which is encoded in I8IMM). 623263509Sdim if (HasEVEX_K) 624263509Sdim ++FirstMemOp;// Skip the mask register 625226584Sdim // FIXME: Maybe lea should have its own form? This is a horrible hack. 626226584Sdim //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || 627226584Sdim // Opcode == X86::LEA16r || Opcode == X86::LEA32r) 628226584Sdim return FirstMemOp; 629226584Sdim } 630226584Sdim case X86II::MRM0r: case X86II::MRM1r: 631226584Sdim case X86II::MRM2r: case X86II::MRM3r: 632226584Sdim case X86II::MRM4r: case X86II::MRM5r: 633226584Sdim case X86II::MRM6r: case X86II::MRM7r: 634226584Sdim return -1; 635226584Sdim case X86II::MRM0m: case X86II::MRM1m: 636226584Sdim case X86II::MRM2m: case X86II::MRM3m: 637226584Sdim case X86II::MRM4m: case X86II::MRM5m: 638235633Sdim case X86II::MRM6m: case X86II::MRM7m: { 639235633Sdim bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 640235633Sdim unsigned FirstMemOp = 0; 641235633Sdim if (HasVEX_4V) 642235633Sdim ++FirstMemOp;// Skip the register dest (which is encoded in VEX_VVVV). 643235633Sdim return FirstMemOp; 644235633Sdim } 645252723Sdim case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3: 646252723Sdim case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9: 647252723Sdim case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_E8: 648252723Sdim case X86II::MRM_F0: case X86II::MRM_F8: case X86II::MRM_F9: 649252723Sdim case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4: 650252723Sdim case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8: 651252723Sdim case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB: 652252723Sdim case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE: 653252723Sdim case X86II::MRM_DF: 654226584Sdim return -1; 655226584Sdim } 656226584Sdim } 657226584Sdim 658226584Sdim /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 659226584Sdim /// higher) register? e.g. r8, xmm8, xmm13, etc. 660245431Sdim inline bool isX86_64ExtendedReg(unsigned RegNo) { 661263509Sdim if ((RegNo > X86::XMM7 && RegNo <= X86::XMM15) || 662263509Sdim (RegNo > X86::XMM23 && RegNo <= X86::XMM31) || 663263509Sdim (RegNo > X86::YMM7 && RegNo <= X86::YMM15) || 664263509Sdim (RegNo > X86::YMM23 && RegNo <= X86::YMM31) || 665263509Sdim (RegNo > X86::ZMM7 && RegNo <= X86::ZMM15) || 666263509Sdim (RegNo > X86::ZMM23 && RegNo <= X86::ZMM31)) 667263509Sdim return true; 668263509Sdim 669226584Sdim switch (RegNo) { 670226584Sdim default: break; 671226584Sdim case X86::R8: case X86::R9: case X86::R10: case X86::R11: 672226584Sdim case X86::R12: case X86::R13: case X86::R14: case X86::R15: 673226584Sdim case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 674226584Sdim case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 675226584Sdim case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 676226584Sdim case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 677226584Sdim case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 678226584Sdim case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 679226584Sdim case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11: 680226584Sdim case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15: 681226584Sdim return true; 682226584Sdim } 683226584Sdim return false; 684226584Sdim } 685263509Sdim 686263509Sdim /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) 687263509Sdim /// registers? e.g. zmm21, etc. 688263509Sdim static inline bool is32ExtendedReg(unsigned RegNo) { 689263509Sdim return ((RegNo > X86::XMM15 && RegNo <= X86::XMM31) || 690263509Sdim (RegNo > X86::YMM15 && RegNo <= X86::YMM31) || 691263509Sdim (RegNo > X86::ZMM15 && RegNo <= X86::ZMM31)); 692263509Sdim } 693263509Sdim 694226584Sdim 695245431Sdim inline bool isX86_64NonExtLowByteReg(unsigned reg) { 696226584Sdim return (reg == X86::SPL || reg == X86::BPL || 697226584Sdim reg == X86::SIL || reg == X86::DIL); 698226584Sdim } 699226584Sdim} 700226584Sdim 701226584Sdim} // end namespace llvm; 702226584Sdim 703226584Sdim#endif 704