X86AsmParser.cpp revision 235633 
1//===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/X86BaseInfo.h"
11#include "llvm/MC/MCTargetAsmParser.h"
12#include "llvm/MC/MCStreamer.h"
13#include "llvm/MC/MCExpr.h"
14#include "llvm/MC/MCInst.h"
15#include "llvm/MC/MCRegisterInfo.h"
16#include "llvm/MC/MCSubtargetInfo.h"
17#include "llvm/MC/MCParser/MCAsmLexer.h"
18#include "llvm/MC/MCParser/MCAsmParser.h"
19#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
20#include "llvm/ADT/SmallString.h"
21#include "llvm/ADT/SmallVector.h"
22#include "llvm/ADT/StringSwitch.h"
23#include "llvm/ADT/Twine.h"
24#include "llvm/Support/SourceMgr.h"
25#include "llvm/Support/TargetRegistry.h"
26#include "llvm/Support/raw_ostream.h"
27
28using namespace llvm;
29
30namespace {
31struct X86Operand;
32
33class X86AsmParser : public MCTargetAsmParser {
34  MCSubtargetInfo &STI;
35  MCAsmParser &Parser;
36private:
37  MCAsmParser &getParser() const { return Parser; }
38
39  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
40
41  bool Error(SMLoc L, const Twine &Msg,
42             ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
43    return Parser.Error(L, Msg, Ranges);
44  }
45
46  X86Operand *ErrorOperand(SMLoc Loc, StringRef Msg) {
47    Error(Loc, Msg);
48    return 0;
49  }
50
51  X86Operand *ParseOperand();
52  X86Operand *ParseATTOperand();
53  X86Operand *ParseIntelOperand();
54  X86Operand *ParseIntelMemOperand();
55  X86Operand *ParseIntelBracExpression(unsigned SegReg, unsigned Size);
56  X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
57
58  bool ParseDirectiveWord(unsigned Size, SMLoc L);
59  bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
60
61  bool processInstruction(MCInst &Inst,
62                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
63
64  bool MatchAndEmitInstruction(SMLoc IDLoc,
65                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
66                               MCStreamer &Out);
67
68  /// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi)
69  /// in 64bit mode or (%esi) or %es:(%esi) in 32bit mode.
70  bool isSrcOp(X86Operand &Op);
71
72  /// isDstOp - Returns true if operand is either (%rdi) or %es:(%rdi)
73  /// in 64bit mode or (%edi) or %es:(%edi) in 32bit mode.
74  bool isDstOp(X86Operand &Op);
75
76  bool is64BitMode() const {
77    // FIXME: Can tablegen auto-generate this?
78    return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
79  }
80  void SwitchMode() {
81    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));
82    setAvailableFeatures(FB);
83  }
84
85  /// @name Auto-generated Matcher Functions
86  /// {
87
88#define GET_ASSEMBLER_HEADER
89#include "X86GenAsmMatcher.inc"
90
91  /// }
92
93public:
94  X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
95    : MCTargetAsmParser(), STI(sti), Parser(parser) {
96
97    // Initialize the set of available features.
98    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
99  }
100  virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
101
102  virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
103                                SmallVectorImpl<MCParsedAsmOperand*> &Operands);
104
105  virtual bool ParseDirective(AsmToken DirectiveID);
106
107  bool isParsingIntelSyntax() {
108    return getParser().getAssemblerDialect();
109  }
110};
111} // end anonymous namespace
112
113/// @name Auto-generated Match Functions
114/// {
115
116static unsigned MatchRegisterName(StringRef Name);
117
118/// }
119
120static  bool isImmSExti16i8Value(uint64_t Value) {
121  return ((                                  Value <= 0x000000000000007FULL)||
122          (0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
123          (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
124}
125
126static bool isImmSExti32i8Value(uint64_t Value) {
127  return ((                                  Value <= 0x000000000000007FULL)||
128          (0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
129          (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
130}
131
132static bool isImmZExtu32u8Value(uint64_t Value) {
133    return (Value <= 0x00000000000000FFULL);
134}
135
136static bool isImmSExti64i8Value(uint64_t Value) {
137  return ((                                  Value <= 0x000000000000007FULL)||
138	  (0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
139}
140
141static bool isImmSExti64i32Value(uint64_t Value) {
142  return ((                                  Value <= 0x000000007FFFFFFFULL)||
143	  (0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
144}
145namespace {
146
147/// X86Operand - Instances of this class represent a parsed X86 machine
148/// instruction.
149struct X86Operand : public MCParsedAsmOperand {
150  enum KindTy {
151    Token,
152    Register,
153    Immediate,
154    Memory
155  } Kind;
156
157  SMLoc StartLoc, EndLoc;
158
159  union {
160    struct {
161      const char *Data;
162      unsigned Length;
163    } Tok;
164
165    struct {
166      unsigned RegNo;
167    } Reg;
168
169    struct {
170      const MCExpr *Val;
171    } Imm;
172
173    struct {
174      unsigned SegReg;
175      const MCExpr *Disp;
176      unsigned BaseReg;
177      unsigned IndexReg;
178      unsigned Scale;
179      unsigned Size;
180    } Mem;
181  };
182
183  X86Operand(KindTy K, SMLoc Start, SMLoc End)
184    : Kind(K), StartLoc(Start), EndLoc(End) {}
185
186  /// getStartLoc - Get the location of the first token of this operand.
187  SMLoc getStartLoc() const { return StartLoc; }
188  /// getEndLoc - Get the location of the last token of this operand.
189  SMLoc getEndLoc() const { return EndLoc; }
190
191  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
192
193  virtual void print(raw_ostream &OS) const {}
194
195  StringRef getToken() const {
196    assert(Kind == Token && "Invalid access!");
197    return StringRef(Tok.Data, Tok.Length);
198  }
199  void setTokenValue(StringRef Value) {
200    assert(Kind == Token && "Invalid access!");
201    Tok.Data = Value.data();
202    Tok.Length = Value.size();
203  }
204
205  unsigned getReg() const {
206    assert(Kind == Register && "Invalid access!");
207    return Reg.RegNo;
208  }
209
210  const MCExpr *getImm() const {
211    assert(Kind == Immediate && "Invalid access!");
212    return Imm.Val;
213  }
214
215  const MCExpr *getMemDisp() const {
216    assert(Kind == Memory && "Invalid access!");
217    return Mem.Disp;
218  }
219  unsigned getMemSegReg() const {
220    assert(Kind == Memory && "Invalid access!");
221    return Mem.SegReg;
222  }
223  unsigned getMemBaseReg() const {
224    assert(Kind == Memory && "Invalid access!");
225    return Mem.BaseReg;
226  }
227  unsigned getMemIndexReg() const {
228    assert(Kind == Memory && "Invalid access!");
229    return Mem.IndexReg;
230  }
231  unsigned getMemScale() const {
232    assert(Kind == Memory && "Invalid access!");
233    return Mem.Scale;
234  }
235
236  bool isToken() const {return Kind == Token; }
237
238  bool isImm() const { return Kind == Immediate; }
239
240  bool isImmSExti16i8() const {
241    if (!isImm())
242      return false;
243
244    // If this isn't a constant expr, just assume it fits and let relaxation
245    // handle it.
246    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
247    if (!CE)
248      return true;
249
250    // Otherwise, check the value is in a range that makes sense for this
251    // extension.
252    return isImmSExti16i8Value(CE->getValue());
253  }
254  bool isImmSExti32i8() const {
255    if (!isImm())
256      return false;
257
258    // If this isn't a constant expr, just assume it fits and let relaxation
259    // handle it.
260    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
261    if (!CE)
262      return true;
263
264    // Otherwise, check the value is in a range that makes sense for this
265    // extension.
266    return isImmSExti32i8Value(CE->getValue());
267  }
268  bool isImmZExtu32u8() const {
269    if (!isImm())
270      return false;
271
272    // If this isn't a constant expr, just assume it fits and let relaxation
273    // handle it.
274    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
275    if (!CE)
276      return true;
277
278    // Otherwise, check the value is in a range that makes sense for this
279    // extension.
280    return isImmZExtu32u8Value(CE->getValue());
281  }
282  bool isImmSExti64i8() const {
283    if (!isImm())
284      return false;
285
286    // If this isn't a constant expr, just assume it fits and let relaxation
287    // handle it.
288    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
289    if (!CE)
290      return true;
291
292    // Otherwise, check the value is in a range that makes sense for this
293    // extension.
294    return isImmSExti64i8Value(CE->getValue());
295  }
296  bool isImmSExti64i32() const {
297    if (!isImm())
298      return false;
299
300    // If this isn't a constant expr, just assume it fits and let relaxation
301    // handle it.
302    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
303    if (!CE)
304      return true;
305
306    // Otherwise, check the value is in a range that makes sense for this
307    // extension.
308    return isImmSExti64i32Value(CE->getValue());
309  }
310
311  bool isMem() const { return Kind == Memory; }
312  bool isMem8() const {
313    return Kind == Memory && (!Mem.Size || Mem.Size == 8);
314  }
315  bool isMem16() const {
316    return Kind == Memory && (!Mem.Size || Mem.Size == 16);
317  }
318  bool isMem32() const {
319    return Kind == Memory && (!Mem.Size || Mem.Size == 32);
320  }
321  bool isMem64() const {
322    return Kind == Memory && (!Mem.Size || Mem.Size == 64);
323  }
324  bool isMem80() const {
325    return Kind == Memory && (!Mem.Size || Mem.Size == 80);
326  }
327  bool isMem128() const {
328    return Kind == Memory && (!Mem.Size || Mem.Size == 128);
329  }
330  bool isMem256() const {
331    return Kind == Memory && (!Mem.Size || Mem.Size == 256);
332  }
333
334  bool isAbsMem() const {
335    return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
336      !getMemIndexReg() && getMemScale() == 1;
337  }
338
339  bool isReg() const { return Kind == Register; }
340
341  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
342    // Add as immediates when possible.
343    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
344      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
345    else
346      Inst.addOperand(MCOperand::CreateExpr(Expr));
347  }
348
349  void addRegOperands(MCInst &Inst, unsigned N) const {
350    assert(N == 1 && "Invalid number of operands!");
351    Inst.addOperand(MCOperand::CreateReg(getReg()));
352  }
353
354  void addImmOperands(MCInst &Inst, unsigned N) const {
355    assert(N == 1 && "Invalid number of operands!");
356    addExpr(Inst, getImm());
357  }
358
359  void addMem8Operands(MCInst &Inst, unsigned N) const {
360    addMemOperands(Inst, N);
361  }
362  void addMem16Operands(MCInst &Inst, unsigned N) const {
363    addMemOperands(Inst, N);
364  }
365  void addMem32Operands(MCInst &Inst, unsigned N) const {
366    addMemOperands(Inst, N);
367  }
368  void addMem64Operands(MCInst &Inst, unsigned N) const {
369    addMemOperands(Inst, N);
370  }
371  void addMem80Operands(MCInst &Inst, unsigned N) const {
372    addMemOperands(Inst, N);
373  }
374  void addMem128Operands(MCInst &Inst, unsigned N) const {
375    addMemOperands(Inst, N);
376  }
377  void addMem256Operands(MCInst &Inst, unsigned N) const {
378    addMemOperands(Inst, N);
379  }
380
381  void addMemOperands(MCInst &Inst, unsigned N) const {
382    assert((N == 5) && "Invalid number of operands!");
383    Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
384    Inst.addOperand(MCOperand::CreateImm(getMemScale()));
385    Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
386    addExpr(Inst, getMemDisp());
387    Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
388  }
389
390  void addAbsMemOperands(MCInst &Inst, unsigned N) const {
391    assert((N == 1) && "Invalid number of operands!");
392    // Add as immediates when possible.
393    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
394      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
395    else
396      Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
397  }
398
399  static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
400    SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size() - 1);
401    X86Operand *Res = new X86Operand(Token, Loc, EndLoc);
402    Res->Tok.Data = Str.data();
403    Res->Tok.Length = Str.size();
404    return Res;
405  }
406
407  static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
408    X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
409    Res->Reg.RegNo = RegNo;
410    return Res;
411  }
412
413  static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
414    X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
415    Res->Imm.Val = Val;
416    return Res;
417  }
418
419  /// Create an absolute memory operand.
420  static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
421                               SMLoc EndLoc, unsigned Size = 0) {
422    X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
423    Res->Mem.SegReg   = 0;
424    Res->Mem.Disp     = Disp;
425    Res->Mem.BaseReg  = 0;
426    Res->Mem.IndexReg = 0;
427    Res->Mem.Scale    = 1;
428    Res->Mem.Size     = Size;
429    return Res;
430  }
431
432  /// Create a generalized memory operand.
433  static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
434                               unsigned BaseReg, unsigned IndexReg,
435                               unsigned Scale, SMLoc StartLoc, SMLoc EndLoc,
436                               unsigned Size = 0) {
437    // We should never just have a displacement, that should be parsed as an
438    // absolute memory operand.
439    assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
440
441    // The scale should always be one of {1,2,4,8}.
442    assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
443           "Invalid scale!");
444    X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
445    Res->Mem.SegReg   = SegReg;
446    Res->Mem.Disp     = Disp;
447    Res->Mem.BaseReg  = BaseReg;
448    Res->Mem.IndexReg = IndexReg;
449    Res->Mem.Scale    = Scale;
450    Res->Mem.Size     = Size;
451    return Res;
452  }
453};
454
455} // end anonymous namespace.
456
457bool X86AsmParser::isSrcOp(X86Operand &Op) {
458  unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI;
459
460  return (Op.isMem() &&
461    (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::DS) &&
462    isa<MCConstantExpr>(Op.Mem.Disp) &&
463    cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
464    Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
465}
466
467bool X86AsmParser::isDstOp(X86Operand &Op) {
468  unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI;
469
470  return Op.isMem() &&
471    (Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::ES) &&
472    isa<MCConstantExpr>(Op.Mem.Disp) &&
473    cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
474    Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
475}
476
477bool X86AsmParser::ParseRegister(unsigned &RegNo,
478                                 SMLoc &StartLoc, SMLoc &EndLoc) {
479  RegNo = 0;
480  if (!isParsingIntelSyntax()) {
481    const AsmToken &TokPercent = Parser.getTok();
482    assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
483    StartLoc = TokPercent.getLoc();
484    Parser.Lex(); // Eat percent token.
485  }
486
487  const AsmToken &Tok = Parser.getTok();
488  if (Tok.isNot(AsmToken::Identifier)) {
489    if (isParsingIntelSyntax()) return true;
490    return Error(StartLoc, "invalid register name",
491                 SMRange(StartLoc, Tok.getEndLoc()));
492  }
493
494  RegNo = MatchRegisterName(Tok.getString());
495
496  // If the match failed, try the register name as lowercase.
497  if (RegNo == 0)
498    RegNo = MatchRegisterName(Tok.getString().lower());
499
500  if (!is64BitMode()) {
501    // FIXME: This should be done using Requires<In32BitMode> and
502    // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
503    // checked.
504    // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
505    // REX prefix.
506    if (RegNo == X86::RIZ ||
507        X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
508        X86II::isX86_64NonExtLowByteReg(RegNo) ||
509        X86II::isX86_64ExtendedReg(RegNo))
510      return Error(StartLoc, "register %"
511                   + Tok.getString() + " is only available in 64-bit mode",
512                   SMRange(StartLoc, Tok.getEndLoc()));
513  }
514
515  // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
516  if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
517    RegNo = X86::ST0;
518    EndLoc = Tok.getLoc();
519    Parser.Lex(); // Eat 'st'
520
521    // Check to see if we have '(4)' after %st.
522    if (getLexer().isNot(AsmToken::LParen))
523      return false;
524    // Lex the paren.
525    getParser().Lex();
526
527    const AsmToken &IntTok = Parser.getTok();
528    if (IntTok.isNot(AsmToken::Integer))
529      return Error(IntTok.getLoc(), "expected stack index");
530    switch (IntTok.getIntVal()) {
531    case 0: RegNo = X86::ST0; break;
532    case 1: RegNo = X86::ST1; break;
533    case 2: RegNo = X86::ST2; break;
534    case 3: RegNo = X86::ST3; break;
535    case 4: RegNo = X86::ST4; break;
536    case 5: RegNo = X86::ST5; break;
537    case 6: RegNo = X86::ST6; break;
538    case 7: RegNo = X86::ST7; break;
539    default: return Error(IntTok.getLoc(), "invalid stack index");
540    }
541
542    if (getParser().Lex().isNot(AsmToken::RParen))
543      return Error(Parser.getTok().getLoc(), "expected ')'");
544
545    EndLoc = Tok.getLoc();
546    Parser.Lex(); // Eat ')'
547    return false;
548  }
549
550  // If this is "db[0-7]", match it as an alias
551  // for dr[0-7].
552  if (RegNo == 0 && Tok.getString().size() == 3 &&
553      Tok.getString().startswith("db")) {
554    switch (Tok.getString()[2]) {
555    case '0': RegNo = X86::DR0; break;
556    case '1': RegNo = X86::DR1; break;
557    case '2': RegNo = X86::DR2; break;
558    case '3': RegNo = X86::DR3; break;
559    case '4': RegNo = X86::DR4; break;
560    case '5': RegNo = X86::DR5; break;
561    case '6': RegNo = X86::DR6; break;
562    case '7': RegNo = X86::DR7; break;
563    }
564
565    if (RegNo != 0) {
566      EndLoc = Tok.getLoc();
567      Parser.Lex(); // Eat it.
568      return false;
569    }
570  }
571
572  if (RegNo == 0) {
573    if (isParsingIntelSyntax()) return true;
574    return Error(StartLoc, "invalid register name",
575                 SMRange(StartLoc, Tok.getEndLoc()));
576  }
577
578  EndLoc = Tok.getEndLoc();
579  Parser.Lex(); // Eat identifier token.
580  return false;
581}
582
583X86Operand *X86AsmParser::ParseOperand() {
584  if (isParsingIntelSyntax())
585    return ParseIntelOperand();
586  return ParseATTOperand();
587}
588
589/// getIntelMemOperandSize - Return intel memory operand size.
590static unsigned getIntelMemOperandSize(StringRef OpStr) {
591  unsigned Size = 0;
592  if (OpStr == "BYTE") Size = 8;
593  if (OpStr == "WORD") Size = 16;
594  if (OpStr == "DWORD") Size = 32;
595  if (OpStr == "QWORD") Size = 64;
596  if (OpStr == "XWORD") Size = 80;
597  if (OpStr == "XMMWORD") Size = 128;
598  if (OpStr == "YMMWORD") Size = 256;
599  return Size;
600}
601
602X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
603                                                   unsigned Size) {
604  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
605  SMLoc Start = Parser.getTok().getLoc(), End;
606
607  const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
608  // Parse [ BaseReg + Scale*IndexReg + Disp ] or [ symbol ]
609
610  // Eat '['
611  if (getLexer().isNot(AsmToken::LBrac))
612    return ErrorOperand(Start, "Expected '[' token!");
613  Parser.Lex();
614
615  if (getLexer().is(AsmToken::Identifier)) {
616    // Parse BaseReg
617    if (ParseRegister(BaseReg, Start, End)) {
618      // Handle '[' 'symbol' ']'
619      if (getParser().ParseExpression(Disp, End)) return 0;
620      if (getLexer().isNot(AsmToken::RBrac))
621        return ErrorOperand(Start, "Expected ']' token!");
622      Parser.Lex();
623      return X86Operand::CreateMem(Disp, Start, End, Size);
624    }
625  } else if (getLexer().is(AsmToken::Integer)) {
626      int64_t Val = Parser.getTok().getIntVal();
627      Parser.Lex();
628      SMLoc Loc = Parser.getTok().getLoc();
629      if (getLexer().is(AsmToken::RBrac)) {
630        // Handle '[' number ']'
631        Parser.Lex();
632        const MCExpr *Disp = MCConstantExpr::Create(Val, getContext());
633        if (SegReg)
634          return X86Operand::CreateMem(SegReg, Disp, 0, 0, Scale,
635                                       Start, End, Size);
636        return X86Operand::CreateMem(Disp, Start, End, Size);
637      } else if (getLexer().is(AsmToken::Star)) {
638        // Handle '[' Scale*IndexReg ']'
639        Parser.Lex();
640        SMLoc IdxRegLoc = Parser.getTok().getLoc();
641	if (ParseRegister(IndexReg, IdxRegLoc, End))
642	  return ErrorOperand(IdxRegLoc, "Expected register");
643        Scale = Val;
644      } else
645        return ErrorOperand(Loc, "Unepxeted token");
646  }
647
648  if (getLexer().is(AsmToken::Plus) || getLexer().is(AsmToken::Minus)) {
649    bool isPlus = getLexer().is(AsmToken::Plus);
650    Parser.Lex();
651    SMLoc PlusLoc = Parser.getTok().getLoc();
652    if (getLexer().is(AsmToken::Integer)) {
653      int64_t Val = Parser.getTok().getIntVal();
654      Parser.Lex();
655      if (getLexer().is(AsmToken::Star)) {
656        Parser.Lex();
657        SMLoc IdxRegLoc = Parser.getTok().getLoc();
658	if (ParseRegister(IndexReg, IdxRegLoc, End))
659	  return ErrorOperand(IdxRegLoc, "Expected register");
660        Scale = Val;
661      } else if (getLexer().is(AsmToken::RBrac)) {
662        const MCExpr *ValExpr = MCConstantExpr::Create(Val, getContext());
663        Disp = isPlus ? ValExpr : MCConstantExpr::Create(0-Val, getContext());
664      } else
665        return ErrorOperand(PlusLoc, "unexpected token after +");
666    } else if (getLexer().is(AsmToken::Identifier)) {
667      // This could be an index register or a displacement expression.
668      End = Parser.getTok().getLoc();
669      if (!IndexReg)
670        ParseRegister(IndexReg, Start, End);
671      else if (getParser().ParseExpression(Disp, End)) return 0;
672    }
673  }
674
675  if (getLexer().isNot(AsmToken::RBrac))
676    if (getParser().ParseExpression(Disp, End)) return 0;
677
678  End = Parser.getTok().getLoc();
679  if (getLexer().isNot(AsmToken::RBrac))
680    return ErrorOperand(End, "expected ']' token!");
681  Parser.Lex();
682  End = Parser.getTok().getLoc();
683
684  // handle [-42]
685  if (!BaseReg && !IndexReg)
686    return X86Operand::CreateMem(Disp, Start, End, Size);
687
688  return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
689                               Start, End, Size);
690}
691
692/// ParseIntelMemOperand - Parse intel style memory operand.
693X86Operand *X86AsmParser::ParseIntelMemOperand() {
694  const AsmToken &Tok = Parser.getTok();
695  SMLoc Start = Parser.getTok().getLoc(), End;
696  unsigned SegReg = 0;
697
698  unsigned Size = getIntelMemOperandSize(Tok.getString());
699  if (Size) {
700    Parser.Lex();
701    assert (Tok.getString() == "PTR" && "Unexpected token!");
702    Parser.Lex();
703  }
704
705  if (getLexer().is(AsmToken::LBrac))
706    return ParseIntelBracExpression(SegReg, Size);
707
708  if (!ParseRegister(SegReg, Start, End)) {
709    // Handel SegReg : [ ... ]
710    if (getLexer().isNot(AsmToken::Colon))
711      return ErrorOperand(Start, "Expected ':' token!");
712    Parser.Lex(); // Eat :
713    if (getLexer().isNot(AsmToken::LBrac))
714      return ErrorOperand(Start, "Expected '[' token!");
715    return ParseIntelBracExpression(SegReg, Size);
716  }
717
718  const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
719  if (getParser().ParseExpression(Disp, End)) return 0;
720  return X86Operand::CreateMem(Disp, Start, End, Size);
721}
722
723X86Operand *X86AsmParser::ParseIntelOperand() {
724  SMLoc Start = Parser.getTok().getLoc(), End;
725
726  // immediate.
727  if (getLexer().is(AsmToken::Integer) || getLexer().is(AsmToken::Real) ||
728      getLexer().is(AsmToken::Minus)) {
729    const MCExpr *Val;
730    if (!getParser().ParseExpression(Val, End)) {
731      End = Parser.getTok().getLoc();
732      return X86Operand::CreateImm(Val, Start, End);
733    }
734  }
735
736  // register
737  unsigned RegNo = 0;
738  if (!ParseRegister(RegNo, Start, End)) {
739    End = Parser.getTok().getLoc();
740    return X86Operand::CreateReg(RegNo, Start, End);
741  }
742
743  // mem operand
744  return ParseIntelMemOperand();
745}
746
747X86Operand *X86AsmParser::ParseATTOperand() {
748  switch (getLexer().getKind()) {
749  default:
750    // Parse a memory operand with no segment register.
751    return ParseMemOperand(0, Parser.getTok().getLoc());
752  case AsmToken::Percent: {
753    // Read the register.
754    unsigned RegNo;
755    SMLoc Start, End;
756    if (ParseRegister(RegNo, Start, End)) return 0;
757    if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
758      Error(Start, "%eiz and %riz can only be used as index registers",
759            SMRange(Start, End));
760      return 0;
761    }
762
763    // If this is a segment register followed by a ':', then this is the start
764    // of a memory reference, otherwise this is a normal register reference.
765    if (getLexer().isNot(AsmToken::Colon))
766      return X86Operand::CreateReg(RegNo, Start, End);
767
768
769    getParser().Lex(); // Eat the colon.
770    return ParseMemOperand(RegNo, Start);
771  }
772  case AsmToken::Dollar: {
773    // $42 -> immediate.
774    SMLoc Start = Parser.getTok().getLoc(), End;
775    Parser.Lex();
776    const MCExpr *Val;
777    if (getParser().ParseExpression(Val, End))
778      return 0;
779    return X86Operand::CreateImm(Val, Start, End);
780  }
781  }
782}
783
784/// ParseMemOperand: segment: disp(basereg, indexreg, scale).  The '%ds:' prefix
785/// has already been parsed if present.
786X86Operand *X86AsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
787
788  // We have to disambiguate a parenthesized expression "(4+5)" from the start
789  // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)".  The
790  // only way to do this without lookahead is to eat the '(' and see what is
791  // after it.
792  const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
793  if (getLexer().isNot(AsmToken::LParen)) {
794    SMLoc ExprEnd;
795    if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
796
797    // After parsing the base expression we could either have a parenthesized
798    // memory address or not.  If not, return now.  If so, eat the (.
799    if (getLexer().isNot(AsmToken::LParen)) {
800      // Unless we have a segment register, treat this as an immediate.
801      if (SegReg == 0)
802        return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
803      return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
804    }
805
806    // Eat the '('.
807    Parser.Lex();
808  } else {
809    // Okay, we have a '('.  We don't know if this is an expression or not, but
810    // so we have to eat the ( to see beyond it.
811    SMLoc LParenLoc = Parser.getTok().getLoc();
812    Parser.Lex(); // Eat the '('.
813
814    if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
815      // Nothing to do here, fall into the code below with the '(' part of the
816      // memory operand consumed.
817    } else {
818      SMLoc ExprEnd;
819
820      // It must be an parenthesized expression, parse it now.
821      if (getParser().ParseParenExpression(Disp, ExprEnd))
822        return 0;
823
824      // After parsing the base expression we could either have a parenthesized
825      // memory address or not.  If not, return now.  If so, eat the (.
826      if (getLexer().isNot(AsmToken::LParen)) {
827        // Unless we have a segment register, treat this as an immediate.
828        if (SegReg == 0)
829          return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
830        return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
831      }
832
833      // Eat the '('.
834      Parser.Lex();
835    }
836  }
837
838  // If we reached here, then we just ate the ( of the memory operand.  Process
839  // the rest of the memory operand.
840  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
841  SMLoc IndexLoc;
842
843  if (getLexer().is(AsmToken::Percent)) {
844    SMLoc StartLoc, EndLoc;
845    if (ParseRegister(BaseReg, StartLoc, EndLoc)) return 0;
846    if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
847      Error(StartLoc, "eiz and riz can only be used as index registers",
848            SMRange(StartLoc, EndLoc));
849      return 0;
850    }
851  }
852
853  if (getLexer().is(AsmToken::Comma)) {
854    Parser.Lex(); // Eat the comma.
855    IndexLoc = Parser.getTok().getLoc();
856
857    // Following the comma we should have either an index register, or a scale
858    // value. We don't support the later form, but we want to parse it
859    // correctly.
860    //
861    // Not that even though it would be completely consistent to support syntax
862    // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
863    if (getLexer().is(AsmToken::Percent)) {
864      SMLoc L;
865      if (ParseRegister(IndexReg, L, L)) return 0;
866
867      if (getLexer().isNot(AsmToken::RParen)) {
868        // Parse the scale amount:
869        //  ::= ',' [scale-expression]
870        if (getLexer().isNot(AsmToken::Comma)) {
871          Error(Parser.getTok().getLoc(),
872                "expected comma in scale expression");
873          return 0;
874        }
875        Parser.Lex(); // Eat the comma.
876
877        if (getLexer().isNot(AsmToken::RParen)) {
878          SMLoc Loc = Parser.getTok().getLoc();
879
880          int64_t ScaleVal;
881          if (getParser().ParseAbsoluteExpression(ScaleVal)){
882            Error(Loc, "expected scale expression");
883            return 0;
884	  }
885
886          // Validate the scale amount.
887          if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
888            Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
889            return 0;
890          }
891          Scale = (unsigned)ScaleVal;
892        }
893      }
894    } else if (getLexer().isNot(AsmToken::RParen)) {
895      // A scale amount without an index is ignored.
896      // index.
897      SMLoc Loc = Parser.getTok().getLoc();
898
899      int64_t Value;
900      if (getParser().ParseAbsoluteExpression(Value))
901        return 0;
902
903      if (Value != 1)
904        Warning(Loc, "scale factor without index register is ignored");
905      Scale = 1;
906    }
907  }
908
909  // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
910  if (getLexer().isNot(AsmToken::RParen)) {
911    Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
912    return 0;
913  }
914  SMLoc MemEnd = Parser.getTok().getLoc();
915  Parser.Lex(); // Eat the ')'.
916
917  // If we have both a base register and an index register make sure they are
918  // both 64-bit or 32-bit registers.
919  if (BaseReg != 0 && IndexReg != 0) {
920    if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
921        !X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) &&
922        IndexReg != X86::RIZ) {
923      Error(IndexLoc, "index register is 32-bit, but base register is 64-bit");
924      return 0;
925    }
926    if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
927        !X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) &&
928        IndexReg != X86::EIZ){
929      Error(IndexLoc, "index register is 64-bit, but base register is 32-bit");
930      return 0;
931    }
932  }
933
934  return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
935                               MemStart, MemEnd);
936}
937
938bool X86AsmParser::
939ParseInstruction(StringRef Name, SMLoc NameLoc,
940                 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
941  StringRef PatchedName = Name;
942
943  // FIXME: Hack to recognize setneb as setne.
944  if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
945      PatchedName != "setb" && PatchedName != "setnb")
946    PatchedName = PatchedName.substr(0, Name.size()-1);
947
948  // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
949  const MCExpr *ExtraImmOp = 0;
950  if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
951      (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
952       PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
953    bool IsVCMP = PatchedName[0] == 'v';
954    unsigned SSECCIdx = IsVCMP ? 4 : 3;
955    unsigned SSEComparisonCode = StringSwitch<unsigned>(
956      PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
957      .Case("eq",       0x00)
958      .Case("lt",       0x01)
959      .Case("le",       0x02)
960      .Case("unord",    0x03)
961      .Case("neq",      0x04)
962      .Case("nlt",      0x05)
963      .Case("nle",      0x06)
964      .Case("ord",      0x07)
965      /* AVX only from here */
966      .Case("eq_uq",    0x08)
967      .Case("nge",      0x09)
968      .Case("ngt",      0x0A)
969      .Case("false",    0x0B)
970      .Case("neq_oq",   0x0C)
971      .Case("ge",       0x0D)
972      .Case("gt",       0x0E)
973      .Case("true",     0x0F)
974      .Case("eq_os",    0x10)
975      .Case("lt_oq",    0x11)
976      .Case("le_oq",    0x12)
977      .Case("unord_s",  0x13)
978      .Case("neq_us",   0x14)
979      .Case("nlt_uq",   0x15)
980      .Case("nle_uq",   0x16)
981      .Case("ord_s",    0x17)
982      .Case("eq_us",    0x18)
983      .Case("nge_uq",   0x19)
984      .Case("ngt_uq",   0x1A)
985      .Case("false_os", 0x1B)
986      .Case("neq_os",   0x1C)
987      .Case("ge_oq",    0x1D)
988      .Case("gt_oq",    0x1E)
989      .Case("true_us",  0x1F)
990      .Default(~0U);
991    if (SSEComparisonCode != ~0U && (IsVCMP || SSEComparisonCode < 8)) {
992      ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
993                                          getParser().getContext());
994      if (PatchedName.endswith("ss")) {
995        PatchedName = IsVCMP ? "vcmpss" : "cmpss";
996      } else if (PatchedName.endswith("sd")) {
997        PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
998      } else if (PatchedName.endswith("ps")) {
999        PatchedName = IsVCMP ? "vcmpps" : "cmpps";
1000      } else {
1001        assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
1002        PatchedName = IsVCMP ? "vcmppd" : "cmppd";
1003      }
1004    }
1005  }
1006
1007  Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
1008
1009  if (ExtraImmOp && !isParsingIntelSyntax())
1010    Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1011
1012  // Determine whether this is an instruction prefix.
1013  bool isPrefix =
1014    Name == "lock" || Name == "rep" ||
1015    Name == "repe" || Name == "repz" ||
1016    Name == "repne" || Name == "repnz" ||
1017    Name == "rex64" || Name == "data16";
1018
1019
1020  // This does the actual operand parsing.  Don't parse any more if we have a
1021  // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
1022  // just want to parse the "lock" as the first instruction and the "incl" as
1023  // the next one.
1024  if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
1025
1026    // Parse '*' modifier.
1027    if (getLexer().is(AsmToken::Star)) {
1028      SMLoc Loc = Parser.getTok().getLoc();
1029      Operands.push_back(X86Operand::CreateToken("*", Loc));
1030      Parser.Lex(); // Eat the star.
1031    }
1032
1033    // Read the first operand.
1034    if (X86Operand *Op = ParseOperand())
1035      Operands.push_back(Op);
1036    else {
1037      Parser.EatToEndOfStatement();
1038      return true;
1039    }
1040
1041    while (getLexer().is(AsmToken::Comma)) {
1042      Parser.Lex();  // Eat the comma.
1043
1044      // Parse and remember the operand.
1045      if (X86Operand *Op = ParseOperand())
1046        Operands.push_back(Op);
1047      else {
1048        Parser.EatToEndOfStatement();
1049        return true;
1050      }
1051    }
1052
1053    if (getLexer().isNot(AsmToken::EndOfStatement)) {
1054      SMLoc Loc = getLexer().getLoc();
1055      Parser.EatToEndOfStatement();
1056      return Error(Loc, "unexpected token in argument list");
1057    }
1058  }
1059
1060  if (getLexer().is(AsmToken::EndOfStatement))
1061    Parser.Lex(); // Consume the EndOfStatement
1062  else if (isPrefix && getLexer().is(AsmToken::Slash))
1063    Parser.Lex(); // Consume the prefix separator Slash
1064
1065  if (ExtraImmOp && isParsingIntelSyntax())
1066    Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1067
1068  // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
1069  // "outb %al, %dx".  Out doesn't take a memory form, but this is a widely
1070  // documented form in various unofficial manuals, so a lot of code uses it.
1071  if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
1072      Operands.size() == 3) {
1073    X86Operand &Op = *(X86Operand*)Operands.back();
1074    if (Op.isMem() && Op.Mem.SegReg == 0 &&
1075        isa<MCConstantExpr>(Op.Mem.Disp) &&
1076        cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1077        Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1078      SMLoc Loc = Op.getEndLoc();
1079      Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1080      delete &Op;
1081    }
1082  }
1083  // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
1084  if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
1085      Operands.size() == 3) {
1086    X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1087    if (Op.isMem() && Op.Mem.SegReg == 0 &&
1088        isa<MCConstantExpr>(Op.Mem.Disp) &&
1089        cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
1090        Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
1091      SMLoc Loc = Op.getEndLoc();
1092      Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
1093      delete &Op;
1094    }
1095  }
1096  // Transform "ins[bwl] %dx, %es:(%edi)" into "ins[bwl]"
1097  if (Name.startswith("ins") && Operands.size() == 3 &&
1098      (Name == "insb" || Name == "insw" || Name == "insl")) {
1099    X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1100    X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1101    if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
1102      Operands.pop_back();
1103      Operands.pop_back();
1104      delete &Op;
1105      delete &Op2;
1106    }
1107  }
1108
1109  // Transform "outs[bwl] %ds:(%esi), %dx" into "out[bwl]"
1110  if (Name.startswith("outs") && Operands.size() == 3 &&
1111      (Name == "outsb" || Name == "outsw" || Name == "outsl")) {
1112    X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1113    X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1114    if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
1115      Operands.pop_back();
1116      Operands.pop_back();
1117      delete &Op;
1118      delete &Op2;
1119    }
1120  }
1121
1122  // Transform "movs[bwl] %ds:(%esi), %es:(%edi)" into "movs[bwl]"
1123  if (Name.startswith("movs") && Operands.size() == 3 &&
1124      (Name == "movsb" || Name == "movsw" || Name == "movsl" ||
1125       (is64BitMode() && Name == "movsq"))) {
1126    X86Operand &Op = *(X86Operand*)Operands.begin()[1];
1127    X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
1128    if (isSrcOp(Op) && isDstOp(Op2)) {
1129      Operands.pop_back();
1130      Operands.pop_back();
1131      delete &Op;
1132      delete &Op2;
1133    }
1134  }
1135  // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]"
1136  if (Name.startswith("lods") && Operands.size() == 3 &&
1137      (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
1138       Name == "lodsl" || (is64BitMode() && Name == "lodsq"))) {
1139    X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1140    X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
1141    if (isSrcOp(*Op1) && Op2->isReg()) {
1142      const char *ins;
1143      unsigned reg = Op2->getReg();
1144      bool isLods = Name == "lods";
1145      if (reg == X86::AL && (isLods || Name == "lodsb"))
1146        ins = "lodsb";
1147      else if (reg == X86::AX && (isLods || Name == "lodsw"))
1148        ins = "lodsw";
1149      else if (reg == X86::EAX && (isLods || Name == "lodsl"))
1150        ins = "lodsl";
1151      else if (reg == X86::RAX && (isLods || Name == "lodsq"))
1152        ins = "lodsq";
1153      else
1154        ins = NULL;
1155      if (ins != NULL) {
1156        Operands.pop_back();
1157        Operands.pop_back();
1158        delete Op1;
1159        delete Op2;
1160        if (Name != ins)
1161          static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
1162      }
1163    }
1164  }
1165  // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"
1166  if (Name.startswith("stos") && Operands.size() == 3 &&
1167      (Name == "stos" || Name == "stosb" || Name == "stosw" ||
1168       Name == "stosl" || (is64BitMode() && Name == "stosq"))) {
1169    X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1170    X86Operand *Op2 = static_cast<X86Operand*>(Operands[2]);
1171    if (isDstOp(*Op2) && Op1->isReg()) {
1172      const char *ins;
1173      unsigned reg = Op1->getReg();
1174      bool isStos = Name == "stos";
1175      if (reg == X86::AL && (isStos || Name == "stosb"))
1176        ins = "stosb";
1177      else if (reg == X86::AX && (isStos || Name == "stosw"))
1178        ins = "stosw";
1179      else if (reg == X86::EAX && (isStos || Name == "stosl"))
1180        ins = "stosl";
1181      else if (reg == X86::RAX && (isStos || Name == "stosq"))
1182        ins = "stosq";
1183      else
1184        ins = NULL;
1185      if (ins != NULL) {
1186        Operands.pop_back();
1187        Operands.pop_back();
1188        delete Op1;
1189        delete Op2;
1190        if (Name != ins)
1191          static_cast<X86Operand*>(Operands[0])->setTokenValue(ins);
1192      }
1193    }
1194  }
1195
1196  // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>.  Canonicalize to
1197  // "shift <op>".
1198  if ((Name.startswith("shr") || Name.startswith("sar") ||
1199       Name.startswith("shl") || Name.startswith("sal") ||
1200       Name.startswith("rcl") || Name.startswith("rcr") ||
1201       Name.startswith("rol") || Name.startswith("ror")) &&
1202      Operands.size() == 3) {
1203    if (isParsingIntelSyntax()) {
1204      // Intel syntax
1205      X86Operand *Op1 = static_cast<X86Operand*>(Operands[2]);
1206      if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1207	  cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
1208	delete Operands[2];
1209	Operands.pop_back();
1210      }
1211    } else {
1212      X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1213      if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1214	  cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
1215	delete Operands[1];
1216	Operands.erase(Operands.begin() + 1);
1217      }
1218    }
1219  }
1220
1221  // Transforms "int $3" into "int3" as a size optimization.  We can't write an
1222  // instalias with an immediate operand yet.
1223  if (Name == "int" && Operands.size() == 2) {
1224    X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
1225    if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
1226        cast<MCConstantExpr>(Op1->getImm())->getValue() == 3) {
1227      delete Operands[1];
1228      Operands.erase(Operands.begin() + 1);
1229      static_cast<X86Operand*>(Operands[0])->setTokenValue("int3");
1230    }
1231  }
1232
1233  return false;
1234}
1235
1236bool X86AsmParser::
1237processInstruction(MCInst &Inst,
1238                   const SmallVectorImpl<MCParsedAsmOperand*> &Ops) {
1239  switch (Inst.getOpcode()) {
1240  default: return false;
1241  case X86::AND16i16: {
1242    if (!Inst.getOperand(0).isImm() ||
1243        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1244      return false;
1245
1246    MCInst TmpInst;
1247    TmpInst.setOpcode(X86::AND16ri8);
1248    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1249    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1250    TmpInst.addOperand(Inst.getOperand(0));
1251    Inst = TmpInst;
1252    return true;
1253  }
1254  case X86::AND32i32: {
1255    if (!Inst.getOperand(0).isImm() ||
1256        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1257      return false;
1258
1259    MCInst TmpInst;
1260    TmpInst.setOpcode(X86::AND32ri8);
1261    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1262    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1263    TmpInst.addOperand(Inst.getOperand(0));
1264    Inst = TmpInst;
1265    return true;
1266  }
1267  case X86::AND64i32: {
1268    if (!Inst.getOperand(0).isImm() ||
1269        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1270      return false;
1271
1272    MCInst TmpInst;
1273    TmpInst.setOpcode(X86::AND64ri8);
1274    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1275    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1276    TmpInst.addOperand(Inst.getOperand(0));
1277    Inst = TmpInst;
1278    return true;
1279  }
1280  case X86::XOR16i16: {
1281    if (!Inst.getOperand(0).isImm() ||
1282        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1283      return false;
1284
1285    MCInst TmpInst;
1286    TmpInst.setOpcode(X86::XOR16ri8);
1287    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1288    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1289    TmpInst.addOperand(Inst.getOperand(0));
1290    Inst = TmpInst;
1291    return true;
1292  }
1293  case X86::XOR32i32: {
1294    if (!Inst.getOperand(0).isImm() ||
1295        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1296      return false;
1297
1298    MCInst TmpInst;
1299    TmpInst.setOpcode(X86::XOR32ri8);
1300    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1301    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1302    TmpInst.addOperand(Inst.getOperand(0));
1303    Inst = TmpInst;
1304    return true;
1305  }
1306  case X86::XOR64i32: {
1307    if (!Inst.getOperand(0).isImm() ||
1308        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1309      return false;
1310
1311    MCInst TmpInst;
1312    TmpInst.setOpcode(X86::XOR64ri8);
1313    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1314    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1315    TmpInst.addOperand(Inst.getOperand(0));
1316    Inst = TmpInst;
1317    return true;
1318  }
1319  case X86::OR16i16: {
1320    if (!Inst.getOperand(0).isImm() ||
1321        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1322      return false;
1323
1324    MCInst TmpInst;
1325    TmpInst.setOpcode(X86::OR16ri8);
1326    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1327    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1328    TmpInst.addOperand(Inst.getOperand(0));
1329    Inst = TmpInst;
1330    return true;
1331  }
1332  case X86::OR32i32: {
1333    if (!Inst.getOperand(0).isImm() ||
1334        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1335      return false;
1336
1337    MCInst TmpInst;
1338    TmpInst.setOpcode(X86::OR32ri8);
1339    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1340    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1341    TmpInst.addOperand(Inst.getOperand(0));
1342    Inst = TmpInst;
1343    return true;
1344  }
1345  case X86::OR64i32: {
1346    if (!Inst.getOperand(0).isImm() ||
1347        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1348      return false;
1349
1350    MCInst TmpInst;
1351    TmpInst.setOpcode(X86::OR64ri8);
1352    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1353    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1354    TmpInst.addOperand(Inst.getOperand(0));
1355    Inst = TmpInst;
1356    return true;
1357  }
1358  case X86::CMP16i16: {
1359    if (!Inst.getOperand(0).isImm() ||
1360        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1361      return false;
1362
1363    MCInst TmpInst;
1364    TmpInst.setOpcode(X86::CMP16ri8);
1365    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1366    TmpInst.addOperand(Inst.getOperand(0));
1367    Inst = TmpInst;
1368    return true;
1369  }
1370  case X86::CMP32i32: {
1371    if (!Inst.getOperand(0).isImm() ||
1372        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1373      return false;
1374
1375    MCInst TmpInst;
1376    TmpInst.setOpcode(X86::CMP32ri8);
1377    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1378    TmpInst.addOperand(Inst.getOperand(0));
1379    Inst = TmpInst;
1380    return true;
1381  }
1382  case X86::CMP64i32: {
1383    if (!Inst.getOperand(0).isImm() ||
1384        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1385      return false;
1386
1387    MCInst TmpInst;
1388    TmpInst.setOpcode(X86::CMP64ri8);
1389    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1390    TmpInst.addOperand(Inst.getOperand(0));
1391    Inst = TmpInst;
1392    return true;
1393  }
1394  case X86::ADD16i16: {
1395    if (!Inst.getOperand(0).isImm() ||
1396        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1397      return false;
1398
1399    MCInst TmpInst;
1400    TmpInst.setOpcode(X86::ADD16ri8);
1401    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1402    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1403    TmpInst.addOperand(Inst.getOperand(0));
1404    Inst = TmpInst;
1405    return true;
1406  }
1407  case X86::ADD32i32: {
1408    if (!Inst.getOperand(0).isImm() ||
1409        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1410      return false;
1411
1412    MCInst TmpInst;
1413    TmpInst.setOpcode(X86::ADD32ri8);
1414    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1415    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1416    TmpInst.addOperand(Inst.getOperand(0));
1417    Inst = TmpInst;
1418    return true;
1419  }
1420  case X86::ADD64i32: {
1421    if (!Inst.getOperand(0).isImm() ||
1422        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1423      return false;
1424
1425    MCInst TmpInst;
1426    TmpInst.setOpcode(X86::ADD64ri8);
1427    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1428    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1429    TmpInst.addOperand(Inst.getOperand(0));
1430    Inst = TmpInst;
1431    return true;
1432  }
1433  case X86::SUB16i16: {
1434    if (!Inst.getOperand(0).isImm() ||
1435        !isImmSExti16i8Value(Inst.getOperand(0).getImm()))
1436      return false;
1437
1438    MCInst TmpInst;
1439    TmpInst.setOpcode(X86::SUB16ri8);
1440    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1441    TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
1442    TmpInst.addOperand(Inst.getOperand(0));
1443    Inst = TmpInst;
1444    return true;
1445  }
1446  case X86::SUB32i32: {
1447    if (!Inst.getOperand(0).isImm() ||
1448        !isImmSExti32i8Value(Inst.getOperand(0).getImm()))
1449      return false;
1450
1451    MCInst TmpInst;
1452    TmpInst.setOpcode(X86::SUB32ri8);
1453    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1454    TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
1455    TmpInst.addOperand(Inst.getOperand(0));
1456    Inst = TmpInst;
1457    return true;
1458  }
1459  case X86::SUB64i32: {
1460    if (!Inst.getOperand(0).isImm() ||
1461        !isImmSExti64i8Value(Inst.getOperand(0).getImm()))
1462      return false;
1463
1464    MCInst TmpInst;
1465    TmpInst.setOpcode(X86::SUB64ri8);
1466    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1467    TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
1468    TmpInst.addOperand(Inst.getOperand(0));
1469    Inst = TmpInst;
1470    return true;
1471  }
1472  }
1473}
1474
1475bool X86AsmParser::
1476MatchAndEmitInstruction(SMLoc IDLoc,
1477                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1478                        MCStreamer &Out) {
1479  assert(!Operands.empty() && "Unexpect empty operand list!");
1480  X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
1481  assert(Op->isToken() && "Leading operand should always be a mnemonic!");
1482
1483  // First, handle aliases that expand to multiple instructions.
1484  // FIXME: This should be replaced with a real .td file alias mechanism.
1485  // Also, MatchInstructionImpl should do actually *do* the EmitInstruction
1486  // call.
1487  if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
1488      Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
1489      Op->getToken() == "finit" || Op->getToken() == "fsave" ||
1490      Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
1491    MCInst Inst;
1492    Inst.setOpcode(X86::WAIT);
1493    Inst.setLoc(IDLoc);
1494    Out.EmitInstruction(Inst);
1495
1496    const char *Repl =
1497      StringSwitch<const char*>(Op->getToken())
1498        .Case("finit",  "fninit")
1499        .Case("fsave",  "fnsave")
1500        .Case("fstcw",  "fnstcw")
1501        .Case("fstcww",  "fnstcw")
1502        .Case("fstenv", "fnstenv")
1503        .Case("fstsw",  "fnstsw")
1504        .Case("fstsww", "fnstsw")
1505        .Case("fclex",  "fnclex")
1506        .Default(0);
1507    assert(Repl && "Unknown wait-prefixed instruction");
1508    delete Operands[0];
1509    Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
1510  }
1511
1512  bool WasOriginallyInvalidOperand = false;
1513  unsigned OrigErrorInfo;
1514  MCInst Inst;
1515
1516  // First, try a direct match.
1517  switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo,
1518                               isParsingIntelSyntax())) {
1519  default: break;
1520  case Match_Success:
1521    // Some instructions need post-processing to, for example, tweak which
1522    // encoding is selected. Loop on it while changes happen so the
1523    // individual transformations can chain off each other.
1524    while (processInstruction(Inst, Operands))
1525      ;
1526
1527    Inst.setLoc(IDLoc);
1528    Out.EmitInstruction(Inst);
1529    return false;
1530  case Match_MissingFeature:
1531    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1532    return true;
1533  case Match_ConversionFail:
1534    return Error(IDLoc, "unable to convert operands to instruction");
1535  case Match_InvalidOperand:
1536    WasOriginallyInvalidOperand = true;
1537    break;
1538  case Match_MnemonicFail:
1539    break;
1540  }
1541
1542  // FIXME: Ideally, we would only attempt suffix matches for things which are
1543  // valid prefixes, and we could just infer the right unambiguous
1544  // type. However, that requires substantially more matcher support than the
1545  // following hack.
1546
1547  // Change the operand to point to a temporary token.
1548  StringRef Base = Op->getToken();
1549  SmallString<16> Tmp;
1550  Tmp += Base;
1551  Tmp += ' ';
1552  Op->setTokenValue(Tmp.str());
1553
1554  // If this instruction starts with an 'f', then it is a floating point stack
1555  // instruction.  These come in up to three forms for 32-bit, 64-bit, and
1556  // 80-bit floating point, which use the suffixes s,l,t respectively.
1557  //
1558  // Otherwise, we assume that this may be an integer instruction, which comes
1559  // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
1560  const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
1561
1562  // Check for the various suffix matches.
1563  Tmp[Base.size()] = Suffixes[0];
1564  unsigned ErrorInfoIgnore;
1565  unsigned Match1, Match2, Match3, Match4;
1566
1567  Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
1568  Tmp[Base.size()] = Suffixes[1];
1569  Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
1570  Tmp[Base.size()] = Suffixes[2];
1571  Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
1572  Tmp[Base.size()] = Suffixes[3];
1573  Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
1574
1575  // Restore the old token.
1576  Op->setTokenValue(Base);
1577
1578  // If exactly one matched, then we treat that as a successful match (and the
1579  // instruction will already have been filled in correctly, since the failing
1580  // matches won't have modified it).
1581  unsigned NumSuccessfulMatches =
1582    (Match1 == Match_Success) + (Match2 == Match_Success) +
1583    (Match3 == Match_Success) + (Match4 == Match_Success);
1584  if (NumSuccessfulMatches == 1) {
1585    Inst.setLoc(IDLoc);
1586    Out.EmitInstruction(Inst);
1587    return false;
1588  }
1589
1590  // Otherwise, the match failed, try to produce a decent error message.
1591
1592  // If we had multiple suffix matches, then identify this as an ambiguous
1593  // match.
1594  if (NumSuccessfulMatches > 1) {
1595    char MatchChars[4];
1596    unsigned NumMatches = 0;
1597    if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
1598    if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
1599    if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
1600    if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
1601
1602    SmallString<126> Msg;
1603    raw_svector_ostream OS(Msg);
1604    OS << "ambiguous instructions require an explicit suffix (could be ";
1605    for (unsigned i = 0; i != NumMatches; ++i) {
1606      if (i != 0)
1607        OS << ", ";
1608      if (i + 1 == NumMatches)
1609        OS << "or ";
1610      OS << "'" << Base << MatchChars[i] << "'";
1611    }
1612    OS << ")";
1613    Error(IDLoc, OS.str());
1614    return true;
1615  }
1616
1617  // Okay, we know that none of the variants matched successfully.
1618
1619  // If all of the instructions reported an invalid mnemonic, then the original
1620  // mnemonic was invalid.
1621  if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
1622      (Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
1623    if (!WasOriginallyInvalidOperand) {
1624      return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
1625                   Op->getLocRange());
1626    }
1627
1628    // Recover location info for the operand if we know which was the problem.
1629    if (OrigErrorInfo != ~0U) {
1630      if (OrigErrorInfo >= Operands.size())
1631        return Error(IDLoc, "too few operands for instruction");
1632
1633      X86Operand *Operand = (X86Operand*)Operands[OrigErrorInfo];
1634      if (Operand->getStartLoc().isValid()) {
1635        SMRange OperandRange = Operand->getLocRange();
1636        return Error(Operand->getStartLoc(), "invalid operand for instruction",
1637                     OperandRange);
1638      }
1639    }
1640
1641    return Error(IDLoc, "invalid operand for instruction");
1642  }
1643
1644  // If one instruction matched with a missing feature, report this as a
1645  // missing feature.
1646  if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
1647      (Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
1648    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1649    return true;
1650  }
1651
1652  // If one instruction matched with an invalid operand, report this as an
1653  // operand failure.
1654  if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
1655      (Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
1656    Error(IDLoc, "invalid operand for instruction");
1657    return true;
1658  }
1659
1660  // If all of these were an outright failure, report it in a useless way.
1661  Error(IDLoc, "unknown use of instruction mnemonic without a size suffix");
1662  return true;
1663}
1664
1665
1666bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
1667  StringRef IDVal = DirectiveID.getIdentifier();
1668  if (IDVal == ".word")
1669    return ParseDirectiveWord(2, DirectiveID.getLoc());
1670  else if (IDVal.startswith(".code"))
1671    return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
1672  else if (IDVal.startswith(".intel_syntax")) {
1673    getParser().setAssemblerDialect(1);
1674    if (getLexer().isNot(AsmToken::EndOfStatement)) {
1675      if(Parser.getTok().getString() == "noprefix") {
1676	// FIXME : Handle noprefix
1677	Parser.Lex();
1678      } else
1679	return true;
1680    }
1681    return false;
1682  }
1683  return true;
1684}
1685
1686/// ParseDirectiveWord
1687///  ::= .word [ expression (, expression)* ]
1688bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1689  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1690    for (;;) {
1691      const MCExpr *Value;
1692      if (getParser().ParseExpression(Value))
1693        return true;
1694
1695      getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
1696
1697      if (getLexer().is(AsmToken::EndOfStatement))
1698        break;
1699
1700      // FIXME: Improve diagnostic.
1701      if (getLexer().isNot(AsmToken::Comma))
1702        return Error(L, "unexpected token in directive");
1703      Parser.Lex();
1704    }
1705  }
1706
1707  Parser.Lex();
1708  return false;
1709}
1710
1711/// ParseDirectiveCode
1712///  ::= .code32 | .code64
1713bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
1714  if (IDVal == ".code32") {
1715    Parser.Lex();
1716    if (is64BitMode()) {
1717      SwitchMode();
1718      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
1719    }
1720  } else if (IDVal == ".code64") {
1721    Parser.Lex();
1722    if (!is64BitMode()) {
1723      SwitchMode();
1724      getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
1725    }
1726  } else {
1727    return Error(L, "unexpected directive " + IDVal);
1728  }
1729
1730  return false;
1731}
1732
1733
1734extern "C" void LLVMInitializeX86AsmLexer();
1735
1736// Force static initialization.
1737extern "C" void LLVMInitializeX86AsmParser() {
1738  RegisterMCAsmParser<X86AsmParser> X(TheX86_32Target);
1739  RegisterMCAsmParser<X86AsmParser> Y(TheX86_64Target);
1740  LLVMInitializeX86AsmLexer();
1741}
1742
1743#define GET_REGISTER_MATCHER
1744#define GET_MATCHER_IMPLEMENTATION
1745#include "X86GenAsmMatcher.inc"
1746