X86AsmParser.cpp revision 205218 
1//===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "llvm/Target/TargetAsmParser.h"
11#include "X86.h"
12#include "llvm/ADT/SmallVector.h"
13#include "llvm/ADT/StringSwitch.h"
14#include "llvm/ADT/Twine.h"
15#include "llvm/MC/MCStreamer.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/MC/MCInst.h"
18#include "llvm/MC/MCParser/MCAsmLexer.h"
19#include "llvm/MC/MCParser/MCAsmParser.h"
20#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21#include "llvm/Support/SourceMgr.h"
22#include "llvm/Target/TargetRegistry.h"
23#include "llvm/Target/TargetAsmParser.h"
24using namespace llvm;
25
26namespace {
27struct X86Operand;
28
29class X86ATTAsmParser : public TargetAsmParser {
30  MCAsmParser &Parser;
31
32private:
33  MCAsmParser &getParser() const { return Parser; }
34
35  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
36
37  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
38
39  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
40
41  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
42
43  X86Operand *ParseOperand();
44  X86Operand *ParseMemOperand();
45
46  bool ParseDirectiveWord(unsigned Size, SMLoc L);
47
48  /// @name Auto-generated Match Functions
49  /// {
50
51  bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
52                        MCInst &Inst);
53
54  /// }
55
56public:
57  X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
58    : TargetAsmParser(T), Parser(_Parser) {}
59
60  virtual bool ParseInstruction(const StringRef &Name, SMLoc NameLoc,
61                                SmallVectorImpl<MCParsedAsmOperand*> &Operands);
62
63  virtual bool ParseDirective(AsmToken DirectiveID);
64};
65
66} // end anonymous namespace
67
68/// @name Auto-generated Match Functions
69/// {
70
71static unsigned MatchRegisterName(StringRef Name);
72
73/// }
74
75namespace {
76
77/// X86Operand - Instances of this class represent a parsed X86 machine
78/// instruction.
79struct X86Operand : public MCParsedAsmOperand {
80  enum KindTy {
81    Token,
82    Register,
83    Immediate,
84    Memory
85  } Kind;
86
87  SMLoc StartLoc, EndLoc;
88
89  union {
90    struct {
91      const char *Data;
92      unsigned Length;
93    } Tok;
94
95    struct {
96      unsigned RegNo;
97    } Reg;
98
99    struct {
100      const MCExpr *Val;
101    } Imm;
102
103    struct {
104      unsigned SegReg;
105      const MCExpr *Disp;
106      unsigned BaseReg;
107      unsigned IndexReg;
108      unsigned Scale;
109    } Mem;
110  };
111
112  X86Operand(KindTy K, SMLoc Start, SMLoc End)
113    : Kind(K), StartLoc(Start), EndLoc(End) {}
114
115  /// getStartLoc - Get the location of the first token of this operand.
116  SMLoc getStartLoc() const { return StartLoc; }
117  /// getEndLoc - Get the location of the last token of this operand.
118  SMLoc getEndLoc() const { return EndLoc; }
119
120  StringRef getToken() const {
121    assert(Kind == Token && "Invalid access!");
122    return StringRef(Tok.Data, Tok.Length);
123  }
124
125  unsigned getReg() const {
126    assert(Kind == Register && "Invalid access!");
127    return Reg.RegNo;
128  }
129
130  const MCExpr *getImm() const {
131    assert(Kind == Immediate && "Invalid access!");
132    return Imm.Val;
133  }
134
135  const MCExpr *getMemDisp() const {
136    assert(Kind == Memory && "Invalid access!");
137    return Mem.Disp;
138  }
139  unsigned getMemSegReg() const {
140    assert(Kind == Memory && "Invalid access!");
141    return Mem.SegReg;
142  }
143  unsigned getMemBaseReg() const {
144    assert(Kind == Memory && "Invalid access!");
145    return Mem.BaseReg;
146  }
147  unsigned getMemIndexReg() const {
148    assert(Kind == Memory && "Invalid access!");
149    return Mem.IndexReg;
150  }
151  unsigned getMemScale() const {
152    assert(Kind == Memory && "Invalid access!");
153    return Mem.Scale;
154  }
155
156  bool isToken() const {return Kind == Token; }
157
158  bool isImm() const { return Kind == Immediate; }
159
160  bool isImmSExt8() const {
161    // Accept immediates which fit in 8 bits when sign extended, and
162    // non-absolute immediates.
163    if (!isImm())
164      return false;
165
166    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
167      int64_t Value = CE->getValue();
168      return Value == (int64_t) (int8_t) Value;
169    }
170
171    return true;
172  }
173
174  bool isMem() const { return Kind == Memory; }
175
176  bool isAbsMem() const {
177    return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
178      !getMemIndexReg() && getMemScale() == 1;
179  }
180
181  bool isNoSegMem() const {
182    return Kind == Memory && !getMemSegReg();
183  }
184
185  bool isReg() const { return Kind == Register; }
186
187  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
188    // Add as immediates when possible.
189    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
190      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
191    else
192      Inst.addOperand(MCOperand::CreateExpr(Expr));
193  }
194
195  void addRegOperands(MCInst &Inst, unsigned N) const {
196    assert(N == 1 && "Invalid number of operands!");
197    Inst.addOperand(MCOperand::CreateReg(getReg()));
198  }
199
200  void addImmOperands(MCInst &Inst, unsigned N) const {
201    assert(N == 1 && "Invalid number of operands!");
202    addExpr(Inst, getImm());
203  }
204
205  void addImmSExt8Operands(MCInst &Inst, unsigned N) const {
206    // FIXME: Support user customization of the render method.
207    assert(N == 1 && "Invalid number of operands!");
208    addExpr(Inst, getImm());
209  }
210
211  void addMemOperands(MCInst &Inst, unsigned N) const {
212    assert((N == 5) && "Invalid number of operands!");
213    Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
214    Inst.addOperand(MCOperand::CreateImm(getMemScale()));
215    Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
216    addExpr(Inst, getMemDisp());
217    Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
218  }
219
220  void addAbsMemOperands(MCInst &Inst, unsigned N) const {
221    assert((N == 1) && "Invalid number of operands!");
222    Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
223  }
224
225  void addNoSegMemOperands(MCInst &Inst, unsigned N) const {
226    assert((N == 4) && "Invalid number of operands!");
227    Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
228    Inst.addOperand(MCOperand::CreateImm(getMemScale()));
229    Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
230    addExpr(Inst, getMemDisp());
231  }
232
233  static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
234    X86Operand *Res = new X86Operand(Token, Loc, Loc);
235    Res->Tok.Data = Str.data();
236    Res->Tok.Length = Str.size();
237    return Res;
238  }
239
240  static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
241    X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
242    Res->Reg.RegNo = RegNo;
243    return Res;
244  }
245
246  static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
247    X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
248    Res->Imm.Val = Val;
249    return Res;
250  }
251
252  /// Create an absolute memory operand.
253  static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
254                               SMLoc EndLoc) {
255    X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
256    Res->Mem.SegReg   = 0;
257    Res->Mem.Disp     = Disp;
258    Res->Mem.BaseReg  = 0;
259    Res->Mem.IndexReg = 0;
260    Res->Mem.Scale    = 1;
261    return Res;
262  }
263
264  /// Create a generalized memory operand.
265  static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
266                               unsigned BaseReg, unsigned IndexReg,
267                               unsigned Scale, SMLoc StartLoc, SMLoc EndLoc) {
268    // We should never just have a displacement, that should be parsed as an
269    // absolute memory operand.
270    assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
271
272    // The scale should always be one of {1,2,4,8}.
273    assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
274           "Invalid scale!");
275    X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
276    Res->Mem.SegReg   = SegReg;
277    Res->Mem.Disp     = Disp;
278    Res->Mem.BaseReg  = BaseReg;
279    Res->Mem.IndexReg = IndexReg;
280    Res->Mem.Scale    = Scale;
281    return Res;
282  }
283};
284
285} // end anonymous namespace.
286
287
288bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
289                                    SMLoc &StartLoc, SMLoc &EndLoc) {
290  RegNo = 0;
291  const AsmToken &TokPercent = Parser.getTok();
292  assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
293  StartLoc = TokPercent.getLoc();
294  Parser.Lex(); // Eat percent token.
295
296  const AsmToken &Tok = Parser.getTok();
297  if (Tok.isNot(AsmToken::Identifier))
298    return Error(Tok.getLoc(), "invalid register name");
299
300  // FIXME: Validate register for the current architecture; we have to do
301  // validation later, so maybe there is no need for this here.
302  RegNo = MatchRegisterName(Tok.getString());
303
304  // Parse %st(1) and "%st" as "%st(0)"
305  if (RegNo == 0 && Tok.getString() == "st") {
306    RegNo = X86::ST0;
307    EndLoc = Tok.getLoc();
308    Parser.Lex(); // Eat 'st'
309
310    // Check to see if we have '(4)' after %st.
311    if (getLexer().isNot(AsmToken::LParen))
312      return false;
313    // Lex the paren.
314    getParser().Lex();
315
316    const AsmToken &IntTok = Parser.getTok();
317    if (IntTok.isNot(AsmToken::Integer))
318      return Error(IntTok.getLoc(), "expected stack index");
319    switch (IntTok.getIntVal()) {
320    case 0: RegNo = X86::ST0; break;
321    case 1: RegNo = X86::ST1; break;
322    case 2: RegNo = X86::ST2; break;
323    case 3: RegNo = X86::ST3; break;
324    case 4: RegNo = X86::ST4; break;
325    case 5: RegNo = X86::ST5; break;
326    case 6: RegNo = X86::ST6; break;
327    case 7: RegNo = X86::ST7; break;
328    default: return Error(IntTok.getLoc(), "invalid stack index");
329    }
330
331    if (getParser().Lex().isNot(AsmToken::RParen))
332      return Error(Parser.getTok().getLoc(), "expected ')'");
333
334    EndLoc = Tok.getLoc();
335    Parser.Lex(); // Eat ')'
336    return false;
337  }
338
339  if (RegNo == 0)
340    return Error(Tok.getLoc(), "invalid register name");
341
342  EndLoc = Tok.getLoc();
343  Parser.Lex(); // Eat identifier token.
344  return false;
345}
346
347X86Operand *X86ATTAsmParser::ParseOperand() {
348  switch (getLexer().getKind()) {
349  default:
350    return ParseMemOperand();
351  case AsmToken::Percent: {
352    // FIXME: if a segment register, this could either be just the seg reg, or
353    // the start of a memory operand.
354    unsigned RegNo;
355    SMLoc Start, End;
356    if (ParseRegister(RegNo, Start, End)) return 0;
357    return X86Operand::CreateReg(RegNo, Start, End);
358  }
359  case AsmToken::Dollar: {
360    // $42 -> immediate.
361    SMLoc Start = Parser.getTok().getLoc(), End;
362    Parser.Lex();
363    const MCExpr *Val;
364    if (getParser().ParseExpression(Val, End))
365      return 0;
366    return X86Operand::CreateImm(Val, Start, End);
367  }
368  }
369}
370
371/// ParseMemOperand: segment: disp(basereg, indexreg, scale)
372X86Operand *X86ATTAsmParser::ParseMemOperand() {
373  SMLoc MemStart = Parser.getTok().getLoc();
374
375  // FIXME: If SegReg ':'  (e.g. %gs:), eat and remember.
376  unsigned SegReg = 0;
377
378  // We have to disambiguate a parenthesized expression "(4+5)" from the start
379  // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)".  The
380  // only way to do this without lookahead is to eat the '(' and see what is
381  // after it.
382  const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
383  if (getLexer().isNot(AsmToken::LParen)) {
384    SMLoc ExprEnd;
385    if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
386
387    // After parsing the base expression we could either have a parenthesized
388    // memory address or not.  If not, return now.  If so, eat the (.
389    if (getLexer().isNot(AsmToken::LParen)) {
390      // Unless we have a segment register, treat this as an immediate.
391      if (SegReg == 0)
392        return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
393      return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
394    }
395
396    // Eat the '('.
397    Parser.Lex();
398  } else {
399    // Okay, we have a '('.  We don't know if this is an expression or not, but
400    // so we have to eat the ( to see beyond it.
401    SMLoc LParenLoc = Parser.getTok().getLoc();
402    Parser.Lex(); // Eat the '('.
403
404    if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
405      // Nothing to do here, fall into the code below with the '(' part of the
406      // memory operand consumed.
407    } else {
408      SMLoc ExprEnd;
409
410      // It must be an parenthesized expression, parse it now.
411      if (getParser().ParseParenExpression(Disp, ExprEnd))
412        return 0;
413
414      // After parsing the base expression we could either have a parenthesized
415      // memory address or not.  If not, return now.  If so, eat the (.
416      if (getLexer().isNot(AsmToken::LParen)) {
417        // Unless we have a segment register, treat this as an immediate.
418        if (SegReg == 0)
419          return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
420        return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
421      }
422
423      // Eat the '('.
424      Parser.Lex();
425    }
426  }
427
428  // If we reached here, then we just ate the ( of the memory operand.  Process
429  // the rest of the memory operand.
430  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
431
432  if (getLexer().is(AsmToken::Percent)) {
433    SMLoc L;
434    if (ParseRegister(BaseReg, L, L)) return 0;
435  }
436
437  if (getLexer().is(AsmToken::Comma)) {
438    Parser.Lex(); // Eat the comma.
439
440    // Following the comma we should have either an index register, or a scale
441    // value. We don't support the later form, but we want to parse it
442    // correctly.
443    //
444    // Not that even though it would be completely consistent to support syntax
445    // like "1(%eax,,1)", the assembler doesn't.
446    if (getLexer().is(AsmToken::Percent)) {
447      SMLoc L;
448      if (ParseRegister(IndexReg, L, L)) return 0;
449
450      if (getLexer().isNot(AsmToken::RParen)) {
451        // Parse the scale amount:
452        //  ::= ',' [scale-expression]
453        if (getLexer().isNot(AsmToken::Comma)) {
454          Error(Parser.getTok().getLoc(),
455                "expected comma in scale expression");
456          return 0;
457        }
458        Parser.Lex(); // Eat the comma.
459
460        if (getLexer().isNot(AsmToken::RParen)) {
461          SMLoc Loc = Parser.getTok().getLoc();
462
463          int64_t ScaleVal;
464          if (getParser().ParseAbsoluteExpression(ScaleVal))
465            return 0;
466
467          // Validate the scale amount.
468          if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
469            Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
470            return 0;
471          }
472          Scale = (unsigned)ScaleVal;
473        }
474      }
475    } else if (getLexer().isNot(AsmToken::RParen)) {
476      // Otherwise we have the unsupported form of a scale amount without an
477      // index.
478      SMLoc Loc = Parser.getTok().getLoc();
479
480      int64_t Value;
481      if (getParser().ParseAbsoluteExpression(Value))
482        return 0;
483
484      Error(Loc, "cannot have scale factor without index register");
485      return 0;
486    }
487  }
488
489  // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
490  if (getLexer().isNot(AsmToken::RParen)) {
491    Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
492    return 0;
493  }
494  SMLoc MemEnd = Parser.getTok().getLoc();
495  Parser.Lex(); // Eat the ')'.
496
497  return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
498                               MemStart, MemEnd);
499}
500
501bool X86ATTAsmParser::
502ParseInstruction(const StringRef &Name, SMLoc NameLoc,
503                 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
504  // FIXME: Hack to recognize "sal..." and "rep..." for now. We need a way to
505  // represent alternative syntaxes in the .td file, without requiring
506  // instruction duplication.
507  StringRef PatchedName = StringSwitch<StringRef>(Name)
508    .Case("sal", "shl")
509    .Case("salb", "shlb")
510    .Case("sall", "shll")
511    .Case("salq", "shlq")
512    .Case("salw", "shlw")
513    .Case("repe", "rep")
514    .Case("repz", "rep")
515    .Case("repnz", "repne")
516    .Default(Name);
517  Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
518
519  if (getLexer().isNot(AsmToken::EndOfStatement)) {
520
521    // Parse '*' modifier.
522    if (getLexer().is(AsmToken::Star)) {
523      SMLoc Loc = Parser.getTok().getLoc();
524      Operands.push_back(X86Operand::CreateToken("*", Loc));
525      Parser.Lex(); // Eat the star.
526    }
527
528    // Read the first operand.
529    if (X86Operand *Op = ParseOperand())
530      Operands.push_back(Op);
531    else
532      return true;
533
534    while (getLexer().is(AsmToken::Comma)) {
535      Parser.Lex();  // Eat the comma.
536
537      // Parse and remember the operand.
538      if (X86Operand *Op = ParseOperand())
539        Operands.push_back(Op);
540      else
541        return true;
542    }
543  }
544
545  // FIXME: Hack to handle recognizing s{hr,ar,hl}? $1.
546  if ((Name.startswith("shr") || Name.startswith("sar") ||
547       Name.startswith("shl")) &&
548      Operands.size() == 3 &&
549      static_cast<X86Operand*>(Operands[1])->isImm() &&
550      isa<MCConstantExpr>(static_cast<X86Operand*>(Operands[1])->getImm()) &&
551      cast<MCConstantExpr>(static_cast<X86Operand*>(Operands[1])->getImm())->getValue() == 1)
552    Operands.erase(Operands.begin() + 1);
553
554  return false;
555}
556
557bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
558  StringRef IDVal = DirectiveID.getIdentifier();
559  if (IDVal == ".word")
560    return ParseDirectiveWord(2, DirectiveID.getLoc());
561  return true;
562}
563
564/// ParseDirectiveWord
565///  ::= .word [ expression (, expression)* ]
566bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
567  if (getLexer().isNot(AsmToken::EndOfStatement)) {
568    for (;;) {
569      const MCExpr *Value;
570      if (getParser().ParseExpression(Value))
571        return true;
572
573      getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
574
575      if (getLexer().is(AsmToken::EndOfStatement))
576        break;
577
578      // FIXME: Improve diagnostic.
579      if (getLexer().isNot(AsmToken::Comma))
580        return Error(L, "unexpected token in directive");
581      Parser.Lex();
582    }
583  }
584
585  Parser.Lex();
586  return false;
587}
588
589extern "C" void LLVMInitializeX86AsmLexer();
590
591// Force static initialization.
592extern "C" void LLVMInitializeX86AsmParser() {
593  RegisterAsmParser<X86ATTAsmParser> X(TheX86_32Target);
594  RegisterAsmParser<X86ATTAsmParser> Y(TheX86_64Target);
595  LLVMInitializeX86AsmLexer();
596}
597
598#include "X86GenAsmMatcher.inc"
599