1251607Sdim//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==// 2251607Sdim// 3251607Sdim// The LLVM Compiler Infrastructure 4251607Sdim// 5251607Sdim// This file is distributed under the University of Illinois Open Source 6251607Sdim// License. See LICENSE.TXT for details. 7251607Sdim// 8251607Sdim//===----------------------------------------------------------------------===// 9251607Sdim 10251607Sdim//===----------------------------------------------------------------------===// 11263509Sdim// Select instructions 12251607Sdim//===----------------------------------------------------------------------===// 13251607Sdim 14251607Sdim// C's ?: operator for floating-point operands. 15251607Sdimdef SelectF32 : SelectWrapper<FP32>; 16251607Sdimdef SelectF64 : SelectWrapper<FP64>; 17251607Sdimdef SelectF128 : SelectWrapper<FP128>; 18251607Sdim 19263509Sdimdefm CondStoreF32 : CondStores<FP32, nonvolatile_store, 20263509Sdim nonvolatile_load, bdxaddr20only>; 21263509Sdimdefm CondStoreF64 : CondStores<FP64, nonvolatile_store, 22263509Sdim nonvolatile_load, bdxaddr20only>; 23263509Sdim 24251607Sdim//===----------------------------------------------------------------------===// 25251607Sdim// Move instructions 26251607Sdim//===----------------------------------------------------------------------===// 27251607Sdim 28251607Sdim// Load zero. 29251607Sdimlet neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 30251607Sdim def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>; 31251607Sdim def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>; 32251607Sdim def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>; 33251607Sdim} 34251607Sdim 35251607Sdim// Moves between two floating-point registers. 36251607Sdimlet neverHasSideEffects = 1 in { 37263509Sdim def LER : UnaryRR <"le", 0x38, null_frag, FP32, FP32>; 38263509Sdim def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>; 39263509Sdim def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>; 40251607Sdim} 41251607Sdim 42263509Sdim// Moves between two floating-point registers that also set the condition 43263509Sdim// codes. 44263509Sdimlet Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 45263509Sdim defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>; 46263509Sdim defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>; 47263509Sdim defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>; 48263509Sdim} 49263509Sdimdef : CompareZeroFP<LTEBRCompare, FP32>; 50263509Sdimdef : CompareZeroFP<LTDBRCompare, FP64>; 51263509Sdimdef : CompareZeroFP<LTXBRCompare, FP128>; 52263509Sdim 53251607Sdim// Moves between 64-bit integer and floating-point registers. 54263509Sdimdef LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>; 55263509Sdimdef LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>; 56251607Sdim 57251607Sdim// fcopysign with an FP32 result. 58251607Sdimlet isCodeGenOnly = 1 in { 59263509Sdim def CPSDRss : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP32>; 60263509Sdim def CPSDRsd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP64>; 61251607Sdim} 62251607Sdim 63263509Sdim// The sign of an FP128 is in the high register. 64251607Sdimdef : Pat<(fcopysign FP32:$src1, FP128:$src2), 65263509Sdim (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 66251607Sdim 67251607Sdim// fcopysign with an FP64 result. 68251607Sdimlet isCodeGenOnly = 1 in 69263509Sdim def CPSDRds : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP32>; 70263509Sdimdef CPSDRdd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP64>; 71251607Sdim 72263509Sdim// The sign of an FP128 is in the high register. 73251607Sdimdef : Pat<(fcopysign FP64:$src1, FP128:$src2), 74263509Sdim (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 75251607Sdim 76251607Sdim// fcopysign with an FP128 result. Use "upper" as the high half and leave 77251607Sdim// the low half as-is. 78251607Sdimclass CopySign128<RegisterOperand cls, dag upper> 79251607Sdim : Pat<(fcopysign FP128:$src1, cls:$src2), 80263509Sdim (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>; 81251607Sdim 82263509Sdimdef : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64), 83263509Sdim FP32:$src2)>; 84263509Sdimdef : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 85263509Sdim FP64:$src2)>; 86263509Sdimdef : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 87263509Sdim (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 88251607Sdim 89263509Sdimdefm LoadStoreF32 : MVCLoadStore<load, f32, MVCSequence, 4>; 90263509Sdimdefm LoadStoreF64 : MVCLoadStore<load, f64, MVCSequence, 8>; 91263509Sdimdefm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>; 92263509Sdim 93251607Sdim//===----------------------------------------------------------------------===// 94251607Sdim// Load instructions 95251607Sdim//===----------------------------------------------------------------------===// 96251607Sdim 97251607Sdimlet canFoldAsLoad = 1, SimpleBDXLoad = 1 in { 98263509Sdim defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>; 99263509Sdim defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>; 100251607Sdim 101251607Sdim // These instructions are split after register allocation, so we don't 102251607Sdim // want a custom inserter. 103251607Sdim let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 104251607Sdim def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src), 105251607Sdim [(set FP128:$dst, (load bdxaddr20only128:$src))]>; 106251607Sdim } 107251607Sdim} 108251607Sdim 109251607Sdim//===----------------------------------------------------------------------===// 110251607Sdim// Store instructions 111251607Sdim//===----------------------------------------------------------------------===// 112251607Sdim 113251607Sdimlet SimpleBDXStore = 1 in { 114263509Sdim defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>; 115263509Sdim defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>; 116251607Sdim 117251607Sdim // These instructions are split after register allocation, so we don't 118251607Sdim // want a custom inserter. 119251607Sdim let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 120251607Sdim def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst), 121251607Sdim [(store FP128:$src, bdxaddr20only128:$dst)]>; 122251607Sdim } 123251607Sdim} 124251607Sdim 125251607Sdim//===----------------------------------------------------------------------===// 126251607Sdim// Conversion instructions 127251607Sdim//===----------------------------------------------------------------------===// 128251607Sdim 129251607Sdim// Convert floating-point values to narrower representations, rounding 130251607Sdim// according to the current mode. The destination of LEXBR and LDXBR 131251607Sdim// is a 128-bit value, but only the first register of the pair is used. 132263509Sdimdef LEDBR : UnaryRRE<"ledb", 0xB344, fround, FP32, FP64>; 133263509Sdimdef LEXBR : UnaryRRE<"lexb", 0xB346, null_frag, FP128, FP128>; 134263509Sdimdef LDXBR : UnaryRRE<"ldxb", 0xB345, null_frag, FP128, FP128>; 135251607Sdim 136251607Sdimdef : Pat<(f32 (fround FP128:$src)), 137263509Sdim (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hh32)>; 138251607Sdimdef : Pat<(f64 (fround FP128:$src)), 139263509Sdim (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>; 140251607Sdim 141251607Sdim// Extend register floating-point values to wider representations. 142263509Sdimdef LDEBR : UnaryRRE<"ldeb", 0xB304, fextend, FP64, FP32>; 143263509Sdimdef LXEBR : UnaryRRE<"lxeb", 0xB306, fextend, FP128, FP32>; 144263509Sdimdef LXDBR : UnaryRRE<"lxdb", 0xB305, fextend, FP128, FP64>; 145251607Sdim 146251607Sdim// Extend memory floating-point values to wider representations. 147263509Sdimdef LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>; 148263509Sdimdef LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128, 4>; 149263509Sdimdef LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>; 150251607Sdim 151251607Sdim// Convert a signed integer register value to a floating-point one. 152263509Sdimdef CEFBR : UnaryRRE<"cefb", 0xB394, sint_to_fp, FP32, GR32>; 153263509Sdimdef CDFBR : UnaryRRE<"cdfb", 0xB395, sint_to_fp, FP64, GR32>; 154263509Sdimdef CXFBR : UnaryRRE<"cxfb", 0xB396, sint_to_fp, FP128, GR32>; 155251607Sdim 156263509Sdimdef CEGBR : UnaryRRE<"cegb", 0xB3A4, sint_to_fp, FP32, GR64>; 157263509Sdimdef CDGBR : UnaryRRE<"cdgb", 0xB3A5, sint_to_fp, FP64, GR64>; 158263509Sdimdef CXGBR : UnaryRRE<"cxgb", 0xB3A6, sint_to_fp, FP128, GR64>; 159251607Sdim 160251607Sdim// Convert a floating-point register value to a signed integer value, 161251607Sdim// with the second operand (modifier M3) specifying the rounding mode. 162263509Sdimlet Defs = [CC] in { 163263509Sdim def CFEBR : UnaryRRF<"cfeb", 0xB398, GR32, FP32>; 164263509Sdim def CFDBR : UnaryRRF<"cfdb", 0xB399, GR32, FP64>; 165263509Sdim def CFXBR : UnaryRRF<"cfxb", 0xB39A, GR32, FP128>; 166251607Sdim 167263509Sdim def CGEBR : UnaryRRF<"cgeb", 0xB3A8, GR64, FP32>; 168263509Sdim def CGDBR : UnaryRRF<"cgdb", 0xB3A9, GR64, FP64>; 169263509Sdim def CGXBR : UnaryRRF<"cgxb", 0xB3AA, GR64, FP128>; 170251607Sdim} 171251607Sdim 172251607Sdim// fp_to_sint always rounds towards zero, which is modifier value 5. 173263509Sdimdef : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>; 174263509Sdimdef : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>; 175263509Sdimdef : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>; 176251607Sdim 177263509Sdimdef : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>; 178263509Sdimdef : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>; 179263509Sdimdef : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>; 180251607Sdim 181251607Sdim//===----------------------------------------------------------------------===// 182251607Sdim// Unary arithmetic 183251607Sdim//===----------------------------------------------------------------------===// 184251607Sdim 185251607Sdim// Negation (Load Complement). 186263509Sdimlet Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 187263509Sdim def LCEBR : UnaryRRE<"lceb", 0xB303, fneg, FP32, FP32>; 188263509Sdim def LCDBR : UnaryRRE<"lcdb", 0xB313, fneg, FP64, FP64>; 189263509Sdim def LCXBR : UnaryRRE<"lcxb", 0xB343, fneg, FP128, FP128>; 190251607Sdim} 191251607Sdim 192251607Sdim// Absolute value (Load Positive). 193263509Sdimlet Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 194263509Sdim def LPEBR : UnaryRRE<"lpeb", 0xB300, fabs, FP32, FP32>; 195263509Sdim def LPDBR : UnaryRRE<"lpdb", 0xB310, fabs, FP64, FP64>; 196263509Sdim def LPXBR : UnaryRRE<"lpxb", 0xB340, fabs, FP128, FP128>; 197251607Sdim} 198251607Sdim 199251607Sdim// Negative absolute value (Load Negative). 200263509Sdimlet Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 201263509Sdim def LNEBR : UnaryRRE<"lneb", 0xB301, fnabs, FP32, FP32>; 202263509Sdim def LNDBR : UnaryRRE<"lndb", 0xB311, fnabs, FP64, FP64>; 203263509Sdim def LNXBR : UnaryRRE<"lnxb", 0xB341, fnabs, FP128, FP128>; 204251607Sdim} 205251607Sdim 206251607Sdim// Square root. 207263509Sdimdef SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32, FP32>; 208263509Sdimdef SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64, FP64>; 209263509Sdimdef SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>; 210251607Sdim 211263509Sdimdef SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>; 212263509Sdimdef SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>; 213251607Sdim 214251607Sdim// Round to an integer, with the second operand (modifier M3) specifying 215263509Sdim// the rounding mode. These forms always check for inexact conditions. 216263509Sdimdef FIEBR : UnaryRRF<"fieb", 0xB357, FP32, FP32>; 217263509Sdimdef FIDBR : UnaryRRF<"fidb", 0xB35F, FP64, FP64>; 218263509Sdimdef FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>; 219251607Sdim 220263509Sdim// Extended forms of the previous three instructions. M4 can be set to 4 221263509Sdim// to suppress detection of inexact conditions. 222263509Sdimdef FIEBRA : UnaryRRF4<"fiebra", 0xB357, FP32, FP32>, 223263509Sdim Requires<[FeatureFPExtension]>; 224263509Sdimdef FIDBRA : UnaryRRF4<"fidbra", 0xB35F, FP64, FP64>, 225263509Sdim Requires<[FeatureFPExtension]>; 226263509Sdimdef FIXBRA : UnaryRRF4<"fixbra", 0xB347, FP128, FP128>, 227263509Sdim Requires<[FeatureFPExtension]>; 228263509Sdim 229251607Sdim// frint rounds according to the current mode (modifier 0) and detects 230251607Sdim// inexact conditions. 231263509Sdimdef : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>; 232263509Sdimdef : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>; 233263509Sdimdef : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>; 234251607Sdim 235263509Sdimlet Predicates = [FeatureFPExtension] in { 236263509Sdim // fnearbyint is like frint but does not detect inexact conditions. 237263509Sdim def : Pat<(fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>; 238263509Sdim def : Pat<(fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>; 239263509Sdim def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>; 240263509Sdim 241263509Sdim // floor is no longer allowed to raise an inexact condition, 242263509Sdim // so restrict it to the cases where the condition can be suppressed. 243263509Sdim // Mode 7 is round towards -inf. 244263509Sdim def : Pat<(ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>; 245263509Sdim def : Pat<(ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>; 246263509Sdim def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>; 247263509Sdim 248263509Sdim // Same idea for ceil, where mode 6 is round towards +inf. 249263509Sdim def : Pat<(fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>; 250263509Sdim def : Pat<(fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>; 251263509Sdim def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>; 252263509Sdim 253263509Sdim // Same idea for trunc, where mode 5 is round towards zero. 254263509Sdim def : Pat<(ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>; 255263509Sdim def : Pat<(ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>; 256263509Sdim def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>; 257263509Sdim 258263509Sdim // Same idea for round, where mode 1 is round towards nearest with 259263509Sdim // ties away from zero. 260263509Sdim def : Pat<(frnd FP32:$src), (FIEBRA 1, FP32:$src, 4)>; 261263509Sdim def : Pat<(frnd FP64:$src), (FIDBRA 1, FP64:$src, 4)>; 262263509Sdim def : Pat<(frnd FP128:$src), (FIXBRA 1, FP128:$src, 4)>; 263263509Sdim} 264263509Sdim 265251607Sdim//===----------------------------------------------------------------------===// 266251607Sdim// Binary arithmetic 267251607Sdim//===----------------------------------------------------------------------===// 268251607Sdim 269251607Sdim// Addition. 270263509Sdimlet Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 271251607Sdim let isCommutable = 1 in { 272263509Sdim def AEBR : BinaryRRE<"aeb", 0xB30A, fadd, FP32, FP32>; 273263509Sdim def ADBR : BinaryRRE<"adb", 0xB31A, fadd, FP64, FP64>; 274263509Sdim def AXBR : BinaryRRE<"axb", 0xB34A, fadd, FP128, FP128>; 275251607Sdim } 276263509Sdim def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>; 277263509Sdim def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>; 278251607Sdim} 279251607Sdim 280251607Sdim// Subtraction. 281263509Sdimlet Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 282263509Sdim def SEBR : BinaryRRE<"seb", 0xB30B, fsub, FP32, FP32>; 283263509Sdim def SDBR : BinaryRRE<"sdb", 0xB31B, fsub, FP64, FP64>; 284263509Sdim def SXBR : BinaryRRE<"sxb", 0xB34B, fsub, FP128, FP128>; 285251607Sdim 286263509Sdim def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>; 287263509Sdim def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>; 288251607Sdim} 289251607Sdim 290251607Sdim// Multiplication. 291251607Sdimlet isCommutable = 1 in { 292263509Sdim def MEEBR : BinaryRRE<"meeb", 0xB317, fmul, FP32, FP32>; 293263509Sdim def MDBR : BinaryRRE<"mdb", 0xB31C, fmul, FP64, FP64>; 294263509Sdim def MXBR : BinaryRRE<"mxb", 0xB34C, fmul, FP128, FP128>; 295251607Sdim} 296263509Sdimdef MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>; 297263509Sdimdef MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>; 298251607Sdim 299251607Sdim// f64 multiplication of two FP32 registers. 300263509Sdimdef MDEBR : BinaryRRE<"mdeb", 0xB30C, null_frag, FP64, FP32>; 301251607Sdimdef : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))), 302251607Sdim (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 303263509Sdim FP32:$src1, subreg_h32), FP32:$src2)>; 304251607Sdim 305251607Sdim// f64 multiplication of an FP32 register and an f32 memory. 306263509Sdimdef MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>; 307251607Sdimdef : Pat<(fmul (f64 (fextend FP32:$src1)), 308251607Sdim (f64 (extloadf32 bdxaddr12only:$addr))), 309263509Sdim (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_h32), 310251607Sdim bdxaddr12only:$addr)>; 311251607Sdim 312251607Sdim// f128 multiplication of two FP64 registers. 313263509Sdimdef MXDBR : BinaryRRE<"mxdb", 0xB307, null_frag, FP128, FP64>; 314251607Sdimdef : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))), 315251607Sdim (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)), 316263509Sdim FP64:$src1, subreg_h64), FP64:$src2)>; 317251607Sdim 318251607Sdim// f128 multiplication of an FP64 register and an f64 memory. 319263509Sdimdef MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>; 320251607Sdimdef : Pat<(fmul (f128 (fextend FP64:$src1)), 321251607Sdim (f128 (extloadf64 bdxaddr12only:$addr))), 322263509Sdim (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64), 323251607Sdim bdxaddr12only:$addr)>; 324251607Sdim 325251607Sdim// Fused multiply-add. 326263509Sdimdef MAEBR : TernaryRRD<"maeb", 0xB30E, z_fma, FP32>; 327263509Sdimdef MADBR : TernaryRRD<"madb", 0xB31E, z_fma, FP64>; 328251607Sdim 329263509Sdimdef MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>; 330263509Sdimdef MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>; 331251607Sdim 332251607Sdim// Fused multiply-subtract. 333263509Sdimdef MSEBR : TernaryRRD<"mseb", 0xB30F, z_fms, FP32>; 334263509Sdimdef MSDBR : TernaryRRD<"msdb", 0xB31F, z_fms, FP64>; 335251607Sdim 336263509Sdimdef MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>; 337263509Sdimdef MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>; 338251607Sdim 339251607Sdim// Division. 340263509Sdimdef DEBR : BinaryRRE<"deb", 0xB30D, fdiv, FP32, FP32>; 341263509Sdimdef DDBR : BinaryRRE<"ddb", 0xB31D, fdiv, FP64, FP64>; 342263509Sdimdef DXBR : BinaryRRE<"dxb", 0xB34D, fdiv, FP128, FP128>; 343251607Sdim 344263509Sdimdef DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>; 345263509Sdimdef DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>; 346251607Sdim 347251607Sdim//===----------------------------------------------------------------------===// 348251607Sdim// Comparisons 349251607Sdim//===----------------------------------------------------------------------===// 350251607Sdim 351263509Sdimlet Defs = [CC], CCValues = 0xF in { 352263509Sdim def CEBR : CompareRRE<"ceb", 0xB309, z_fcmp, FP32, FP32>; 353263509Sdim def CDBR : CompareRRE<"cdb", 0xB319, z_fcmp, FP64, FP64>; 354263509Sdim def CXBR : CompareRRE<"cxb", 0xB349, z_fcmp, FP128, FP128>; 355251607Sdim 356263509Sdim def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>; 357263509Sdim def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>; 358251607Sdim} 359251607Sdim 360251607Sdim//===----------------------------------------------------------------------===// 361251607Sdim// Peepholes 362251607Sdim//===----------------------------------------------------------------------===// 363251607Sdim 364251607Sdimdef : Pat<(f32 fpimmneg0), (LCEBR (LZER))>; 365251607Sdimdef : Pat<(f64 fpimmneg0), (LCDBR (LZDR))>; 366251607Sdimdef : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>; 367