1235633Sdim//===-- SparcRegisterInfo.td - Sparc Register defs ---------*- tablegen -*-===// 2235633Sdim// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7235633Sdim// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11263509Sdim// Declarations that describe the Sparc register file 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14263509Sdimclass SparcReg<bits<16> Enc, string n> : Register<n> { 15263509Sdim let HWEncoding = Enc; 16193323Sed let Namespace = "SP"; 17193323Sed} 18193323Sed 19198090Srdivackyclass SparcCtrlReg<string n>: Register<n> { 20198090Srdivacky let Namespace = "SP"; 21198090Srdivacky} 22198090Srdivacky 23208599Srdivackylet Namespace = "SP" in { 24263509Sdimdef sub_even : SubRegIndex<32>; 25263509Sdimdef sub_odd : SubRegIndex<32, 32>; 26263509Sdimdef sub_even64 : SubRegIndex<64>; 27263509Sdimdef sub_odd64 : SubRegIndex<64, 64>; 28208599Srdivacky} 29208599Srdivacky 30193323Sed// Registers are identified with 5-bit ID numbers. 31193323Sed// Ri - 32-bit integer registers 32263509Sdimclass Ri<bits<16> Enc, string n> : SparcReg<Enc, n>; 33263509Sdim 34193323Sed// Rf - 32-bit floating-point registers 35263509Sdimclass Rf<bits<16> Enc, string n> : SparcReg<Enc, n>; 36263509Sdim 37193323Sed// Rd - Slots in the FP register file for 64-bit floating-point values. 38263509Sdimclass Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { 39193323Sed let SubRegs = subregs; 40208599Srdivacky let SubRegIndices = [sub_even, sub_odd]; 41235633Sdim let CoveredBySubRegs = 1; 42193323Sed} 43193323Sed 44263509Sdim// Rq - Slots in the FP register file for 128-bit floating-point values. 45263509Sdimclass Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { 46263509Sdim let SubRegs = subregs; 47263509Sdim let SubRegIndices = [sub_even64, sub_odd64]; 48263509Sdim let CoveredBySubRegs = 1; 49263509Sdim} 50263509Sdim 51198090Srdivacky// Control Registers 52252723Sdimdef ICC : SparcCtrlReg<"ICC">; // This represents icc and xcc in 64-bit code. 53198090Srdivackydef FCC : SparcCtrlReg<"FCC">; 54198090Srdivacky 55218893Sdim// Y register 56218893Sdimdef Y : SparcCtrlReg<"Y">; 57218893Sdim 58193323Sed// Integer registers 59193323Seddef G0 : Ri< 0, "G0">, DwarfRegNum<[0]>; 60193323Seddef G1 : Ri< 1, "G1">, DwarfRegNum<[1]>; 61263509Sdimdef G2 : Ri< 2, "G2">, DwarfRegNum<[2]>; 62193323Seddef G3 : Ri< 3, "G3">, DwarfRegNum<[3]>; 63193323Seddef G4 : Ri< 4, "G4">, DwarfRegNum<[4]>; 64263509Sdimdef G5 : Ri< 5, "G5">, DwarfRegNum<[5]>; 65193323Seddef G6 : Ri< 6, "G6">, DwarfRegNum<[6]>; 66193323Seddef G7 : Ri< 7, "G7">, DwarfRegNum<[7]>; 67193323Seddef O0 : Ri< 8, "O0">, DwarfRegNum<[8]>; 68193323Seddef O1 : Ri< 9, "O1">, DwarfRegNum<[9]>; 69263509Sdimdef O2 : Ri<10, "O2">, DwarfRegNum<[10]>; 70193323Seddef O3 : Ri<11, "O3">, DwarfRegNum<[11]>; 71193323Seddef O4 : Ri<12, "O4">, DwarfRegNum<[12]>; 72263509Sdimdef O5 : Ri<13, "O5">, DwarfRegNum<[13]>; 73198090Srdivackydef O6 : Ri<14, "SP">, DwarfRegNum<[14]>; 74193323Seddef O7 : Ri<15, "O7">, DwarfRegNum<[15]>; 75193323Seddef L0 : Ri<16, "L0">, DwarfRegNum<[16]>; 76193323Seddef L1 : Ri<17, "L1">, DwarfRegNum<[17]>; 77263509Sdimdef L2 : Ri<18, "L2">, DwarfRegNum<[18]>; 78193323Seddef L3 : Ri<19, "L3">, DwarfRegNum<[19]>; 79193323Seddef L4 : Ri<20, "L4">, DwarfRegNum<[20]>; 80263509Sdimdef L5 : Ri<21, "L5">, DwarfRegNum<[21]>; 81193323Seddef L6 : Ri<22, "L6">, DwarfRegNum<[22]>; 82193323Seddef L7 : Ri<23, "L7">, DwarfRegNum<[23]>; 83193323Seddef I0 : Ri<24, "I0">, DwarfRegNum<[24]>; 84193323Seddef I1 : Ri<25, "I1">, DwarfRegNum<[25]>; 85263509Sdimdef I2 : Ri<26, "I2">, DwarfRegNum<[26]>; 86193323Seddef I3 : Ri<27, "I3">, DwarfRegNum<[27]>; 87193323Seddef I4 : Ri<28, "I4">, DwarfRegNum<[28]>; 88263509Sdimdef I5 : Ri<29, "I5">, DwarfRegNum<[29]>; 89198090Srdivackydef I6 : Ri<30, "FP">, DwarfRegNum<[30]>; 90193323Seddef I7 : Ri<31, "I7">, DwarfRegNum<[31]>; 91193323Sed 92193323Sed// Floating-point registers 93193323Seddef F0 : Rf< 0, "F0">, DwarfRegNum<[32]>; 94193323Seddef F1 : Rf< 1, "F1">, DwarfRegNum<[33]>; 95263509Sdimdef F2 : Rf< 2, "F2">, DwarfRegNum<[34]>; 96193323Seddef F3 : Rf< 3, "F3">, DwarfRegNum<[35]>; 97193323Seddef F4 : Rf< 4, "F4">, DwarfRegNum<[36]>; 98263509Sdimdef F5 : Rf< 5, "F5">, DwarfRegNum<[37]>; 99193323Seddef F6 : Rf< 6, "F6">, DwarfRegNum<[38]>; 100193323Seddef F7 : Rf< 7, "F7">, DwarfRegNum<[39]>; 101263509Sdimdef F8 : Rf< 8, "F8">, DwarfRegNum<[40]>; 102193323Seddef F9 : Rf< 9, "F9">, DwarfRegNum<[41]>; 103193323Seddef F10 : Rf<10, "F10">, DwarfRegNum<[42]>; 104263509Sdimdef F11 : Rf<11, "F11">, DwarfRegNum<[43]>; 105193323Seddef F12 : Rf<12, "F12">, DwarfRegNum<[44]>; 106193323Seddef F13 : Rf<13, "F13">, DwarfRegNum<[45]>; 107263509Sdimdef F14 : Rf<14, "F14">, DwarfRegNum<[46]>; 108193323Seddef F15 : Rf<15, "F15">, DwarfRegNum<[47]>; 109193323Seddef F16 : Rf<16, "F16">, DwarfRegNum<[48]>; 110263509Sdimdef F17 : Rf<17, "F17">, DwarfRegNum<[49]>; 111193323Seddef F18 : Rf<18, "F18">, DwarfRegNum<[50]>; 112193323Seddef F19 : Rf<19, "F19">, DwarfRegNum<[51]>; 113263509Sdimdef F20 : Rf<20, "F20">, DwarfRegNum<[52]>; 114193323Seddef F21 : Rf<21, "F21">, DwarfRegNum<[53]>; 115193323Seddef F22 : Rf<22, "F22">, DwarfRegNum<[54]>; 116193323Seddef F23 : Rf<23, "F23">, DwarfRegNum<[55]>; 117193323Seddef F24 : Rf<24, "F24">, DwarfRegNum<[56]>; 118193323Seddef F25 : Rf<25, "F25">, DwarfRegNum<[57]>; 119263509Sdimdef F26 : Rf<26, "F26">, DwarfRegNum<[58]>; 120193323Seddef F27 : Rf<27, "F27">, DwarfRegNum<[59]>; 121193323Seddef F28 : Rf<28, "F28">, DwarfRegNum<[60]>; 122263509Sdimdef F29 : Rf<29, "F29">, DwarfRegNum<[61]>; 123193323Seddef F30 : Rf<30, "F30">, DwarfRegNum<[62]>; 124193323Seddef F31 : Rf<31, "F31">, DwarfRegNum<[63]>; 125193323Sed 126193323Sed// Aliases of the F* registers used to hold 64-bit fp values (doubles) 127223017Sdimdef D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>; 128223017Sdimdef D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>; 129223017Sdimdef D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>; 130223017Sdimdef D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>; 131223017Sdimdef D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>; 132223017Sdimdef D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>; 133223017Sdimdef D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>; 134223017Sdimdef D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>; 135223017Sdimdef D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[80]>; 136223017Sdimdef D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[81]>; 137223017Sdimdef D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>; 138223017Sdimdef D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<[83]>; 139223017Sdimdef D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<[84]>; 140223017Sdimdef D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[85]>; 141223017Sdimdef D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[86]>; 142223017Sdimdef D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>; 143193323Sed 144263509Sdim// Unaliased double precision floating point registers. 145263509Sdim// FIXME: Define DwarfRegNum for these registers. 146263509Sdimdef D16 : SparcReg< 1, "F32">; 147263509Sdimdef D17 : SparcReg< 3, "F34">; 148263509Sdimdef D18 : SparcReg< 5, "F36">; 149263509Sdimdef D19 : SparcReg< 7, "F38">; 150263509Sdimdef D20 : SparcReg< 9, "F40">; 151263509Sdimdef D21 : SparcReg<11, "F42">; 152263509Sdimdef D22 : SparcReg<13, "F44">; 153263509Sdimdef D23 : SparcReg<15, "F46">; 154263509Sdimdef D24 : SparcReg<17, "F48">; 155263509Sdimdef D25 : SparcReg<19, "F50">; 156263509Sdimdef D26 : SparcReg<21, "F52">; 157263509Sdimdef D27 : SparcReg<23, "F54">; 158263509Sdimdef D28 : SparcReg<25, "F56">; 159263509Sdimdef D29 : SparcReg<27, "F58">; 160263509Sdimdef D30 : SparcReg<29, "F60">; 161263509Sdimdef D31 : SparcReg<31, "F62">; 162263509Sdim 163263509Sdim// Aliases of the F* registers used to hold 128-bit for values (long doubles). 164263509Sdimdef Q0 : Rq< 0, "F0", [D0, D1]>; 165263509Sdimdef Q1 : Rq< 4, "F4", [D2, D3]>; 166263509Sdimdef Q2 : Rq< 8, "F8", [D4, D5]>; 167263509Sdimdef Q3 : Rq<12, "F12", [D6, D7]>; 168263509Sdimdef Q4 : Rq<16, "F16", [D8, D9]>; 169263509Sdimdef Q5 : Rq<20, "F20", [D10, D11]>; 170263509Sdimdef Q6 : Rq<24, "F24", [D12, D13]>; 171263509Sdimdef Q7 : Rq<28, "F28", [D14, D15]>; 172263509Sdimdef Q8 : Rq< 1, "F32", [D16, D17]>; 173263509Sdimdef Q9 : Rq< 5, "F36", [D18, D19]>; 174263509Sdimdef Q10 : Rq< 9, "F40", [D20, D21]>; 175263509Sdimdef Q11 : Rq<13, "F44", [D22, D23]>; 176263509Sdimdef Q12 : Rq<17, "F48", [D24, D25]>; 177263509Sdimdef Q13 : Rq<21, "F52", [D26, D27]>; 178263509Sdimdef Q14 : Rq<25, "F56", [D28, D29]>; 179263509Sdimdef Q15 : Rq<29, "F60", [D30, D31]>; 180263509Sdim 181193323Sed// Register classes. 182193323Sed// 183193323Sed// FIXME: the register order should be defined in terms of the preferred 184193323Sed// allocation order... 185193323Sed// 186252723Sdim// This register class should not be used to hold i64 values, use the I64Regs 187252723Sdim// register class for that. The i64 type is included here to allow i64 patterns 188252723Sdim// using the integer instructions. 189252723Sdimdef IntRegs : RegisterClass<"SP", [i32, i64], 32, 190263509Sdim (add (sequence "I%u", 0, 7), 191263509Sdim (sequence "G%u", 0, 7), 192263509Sdim (sequence "L%u", 0, 7), 193263509Sdim (sequence "O%u", 0, 7))>; 194193323Sed 195252723Sdim// Register class for 64-bit mode, with a 64-bit spill slot size. 196252723Sdim// These are the same as the 32-bit registers, so TableGen will consider this 197252723Sdim// to be a sub-class of IntRegs. That works out because requiring a 64-bit 198252723Sdim// spill slot is a stricter constraint than only requiring a 32-bit spill slot. 199252723Sdimdef I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>; 200252723Sdim 201252723Sdim// Floating point register classes. 202224145Sdimdef FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>; 203193323Sed 204263509Sdimdef DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>; 205263509Sdim 206263509Sdimdef QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>; 207