1156952Sume//===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===// 2156952Sume// 3156952Sume// The LLVM Compiler Infrastructure 4156952Sume// 5156952Sume// This file is distributed under the University of Illinois Open Source 6156952Sume// License. See LICENSE.TXT for details. 7156952Sume// 8156952Sume//===----------------------------------------------------------------------===// 9156952Sume// 10156952Sume// This file contains the Sparc implementation of the TargetInstrInfo class. 11156952Sume// 12156952Sume//===----------------------------------------------------------------------===// 13156952Sume 14156952Sume#include "SparcInstrInfo.h" 15156952Sume#include "Sparc.h" 16156952Sume#include "SparcMachineFunctionInfo.h" 17156952Sume#include "SparcSubtarget.h" 18156952Sume#include "llvm/ADT/STLExtras.h" 19156952Sume#include "llvm/ADT/SmallVector.h" 20156952Sume#include "llvm/CodeGen/MachineFrameInfo.h" 21156952Sume#include "llvm/CodeGen/MachineInstrBuilder.h" 22156952Sume#include "llvm/CodeGen/MachineMemOperand.h" 23156952Sume#include "llvm/CodeGen/MachineRegisterInfo.h" 24156952Sume#include "llvm/Support/ErrorHandling.h" 25156952Sume#include "llvm/Support/TargetRegistry.h" 26156952Sume 27156952Sume#define GET_INSTRINFO_CTOR_DTOR 28156952Sume#include "SparcGenInstrInfo.inc" 29156952Sume 30156952Sumeusing namespace llvm; 31156952Sume 32156952Sume 33156952Sume// Pin the vtable to this file. 34156952Sumevoid SparcInstrInfo::anchor() {} 35156952Sume 36156952SumeSparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) 37156952Sume : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), 38156952Sume RI(ST), Subtarget(ST) { 39156952Sume} 40156952Sume 41156952Sume/// isLoadFromStackSlot - If the specified machine instruction is a direct 42156952Sume/// load from a stack slot, return the virtual or physical register number of 43156952Sume/// the destination along with the FrameIndex of the loaded stack slot. If 44156952Sume/// not, return 0. This predicate must return 0 if the instruction has 45156952Sume/// any side effects other than loading from the stack slot. 46156952Sumeunsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 47156952Sume int &FrameIndex) const { 48156952Sume if (MI->getOpcode() == SP::LDri || 49156952Sume MI->getOpcode() == SP::LDXri || 50156952Sume MI->getOpcode() == SP::LDFri || 51156952Sume MI->getOpcode() == SP::LDDFri || 52156952Sume MI->getOpcode() == SP::LDQFri) { 53156952Sume if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && 54156952Sume MI->getOperand(2).getImm() == 0) { 55156952Sume FrameIndex = MI->getOperand(1).getIndex(); 56156952Sume return MI->getOperand(0).getReg(); 57156952Sume } 58156952Sume } 59156952Sume return 0; 60156952Sume} 61156952Sume 62156952Sume/// isStoreToStackSlot - If the specified machine instruction is a direct 63156952Sume/// store to a stack slot, return the virtual or physical register number of 64156952Sume/// the source reg along with the FrameIndex of the loaded stack slot. If 65156952Sume/// not, return 0. This predicate must return 0 if the instruction has 66156952Sume/// any side effects other than storing to the stack slot. 67156952Sumeunsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 68156952Sume int &FrameIndex) const { 69186090Sume if (MI->getOpcode() == SP::STri || 70156952Sume MI->getOpcode() == SP::STXri || 71156956Sume MI->getOpcode() == SP::STFri || 72156956Sume MI->getOpcode() == SP::STDFri || 73156952Sume MI->getOpcode() == SP::STQFri) { 74156952Sume if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && 75156952Sume MI->getOperand(1).getImm() == 0) { 76156952Sume FrameIndex = MI->getOperand(0).getIndex(); 77156952Sume return MI->getOperand(2).getReg(); 78156952Sume } 79156952Sume } 80156952Sume return 0; 81156952Sume} 82156952Sume 83156952Sumestatic bool IsIntegerCC(unsigned CC) 84156952Sume{ 85156952Sume return (CC <= SPCC::ICC_VC); 86156952Sume} 87156956Sume 88156952Sume 89156952Sumestatic SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) 90156952Sume{ 91156952Sume switch(CC) { 92156952Sume case SPCC::ICC_NE: return SPCC::ICC_E; 93156952Sume case SPCC::ICC_E: return SPCC::ICC_NE; 94156952Sume case SPCC::ICC_G: return SPCC::ICC_LE; 95156952Sume case SPCC::ICC_LE: return SPCC::ICC_G; 96156952Sume case SPCC::ICC_GE: return SPCC::ICC_L; 97156952Sume case SPCC::ICC_L: return SPCC::ICC_GE; 98156952Sume case SPCC::ICC_GU: return SPCC::ICC_LEU; 99170244Sume case SPCC::ICC_LEU: return SPCC::ICC_GU; 100156952Sume case SPCC::ICC_CC: return SPCC::ICC_CS; 101156952Sume case SPCC::ICC_CS: return SPCC::ICC_CC; 102156952Sume case SPCC::ICC_POS: return SPCC::ICC_NEG; 103156952Sume case SPCC::ICC_NEG: return SPCC::ICC_POS; 104156952Sume case SPCC::ICC_VC: return SPCC::ICC_VS; 105156952Sume case SPCC::ICC_VS: return SPCC::ICC_VC; 106156952Sume 107156952Sume case SPCC::FCC_U: return SPCC::FCC_O; 108156952Sume case SPCC::FCC_O: return SPCC::FCC_U; 109156952Sume case SPCC::FCC_G: return SPCC::FCC_ULE; 110156952Sume case SPCC::FCC_LE: return SPCC::FCC_UG; 111170244Sume case SPCC::FCC_UG: return SPCC::FCC_LE; 112170244Sume case SPCC::FCC_ULE: return SPCC::FCC_G; 113170244Sume case SPCC::FCC_L: return SPCC::FCC_UGE; 114170244Sume case SPCC::FCC_GE: return SPCC::FCC_UL; 115156952Sume case SPCC::FCC_UL: return SPCC::FCC_GE; 116156952Sume case SPCC::FCC_UGE: return SPCC::FCC_L; 117156952Sume case SPCC::FCC_LG: return SPCC::FCC_UE; 118186090Sume case SPCC::FCC_UE: return SPCC::FCC_LG; 119186090Sume case SPCC::FCC_NE: return SPCC::FCC_E; 120156952Sume case SPCC::FCC_E: return SPCC::FCC_NE; 121156952Sume } 122156952Sume llvm_unreachable("Invalid cond code"); 123156952Sume} 124156952Sume 125170244Sumebool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 126156952Sume MachineBasicBlock *&TBB, 127156952Sume MachineBasicBlock *&FBB, 128156952Sume SmallVectorImpl<MachineOperand> &Cond, 129156952Sume bool AllowModify) const 130156952Sume{ 131156952Sume 132156952Sume MachineBasicBlock::iterator I = MBB.end(); 133156952Sume MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 134156952Sume while (I != MBB.begin()) { 135186090Sume --I; 136156952Sume 137186090Sume if (I->isDebugValue()) 138186090Sume continue; 139186090Sume 140186090Sume // When we see a non-terminator, we are done. 141186090Sume if (!isUnpredicatedTerminator(I)) 142186090Sume break; 143156952Sume 144156952Sume // Terminator is not a branch. 145156952Sume if (!I->isBranch()) 146156952Sume return true; 147156952Sume 148156952Sume // Handle Unconditional branches. 149156952Sume if (I->getOpcode() == SP::BA) { 150156952Sume UnCondBrIter = I; 151156952Sume 152186090Sume if (!AllowModify) { 153156952Sume TBB = I->getOperand(0).getMBB(); 154156952Sume continue; 155156952Sume } 156156952Sume 157156952Sume while (llvm::next(I) != MBB.end()) 158156952Sume llvm::next(I)->eraseFromParent(); 159156952Sume 160156952Sume Cond.clear(); 161156952Sume FBB = 0; 162156952Sume 163156952Sume if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 164156952Sume TBB = 0; 165156952Sume I->eraseFromParent(); 166156952Sume I = MBB.end(); 167156952Sume UnCondBrIter = MBB.end(); 168156952Sume continue; 169156952Sume } 170156952Sume 171156952Sume TBB = I->getOperand(0).getMBB(); 172156952Sume continue; 173156952Sume } 174156952Sume 175156952Sume unsigned Opcode = I->getOpcode(); 176156952Sume if (Opcode != SP::BCOND && Opcode != SP::FBCOND) 177156952Sume return true; // Unknown Opcode. 178156952Sume 179156952Sume SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm(); 180156952Sume 181156952Sume if (Cond.empty()) { 182156952Sume MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 183156952Sume if (AllowModify && UnCondBrIter != MBB.end() && 184156952Sume MBB.isLayoutSuccessor(TargetBB)) { 185156952Sume 186156952Sume // Transform the code 187156952Sume // 188156952Sume // brCC L1 189156952Sume // ba L2 190156952Sume // L1: 191156952Sume // .. 192156952Sume // L2: 193156952Sume // 194156952Sume // into 195156952Sume // 196156952Sume // brnCC L2 197156952Sume // L1: 198156952Sume // ... 199156952Sume // L2: 200156952Sume // 201156952Sume BranchCode = GetOppositeBranchCondition(BranchCode); 202156952Sume MachineBasicBlock::iterator OldInst = I; 203156952Sume BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode)) 204170244Sume .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode); 205156952Sume BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA)) 206156952Sume .addMBB(TargetBB); 207156952Sume 208156952Sume OldInst->eraseFromParent(); 209156952Sume UnCondBrIter->eraseFromParent(); 210156952Sume 211156952Sume UnCondBrIter = MBB.end(); 212170244Sume I = MBB.end(); 213170244Sume continue; 214170244Sume } 215170244Sume FBB = TBB; 216156952Sume TBB = I->getOperand(0).getMBB(); 217156952Sume Cond.push_back(MachineOperand::CreateImm(BranchCode)); 218157093Sume continue; 219156952Sume } 220156952Sume // FIXME: Handle subsequent conditional branches. 221156952Sume // For now, we can't handle multiple conditional branches. 222156952Sume return true; 223156952Sume } 224156952Sume return false; 225156952Sume} 226156952Sume 227170244Sumeunsigned 228156952SumeSparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 229156952Sume MachineBasicBlock *FBB, 230156952Sume const SmallVectorImpl<MachineOperand> &Cond, 231156952Sume DebugLoc DL) const { 232156952Sume assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 233156952Sume assert((Cond.size() == 1 || Cond.size() == 0) && 234156952Sume "Sparc branch conditions should have one component!"); 235156952Sume 236156952Sume if (Cond.empty()) { 237156952Sume assert(!FBB && "Unconditional branch with multiple successors!"); 238156952Sume BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); 239156952Sume return 1; 240156952Sume } 241156952Sume 242156952Sume // Conditional branch 243156952Sume unsigned CC = Cond[0].getImm(); 244156952Sume 245156952Sume if (IsIntegerCC(CC)) 246156952Sume BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); 247156952Sume else 248156952Sume BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); 249156952Sume if (!FBB) 250156956Sume return 1; 251156956Sume 252156956Sume BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); 253156956Sume return 2; 254156956Sume} 255156956Sume 256156956Sumeunsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const 257156956Sume{ 258157093Sume MachineBasicBlock::iterator I = MBB.end(); 259157093Sume unsigned Count = 0; 260157093Sume while (I != MBB.begin()) { 261157093Sume --I; 262156956Sume 263156956Sume if (I->isDebugValue()) 264156956Sume continue; 265156952Sume 266156952Sume if (I->getOpcode() != SP::BA 267156952Sume && I->getOpcode() != SP::BCOND 268156952Sume && I->getOpcode() != SP::FBCOND) 269156952Sume break; // Not a branch 270156952Sume 271156952Sume I->eraseFromParent(); 272156952Sume I = MBB.end(); 273156952Sume ++Count; 274156952Sume } 275156952Sume return Count; 276156952Sume} 277156952Sume 278156952Sumevoid SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 279156952Sume MachineBasicBlock::iterator I, DebugLoc DL, 280156952Sume unsigned DestReg, unsigned SrcReg, 281156952Sume bool KillSrc) const { 282156952Sume unsigned numSubRegs = 0; 283156952Sume unsigned movOpc = 0; 284156952Sume const unsigned *subRegIdx = 0; 285156952Sume 286156952Sume const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd }; 287156952Sume const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 }; 288156956Sume const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd, 289156956Sume SP::sub_odd64_then_sub_even, 290156956Sume SP::sub_odd64_then_sub_odd }; 291156952Sume 292156952Sume if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) 293156952Sume BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) 294156952Sume .addReg(SrcReg, getKillRegState(KillSrc)); 295156952Sume else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) 296156952Sume BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) 297156952Sume .addReg(SrcReg, getKillRegState(KillSrc)); 298156952Sume else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { 299156952Sume if (Subtarget.isV9()) { 300156952Sume BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) 301156952Sume .addReg(SrcReg, getKillRegState(KillSrc)); 302156952Sume } else { 303156952Sume // Use two FMOVS instructions. 304156952Sume subRegIdx = DFP_FP_SubRegsIdx; 305156952Sume numSubRegs = 2; 306156952Sume movOpc = SP::FMOVS; 307156952Sume } 308156952Sume } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { 309156952Sume if (Subtarget.isV9()) { 310156952Sume if (Subtarget.hasHardQuad()) { 311156952Sume BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) 312156952Sume .addReg(SrcReg, getKillRegState(KillSrc)); 313156952Sume } else { 314156952Sume // Use two FMOVD instructions. 315156952Sume subRegIdx = QFP_DFP_SubRegsIdx; 316156952Sume numSubRegs = 2; 317156952Sume movOpc = SP::FMOVD; 318156952Sume } 319156952Sume } else { 320156952Sume // Use four FMOVS instructions. 321156952Sume subRegIdx = QFP_FP_SubRegsIdx; 322156952Sume numSubRegs = 4; 323156956Sume movOpc = SP::FMOVS; 324156956Sume } 325156956Sume } else 326156956Sume llvm_unreachable("Impossible reg-to-reg copy"); 327156956Sume 328156956Sume if (numSubRegs == 0 || subRegIdx == 0 || movOpc == 0) 329156956Sume return; 330157093Sume 331157093Sume const TargetRegisterInfo *TRI = &getRegisterInfo(); 332157093Sume MachineInstr *MovMI = 0; 333157093Sume 334156956Sume for (unsigned i = 0; i != numSubRegs; ++i) { 335156956Sume unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]); 336156956Sume unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]); 337156956Sume assert(Dst && Src && "Bad sub-register"); 338156956Sume 339156956Sume MovMI = BuildMI(MBB, I, DL, get(movOpc), Dst).addReg(Src); 340156956Sume } 341157093Sume // Add implicit super-register defs and kills to the last MovMI. 342157093Sume MovMI->addRegisterDefined(DestReg, TRI); 343157093Sume if (KillSrc) 344157093Sume MovMI->addRegisterKilled(SrcReg, TRI); 345156952Sume} 346156952Sume 347156952Sumevoid SparcInstrInfo:: 348156952SumestoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 349156952Sume unsigned SrcReg, bool isKill, int FI, 350156952Sume const TargetRegisterClass *RC, 351156952Sume const TargetRegisterInfo *TRI) const { 352156952Sume DebugLoc DL; 353156952Sume if (I != MBB.end()) DL = I->getDebugLoc(); 354156952Sume 355156952Sume MachineFunction *MF = MBB.getParent(); 356156952Sume const MachineFrameInfo &MFI = *MF->getFrameInfo(); 357156952Sume MachineMemOperand *MMO = 358156952Sume MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 359156956Sume MachineMemOperand::MOStore, 360156956Sume MFI.getObjectSize(FI), 361156956Sume MFI.getObjectAlignment(FI)); 362156956Sume 363157093Sume // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 364157093Sume if (RC == &SP::I64RegsRegClass) 365157093Sume BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0) 366157093Sume .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 367156956Sume else if (RC == &SP::IntRegsRegClass) 368156956Sume BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) 369156956Sume .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 370156956Sume else if (RC == &SP::FPRegsRegClass) 371156952Sume BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) 372156952Sume .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 373156952Sume else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) 374156952Sume BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) 375156952Sume .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 376156952Sume else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) 377156952Sume // Use STQFri irrespective of its legality. If STQ is not legal, it will be 378156952Sume // lowered into two STDs in eliminateFrameIndex. 379156952Sume BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0) 380156952Sume .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 381156952Sume else 382156952Sume llvm_unreachable("Can't store this register to stack slot"); 383156952Sume} 384156952Sume 385156952Sumevoid SparcInstrInfo:: 386156952SumeloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 387156952Sume unsigned DestReg, int FI, 388156952Sume const TargetRegisterClass *RC, 389156952Sume const TargetRegisterInfo *TRI) const { 390156956Sume DebugLoc DL; 391156952Sume if (I != MBB.end()) DL = I->getDebugLoc(); 392156952Sume 393156952Sume MachineFunction *MF = MBB.getParent(); 394156952Sume const MachineFrameInfo &MFI = *MF->getFrameInfo(); 395156952Sume MachineMemOperand *MMO = 396156952Sume MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 397156952Sume MachineMemOperand::MOLoad, 398156952Sume MFI.getObjectSize(FI), 399156952Sume MFI.getObjectAlignment(FI)); 400170244Sume 401156952Sume if (RC == &SP::I64RegsRegClass) 402156952Sume BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0) 403156952Sume .addMemOperand(MMO); 404156952Sume else if (RC == &SP::IntRegsRegClass) 405156952Sume BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0) 406156952Sume .addMemOperand(MMO); 407156952Sume else if (RC == &SP::FPRegsRegClass) 408170244Sume BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0) 409170244Sume .addMemOperand(MMO); 410170244Sume else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) 411156952Sume BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0) 412156952Sume .addMemOperand(MMO); 413156952Sume else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) 414156952Sume // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be 415156952Sume // lowered into two LDDs in eliminateFrameIndex. 416156952Sume BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0) 417156952Sume .addMemOperand(MMO); 418156952Sume else 419156952Sume llvm_unreachable("Can't load this register from stack slot"); 420156952Sume} 421156952Sume 422156952Sumeunsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const 423156952Sume{ 424156952Sume SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>(); 425156952Sume unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg(); 426156952Sume if (GlobalBaseReg != 0) 427156952Sume return GlobalBaseReg; 428156952Sume 429156952Sume // Insert the set of GlobalBaseReg into the first MBB of the function 430156952Sume MachineBasicBlock &FirstMBB = MF->front(); 431156952Sume MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 432156952Sume MachineRegisterInfo &RegInfo = MF->getRegInfo(); 433156952Sume 434156952Sume const TargetRegisterClass *PtrRC = 435156952Sume Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; 436156952Sume GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC); 437156952Sume 438156952Sume DebugLoc dl; 439156952Sume 440156952Sume BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg); 441156952Sume SparcFI->setGlobalBaseReg(GlobalBaseReg); 442156952Sume return GlobalBaseReg; 443156952Sume} 444156952Sume