1235633Sdim//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===// 2235633Sdim// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7235633Sdim// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10263509Sdimclass InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> 11263509Sdim : Instruction { 12193323Sed field bits<32> Inst; 13193323Sed 14193323Sed let Namespace = "SP"; 15263764Sdim let Size = 4; 16193323Sed 17193323Sed bits<2> op; 18193323Sed let Inst{31-30} = op; // Top two bits are the 'op' field 19263509Sdim 20193323Sed dag OutOperandList = outs; 21193323Sed dag InOperandList = ins; 22193323Sed let AsmString = asmstr; 23193323Sed let Pattern = pattern; 24263764Sdim 25263764Sdim let DecoderNamespace = "Sparc"; 26263764Sdim field bits<32> SoftFail = 0; 27193323Sed} 28193323Sed 29193323Sed//===----------------------------------------------------------------------===// 30193323Sed// Format #2 instruction classes in the Sparc 31193323Sed//===----------------------------------------------------------------------===// 32193323Sed 33193323Sed// Format 2 instructions 34193323Sedclass F2<dag outs, dag ins, string asmstr, list<dag> pattern> 35193323Sed : InstSP<outs, ins, asmstr, pattern> { 36193323Sed bits<3> op2; 37193323Sed bits<22> imm22; 38193323Sed let op = 0; // op = 0 39193323Sed let Inst{24-22} = op2; 40193323Sed let Inst{21-0} = imm22; 41193323Sed} 42193323Sed 43193323Sed// Specific F2 classes: SparcV8 manual, page 44 44193323Sed// 45193323Sedclass F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern> 46193323Sed : F2<outs, ins, asmstr, pattern> { 47193323Sed bits<5> rd; 48193323Sed 49193323Sed let op2 = op2Val; 50193323Sed 51193323Sed let Inst{29-25} = rd; 52193323Sed} 53193323Sed 54263509Sdimclass F2_2<bits<3> op2Val, dag outs, dag ins, string asmstr, 55193323Sed list<dag> pattern> : F2<outs, ins, asmstr, pattern> { 56193323Sed bits<4> cond; 57193323Sed bit annul = 0; // currently unused 58193323Sed 59193323Sed let op2 = op2Val; 60193323Sed 61193323Sed let Inst{29} = annul; 62193323Sed let Inst{28-25} = cond; 63193323Sed} 64193323Sed 65263764Sdimclass F2_3<bits<3> op2Val, bits<2> ccVal, dag outs, dag ins, string asmstr, 66263764Sdim list<dag> pattern> 67263764Sdim : InstSP<outs, ins, asmstr, pattern> { 68263764Sdim bit annul; 69263764Sdim bits<4> cond; 70263764Sdim bit pred; 71263764Sdim bits<19> imm19; 72263764Sdim 73263764Sdim let op = 0; // op = 0 74263764Sdim 75263764Sdim bit annul = 0; // currently unused 76263764Sdim let pred = 1; // default is predict taken 77263764Sdim 78263764Sdim let Inst{29} = annul; 79263764Sdim let Inst{28-25} = cond; 80263764Sdim let Inst{24-22} = op2Val; 81263764Sdim let Inst{21-20} = ccVal; 82263764Sdim let Inst{19} = pred; 83263764Sdim let Inst{18-0} = imm19; 84263764Sdim} 85263764Sdim 86193323Sed//===----------------------------------------------------------------------===// 87193323Sed// Format #3 instruction classes in the Sparc 88193323Sed//===----------------------------------------------------------------------===// 89193323Sed 90193323Sedclass F3<dag outs, dag ins, string asmstr, list<dag> pattern> 91193323Sed : InstSP<outs, ins, asmstr, pattern> { 92193323Sed bits<5> rd; 93193323Sed bits<6> op3; 94193323Sed bits<5> rs1; 95193323Sed let op{1} = 1; // Op = 2 or 3 96193323Sed let Inst{29-25} = rd; 97193323Sed let Inst{24-19} = op3; 98193323Sed let Inst{18-14} = rs1; 99193323Sed} 100193323Sed 101193323Sed// Specific F3 classes: SparcV8 manual, page 44 102193323Sed// 103263764Sdimclass F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8> asi, dag outs, dag ins, 104193323Sed string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 105193323Sed bits<5> rs2; 106193323Sed 107193323Sed let op = opVal; 108193323Sed let op3 = op3val; 109193323Sed 110193323Sed let Inst{13} = 0; // i field = 0 111193323Sed let Inst{12-5} = asi; // address space identifier 112193323Sed let Inst{4-0} = rs2; 113193323Sed} 114193323Sed 115263764Sdimclass F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr, 116263764Sdim list<dag> pattern> : F3_1_asi<opVal, op3val, 0, outs, ins, 117263764Sdim asmstr, pattern>; 118263764Sdim 119263509Sdimclass F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 120193323Sed string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 121193323Sed bits<13> simm13; 122193323Sed 123193323Sed let op = opVal; 124193323Sed let op3 = op3val; 125193323Sed 126193323Sed let Inst{13} = 1; // i field = 1 127193323Sed let Inst{12-0} = simm13; 128193323Sed} 129193323Sed 130193323Sed// floating-point 131193323Sedclass F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 132193323Sed string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 133193323Sed bits<5> rs2; 134193323Sed 135193323Sed let op = opVal; 136193323Sed let op3 = op3val; 137193323Sed 138193323Sed let Inst{13-5} = opfval; // fp opcode 139193323Sed let Inst{4-0} = rs2; 140193323Sed} 141193323Sed 142263509Sdim// floating-point unary operations. 143263509Sdimclass F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 144263509Sdim string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 145263509Sdim bits<5> rs2; 146263509Sdim 147263509Sdim let op = opVal; 148263509Sdim let op3 = op3val; 149263509Sdim let rs1 = 0; 150263509Sdim 151263509Sdim let Inst{13-5} = opfval; // fp opcode 152263509Sdim let Inst{4-0} = rs2; 153263509Sdim} 154263509Sdim 155263509Sdim// floating-point compares. 156263509Sdimclass F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 157263509Sdim string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 158263509Sdim bits<5> rs2; 159263509Sdim 160263509Sdim let op = opVal; 161263509Sdim let op3 = op3val; 162263509Sdim let rd = 0; 163263509Sdim 164263509Sdim let Inst{13-5} = opfval; // fp opcode 165263509Sdim let Inst{4-0} = rs2; 166263509Sdim} 167263509Sdim 168252723Sdim// Shift by register rs2. 169252723Sdimclass F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 170252723Sdim string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 171252723Sdim bit x = xVal; // 1 for 64-bit shifts. 172252723Sdim bits<5> rs2; 173193323Sed 174252723Sdim let op = opVal; 175252723Sdim let op3 = op3val; 176252723Sdim 177252723Sdim let Inst{13} = 0; // i field = 0 178252723Sdim let Inst{12} = x; // extended registers. 179252723Sdim let Inst{4-0} = rs2; 180252723Sdim} 181252723Sdim 182252723Sdim// Shift by immediate. 183252723Sdimclass F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 184252723Sdim string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 185252723Sdim bit x = xVal; // 1 for 64-bit shifts. 186252723Sdim bits<6> shcnt; // shcnt32 / shcnt64. 187252723Sdim 188252723Sdim let op = opVal; 189252723Sdim let op3 = op3val; 190252723Sdim 191252723Sdim let Inst{13} = 1; // i field = 1 192252723Sdim let Inst{12} = x; // extended registers. 193252723Sdim let Inst{5-0} = shcnt; 194252723Sdim} 195252723Sdim 196252723Sdim// Define rr and ri shift instructions with patterns. 197252723Sdimmulticlass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode, 198252723Sdim ValueType VT, RegisterClass RC> { 199263764Sdim def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2), 200263764Sdim !strconcat(OpcStr, " $rs1, $rs2, $rd"), 201263764Sdim [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>; 202263764Sdim def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt), 203263764Sdim !strconcat(OpcStr, " $rs1, $shcnt, $rd"), 204263764Sdim [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>; 205252723Sdim} 206263509Sdim 207263509Sdimclass F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern> 208263509Sdim : InstSP<outs, ins, asmstr, pattern> { 209263509Sdim bits<5> rd; 210263509Sdim 211263509Sdim let op = 2; 212263509Sdim let Inst{29-25} = rd; 213263509Sdim let Inst{24-19} = op3; 214263509Sdim} 215263509Sdim 216263509Sdim 217263509Sdimclass F4_1<bits<6> op3, dag outs, dag ins, 218263509Sdim string asmstr, list<dag> pattern> 219263509Sdim : F4<op3, outs, ins, asmstr, pattern> { 220263509Sdim 221263509Sdim bits<3> cc; 222263509Sdim bits<4> cond; 223263509Sdim bits<5> rs2; 224263509Sdim 225263509Sdim let Inst{4-0} = rs2; 226263509Sdim let Inst{11} = cc{0}; 227263509Sdim let Inst{12} = cc{1}; 228263509Sdim let Inst{13} = 0; 229263509Sdim let Inst{17-14} = cond; 230263509Sdim let Inst{18} = cc{2}; 231263509Sdim 232263509Sdim} 233263509Sdim 234263509Sdimclass F4_2<bits<6> op3, dag outs, dag ins, 235263509Sdim string asmstr, list<dag> pattern> 236263509Sdim : F4<op3, outs, ins, asmstr, pattern> { 237263509Sdim bits<3> cc; 238263509Sdim bits<4> cond; 239263509Sdim bits<11> simm11; 240263509Sdim 241263509Sdim let Inst{10-0} = simm11; 242263509Sdim let Inst{11} = cc{0}; 243263509Sdim let Inst{12} = cc{1}; 244263509Sdim let Inst{13} = 1; 245263509Sdim let Inst{17-14} = cond; 246263509Sdim let Inst{18} = cc{2}; 247263509Sdim} 248263509Sdim 249263509Sdimclass F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins, 250263509Sdim string asmstr, list<dag> pattern> 251263509Sdim : F4<op3, outs, ins, asmstr, pattern> { 252263509Sdim bits<4> cond; 253263509Sdim bits<3> opf_cc; 254263509Sdim bits<5> rs2; 255263509Sdim 256263509Sdim let Inst{18} = 0; 257263509Sdim let Inst{17-14} = cond; 258263509Sdim let Inst{13-11} = opf_cc; 259263509Sdim let Inst{10-5} = opf_low; 260263509Sdim let Inst{4-0} = rs2; 261263509Sdim} 262