PPCISelLowering.h revision 263509
1251876Speter//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2251876Speter// 3251876Speter// The LLVM Compiler Infrastructure 4251876Speter// 5251876Speter// This file is distributed under the University of Illinois Open Source 6251876Speter// License. See LICENSE.TXT for details. 7251876Speter// 8251876Speter//===----------------------------------------------------------------------===// 9251876Speter// 10251876Speter// This file defines the interfaces that PPC uses to lower LLVM code into a 11251876Speter// selection DAG. 12251876Speter// 13251876Speter//===----------------------------------------------------------------------===// 14251876Speter 15251876Speter#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 16251876Speter#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 17251876Speter 18251876Speter#include "PPC.h" 19251876Speter#include "PPCInstrInfo.h" 20251876Speter#include "PPCRegisterInfo.h" 21251876Speter#include "PPCSubtarget.h" 22251876Speter#include "llvm/CodeGen/SelectionDAG.h" 23251876Speter#include "llvm/CodeGen/CallingConvLower.h" 24251876Speter#include "llvm/Target/TargetLowering.h" 25251876Speter 26251876Speternamespace llvm { 27251876Speter namespace PPCISD { 28251876Speter enum NodeType { 29251876Speter // Start the numbering where the builtin ops and target ops leave off. 30251876Speter FIRST_NUMBER = ISD::BUILTIN_OP_END, 31251876Speter 32251876Speter /// FSEL - Traditional three-operand fsel node. 33251876Speter /// 34251876Speter FSEL, 35251876Speter 36251876Speter /// FCFID - The FCFID instruction, taking an f64 operand and producing 37251876Speter /// and f64 value containing the FP representation of the integer that 38251876Speter /// was temporarily in the f64 operand. 39251876Speter FCFID, 40251876Speter 41251876Speter /// Newer FCFID[US] integer-to-floating-point conversion instructions for 42251876Speter /// unsigned integers and single-precision outputs. 43251876Speter FCFIDU, FCFIDS, FCFIDUS, 44251876Speter 45251876Speter /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 46251876Speter /// operand, producing an f64 value containing the integer representation 47251876Speter /// of that FP value. 48251876Speter FCTIDZ, FCTIWZ, 49251876Speter 50251876Speter /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 51251876Speter /// unsigned integers. 52251876Speter FCTIDUZ, FCTIWUZ, 53251876Speter 54251876Speter /// Reciprocal estimate instructions (unary FP ops). 55251876Speter FRE, FRSQRTE, 56251876Speter 57251876Speter // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 58251876Speter // three v4f32 operands and producing a v4f32 result. 59251876Speter VMADDFP, VNMSUBFP, 60251876Speter 61251876Speter /// VPERM - The PPC VPERM Instruction. 62251876Speter /// 63251876Speter VPERM, 64251876Speter 65251876Speter /// Hi/Lo - These represent the high and low 16-bit parts of a global 66251876Speter /// address respectively. These nodes have two operands, the first of 67251876Speter /// which must be a TargetGlobalAddress, and the second of which must be a 68251876Speter /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 69251876Speter /// though these are usually folded into other nodes. 70251876Speter Hi, Lo, 71251876Speter 72251876Speter TOC_ENTRY, 73251876Speter 74251876Speter /// The following three target-specific nodes are used for calls through 75251876Speter /// function pointers in the 64-bit SVR4 ABI. 76251876Speter 77251876Speter /// Restore the TOC from the TOC save area of the current stack frame. 78251876Speter /// This is basically a hard coded load instruction which additionally 79251876Speter /// takes/produces a flag. 80251876Speter TOC_RESTORE, 81251876Speter 82251876Speter /// Like a regular LOAD but additionally taking/producing a flag. 83251876Speter LOAD, 84251876Speter 85251876Speter /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is 86251876Speter /// a hard coded load instruction. 87251876Speter LOAD_TOC, 88251876Speter 89251876Speter /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 90251876Speter /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 91251876Speter /// compute an allocation on the stack. 92251876Speter DYNALLOC, 93251876Speter 94251876Speter /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 95251876Speter /// at function entry, used for PIC code. 96251876Speter GlobalBaseReg, 97251876Speter 98251876Speter /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 99251876Speter /// shift amounts. These nodes are generated by the multi-precision shift 100251876Speter /// code. 101251876Speter SRL, SRA, SHL, 102251876Speter 103251876Speter /// CALL - A direct function call. 104251876Speter /// CALL_NOP is a call with the special NOP which follows 64-bit 105251876Speter /// SVR4 calls. 106251876Speter CALL, CALL_NOP, 107251876Speter 108251876Speter /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 109251876Speter /// MTCTR instruction. 110251876Speter MTCTR, 111251876Speter 112251876Speter /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 113251876Speter /// BCTRL instruction. 114251876Speter BCTRL, 115251876Speter 116251876Speter /// Return with a flag operand, matched by 'blr' 117251876Speter RET_FLAG, 118251876Speter 119251876Speter /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 120251876Speter /// This copies the bits corresponding to the specified CRREG into the 121251876Speter /// resultant GPR. Bits corresponding to other CR regs are undefined. 122251876Speter MFOCRF, 123251876Speter 124251876Speter // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 125251876Speter EH_SJLJ_SETJMP, 126251876Speter 127251876Speter // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 128251876Speter EH_SJLJ_LONGJMP, 129251876Speter 130251876Speter /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 131251876Speter /// instructions. For lack of better number, we use the opcode number 132251876Speter /// encoding for the OPC field to identify the compare. For example, 838 133251876Speter /// is VCMPGTSH. 134251876Speter VCMP, 135251876Speter 136251876Speter /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 137251876Speter /// altivec VCMP*o instructions. For lack of better number, we use the 138251876Speter /// opcode number encoding for the OPC field to identify the compare. For 139251876Speter /// example, 838 is VCMPGTSH. 140251876Speter VCMPo, 141251876Speter 142251876Speter /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 143251876Speter /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 144251876Speter /// condition register to branch on, OPC is the branch opcode to use (e.g. 145251876Speter /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 146251876Speter /// an optional input flag argument. 147251876Speter COND_BRANCH, 148251876Speter 149251876Speter /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 150251876Speter /// loops. 151251876Speter BDNZ, BDZ, 152251876Speter 153251876Speter /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 154251876Speter /// towards zero. Used only as part of the long double-to-int 155251876Speter /// conversion sequence. 156251876Speter FADDRTZ, 157251876Speter 158251876Speter /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 159251876Speter MFFS, 160251876Speter 161251876Speter /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and 162251876Speter /// reserve indexed. This is used to implement atomic operations. 163251876Speter LARX, 164251876Speter 165251876Speter /// STCX = This corresponds to PPC stcx. instrcution: store conditional 166251876Speter /// indexed. This is used to implement atomic operations. 167251876Speter STCX, 168251876Speter 169251876Speter /// TC_RETURN - A tail call return. 170251876Speter /// operand #0 chain 171251876Speter /// operand #1 callee (register or absolute) 172251876Speter /// operand #2 stack adjustment 173251876Speter /// operand #3 optional in flag 174251876Speter TC_RETURN, 175251876Speter 176251876Speter /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 177251876Speter CR6SET, 178251876Speter CR6UNSET, 179251876Speter 180251876Speter /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec 181251876Speter /// TLS model, produces an ADDIS8 instruction that adds the GOT 182251876Speter /// base to sym\@got\@tprel\@ha. 183251876Speter ADDIS_GOT_TPREL_HA, 184251876Speter 185251876Speter /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 186251876Speter /// TLS model, produces a LD instruction with base register G8RReg 187251876Speter /// and offset sym\@got\@tprel\@l. This completes the addition that 188251876Speter /// finds the offset of "sym" relative to the thread pointer. 189251876Speter LD_GOT_TPREL_L, 190251876Speter 191251876Speter /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 192251876Speter /// model, produces an ADD instruction that adds the contents of 193251876Speter /// G8RReg to the thread pointer. Symbol contains a relocation 194251876Speter /// sym\@tls which is to be replaced by the thread pointer and 195251876Speter /// identifies to the linker that the instruction is part of a 196251876Speter /// TLS sequence. 197251876Speter ADD_TLS, 198251876Speter 199251876Speter /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS 200251876Speter /// model, produces an ADDIS8 instruction that adds the GOT base 201251876Speter /// register to sym\@got\@tlsgd\@ha. 202251876Speter ADDIS_TLSGD_HA, 203251876Speter 204251876Speter /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 205251876Speter /// model, produces an ADDI8 instruction that adds G8RReg to 206251876Speter /// sym\@got\@tlsgd\@l. 207251876Speter ADDI_TLSGD_L, 208251876Speter 209251876Speter /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS 210251876Speter /// model, produces a call to __tls_get_addr(sym\@tlsgd). 211251876Speter GET_TLS_ADDR, 212251876Speter 213251876Speter /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS 214251876Speter /// model, produces an ADDIS8 instruction that adds the GOT base 215251876Speter /// register to sym\@got\@tlsld\@ha. 216251876Speter ADDIS_TLSLD_HA, 217251876Speter 218251876Speter /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 219251876Speter /// model, produces an ADDI8 instruction that adds G8RReg to 220251876Speter /// sym\@got\@tlsld\@l. 221251876Speter ADDI_TLSLD_L, 222251876Speter 223251876Speter /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS 224251876Speter /// model, produces a call to __tls_get_addr(sym\@tlsld). 225251876Speter GET_TLSLD_ADDR, 226251876Speter 227251876Speter /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the 228251876Speter /// local-dynamic TLS model, produces an ADDIS8 instruction 229251876Speter /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed 230251876Speter /// to tie this in place following a copy to %X3 from the result 231251876Speter /// of a GET_TLSLD_ADDR. 232251876Speter ADDIS_DTPREL_HA, 233251876Speter 234251876Speter /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 235251876Speter /// model, produces an ADDI8 instruction that adds G8RReg to 236251876Speter /// sym\@got\@dtprel\@l. 237251876Speter ADDI_DTPREL_L, 238251876Speter 239251876Speter /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 240251876Speter /// during instruction selection to optimize a BUILD_VECTOR into 241251876Speter /// operations on splats. This is necessary to avoid losing these 242251876Speter /// optimizations due to constant folding. 243251876Speter VADD_SPLAT, 244251876Speter 245251876Speter /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 246251876Speter /// operand identifies the operating system entry point. 247251876Speter SC, 248251876Speter 249251876Speter /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 250251876Speter /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 251251876Speter /// the GPRC input, then stores it through Ptr. Type can be either i16 or 252251876Speter /// i32. 253251876Speter STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 254251876Speter 255251876Speter /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 256251876Speter /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 257251876Speter /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 258251876Speter /// or i32. 259251876Speter LBRX, 260251876Speter 261251876Speter /// STFIWX - The STFIWX instruction. The first operand is an input token 262251876Speter /// chain, then an f64 value to store, then an address to store it to. 263251876Speter STFIWX, 264251876Speter 265251876Speter /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 266251876Speter /// load which sign-extends from a 32-bit integer value into the 267251876Speter /// destination 64-bit register. 268251876Speter LFIWAX, 269251876Speter 270251876Speter /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 271251876Speter /// load which zero-extends from a 32-bit integer value into the 272251876Speter /// destination 64-bit register. 273251876Speter LFIWZX, 274251876Speter 275251876Speter /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model, 276251876Speter /// produces an ADDIS8 instruction that adds the TOC base register to 277251876Speter /// sym\@toc\@ha. 278251876Speter ADDIS_TOC_HA, 279251876Speter 280251876Speter /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model, 281251876Speter /// produces a LD instruction with base register G8RReg and offset 282251876Speter /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 283251876Speter LD_TOC_L, 284251876Speter 285251876Speter /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces 286251876Speter /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l. 287251876Speter /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 288251876Speter ADDI_TOC_L 289251876Speter }; 290251876Speter } 291251876Speter 292251876Speter /// Define some predicates that are used for node matching. 293251876Speter namespace PPC { 294251876Speter /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 295251876Speter /// VPKUHUM instruction. 296251876Speter bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 297251876Speter 298251876Speter /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 299251876Speter /// VPKUWUM instruction. 300251876Speter bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 301251876Speter 302251876Speter /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 303251876Speter /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 304251876Speter bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 305251876Speter bool isUnary); 306251876Speter 307251876Speter /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 308251876Speter /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 309251876Speter bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 310251876Speter bool isUnary); 311251876Speter 312251876Speter /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 313251876Speter /// amount, otherwise return -1. 314251876Speter int isVSLDOIShuffleMask(SDNode *N, bool isUnary); 315251876Speter 316251876Speter /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 317251876Speter /// specifies a splat of a single element that is suitable for input to 318251876Speter /// VSPLTB/VSPLTH/VSPLTW. 319251876Speter bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 320251876Speter 321251876Speter /// isAllNegativeZeroVector - Returns true if all elements of build_vector 322251876Speter /// are -0.0. 323251876Speter bool isAllNegativeZeroVector(SDNode *N); 324251876Speter 325251876Speter /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 326251876Speter /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 327251876Speter unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); 328251876Speter 329251876Speter /// get_VSPLTI_elt - If this is a build_vector of constants which can be 330251876Speter /// formed by using a vspltis[bhw] instruction of the specified element 331251876Speter /// size, return the constant being splatted. The ByteSize field indicates 332251876Speter /// the number of bytes of each element [124] -> [bhw]. 333251876Speter SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 334251876Speter } 335251876Speter 336251876Speter class PPCTargetLowering : public TargetLowering { 337251876Speter const PPCSubtarget &PPCSubTarget; 338251876Speter 339251876Speter public: 340251876Speter explicit PPCTargetLowering(PPCTargetMachine &TM); 341251876Speter 342251876Speter /// getTargetNodeName() - This method returns the name of a target specific 343251876Speter /// DAG node. 344251876Speter virtual const char *getTargetNodeName(unsigned Opcode) const; 345251876Speter 346251876Speter virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 347251876Speter 348251876Speter /// getSetCCResultType - Return the ISD::SETCC ValueType 349251876Speter virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 350251876Speter 351251876Speter /// getPreIndexedAddressParts - returns true by value, base pointer and 352251876Speter /// offset pointer and addressing mode by reference if the node's address 353251876Speter /// can be legally represented as pre-indexed load / store address. 354251876Speter virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 355251876Speter SDValue &Offset, 356251876Speter ISD::MemIndexedMode &AM, 357251876Speter SelectionDAG &DAG) const; 358251876Speter 359251876Speter /// SelectAddressRegReg - Given the specified addressed, check to see if it 360251876Speter /// can be represented as an indexed [r+r] operation. Returns false if it 361251876Speter /// can be more efficiently represented with [r+imm]. 362251876Speter bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 363251876Speter SelectionDAG &DAG) const; 364251876Speter 365251876Speter /// SelectAddressRegImm - Returns true if the address N can be represented 366251876Speter /// by a base register plus a signed 16-bit displacement [r+imm], and if it 367251876Speter /// is not better represented as reg+reg. If Aligned is true, only accept 368251876Speter /// displacements suitable for STD and friends, i.e. multiples of 4. 369251876Speter bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 370251876Speter SelectionDAG &DAG, bool Aligned) const; 371251876Speter 372251876Speter /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 373251876Speter /// represented as an indexed [r+r] operation. 374251876Speter bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 375251876Speter SelectionDAG &DAG) const; 376251876Speter 377251876Speter Sched::Preference getSchedulingPreference(SDNode *N) const; 378251876Speter 379251876Speter /// LowerOperation - Provide custom lowering hooks for some operations. 380251876Speter /// 381251876Speter virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 382251876Speter 383251876Speter /// ReplaceNodeResults - Replace the results of node with an illegal result 384251876Speter /// type with new values built out of custom code. 385251876Speter /// 386251876Speter virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 387251876Speter SelectionDAG &DAG) const; 388251876Speter 389251876Speter virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 390251876Speter 391251876Speter virtual void computeMaskedBitsForTargetNode(const SDValue Op, 392251876Speter APInt &KnownZero, 393251876Speter APInt &KnownOne, 394251876Speter const SelectionDAG &DAG, 395251876Speter unsigned Depth = 0) const; 396251876Speter 397251876Speter virtual MachineBasicBlock * 398251876Speter EmitInstrWithCustomInserter(MachineInstr *MI, 399251876Speter MachineBasicBlock *MBB) const; 400251876Speter MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 401251876Speter MachineBasicBlock *MBB, bool is64Bit, 402251876Speter unsigned BinOpcode) const; 403251876Speter MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 404251876Speter MachineBasicBlock *MBB, 405251876Speter bool is8bit, unsigned Opcode) const; 406251876Speter 407251876Speter MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, 408251876Speter MachineBasicBlock *MBB) const; 409251876Speter 410251876Speter MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, 411251876Speter MachineBasicBlock *MBB) const; 412251876Speter 413251876Speter ConstraintType getConstraintType(const std::string &Constraint) const; 414251876Speter 415251876Speter /// Examine constraint string and operand type and determine a weight value. 416251876Speter /// The operand object must already have been set up with the operand type. 417251876Speter ConstraintWeight getSingleConstraintMatchWeight( 418251876Speter AsmOperandInfo &info, const char *constraint) const; 419251876Speter 420251876Speter std::pair<unsigned, const TargetRegisterClass*> 421251876Speter getRegForInlineAsmConstraint(const std::string &Constraint, 422251876Speter MVT VT) const; 423251876Speter 424251876Speter /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 425251876Speter /// function arguments in the caller parameter area. This is the actual 426251876Speter /// alignment, not its logarithm. 427251876Speter unsigned getByValTypeAlignment(Type *Ty) const; 428251876Speter 429251876Speter /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 430251876Speter /// vector. If it is invalid, don't add anything to Ops. 431251876Speter virtual void LowerAsmOperandForConstraint(SDValue Op, 432251876Speter std::string &Constraint, 433251876Speter std::vector<SDValue> &Ops, 434251876Speter SelectionDAG &DAG) const; 435251876Speter 436251876Speter /// isLegalAddressingMode - Return true if the addressing mode represented 437251876Speter /// by AM is legal for this target, for a load/store of the specified type. 438251876Speter virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 439251876Speter 440251876Speter virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 441251876Speter 442251876Speter /// getOptimalMemOpType - Returns the target specific optimal type for load 443251876Speter /// and store operations as a result of memset, memcpy, and memmove 444251876Speter /// lowering. If DstAlign is zero that means it's safe to destination 445251876Speter /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 446251876Speter /// means there isn't a need to check it against alignment requirement, 447251876Speter /// probably because the source does not need to be loaded. If 'IsMemset' is 448251876Speter /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 449251876Speter /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 450251876Speter /// source is constant so it does not need to be loaded. 451251876Speter /// It returns EVT::Other if the type should be determined using generic 452251876Speter /// target-independent logic. 453251876Speter virtual EVT 454251876Speter getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 455251876Speter bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 456251876Speter MachineFunction &MF) const; 457251876Speter 458251876Speter /// Is unaligned memory access allowed for the given type, and is it fast 459251876Speter /// relative to software emulation. 460251876Speter virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast = 0) const; 461251876Speter 462251876Speter /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 463251876Speter /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 464251876Speter /// expanded to FMAs when this method returns true, otherwise fmuladd is 465251876Speter /// expanded to fmul + fadd. 466251876Speter virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const; 467251876Speter 468251876Speter /// createFastISel - This method returns a target-specific FastISel object, 469251876Speter /// or null if the target does not support "fast" instruction selection. 470251876Speter virtual FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 471251876Speter const TargetLibraryInfo *LibInfo) const; 472251876Speter 473251876Speter private: 474251876Speter SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 475251876Speter SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 476251876Speter 477251876Speter bool 478251876Speter IsEligibleForTailCallOptimization(SDValue Callee, 479251876Speter CallingConv::ID CalleeCC, 480251876Speter bool isVarArg, 481251876Speter const SmallVectorImpl<ISD::InputArg> &Ins, 482251876Speter SelectionDAG& DAG) const; 483251876Speter 484251876Speter SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 485251876Speter int SPDiff, 486251876Speter SDValue Chain, 487251876Speter SDValue &LROpOut, 488251876Speter SDValue &FPOpOut, 489251876Speter bool isDarwinABI, 490251876Speter SDLoc dl) const; 491251876Speter 492251876Speter SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 493251876Speter SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 494251876Speter SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 495251876Speter SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 496251876Speter SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 497251876Speter SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 498251876Speter SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 499251876Speter SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 500251876Speter SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 501251876Speter SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 502251876Speter SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 503251876Speter const PPCSubtarget &Subtarget) const; 504251876Speter SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, 505251876Speter const PPCSubtarget &Subtarget) const; 506251876Speter SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG, 507251876Speter const PPCSubtarget &Subtarget) const; 508251876Speter SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 509251876Speter const PPCSubtarget &Subtarget) const; 510251876Speter SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 511251876Speter const PPCSubtarget &Subtarget) const; 512251876Speter SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 513251876Speter SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const; 514251876Speter SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 515251876Speter SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 516251876Speter SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 517251876Speter SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 518251876Speter SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 519251876Speter SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 520251876Speter SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 521251876Speter SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 522251876Speter SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 523251876Speter SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 524251876Speter 525251876Speter SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 526251876Speter CallingConv::ID CallConv, bool isVarArg, 527251876Speter const SmallVectorImpl<ISD::InputArg> &Ins, 528251876Speter SDLoc dl, SelectionDAG &DAG, 529251876Speter SmallVectorImpl<SDValue> &InVals) const; 530251876Speter SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall, 531251876Speter bool isVarArg, 532251876Speter SelectionDAG &DAG, 533251876Speter SmallVector<std::pair<unsigned, SDValue>, 8> 534251876Speter &RegsToPass, 535251876Speter SDValue InFlag, SDValue Chain, 536251876Speter SDValue &Callee, 537251876Speter int SPDiff, unsigned NumBytes, 538251876Speter const SmallVectorImpl<ISD::InputArg> &Ins, 539251876Speter SmallVectorImpl<SDValue> &InVals) const; 540251876Speter 541251876Speter virtual SDValue 542251876Speter LowerFormalArguments(SDValue Chain, 543251876Speter CallingConv::ID CallConv, bool isVarArg, 544251876Speter const SmallVectorImpl<ISD::InputArg> &Ins, 545251876Speter SDLoc dl, SelectionDAG &DAG, 546251876Speter SmallVectorImpl<SDValue> &InVals) const; 547251876Speter 548251876Speter virtual SDValue 549251876Speter LowerCall(TargetLowering::CallLoweringInfo &CLI, 550251876Speter SmallVectorImpl<SDValue> &InVals) const; 551251876Speter 552251876Speter virtual bool 553251876Speter CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 554251876Speter bool isVarArg, 555251876Speter const SmallVectorImpl<ISD::OutputArg> &Outs, 556251876Speter LLVMContext &Context) const; 557251876Speter 558251876Speter virtual SDValue 559251876Speter LowerReturn(SDValue Chain, 560251876Speter CallingConv::ID CallConv, bool isVarArg, 561251876Speter const SmallVectorImpl<ISD::OutputArg> &Outs, 562251876Speter const SmallVectorImpl<SDValue> &OutVals, 563251876Speter SDLoc dl, SelectionDAG &DAG) const; 564251876Speter 565251876Speter SDValue 566251876Speter extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, 567251876Speter SDValue ArgVal, SDLoc dl) const; 568251876Speter 569251876Speter void 570251876Speter setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG, 571251876Speter unsigned nAltivecParamsAtEnd, 572251876Speter unsigned MinReservedArea, bool isPPC64) const; 573251876Speter 574251876Speter SDValue 575251876Speter LowerFormalArguments_Darwin(SDValue Chain, 576251876Speter CallingConv::ID CallConv, bool isVarArg, 577251876Speter const SmallVectorImpl<ISD::InputArg> &Ins, 578251876Speter SDLoc dl, SelectionDAG &DAG, 579251876Speter SmallVectorImpl<SDValue> &InVals) const; 580251876Speter SDValue 581251876Speter LowerFormalArguments_64SVR4(SDValue Chain, 582251876Speter CallingConv::ID CallConv, bool isVarArg, 583251876Speter const SmallVectorImpl<ISD::InputArg> &Ins, 584251876Speter SDLoc dl, SelectionDAG &DAG, 585251876Speter SmallVectorImpl<SDValue> &InVals) const; 586251876Speter SDValue 587251876Speter LowerFormalArguments_32SVR4(SDValue Chain, 588251876Speter CallingConv::ID CallConv, bool isVarArg, 589251876Speter const SmallVectorImpl<ISD::InputArg> &Ins, 590251876Speter SDLoc dl, SelectionDAG &DAG, 591251876Speter SmallVectorImpl<SDValue> &InVals) const; 592251876Speter 593251876Speter SDValue 594251876Speter createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 595251876Speter SDValue CallSeqStart, ISD::ArgFlagsTy Flags, 596251876Speter SelectionDAG &DAG, SDLoc dl) const; 597251876Speter 598251876Speter SDValue 599251876Speter LowerCall_Darwin(SDValue Chain, SDValue Callee, 600251876Speter CallingConv::ID CallConv, 601251876Speter bool isVarArg, bool isTailCall, 602251876Speter const SmallVectorImpl<ISD::OutputArg> &Outs, 603251876Speter const SmallVectorImpl<SDValue> &OutVals, 604251876Speter const SmallVectorImpl<ISD::InputArg> &Ins, 605251876Speter SDLoc dl, SelectionDAG &DAG, 606251876Speter SmallVectorImpl<SDValue> &InVals) const; 607251876Speter SDValue 608251876Speter LowerCall_64SVR4(SDValue Chain, SDValue Callee, 609251876Speter CallingConv::ID CallConv, 610251876Speter bool isVarArg, bool isTailCall, 611251876Speter const SmallVectorImpl<ISD::OutputArg> &Outs, 612251876Speter const SmallVectorImpl<SDValue> &OutVals, 613251876Speter const SmallVectorImpl<ISD::InputArg> &Ins, 614251876Speter SDLoc dl, SelectionDAG &DAG, 615251876Speter SmallVectorImpl<SDValue> &InVals) const; 616251876Speter SDValue 617251876Speter LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, 618251876Speter bool isVarArg, bool isTailCall, 619251876Speter const SmallVectorImpl<ISD::OutputArg> &Outs, 620251876Speter const SmallVectorImpl<SDValue> &OutVals, 621251876Speter const SmallVectorImpl<ISD::InputArg> &Ins, 622251876Speter SDLoc dl, SelectionDAG &DAG, 623251876Speter SmallVectorImpl<SDValue> &InVals) const; 624251876Speter 625251876Speter SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 626251876Speter SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 627251876Speter 628251876Speter SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const; 629251876Speter SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const; 630251876Speter 631251876Speter CCAssignFn *useFastISelCCs(unsigned Flag) const; 632251876Speter }; 633251876Speter 634251876Speter namespace PPC { 635251876Speter FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 636251876Speter const TargetLibraryInfo *LibInfo); 637251876Speter } 638 639 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 640 CCValAssign::LocInfo &LocInfo, 641 ISD::ArgFlagsTy &ArgFlags, 642 CCState &State); 643 644 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 645 MVT &LocVT, 646 CCValAssign::LocInfo &LocInfo, 647 ISD::ArgFlagsTy &ArgFlags, 648 CCState &State); 649 650 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 651 MVT &LocVT, 652 CCValAssign::LocInfo &LocInfo, 653 ISD::ArgFlagsTy &ArgFlags, 654 CCState &State); 655} 656 657#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 658