PPCISelLowering.h revision 252723
1//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that PPC uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 16#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 17 18#include "PPC.h" 19#include "PPCInstrInfo.h" 20#include "PPCRegisterInfo.h" 21#include "PPCSubtarget.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/Target/TargetLowering.h" 24 25namespace llvm { 26 namespace PPCISD { 27 enum NodeType { 28 // Start the numbering where the builtin ops and target ops leave off. 29 FIRST_NUMBER = ISD::BUILTIN_OP_END, 30 31 /// FSEL - Traditional three-operand fsel node. 32 /// 33 FSEL, 34 35 /// FCFID - The FCFID instruction, taking an f64 operand and producing 36 /// and f64 value containing the FP representation of the integer that 37 /// was temporarily in the f64 operand. 38 FCFID, 39 40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 41 /// unsigned integers and single-precision outputs. 42 FCFIDU, FCFIDS, FCFIDUS, 43 44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 45 /// operand, producing an f64 value containing the integer representation 46 /// of that FP value. 47 FCTIDZ, FCTIWZ, 48 49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 50 /// unsigned integers. 51 FCTIDUZ, FCTIWUZ, 52 53 /// Reciprocal estimate instructions (unary FP ops). 54 FRE, FRSQRTE, 55 56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 57 // three v4f32 operands and producing a v4f32 result. 58 VMADDFP, VNMSUBFP, 59 60 /// VPERM - The PPC VPERM Instruction. 61 /// 62 VPERM, 63 64 /// Hi/Lo - These represent the high and low 16-bit parts of a global 65 /// address respectively. These nodes have two operands, the first of 66 /// which must be a TargetGlobalAddress, and the second of which must be a 67 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 68 /// though these are usually folded into other nodes. 69 Hi, Lo, 70 71 TOC_ENTRY, 72 73 /// The following three target-specific nodes are used for calls through 74 /// function pointers in the 64-bit SVR4 ABI. 75 76 /// Restore the TOC from the TOC save area of the current stack frame. 77 /// This is basically a hard coded load instruction which additionally 78 /// takes/produces a flag. 79 TOC_RESTORE, 80 81 /// Like a regular LOAD but additionally taking/producing a flag. 82 LOAD, 83 84 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is 85 /// a hard coded load instruction. 86 LOAD_TOC, 87 88 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 89 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 90 /// compute an allocation on the stack. 91 DYNALLOC, 92 93 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 94 /// at function entry, used for PIC code. 95 GlobalBaseReg, 96 97 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 98 /// shift amounts. These nodes are generated by the multi-precision shift 99 /// code. 100 SRL, SRA, SHL, 101 102 /// CALL - A direct function call. 103 /// CALL_NOP is a call with the special NOP which follows 64-bit 104 /// SVR4 calls. 105 CALL, CALL_NOP, 106 107 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 108 /// MTCTR instruction. 109 MTCTR, 110 111 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 112 /// BCTRL instruction. 113 BCTRL, 114 115 /// Return with a flag operand, matched by 'blr' 116 RET_FLAG, 117 118 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF 119 /// instructions. This copies the bits corresponding to the specified 120 /// CRREG into the resultant GPR. Bits corresponding to other CR regs 121 /// are undefined. 122 MFCR, 123 124 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 125 EH_SJLJ_SETJMP, 126 127 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 128 EH_SJLJ_LONGJMP, 129 130 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 131 /// instructions. For lack of better number, we use the opcode number 132 /// encoding for the OPC field to identify the compare. For example, 838 133 /// is VCMPGTSH. 134 VCMP, 135 136 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 137 /// altivec VCMP*o instructions. For lack of better number, we use the 138 /// opcode number encoding for the OPC field to identify the compare. For 139 /// example, 838 is VCMPGTSH. 140 VCMPo, 141 142 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 143 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 144 /// condition register to branch on, OPC is the branch opcode to use (e.g. 145 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 146 /// an optional input flag argument. 147 COND_BRANCH, 148 149 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 150 /// towards zero. Used only as part of the long double-to-int 151 /// conversion sequence. 152 FADDRTZ, 153 154 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 155 MFFS, 156 157 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and 158 /// reserve indexed. This is used to implement atomic operations. 159 LARX, 160 161 /// STCX = This corresponds to PPC stcx. instrcution: store conditional 162 /// indexed. This is used to implement atomic operations. 163 STCX, 164 165 /// TC_RETURN - A tail call return. 166 /// operand #0 chain 167 /// operand #1 callee (register or absolute) 168 /// operand #2 stack adjustment 169 /// operand #3 optional in flag 170 TC_RETURN, 171 172 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 173 CR6SET, 174 CR6UNSET, 175 176 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec 177 /// TLS model, produces an ADDIS8 instruction that adds the GOT 178 /// base to sym@got@tprel@ha. 179 ADDIS_GOT_TPREL_HA, 180 181 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 182 /// TLS model, produces a LD instruction with base register G8RReg 183 /// and offset sym@got@tprel@l. This completes the addition that 184 /// finds the offset of "sym" relative to the thread pointer. 185 LD_GOT_TPREL_L, 186 187 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 188 /// model, produces an ADD instruction that adds the contents of 189 /// G8RReg to the thread pointer. Symbol contains a relocation 190 /// sym@tls which is to be replaced by the thread pointer and 191 /// identifies to the linker that the instruction is part of a 192 /// TLS sequence. 193 ADD_TLS, 194 195 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS 196 /// model, produces an ADDIS8 instruction that adds the GOT base 197 /// register to sym@got@tlsgd@ha. 198 ADDIS_TLSGD_HA, 199 200 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 201 /// model, produces an ADDI8 instruction that adds G8RReg to 202 /// sym@got@tlsgd@l. 203 ADDI_TLSGD_L, 204 205 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS 206 /// model, produces a call to __tls_get_addr(sym@tlsgd). 207 GET_TLS_ADDR, 208 209 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS 210 /// model, produces an ADDIS8 instruction that adds the GOT base 211 /// register to sym@got@tlsld@ha. 212 ADDIS_TLSLD_HA, 213 214 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 215 /// model, produces an ADDI8 instruction that adds G8RReg to 216 /// sym@got@tlsld@l. 217 ADDI_TLSLD_L, 218 219 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS 220 /// model, produces a call to __tls_get_addr(sym@tlsld). 221 GET_TLSLD_ADDR, 222 223 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the 224 /// local-dynamic TLS model, produces an ADDIS8 instruction 225 /// that adds X3 to sym@dtprel@ha. The Chain operand is needed 226 /// to tie this in place following a copy to %X3 from the result 227 /// of a GET_TLSLD_ADDR. 228 ADDIS_DTPREL_HA, 229 230 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 231 /// model, produces an ADDI8 instruction that adds G8RReg to 232 /// sym@got@dtprel@l. 233 ADDI_DTPREL_L, 234 235 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 236 /// during instruction selection to optimize a BUILD_VECTOR into 237 /// operations on splats. This is necessary to avoid losing these 238 /// optimizations due to constant folding. 239 VADD_SPLAT, 240 241 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 242 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 243 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 244 /// i32. 245 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 246 247 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 248 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 249 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 250 /// or i32. 251 LBRX, 252 253 /// STFIWX - The STFIWX instruction. The first operand is an input token 254 /// chain, then an f64 value to store, then an address to store it to. 255 STFIWX, 256 257 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 258 /// load which sign-extends from a 32-bit integer value into the 259 /// destination 64-bit register. 260 LFIWAX, 261 262 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 263 /// load which zero-extends from a 32-bit integer value into the 264 /// destination 64-bit register. 265 LFIWZX, 266 267 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model, 268 /// produces an ADDIS8 instruction that adds the TOC base register to 269 /// sym@toc@ha. 270 ADDIS_TOC_HA, 271 272 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model, 273 /// produces a LD instruction with base register G8RReg and offset 274 /// sym@toc@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 275 LD_TOC_L, 276 277 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces 278 /// an ADDI8 instruction that adds G8RReg to sym@toc@l. 279 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 280 ADDI_TOC_L 281 }; 282 } 283 284 /// Define some predicates that are used for node matching. 285 namespace PPC { 286 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 287 /// VPKUHUM instruction. 288 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 289 290 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 291 /// VPKUWUM instruction. 292 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 293 294 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 295 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 296 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 297 bool isUnary); 298 299 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 300 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 301 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 302 bool isUnary); 303 304 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 305 /// amount, otherwise return -1. 306 int isVSLDOIShuffleMask(SDNode *N, bool isUnary); 307 308 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 309 /// specifies a splat of a single element that is suitable for input to 310 /// VSPLTB/VSPLTH/VSPLTW. 311 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 312 313 /// isAllNegativeZeroVector - Returns true if all elements of build_vector 314 /// are -0.0. 315 bool isAllNegativeZeroVector(SDNode *N); 316 317 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 318 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 319 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); 320 321 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 322 /// formed by using a vspltis[bhw] instruction of the specified element 323 /// size, return the constant being splatted. The ByteSize field indicates 324 /// the number of bytes of each element [124] -> [bhw]. 325 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 326 } 327 328 class PPCTargetLowering : public TargetLowering { 329 const PPCSubtarget &PPCSubTarget; 330 const PPCRegisterInfo *PPCRegInfo; 331 const PPCInstrInfo *PPCII; 332 333 public: 334 explicit PPCTargetLowering(PPCTargetMachine &TM); 335 336 /// getTargetNodeName() - This method returns the name of a target specific 337 /// DAG node. 338 virtual const char *getTargetNodeName(unsigned Opcode) const; 339 340 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 341 342 /// getSetCCResultType - Return the ISD::SETCC ValueType 343 virtual EVT getSetCCResultType(EVT VT) const; 344 345 /// getPreIndexedAddressParts - returns true by value, base pointer and 346 /// offset pointer and addressing mode by reference if the node's address 347 /// can be legally represented as pre-indexed load / store address. 348 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 349 SDValue &Offset, 350 ISD::MemIndexedMode &AM, 351 SelectionDAG &DAG) const; 352 353 /// SelectAddressRegReg - Given the specified addressed, check to see if it 354 /// can be represented as an indexed [r+r] operation. Returns false if it 355 /// can be more efficiently represented with [r+imm]. 356 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 357 SelectionDAG &DAG) const; 358 359 /// SelectAddressRegImm - Returns true if the address N can be represented 360 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 361 /// is not better represented as reg+reg. 362 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 363 SelectionDAG &DAG) const; 364 365 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 366 /// represented as an indexed [r+r] operation. 367 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 368 SelectionDAG &DAG) const; 369 370 /// SelectAddressRegImmShift - Returns true if the address N can be 371 /// represented by a base register plus a signed 14-bit displacement 372 /// [r+imm*4]. Suitable for use by STD and friends. 373 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base, 374 SelectionDAG &DAG) const; 375 376 Sched::Preference getSchedulingPreference(SDNode *N) const; 377 378 /// LowerOperation - Provide custom lowering hooks for some operations. 379 /// 380 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 381 382 /// ReplaceNodeResults - Replace the results of node with an illegal result 383 /// type with new values built out of custom code. 384 /// 385 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 386 SelectionDAG &DAG) const; 387 388 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 389 390 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 391 APInt &KnownZero, 392 APInt &KnownOne, 393 const SelectionDAG &DAG, 394 unsigned Depth = 0) const; 395 396 virtual MachineBasicBlock * 397 EmitInstrWithCustomInserter(MachineInstr *MI, 398 MachineBasicBlock *MBB) const; 399 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 400 MachineBasicBlock *MBB, bool is64Bit, 401 unsigned BinOpcode) const; 402 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 403 MachineBasicBlock *MBB, 404 bool is8bit, unsigned Opcode) const; 405 406 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, 407 MachineBasicBlock *MBB) const; 408 409 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, 410 MachineBasicBlock *MBB) const; 411 412 ConstraintType getConstraintType(const std::string &Constraint) const; 413 414 /// Examine constraint string and operand type and determine a weight value. 415 /// The operand object must already have been set up with the operand type. 416 ConstraintWeight getSingleConstraintMatchWeight( 417 AsmOperandInfo &info, const char *constraint) const; 418 419 std::pair<unsigned, const TargetRegisterClass*> 420 getRegForInlineAsmConstraint(const std::string &Constraint, 421 EVT VT) const; 422 423 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 424 /// function arguments in the caller parameter area. This is the actual 425 /// alignment, not its logarithm. 426 unsigned getByValTypeAlignment(Type *Ty) const; 427 428 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 429 /// vector. If it is invalid, don't add anything to Ops. 430 virtual void LowerAsmOperandForConstraint(SDValue Op, 431 std::string &Constraint, 432 std::vector<SDValue> &Ops, 433 SelectionDAG &DAG) const; 434 435 /// isLegalAddressingMode - Return true if the addressing mode represented 436 /// by AM is legal for this target, for a load/store of the specified type. 437 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 438 439 /// isLegalAddressImmediate - Return true if the integer value can be used 440 /// as the offset of the target addressing mode for load / store of the 441 /// given type. 442 virtual bool isLegalAddressImmediate(int64_t V, Type *Ty) const; 443 444 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as 445 /// the offset of the target addressing mode. 446 virtual bool isLegalAddressImmediate(GlobalValue *GV) const; 447 448 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 449 450 /// getOptimalMemOpType - Returns the target specific optimal type for load 451 /// and store operations as a result of memset, memcpy, and memmove 452 /// lowering. If DstAlign is zero that means it's safe to destination 453 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 454 /// means there isn't a need to check it against alignment requirement, 455 /// probably because the source does not need to be loaded. If 'IsMemset' is 456 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 457 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 458 /// source is constant so it does not need to be loaded. 459 /// It returns EVT::Other if the type should be determined using generic 460 /// target-independent logic. 461 virtual EVT 462 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 463 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 464 MachineFunction &MF) const; 465 466 /// Is unaligned memory access allowed for the given type, and is it fast 467 /// relative to software emulation. 468 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast = 0) const; 469 470 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 471 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 472 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 473 /// is expanded to mul + add. 474 virtual bool isFMAFasterThanMulAndAdd(EVT VT) const; 475 476 private: 477 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 478 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 479 480 bool 481 IsEligibleForTailCallOptimization(SDValue Callee, 482 CallingConv::ID CalleeCC, 483 bool isVarArg, 484 const SmallVectorImpl<ISD::InputArg> &Ins, 485 SelectionDAG& DAG) const; 486 487 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 488 int SPDiff, 489 SDValue Chain, 490 SDValue &LROpOut, 491 SDValue &FPOpOut, 492 bool isDarwinABI, 493 DebugLoc dl) const; 494 495 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 496 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 497 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 498 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 499 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 500 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 501 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 502 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 503 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 504 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 505 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 506 const PPCSubtarget &Subtarget) const; 507 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, 508 const PPCSubtarget &Subtarget) const; 509 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 510 const PPCSubtarget &Subtarget) const; 511 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 512 const PPCSubtarget &Subtarget) const; 513 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 514 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const; 515 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 516 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 517 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 518 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 519 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 520 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 521 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 522 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 523 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 524 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 525 526 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 527 CallingConv::ID CallConv, bool isVarArg, 528 const SmallVectorImpl<ISD::InputArg> &Ins, 529 DebugLoc dl, SelectionDAG &DAG, 530 SmallVectorImpl<SDValue> &InVals) const; 531 SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall, 532 bool isVarArg, 533 SelectionDAG &DAG, 534 SmallVector<std::pair<unsigned, SDValue>, 8> 535 &RegsToPass, 536 SDValue InFlag, SDValue Chain, 537 SDValue &Callee, 538 int SPDiff, unsigned NumBytes, 539 const SmallVectorImpl<ISD::InputArg> &Ins, 540 SmallVectorImpl<SDValue> &InVals) const; 541 542 virtual SDValue 543 LowerFormalArguments(SDValue Chain, 544 CallingConv::ID CallConv, bool isVarArg, 545 const SmallVectorImpl<ISD::InputArg> &Ins, 546 DebugLoc dl, SelectionDAG &DAG, 547 SmallVectorImpl<SDValue> &InVals) const; 548 549 virtual SDValue 550 LowerCall(TargetLowering::CallLoweringInfo &CLI, 551 SmallVectorImpl<SDValue> &InVals) const; 552 553 virtual bool 554 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 555 bool isVarArg, 556 const SmallVectorImpl<ISD::OutputArg> &Outs, 557 LLVMContext &Context) const; 558 559 virtual SDValue 560 LowerReturn(SDValue Chain, 561 CallingConv::ID CallConv, bool isVarArg, 562 const SmallVectorImpl<ISD::OutputArg> &Outs, 563 const SmallVectorImpl<SDValue> &OutVals, 564 DebugLoc dl, SelectionDAG &DAG) const; 565 566 SDValue 567 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, 568 SDValue ArgVal, DebugLoc dl) const; 569 570 void 571 setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG, 572 unsigned nAltivecParamsAtEnd, 573 unsigned MinReservedArea, bool isPPC64) const; 574 575 SDValue 576 LowerFormalArguments_Darwin(SDValue Chain, 577 CallingConv::ID CallConv, bool isVarArg, 578 const SmallVectorImpl<ISD::InputArg> &Ins, 579 DebugLoc dl, SelectionDAG &DAG, 580 SmallVectorImpl<SDValue> &InVals) const; 581 SDValue 582 LowerFormalArguments_64SVR4(SDValue Chain, 583 CallingConv::ID CallConv, bool isVarArg, 584 const SmallVectorImpl<ISD::InputArg> &Ins, 585 DebugLoc dl, SelectionDAG &DAG, 586 SmallVectorImpl<SDValue> &InVals) const; 587 SDValue 588 LowerFormalArguments_32SVR4(SDValue Chain, 589 CallingConv::ID CallConv, bool isVarArg, 590 const SmallVectorImpl<ISD::InputArg> &Ins, 591 DebugLoc dl, SelectionDAG &DAG, 592 SmallVectorImpl<SDValue> &InVals) const; 593 594 SDValue 595 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 596 SDValue CallSeqStart, ISD::ArgFlagsTy Flags, 597 SelectionDAG &DAG, DebugLoc dl) const; 598 599 SDValue 600 LowerCall_Darwin(SDValue Chain, SDValue Callee, 601 CallingConv::ID CallConv, 602 bool isVarArg, bool isTailCall, 603 const SmallVectorImpl<ISD::OutputArg> &Outs, 604 const SmallVectorImpl<SDValue> &OutVals, 605 const SmallVectorImpl<ISD::InputArg> &Ins, 606 DebugLoc dl, SelectionDAG &DAG, 607 SmallVectorImpl<SDValue> &InVals) const; 608 SDValue 609 LowerCall_64SVR4(SDValue Chain, SDValue Callee, 610 CallingConv::ID CallConv, 611 bool isVarArg, bool isTailCall, 612 const SmallVectorImpl<ISD::OutputArg> &Outs, 613 const SmallVectorImpl<SDValue> &OutVals, 614 const SmallVectorImpl<ISD::InputArg> &Ins, 615 DebugLoc dl, SelectionDAG &DAG, 616 SmallVectorImpl<SDValue> &InVals) const; 617 SDValue 618 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, 619 bool isVarArg, bool isTailCall, 620 const SmallVectorImpl<ISD::OutputArg> &Outs, 621 const SmallVectorImpl<SDValue> &OutVals, 622 const SmallVectorImpl<ISD::InputArg> &Ins, 623 DebugLoc dl, SelectionDAG &DAG, 624 SmallVectorImpl<SDValue> &InVals) const; 625 626 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 627 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 628 629 SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const; 630 SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const; 631 }; 632} 633 634#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 635