1193323Sed//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines the interfaces that PPC uses to lower LLVM code into a 11193323Sed// selection DAG. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 16193323Sed#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 17193323Sed 18235633Sdim#include "PPC.h" 19252723Sdim#include "PPCInstrInfo.h" 20252723Sdim#include "PPCRegisterInfo.h" 21235633Sdim#include "PPCSubtarget.h" 22252723Sdim#include "llvm/CodeGen/SelectionDAG.h" 23263509Sdim#include "llvm/CodeGen/CallingConvLower.h" 24193323Sed#include "llvm/Target/TargetLowering.h" 25193323Sed 26193323Sednamespace llvm { 27193323Sed namespace PPCISD { 28193323Sed enum NodeType { 29193323Sed // Start the numbering where the builtin ops and target ops leave off. 30193323Sed FIRST_NUMBER = ISD::BUILTIN_OP_END, 31193323Sed 32193323Sed /// FSEL - Traditional three-operand fsel node. 33193323Sed /// 34193323Sed FSEL, 35219077Sdim 36193323Sed /// FCFID - The FCFID instruction, taking an f64 operand and producing 37193323Sed /// and f64 value containing the FP representation of the integer that 38193323Sed /// was temporarily in the f64 operand. 39193323Sed FCFID, 40219077Sdim 41252723Sdim /// Newer FCFID[US] integer-to-floating-point conversion instructions for 42252723Sdim /// unsigned integers and single-precision outputs. 43252723Sdim FCFIDU, FCFIDS, FCFIDUS, 44252723Sdim 45219077Sdim /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 46193323Sed /// operand, producing an f64 value containing the integer representation 47193323Sed /// of that FP value. 48193323Sed FCTIDZ, FCTIWZ, 49219077Sdim 50252723Sdim /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 51252723Sdim /// unsigned integers. 52252723Sdim FCTIDUZ, FCTIWUZ, 53219077Sdim 54252723Sdim /// Reciprocal estimate instructions (unary FP ops). 55252723Sdim FRE, FRSQRTE, 56252723Sdim 57193323Sed // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 58193323Sed // three v4f32 operands and producing a v4f32 result. 59193323Sed VMADDFP, VNMSUBFP, 60219077Sdim 61193323Sed /// VPERM - The PPC VPERM Instruction. 62193323Sed /// 63193323Sed VPERM, 64219077Sdim 65193323Sed /// Hi/Lo - These represent the high and low 16-bit parts of a global 66193323Sed /// address respectively. These nodes have two operands, the first of 67193323Sed /// which must be a TargetGlobalAddress, and the second of which must be a 68193323Sed /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 69193323Sed /// though these are usually folded into other nodes. 70193323Sed Hi, Lo, 71219077Sdim 72198090Srdivacky TOC_ENTRY, 73198090Srdivacky 74201360Srdivacky /// The following three target-specific nodes are used for calls through 75201360Srdivacky /// function pointers in the 64-bit SVR4 ABI. 76201360Srdivacky 77201360Srdivacky /// Restore the TOC from the TOC save area of the current stack frame. 78201360Srdivacky /// This is basically a hard coded load instruction which additionally 79201360Srdivacky /// takes/produces a flag. 80201360Srdivacky TOC_RESTORE, 81201360Srdivacky 82201360Srdivacky /// Like a regular LOAD but additionally taking/producing a flag. 83201360Srdivacky LOAD, 84201360Srdivacky 85201360Srdivacky /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is 86201360Srdivacky /// a hard coded load instruction. 87201360Srdivacky LOAD_TOC, 88201360Srdivacky 89193323Sed /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 90193323Sed /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 91193323Sed /// compute an allocation on the stack. 92193323Sed DYNALLOC, 93219077Sdim 94193323Sed /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 95193323Sed /// at function entry, used for PIC code. 96193323Sed GlobalBaseReg, 97219077Sdim 98193323Sed /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 99193323Sed /// shift amounts. These nodes are generated by the multi-precision shift 100193323Sed /// code. 101193323Sed SRL, SRA, SHL, 102219077Sdim 103193323Sed /// CALL - A direct function call. 104252723Sdim /// CALL_NOP is a call with the special NOP which follows 64-bit 105235633Sdim /// SVR4 calls. 106252723Sdim CALL, CALL_NOP, 107219077Sdim 108193323Sed /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 109193323Sed /// MTCTR instruction. 110193323Sed MTCTR, 111219077Sdim 112193323Sed /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 113193323Sed /// BCTRL instruction. 114252723Sdim BCTRL, 115219077Sdim 116193323Sed /// Return with a flag operand, matched by 'blr' 117193323Sed RET_FLAG, 118219077Sdim 119263509Sdim /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 120263509Sdim /// This copies the bits corresponding to the specified CRREG into the 121263509Sdim /// resultant GPR. Bits corresponding to other CR regs are undefined. 122263509Sdim MFOCRF, 123193323Sed 124252723Sdim // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 125252723Sdim EH_SJLJ_SETJMP, 126252723Sdim 127252723Sdim // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 128252723Sdim EH_SJLJ_LONGJMP, 129252723Sdim 130193323Sed /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 131193323Sed /// instructions. For lack of better number, we use the opcode number 132193323Sed /// encoding for the OPC field to identify the compare. For example, 838 133193323Sed /// is VCMPGTSH. 134193323Sed VCMP, 135219077Sdim 136193323Sed /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 137219077Sdim /// altivec VCMP*o instructions. For lack of better number, we use the 138193323Sed /// opcode number encoding for the OPC field to identify the compare. For 139193323Sed /// example, 838 is VCMPGTSH. 140193323Sed VCMPo, 141219077Sdim 142193323Sed /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 143193323Sed /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 144193323Sed /// condition register to branch on, OPC is the branch opcode to use (e.g. 145193323Sed /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 146193323Sed /// an optional input flag argument. 147193323Sed COND_BRANCH, 148219077Sdim 149263509Sdim /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 150263509Sdim /// loops. 151263509Sdim BDNZ, BDZ, 152263509Sdim 153252723Sdim /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 154252723Sdim /// towards zero. Used only as part of the long double-to-int 155252723Sdim /// conversion sequence. 156252723Sdim FADDRTZ, 157193323Sed 158252723Sdim /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 159193323Sed MFFS, 160193323Sed 161193323Sed /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and 162193323Sed /// reserve indexed. This is used to implement atomic operations. 163193323Sed LARX, 164193323Sed 165193323Sed /// STCX = This corresponds to PPC stcx. instrcution: store conditional 166193323Sed /// indexed. This is used to implement atomic operations. 167193323Sed STCX, 168193323Sed 169193323Sed /// TC_RETURN - A tail call return. 170193323Sed /// operand #0 chain 171193323Sed /// operand #1 callee (register or absolute) 172193323Sed /// operand #2 stack adjustment 173193323Sed /// operand #3 optional in flag 174198090Srdivacky TC_RETURN, 175198090Srdivacky 176245431Sdim /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 177245431Sdim CR6SET, 178245431Sdim CR6UNSET, 179245431Sdim 180252723Sdim /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec 181252723Sdim /// TLS model, produces an ADDIS8 instruction that adds the GOT 182263509Sdim /// base to sym\@got\@tprel\@ha. 183252723Sdim ADDIS_GOT_TPREL_HA, 184219077Sdim 185252723Sdim /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 186252723Sdim /// TLS model, produces a LD instruction with base register G8RReg 187263509Sdim /// and offset sym\@got\@tprel\@l. This completes the addition that 188252723Sdim /// finds the offset of "sym" relative to the thread pointer. 189252723Sdim LD_GOT_TPREL_L, 190252723Sdim 191252723Sdim /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 192252723Sdim /// model, produces an ADD instruction that adds the contents of 193252723Sdim /// G8RReg to the thread pointer. Symbol contains a relocation 194263509Sdim /// sym\@tls which is to be replaced by the thread pointer and 195252723Sdim /// identifies to the linker that the instruction is part of a 196252723Sdim /// TLS sequence. 197252723Sdim ADD_TLS, 198252723Sdim 199252723Sdim /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS 200252723Sdim /// model, produces an ADDIS8 instruction that adds the GOT base 201263509Sdim /// register to sym\@got\@tlsgd\@ha. 202252723Sdim ADDIS_TLSGD_HA, 203252723Sdim 204252723Sdim /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 205252723Sdim /// model, produces an ADDI8 instruction that adds G8RReg to 206263509Sdim /// sym\@got\@tlsgd\@l. 207252723Sdim ADDI_TLSGD_L, 208252723Sdim 209252723Sdim /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS 210263509Sdim /// model, produces a call to __tls_get_addr(sym\@tlsgd). 211252723Sdim GET_TLS_ADDR, 212252723Sdim 213252723Sdim /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS 214252723Sdim /// model, produces an ADDIS8 instruction that adds the GOT base 215263509Sdim /// register to sym\@got\@tlsld\@ha. 216252723Sdim ADDIS_TLSLD_HA, 217252723Sdim 218252723Sdim /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 219252723Sdim /// model, produces an ADDI8 instruction that adds G8RReg to 220263509Sdim /// sym\@got\@tlsld\@l. 221252723Sdim ADDI_TLSLD_L, 222252723Sdim 223252723Sdim /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS 224263509Sdim /// model, produces a call to __tls_get_addr(sym\@tlsld). 225252723Sdim GET_TLSLD_ADDR, 226252723Sdim 227252723Sdim /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the 228252723Sdim /// local-dynamic TLS model, produces an ADDIS8 instruction 229263509Sdim /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed 230252723Sdim /// to tie this in place following a copy to %X3 from the result 231252723Sdim /// of a GET_TLSLD_ADDR. 232252723Sdim ADDIS_DTPREL_HA, 233252723Sdim 234252723Sdim /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 235252723Sdim /// model, produces an ADDI8 instruction that adds G8RReg to 236263509Sdim /// sym\@got\@dtprel\@l. 237252723Sdim ADDI_DTPREL_L, 238252723Sdim 239252723Sdim /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 240252723Sdim /// during instruction selection to optimize a BUILD_VECTOR into 241252723Sdim /// operations on splats. This is necessary to avoid losing these 242252723Sdim /// optimizations due to constant folding. 243252723Sdim VADD_SPLAT, 244252723Sdim 245263509Sdim /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 246263509Sdim /// operand identifies the operating system entry point. 247263509Sdim SC, 248263509Sdim 249219077Sdim /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 250198090Srdivacky /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 251198090Srdivacky /// the GPRC input, then stores it through Ptr. Type can be either i16 or 252198090Srdivacky /// i32. 253252723Sdim STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 254219077Sdim 255219077Sdim /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 256198090Srdivacky /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 257198090Srdivacky /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 258198090Srdivacky /// or i32. 259252723Sdim LBRX, 260252723Sdim 261252723Sdim /// STFIWX - The STFIWX instruction. The first operand is an input token 262252723Sdim /// chain, then an f64 value to store, then an address to store it to. 263252723Sdim STFIWX, 264252723Sdim 265252723Sdim /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 266252723Sdim /// load which sign-extends from a 32-bit integer value into the 267252723Sdim /// destination 64-bit register. 268252723Sdim LFIWAX, 269252723Sdim 270252723Sdim /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 271252723Sdim /// load which zero-extends from a 32-bit integer value into the 272252723Sdim /// destination 64-bit register. 273252723Sdim LFIWZX, 274252723Sdim 275252723Sdim /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model, 276252723Sdim /// produces an ADDIS8 instruction that adds the TOC base register to 277263509Sdim /// sym\@toc\@ha. 278252723Sdim ADDIS_TOC_HA, 279252723Sdim 280252723Sdim /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model, 281252723Sdim /// produces a LD instruction with base register G8RReg and offset 282263509Sdim /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 283252723Sdim LD_TOC_L, 284252723Sdim 285252723Sdim /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces 286263509Sdim /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l. 287252723Sdim /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 288252723Sdim ADDI_TOC_L 289193323Sed }; 290193323Sed } 291193323Sed 292193323Sed /// Define some predicates that are used for node matching. 293193323Sed namespace PPC { 294193323Sed /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 295193323Sed /// VPKUHUM instruction. 296193323Sed bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 297219077Sdim 298193323Sed /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 299193323Sed /// VPKUWUM instruction. 300193323Sed bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary); 301193323Sed 302193323Sed /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 303193323Sed /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 304193323Sed bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 305193323Sed bool isUnary); 306193323Sed 307193323Sed /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 308193323Sed /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 309193323Sed bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 310193323Sed bool isUnary); 311219077Sdim 312193323Sed /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 313193323Sed /// amount, otherwise return -1. 314193323Sed int isVSLDOIShuffleMask(SDNode *N, bool isUnary); 315219077Sdim 316193323Sed /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 317193323Sed /// specifies a splat of a single element that is suitable for input to 318193323Sed /// VSPLTB/VSPLTH/VSPLTW. 319193323Sed bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 320219077Sdim 321193323Sed /// isAllNegativeZeroVector - Returns true if all elements of build_vector 322193323Sed /// are -0.0. 323193323Sed bool isAllNegativeZeroVector(SDNode *N); 324193323Sed 325193323Sed /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 326193323Sed /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 327193323Sed unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize); 328219077Sdim 329193323Sed /// get_VSPLTI_elt - If this is a build_vector of constants which can be 330193323Sed /// formed by using a vspltis[bhw] instruction of the specified element 331193323Sed /// size, return the constant being splatted. The ByteSize field indicates 332193323Sed /// the number of bytes of each element [124] -> [bhw]. 333193323Sed SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 334193323Sed } 335219077Sdim 336193323Sed class PPCTargetLowering : public TargetLowering { 337193323Sed const PPCSubtarget &PPCSubTarget; 338207618Srdivacky 339193323Sed public: 340193323Sed explicit PPCTargetLowering(PPCTargetMachine &TM); 341219077Sdim 342193323Sed /// getTargetNodeName() - This method returns the name of a target specific 343193323Sed /// DAG node. 344193323Sed virtual const char *getTargetNodeName(unsigned Opcode) const; 345193323Sed 346252723Sdim virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 347219077Sdim 348193323Sed /// getSetCCResultType - Return the ISD::SETCC ValueType 349263509Sdim virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 350193323Sed 351193323Sed /// getPreIndexedAddressParts - returns true by value, base pointer and 352193323Sed /// offset pointer and addressing mode by reference if the node's address 353193323Sed /// can be legally represented as pre-indexed load / store address. 354193323Sed virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 355193323Sed SDValue &Offset, 356193323Sed ISD::MemIndexedMode &AM, 357193323Sed SelectionDAG &DAG) const; 358219077Sdim 359193323Sed /// SelectAddressRegReg - Given the specified addressed, check to see if it 360193323Sed /// can be represented as an indexed [r+r] operation. Returns false if it 361193323Sed /// can be more efficiently represented with [r+imm]. 362193323Sed bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 363193323Sed SelectionDAG &DAG) const; 364219077Sdim 365193323Sed /// SelectAddressRegImm - Returns true if the address N can be represented 366193323Sed /// by a base register plus a signed 16-bit displacement [r+imm], and if it 367263509Sdim /// is not better represented as reg+reg. If Aligned is true, only accept 368263509Sdim /// displacements suitable for STD and friends, i.e. multiples of 4. 369193323Sed bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 370263509Sdim SelectionDAG &DAG, bool Aligned) const; 371219077Sdim 372193323Sed /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 373193323Sed /// represented as an indexed [r+r] operation. 374193323Sed bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 375193323Sed SelectionDAG &DAG) const; 376193323Sed 377235633Sdim Sched::Preference getSchedulingPreference(SDNode *N) const; 378219077Sdim 379193323Sed /// LowerOperation - Provide custom lowering hooks for some operations. 380193323Sed /// 381207618Srdivacky virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 382193323Sed 383193323Sed /// ReplaceNodeResults - Replace the results of node with an illegal result 384193323Sed /// type with new values built out of custom code. 385193323Sed /// 386193323Sed virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 387207618Srdivacky SelectionDAG &DAG) const; 388193323Sed 389193323Sed virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 390219077Sdim 391193323Sed virtual void computeMaskedBitsForTargetNode(const SDValue Op, 392219077Sdim APInt &KnownZero, 393193323Sed APInt &KnownOne, 394193323Sed const SelectionDAG &DAG, 395193323Sed unsigned Depth = 0) const; 396193323Sed 397207618Srdivacky virtual MachineBasicBlock * 398207618Srdivacky EmitInstrWithCustomInserter(MachineInstr *MI, 399207618Srdivacky MachineBasicBlock *MBB) const; 400219077Sdim MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 401193323Sed MachineBasicBlock *MBB, bool is64Bit, 402193323Sed unsigned BinOpcode) const; 403219077Sdim MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 404219077Sdim MachineBasicBlock *MBB, 405193323Sed bool is8bit, unsigned Opcode) const; 406219077Sdim 407252723Sdim MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, 408252723Sdim MachineBasicBlock *MBB) const; 409252723Sdim 410252723Sdim MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, 411252723Sdim MachineBasicBlock *MBB) const; 412252723Sdim 413193323Sed ConstraintType getConstraintType(const std::string &Constraint) const; 414218893Sdim 415218893Sdim /// Examine constraint string and operand type and determine a weight value. 416218893Sdim /// The operand object must already have been set up with the operand type. 417218893Sdim ConstraintWeight getSingleConstraintMatchWeight( 418218893Sdim AsmOperandInfo &info, const char *constraint) const; 419218893Sdim 420219077Sdim std::pair<unsigned, const TargetRegisterClass*> 421193323Sed getRegForInlineAsmConstraint(const std::string &Constraint, 422263509Sdim MVT VT) const; 423193323Sed 424193323Sed /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 425193323Sed /// function arguments in the caller parameter area. This is the actual 426193323Sed /// alignment, not its logarithm. 427226890Sdim unsigned getByValTypeAlignment(Type *Ty) const; 428193323Sed 429193323Sed /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 430210299Sed /// vector. If it is invalid, don't add anything to Ops. 431193323Sed virtual void LowerAsmOperandForConstraint(SDValue Op, 432223017Sdim std::string &Constraint, 433193323Sed std::vector<SDValue> &Ops, 434193323Sed SelectionDAG &DAG) const; 435219077Sdim 436193323Sed /// isLegalAddressingMode - Return true if the addressing mode represented 437193323Sed /// by AM is legal for this target, for a load/store of the specified type. 438226890Sdim virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 439219077Sdim 440193323Sed virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 441219077Sdim 442206083Srdivacky /// getOptimalMemOpType - Returns the target specific optimal type for load 443206124Srdivacky /// and store operations as a result of memset, memcpy, and memmove 444206124Srdivacky /// lowering. If DstAlign is zero that means it's safe to destination 445206124Srdivacky /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 446206124Srdivacky /// means there isn't a need to check it against alignment requirement, 447252723Sdim /// probably because the source does not need to be loaded. If 'IsMemset' is 448252723Sdim /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 449252723Sdim /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 450252723Sdim /// source is constant so it does not need to be loaded. 451207618Srdivacky /// It returns EVT::Other if the type should be determined using generic 452207618Srdivacky /// target-independent logic. 453206124Srdivacky virtual EVT 454263509Sdim getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 455252723Sdim bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 456207618Srdivacky MachineFunction &MF) const; 457193323Sed 458252723Sdim /// Is unaligned memory access allowed for the given type, and is it fast 459252723Sdim /// relative to software emulation. 460252723Sdim virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast = 0) const; 461252723Sdim 462263509Sdim /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 463263509Sdim /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 464263509Sdim /// expanded to FMAs when this method returns true, otherwise fmuladd is 465263509Sdim /// expanded to fmul + fadd. 466263509Sdim virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const; 467245431Sdim 468263509Sdim /// createFastISel - This method returns a target-specific FastISel object, 469263509Sdim /// or null if the target does not support "fast" instruction selection. 470263509Sdim virtual FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 471263509Sdim const TargetLibraryInfo *LibInfo) const; 472263509Sdim 473193323Sed private: 474193323Sed SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 475193323Sed SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 476193323Sed 477203954Srdivacky bool 478203954Srdivacky IsEligibleForTailCallOptimization(SDValue Callee, 479203954Srdivacky CallingConv::ID CalleeCC, 480203954Srdivacky bool isVarArg, 481203954Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 482203954Srdivacky SelectionDAG& DAG) const; 483203954Srdivacky 484193323Sed SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 485193323Sed int SPDiff, 486193323Sed SDValue Chain, 487193323Sed SDValue &LROpOut, 488193323Sed SDValue &FPOpOut, 489195340Sed bool isDarwinABI, 490263509Sdim SDLoc dl) const; 491193323Sed 492207618Srdivacky SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 493207618Srdivacky SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 494207618Srdivacky SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 495207618Srdivacky SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 496245431Sdim SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 497207618Srdivacky SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 498207618Srdivacky SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 499207618Srdivacky SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 500226890Sdim SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 501226890Sdim SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 502193323Sed SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 503207618Srdivacky const PPCSubtarget &Subtarget) const; 504207618Srdivacky SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, 505207618Srdivacky const PPCSubtarget &Subtarget) const; 506263509Sdim SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG, 507263509Sdim const PPCSubtarget &Subtarget) const; 508193323Sed SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 509207618Srdivacky const PPCSubtarget &Subtarget) const; 510193323Sed SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 511207618Srdivacky const PPCSubtarget &Subtarget) const; 512207618Srdivacky SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 513263509Sdim SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const; 514252723Sdim SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 515207618Srdivacky SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 516207618Srdivacky SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 517207618Srdivacky SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 518207618Srdivacky SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 519207618Srdivacky SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 520207618Srdivacky SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 521207618Srdivacky SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 522207618Srdivacky SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 523207618Srdivacky SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 524198090Srdivacky 525198090Srdivacky SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 526198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 527198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 528263509Sdim SDLoc dl, SelectionDAG &DAG, 529207618Srdivacky SmallVectorImpl<SDValue> &InVals) const; 530263509Sdim SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall, 531198090Srdivacky bool isVarArg, 532198090Srdivacky SelectionDAG &DAG, 533198090Srdivacky SmallVector<std::pair<unsigned, SDValue>, 8> 534198090Srdivacky &RegsToPass, 535198090Srdivacky SDValue InFlag, SDValue Chain, 536198090Srdivacky SDValue &Callee, 537198090Srdivacky int SPDiff, unsigned NumBytes, 538198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 539207618Srdivacky SmallVectorImpl<SDValue> &InVals) const; 540198090Srdivacky 541198090Srdivacky virtual SDValue 542198090Srdivacky LowerFormalArguments(SDValue Chain, 543198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 544198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 545263509Sdim SDLoc dl, SelectionDAG &DAG, 546207618Srdivacky SmallVectorImpl<SDValue> &InVals) const; 547198090Srdivacky 548198090Srdivacky virtual SDValue 549245431Sdim LowerCall(TargetLowering::CallLoweringInfo &CLI, 550207618Srdivacky SmallVectorImpl<SDValue> &InVals) const; 551198090Srdivacky 552226890Sdim virtual bool 553226890Sdim CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 554226890Sdim bool isVarArg, 555226890Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 556226890Sdim LLVMContext &Context) const; 557226890Sdim 558198090Srdivacky virtual SDValue 559198090Srdivacky LowerReturn(SDValue Chain, 560198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 561198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 562210299Sed const SmallVectorImpl<SDValue> &OutVals, 563263509Sdim SDLoc dl, SelectionDAG &DAG) const; 564198090Srdivacky 565198090Srdivacky SDValue 566245431Sdim extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, 567263509Sdim SDValue ArgVal, SDLoc dl) const; 568245431Sdim 569245431Sdim void 570245431Sdim setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG, 571245431Sdim unsigned nAltivecParamsAtEnd, 572245431Sdim unsigned MinReservedArea, bool isPPC64) const; 573245431Sdim 574245431Sdim SDValue 575198090Srdivacky LowerFormalArguments_Darwin(SDValue Chain, 576198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 577198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 578263509Sdim SDLoc dl, SelectionDAG &DAG, 579207618Srdivacky SmallVectorImpl<SDValue> &InVals) const; 580198090Srdivacky SDValue 581245431Sdim LowerFormalArguments_64SVR4(SDValue Chain, 582245431Sdim CallingConv::ID CallConv, bool isVarArg, 583245431Sdim const SmallVectorImpl<ISD::InputArg> &Ins, 584263509Sdim SDLoc dl, SelectionDAG &DAG, 585245431Sdim SmallVectorImpl<SDValue> &InVals) const; 586245431Sdim SDValue 587245431Sdim LowerFormalArguments_32SVR4(SDValue Chain, 588245431Sdim CallingConv::ID CallConv, bool isVarArg, 589245431Sdim const SmallVectorImpl<ISD::InputArg> &Ins, 590263509Sdim SDLoc dl, SelectionDAG &DAG, 591245431Sdim SmallVectorImpl<SDValue> &InVals) const; 592198090Srdivacky 593198090Srdivacky SDValue 594245431Sdim createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 595245431Sdim SDValue CallSeqStart, ISD::ArgFlagsTy Flags, 596263509Sdim SelectionDAG &DAG, SDLoc dl) const; 597245431Sdim 598245431Sdim SDValue 599245431Sdim LowerCall_Darwin(SDValue Chain, SDValue Callee, 600245431Sdim CallingConv::ID CallConv, 601235633Sdim bool isVarArg, bool isTailCall, 602198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 603210299Sed const SmallVectorImpl<SDValue> &OutVals, 604198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 605263509Sdim SDLoc dl, SelectionDAG &DAG, 606207618Srdivacky SmallVectorImpl<SDValue> &InVals) const; 607198090Srdivacky SDValue 608245431Sdim LowerCall_64SVR4(SDValue Chain, SDValue Callee, 609245431Sdim CallingConv::ID CallConv, 610245431Sdim bool isVarArg, bool isTailCall, 611245431Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 612245431Sdim const SmallVectorImpl<SDValue> &OutVals, 613245431Sdim const SmallVectorImpl<ISD::InputArg> &Ins, 614263509Sdim SDLoc dl, SelectionDAG &DAG, 615245431Sdim SmallVectorImpl<SDValue> &InVals) const; 616245431Sdim SDValue 617245431Sdim LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, 618245431Sdim bool isVarArg, bool isTailCall, 619245431Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 620245431Sdim const SmallVectorImpl<SDValue> &OutVals, 621245431Sdim const SmallVectorImpl<ISD::InputArg> &Ins, 622263509Sdim SDLoc dl, SelectionDAG &DAG, 623245431Sdim SmallVectorImpl<SDValue> &InVals) const; 624252723Sdim 625252723Sdim SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 626252723Sdim SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 627252723Sdim 628252723Sdim SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const; 629252723Sdim SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const; 630263509Sdim 631263509Sdim CCAssignFn *useFastISelCCs(unsigned Flag) const; 632193323Sed }; 633263509Sdim 634263509Sdim namespace PPC { 635263509Sdim FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 636263509Sdim const TargetLibraryInfo *LibInfo); 637263509Sdim } 638263509Sdim 639263509Sdim bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 640263509Sdim CCValAssign::LocInfo &LocInfo, 641263509Sdim ISD::ArgFlagsTy &ArgFlags, 642263509Sdim CCState &State); 643263509Sdim 644263509Sdim bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 645263509Sdim MVT &LocVT, 646263509Sdim CCValAssign::LocInfo &LocInfo, 647263509Sdim ISD::ArgFlagsTy &ArgFlags, 648263509Sdim CCState &State); 649263509Sdim 650263509Sdim bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 651263509Sdim MVT &LocVT, 652263509Sdim CCValAssign::LocInfo &LocInfo, 653263509Sdim ISD::ArgFlagsTy &ArgFlags, 654263509Sdim CCState &State); 655193323Sed} 656193323Sed 657193323Sed#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 658