1212904Sdim//===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===// 2235633Sdim// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7235633Sdim// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This describes the calling conventions for the PowerPC 32- and 64-bit 11193323Sed// architectures. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15245431Sdim/// CCIfSubtarget - Match if the current subtarget has a feature F. 16245431Sdimclass CCIfSubtarget<string F, CCAction A> 17245431Sdim : CCIf<!strconcat("State.getTarget().getSubtarget<PPCSubtarget>().", F), A>; 18245431Sdim 19193323Sed//===----------------------------------------------------------------------===// 20193323Sed// Return Value Calling Convention 21193323Sed//===----------------------------------------------------------------------===// 22193323Sed 23193323Sed// Return-value convention for PowerPC 24193323Seddef RetCC_PPC : CallingConv<[ 25245431Sdim // On PPC64, integer return values are always promoted to i64 26245431Sdim CCIfType<[i32], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>, 27245431Sdim 28193323Sed CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, 29193323Sed CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>, 30252723Sdim CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>, 31193323Sed 32252723Sdim CCIfType<[f32], CCAssignToReg<[F1, F2]>>, 33252723Sdim CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>, 34193323Sed 35193323Sed // Vector types are always returned in V2. 36193323Sed CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>> 37193323Sed]>; 38193323Sed 39193323Sed 40263509Sdim// Note that we don't currently have calling conventions for 64-bit 41263509Sdim// PowerPC, but handle all the complexities of the ABI in the lowering 42263509Sdim// logic. FIXME: See if the logic can be simplified with use of CCs. 43263509Sdim// This may require some extensions to current table generation. 44263509Sdim 45263509Sdim// Simple calling convention for 64-bit ELF PowerPC fast isel. 46263509Sdim// Only handle ints and floats. All ints are promoted to i64. 47263509Sdim// Vector types and quadword ints are not handled. 48263509Sdimdef CC_PPC64_ELF_FIS : CallingConv<[ 49263509Sdim CCIfType<[i8], CCPromoteToType<i64>>, 50263509Sdim CCIfType<[i16], CCPromoteToType<i64>>, 51263509Sdim CCIfType<[i32], CCPromoteToType<i64>>, 52263509Sdim CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>, 53263509Sdim CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>> 54263509Sdim]>; 55263509Sdim 56263509Sdim// Simple return-value convention for 64-bit ELF PowerPC fast isel. 57263509Sdim// All small ints are promoted to i64. Vector types, quadword ints, 58263509Sdim// and multiple register returns are "supported" to avoid compile 59263509Sdim// errors, but none are handled by the fast selector. 60263509Sdimdef RetCC_PPC64_ELF_FIS : CallingConv<[ 61263509Sdim CCIfType<[i8], CCPromoteToType<i64>>, 62263509Sdim CCIfType<[i16], CCPromoteToType<i64>>, 63263509Sdim CCIfType<[i32], CCPromoteToType<i64>>, 64263509Sdim CCIfType<[i64], CCAssignToReg<[X3, X4]>>, 65263509Sdim CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>, 66263509Sdim CCIfType<[f32], CCAssignToReg<[F1, F2]>>, 67263509Sdim CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>, 68263509Sdim CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>> 69263509Sdim]>; 70263509Sdim 71193323Sed//===----------------------------------------------------------------------===// 72252723Sdim// PowerPC System V Release 4 32-bit ABI 73193323Sed//===----------------------------------------------------------------------===// 74193323Sed 75252723Sdimdef CC_PPC32_SVR4_Common : CallingConv<[ 76195340Sed // The ABI requires i64 to be passed in two adjacent registers with the first 77195340Sed // register having an odd register number. 78252723Sdim CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>, 79195340Sed 80195340Sed // The first 8 integer arguments are passed in integer registers. 81203954Srdivacky CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>, 82195340Sed 83195340Sed // Make sure the i64 words from a long double are either both passed in 84195340Sed // registers or both passed on the stack. 85252723Sdim CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>, 86195340Sed 87195340Sed // FP values are passed in F1 - F8. 88195340Sed CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, 89195340Sed 90195340Sed // Split arguments have an alignment of 8 bytes on the stack. 91195340Sed CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>, 92195340Sed 93195340Sed CCIfType<[i32], CCAssignToStack<4, 4>>, 94195340Sed 95195340Sed // Floats are stored in double precision format, thus they have the same 96195340Sed // alignment and size as doubles. 97195340Sed CCIfType<[f32,f64], CCAssignToStack<8, 8>>, 98195340Sed 99195340Sed // Vectors get 16-byte stack slots that are 16-byte aligned. 100195340Sed CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToStack<16, 16>> 101195340Sed]>; 102195340Sed 103195340Sed// This calling convention puts vector arguments always on the stack. It is used 104195340Sed// to assign vector arguments which belong to the variable portion of the 105195340Sed// parameter list of a variable argument function. 106252723Sdimdef CC_PPC32_SVR4_VarArg : CallingConv<[ 107252723Sdim CCDelegateTo<CC_PPC32_SVR4_Common> 108195340Sed]>; 109195340Sed 110252723Sdim// In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to 111252723Sdim// put vector arguments in vector registers before putting them on the stack. 112252723Sdimdef CC_PPC32_SVR4 : CallingConv<[ 113195340Sed // The first 12 Vector arguments are passed in AltiVec registers. 114195340Sed CCIfType<[v16i8, v8i16, v4i32, v4f32], 115195340Sed CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>, 116195340Sed 117252723Sdim CCDelegateTo<CC_PPC32_SVR4_Common> 118195340Sed]>; 119195340Sed 120195340Sed// Helper "calling convention" to handle aggregate by value arguments. 121195340Sed// Aggregate by value arguments are always placed in the local variable space 122195340Sed// of the caller. This calling convention is only used to assign those stack 123195340Sed// offsets in the callers stack frame. 124195340Sed// 125195340Sed// Still, the address of the aggregate copy in the callers stack frame is passed 126195340Sed// in a GPR (or in the parameter list area if all GPRs are allocated) from the 127195340Sed// caller to the callee. The location for the address argument is assigned by 128252723Sdim// the CC_PPC32_SVR4 calling convention. 129195340Sed// 130252723Sdim// The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are 131195340Sed// not passed by value. 132195340Sed 133252723Sdimdef CC_PPC32_SVR4_ByVal : CallingConv<[ 134195340Sed CCIfByVal<CCPassByVal<4, 4>>, 135195340Sed 136252723Sdim CCCustom<"CC_PPC32_SVR4_Custom_Dummy"> 137195340Sed]>; 138195340Sed 139263509Sdimdef CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27, 140263509Sdim V28, V29, V30, V31)>; 141263509Sdim 142235633Sdimdef CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20, 143235633Sdim R21, R22, R23, R24, R25, R26, R27, R28, 144235633Sdim R29, R30, R31, F14, F15, F16, F17, F18, 145235633Sdim F19, F20, F21, F22, F23, F24, F25, F26, 146263509Sdim F27, F28, F29, F30, F31, CR2, CR3, CR4 147263509Sdim )>; 148235633Sdim 149263509Sdimdef CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>; 150263509Sdim 151263509Sdimdef CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20, 152235633Sdim R21, R22, R23, R24, R25, R26, R27, R28, 153235633Sdim R29, R30, R31, F14, F15, F16, F17, F18, 154235633Sdim F19, F20, F21, F22, F23, F24, F25, F26, 155263509Sdim F27, F28, F29, F30, F31, CR2, CR3, CR4 156263509Sdim )>; 157235633Sdim 158263509Sdimdef CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>; 159263509Sdim 160235633Sdimdef CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20, 161235633Sdim X21, X22, X23, X24, X25, X26, X27, X28, 162235633Sdim X29, X30, X31, F14, F15, F16, F17, F18, 163235633Sdim F19, F20, F21, F22, F23, F24, F25, F26, 164263509Sdim F27, F28, F29, F30, F31, CR2, CR3, CR4 165263509Sdim )>; 166235633Sdim 167263509Sdimdef CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>; 168263509Sdim 169263509Sdimdef CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, 170235633Sdim X21, X22, X23, X24, X25, X26, X27, X28, 171235633Sdim X29, X30, X31, F14, F15, F16, F17, F18, 172235633Sdim F19, F20, F21, F22, F23, F24, F25, F26, 173263509Sdim F27, F28, F29, F30, F31, CR2, CR3, CR4 174263509Sdim )>; 175252723Sdim 176252723Sdim 177263509Sdimdef CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>; 178252723Sdim 179263509Sdimdef CSR_NoRegs : CalleeSavedRegs<(add)>; 180263509Sdim 181