1235633Sdim//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10223017Sdim// This file describes the Mips FPU instruction set. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed//===----------------------------------------------------------------------===// 15193323Sed// Floating Point Instructions 16193323Sed// ------------------------ 17193323Sed// * 64bit fp: 18193323Sed// - 32 64-bit registers (default mode) 19193323Sed// - 16 even 32-bit registers (32-bit compatible mode) for 20193323Sed// single and double access. 21193323Sed// * 32bit fp: 22193323Sed// - 16 even 32-bit registers - single and double (aliased) 23193323Sed// - 32 32-bit registers (within single-only mode) 24193323Sed//===----------------------------------------------------------------------===// 25193323Sed 26193323Sed// Floating Point Compare and Branch 27263509Sdimdef SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>, 28263509Sdim SDTCisVT<1, i32>, 29263509Sdim SDTCisVT<2, OtherVT>]>; 30221345Sdimdef SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 31226890Sdim SDTCisVT<2, i32>]>; 32263509Sdimdef SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, 33263509Sdim SDTCisSameAs<1, 3>]>; 34263509Sdimdef SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; 35221345Sdimdef SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 36221345Sdim SDTCisVT<1, i32>, 37221345Sdim SDTCisSameAs<1, 2>]>; 38221345Sdimdef SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 39221345Sdim SDTCisVT<1, f64>, 40226890Sdim SDTCisVT<2, i32>]>; 41193323Sed 42221345Sdimdef MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 43221345Sdimdef MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 44221345Sdimdef MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 45221345Sdimdef MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 46221345Sdim [SDNPHasChain, SDNPOptInGlue]>; 47263509Sdimdef MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; 48221345Sdimdef MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 49221345Sdimdef MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 50221345Sdim SDT_MipsExtractElementF64>; 51193323Sed 52193323Sed// Operand for printing out a condition code. 53235633Sdimlet PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 54193323Sed def condcode : Operand<i32>; 55193323Sed 56193323Sed//===----------------------------------------------------------------------===// 57193323Sed// Feature predicates. 58193323Sed//===----------------------------------------------------------------------===// 59193323Sed 60245431Sdimdef IsFP64bit : Predicate<"Subtarget.isFP64bit()">, 61245431Sdim AssemblerPredicate<"FeatureFP64Bit">; 62245431Sdimdef NotFP64bit : Predicate<"!Subtarget.isFP64bit()">, 63245431Sdim AssemblerPredicate<"!FeatureFP64Bit">; 64245431Sdimdef IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">, 65245431Sdim AssemblerPredicate<"FeatureSingleFloat">; 66245431Sdimdef IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">, 67245431Sdim AssemblerPredicate<"!FeatureSingleFloat">; 68193323Sed 69235633Sdim// FP immediate patterns. 70235633Sdimdef fpimm0 : PatLeaf<(fpimm), [{ 71235633Sdim return N->isExactlyValue(+0.0); 72235633Sdim}]>; 73235633Sdim 74235633Sdimdef fpimm0neg : PatLeaf<(fpimm), [{ 75235633Sdim return N->isExactlyValue(-0.0); 76235633Sdim}]>; 77235633Sdim 78193323Sed//===----------------------------------------------------------------------===// 79193323Sed// Instruction Class Templates 80193323Sed// 81221345Sdim// A set of multiclasses is used to address the register usage. 82193323Sed// 83193323Sed// S32 - single precision in 16 32bit even fp registers 84193323Sed// single precision in 32 32bit fp registers in SingleOnly mode 85193323Sed// S64 - single precision in 32 64bit fp registers (In64BitMode) 86193323Sed// D32 - double precision in 16 32bit even fp registers 87193323Sed// D64 - double precision in 32 64bit fp registers (In64BitMode) 88193323Sed// 89193323Sed// Only S32 and D32 are supported right now. 90193323Sed//===----------------------------------------------------------------------===// 91193323Sed 92263509Sdimclass ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm, 93252723Sdim SDPatternOperator OpNode= null_frag> : 94252723Sdim InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 95252723Sdim !strconcat(opstr, "\t$fd, $fs, $ft"), 96252723Sdim [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> { 97252723Sdim let isCommutable = IsComm; 98252723Sdim} 99193323Sed 100252723Sdimmulticlass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 101252723Sdim SDPatternOperator OpNode = null_frag> { 102263509Sdim def _D32 : ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, 103252723Sdim Requires<[NotFP64bit, HasStdEnc]>; 104263509Sdim def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, 105252723Sdim Requires<[IsFP64bit, HasStdEnc]> { 106252723Sdim string DecoderNamespace = "Mips64"; 107252723Sdim } 108235633Sdim} 109226890Sdim 110263509Sdimclass ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 111252723Sdim InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 112252723Sdim InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 113252723Sdim [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>, 114252723Sdim NeverHasSideEffects; 115252723Sdim 116252723Sdimmulticlass ABSS_M<string opstr, InstrItinClass Itin, 117252723Sdim SDPatternOperator OpNode= null_frag> { 118263509Sdim def _D32 : ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, 119252723Sdim Requires<[NotFP64bit, HasStdEnc]>; 120263509Sdim def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, 121252723Sdim Requires<[IsFP64bit, HasStdEnc]> { 122252723Sdim string DecoderNamespace = "Mips64"; 123252723Sdim } 124235633Sdim} 125235633Sdim 126252723Sdimmulticlass ROUND_M<string opstr, InstrItinClass Itin> { 127263509Sdim def _D32 : ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, 128252723Sdim Requires<[NotFP64bit, HasStdEnc]>; 129263509Sdim def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, 130252723Sdim Requires<[IsFP64bit, HasStdEnc]> { 131235633Sdim let DecoderNamespace = "Mips64"; 132235633Sdim } 133193323Sed} 134193323Sed 135263509Sdimclass MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 136252723Sdim InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 137252723Sdim InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 138252723Sdim [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>; 139252723Sdim 140263509Sdimclass MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 141252723Sdim InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 142252723Sdim InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 143252723Sdim [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>; 144252723Sdim 145263509Sdimclass LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 146263509Sdim SDPatternOperator OpNode= null_frag> : 147263509Sdim InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 148252723Sdim [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> { 149252723Sdim let DecoderMethod = "DecodeFMem"; 150263509Sdim let mayLoad = 1; 151226890Sdim} 152193323Sed 153263509Sdimclass SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 154263509Sdim SDPatternOperator OpNode= null_frag> : 155263509Sdim InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 156252723Sdim [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> { 157252723Sdim let DecoderMethod = "DecodeFMem"; 158263509Sdim let mayStore = 1; 159193323Sed} 160193323Sed 161263509Sdimclass MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 162252723Sdim SDPatternOperator OpNode = null_frag> : 163252723Sdim InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 164252723Sdim !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 165252723Sdim [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>; 166252723Sdim 167263509Sdimclass NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 168252723Sdim SDPatternOperator OpNode = null_frag> : 169252723Sdim InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 170252723Sdim !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 171252723Sdim [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 172252723Sdim Itin, FrmFR>; 173252723Sdim 174263509Sdimclass LWXC1_FT<string opstr, RegisterOperand DRC, 175252723Sdim InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 176263509Sdim InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index), 177252723Sdim !strconcat(opstr, "\t$fd, ${index}(${base})"), 178263509Sdim [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin, FrmFI> { 179252723Sdim let AddedComplexity = 20; 180193323Sed} 181252723Sdim 182263509Sdimclass SWXC1_FT<string opstr, RegisterOperand DRC, 183252723Sdim InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 184263509Sdim InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index), 185252723Sdim !strconcat(opstr, "\t$fs, ${index}(${base})"), 186263509Sdim [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin, FrmFI> { 187252723Sdim let AddedComplexity = 20; 188235633Sdim} 189193323Sed 190252723Sdimclass BC1F_FT<string opstr, InstrItinClass Itin, 191252723Sdim SDPatternOperator Op = null_frag> : 192263509Sdim InstSE<(outs), (ins FCCRegsOpnd:$fcc, brtarget:$offset), 193263509Sdim !strconcat(opstr, "\t$fcc, $offset"), 194263509Sdim [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, FrmFI> { 195252723Sdim let isBranch = 1; 196252723Sdim let isTerminator = 1; 197252723Sdim let hasDelaySlot = 1; 198252723Sdim let Defs = [AT]; 199252723Sdim} 200235633Sdim 201252723Sdimclass CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 202252723Sdim SDPatternOperator OpNode = null_frag> : 203252723Sdim InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 204252723Sdim !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 205252723Sdim [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> { 206263509Sdim let Defs = [FCC0]; 207263509Sdim let isCodeGenOnly = 1; 208252723Sdim} 209235633Sdim 210263509Sdimclass C_COND_FT<string CondStr, string Typestr, RegisterOperand RC> : 211263509Sdim InstSE<(outs), (ins RC:$fs, RC:$ft), 212263509Sdim !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], IIFcmp, 213263509Sdim FrmFR>; 214263509Sdim 215263509Sdimmulticlass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt> { 216263509Sdim def C_F_#NAME : C_COND_FT<"f", TypeStr, RC>, C_COND_FM<fmt, 0>; 217263509Sdim def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC>, C_COND_FM<fmt, 1>; 218263509Sdim def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC>, C_COND_FM<fmt, 2>; 219263509Sdim def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC>, C_COND_FM<fmt, 3>; 220263509Sdim def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC>, C_COND_FM<fmt, 4>; 221263509Sdim def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC>, C_COND_FM<fmt, 5>; 222263509Sdim def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC>, C_COND_FM<fmt, 6>; 223263509Sdim def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC>, C_COND_FM<fmt, 7>; 224263509Sdim def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC>, C_COND_FM<fmt, 8>; 225263509Sdim def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC>, C_COND_FM<fmt, 9>; 226263509Sdim def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC>, C_COND_FM<fmt, 10>; 227263509Sdim def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC>, C_COND_FM<fmt, 11>; 228263509Sdim def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC>, C_COND_FM<fmt, 12>; 229263509Sdim def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC>, C_COND_FM<fmt, 13>; 230263509Sdim def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC>, C_COND_FM<fmt, 14>; 231263509Sdim def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC>, C_COND_FM<fmt, 15>; 232263509Sdim} 233263509Sdim 234263509Sdimdefm S : C_COND_M<"s", FGR32Opnd, 16>; 235263509Sdimdefm D32 : C_COND_M<"d", AFGR64Opnd, 17>, 236263509Sdim Requires<[NotFP64bit, HasStdEnc]>; 237263509Sdimlet DecoderNamespace = "Mips64" in 238263509Sdimdefm D64 : C_COND_M<"d", FGR64Opnd, 17>, Requires<[IsFP64bit, HasStdEnc]>; 239263509Sdim 240193323Sed//===----------------------------------------------------------------------===// 241193323Sed// Floating Point Instructions 242193323Sed//===----------------------------------------------------------------------===// 243263509Sdimdef ROUND_W_S : ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 244263509Sdim ABSS_FM<0xc, 16>; 245263509Sdimdef TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 246263509Sdim ABSS_FM<0xd, 16>; 247263509Sdimdef CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 248263509Sdim ABSS_FM<0xe, 16>; 249263509Sdimdef FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 250263509Sdim ABSS_FM<0xf, 16>; 251263509Sdimdef CVT_W_S : ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, IIFcvt>, 252263509Sdim ABSS_FM<0x24, 16>; 253193323Sed 254252723Sdimdefm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>; 255252723Sdimdefm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>; 256252723Sdimdefm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>; 257252723Sdimdefm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>; 258252723Sdimdefm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>; 259193323Sed 260252723Sdimlet Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 261263509Sdim def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 262263509Sdim ABSS_FM<0x8, 16>; 263263509Sdim def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 264252723Sdim ABSS_FM<0x8, 17>; 265263509Sdim def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 266263509Sdim ABSS_FM<0x9, 16>; 267263509Sdim def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 268252723Sdim ABSS_FM<0x9, 17>; 269263509Sdim def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 270263509Sdim ABSS_FM<0xa, 16>; 271263509Sdim def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 272263509Sdim ABSS_FM<0xa, 17>; 273263509Sdim def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 274263509Sdim ABSS_FM<0xb, 16>; 275263509Sdim def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 276252723Sdim ABSS_FM<0xb, 17>; 277226890Sdim} 278193323Sed 279263509Sdimdef CVT_S_W : ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, IIFcvt>, 280263509Sdim ABSS_FM<0x20, 20>; 281263509Sdimdef CVT_L_S : ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 282263509Sdim ABSS_FM<0x25, 16>; 283263509Sdimdef CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, IIFcvt>, 284263509Sdim ABSS_FM<0x25, 17>; 285252723Sdim 286252723Sdimlet Predicates = [NotFP64bit, HasStdEnc] in { 287263509Sdim def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, IIFcvt>, 288263509Sdim ABSS_FM<0x20, 17>; 289263509Sdim def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, IIFcvt>, 290263509Sdim ABSS_FM<0x21, 20>; 291263509Sdim def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, IIFcvt>, 292263509Sdim ABSS_FM<0x21, 16>; 293226890Sdim} 294193323Sed 295252723Sdimlet Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 296263509Sdim def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, IIFcvt>, 297263509Sdim ABSS_FM<0x20, 17>; 298263509Sdim def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, IIFcvt>, 299263509Sdim ABSS_FM<0x20, 21>; 300263509Sdim def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, IIFcvt>, 301263509Sdim ABSS_FM<0x21, 20>; 302263509Sdim def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, IIFcvt>, 303263509Sdim ABSS_FM<0x21, 16>; 304263509Sdim def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, IIFcvt>, 305263509Sdim ABSS_FM<0x21, 21>; 306235633Sdim} 307193323Sed 308263509Sdimlet isPseudo = 1, isCodeGenOnly = 1 in { 309263509Sdim def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, IIFcvt>; 310263509Sdim def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, IIFcvt>; 311263509Sdim def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>; 312263509Sdim def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, IIFcvt>; 313263509Sdim def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, IIFcvt>; 314263509Sdim} 315263509Sdim 316252723Sdimlet Predicates = [NoNaNsFPMath, HasStdEnc] in { 317263509Sdim def FABS_S : ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, IIFcvt, fabs>, 318263509Sdim ABSS_FM<0x5, 16>; 319263509Sdim def FNEG_S : ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, IIFcvt, fneg>, 320263509Sdim ABSS_FM<0x7, 16>; 321252723Sdim defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>; 322252723Sdim defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>; 323252723Sdim} 324252723Sdim 325263509Sdimdef FSQRT_S : ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, IIFsqrtSingle, 326263509Sdim fsqrt>, ABSS_FM<0x4, 16>; 327252723Sdimdefm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>; 328252723Sdim 329193323Sed// The odd-numbered registers are only referenced when doing loads, 330193323Sed// stores, and moves between floating-point and integer registers. 331221345Sdim// When defining instructions, we reference all 32-bit registers, 332193323Sed// regardless of register aliasing. 333229042Sdim 334229042Sdim/// Move Control Registers From/To CPU Registers 335263509Sdimdef CFC1 : MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, IIFmove>, MFC1_FM<2>; 336263509Sdimdef CTC1 : MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, IIFmove>, MFC1_FM<6>; 337263509Sdimdef MFC1 : MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, IIFmoveC1, bitconvert>, 338263509Sdim MFC1_FM<0>; 339263509Sdimdef MTC1 : MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, IIFmoveC1, bitconvert>, 340263509Sdim MFC1_FM<4>; 341263509Sdimdef MFHC1 : MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, IIFmoveC1>, 342263509Sdim MFC1_FM<3>; 343263509Sdimdef MTHC1 : MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, IIFmoveC1>, 344263509Sdim MFC1_FM<7>; 345263509Sdimdef DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, IIFmoveC1, 346263509Sdim bitconvert>, MFC1_FM<1>; 347263509Sdimdef DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, IIFmoveC1, 348263509Sdim bitconvert>, MFC1_FM<5>; 349193323Sed 350263509Sdimdef FMOV_S : ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, IIFmove>, 351263509Sdim ABSS_FM<0x6, 16>; 352263509Sdimdef FMOV_D32 : ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, IIFmove>, 353263509Sdim ABSS_FM<0x6, 17>, Requires<[NotFP64bit, HasStdEnc]>; 354263509Sdimdef FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, IIFmove>, 355263509Sdim ABSS_FM<0x6, 17>, Requires<[IsFP64bit, HasStdEnc]> { 356263509Sdim let DecoderNamespace = "Mips64"; 357235633Sdim} 358203954Srdivacky 359193323Sed/// Floating Point Memory Instructions 360263509Sdimlet Predicates = [HasStdEnc] in { 361263509Sdim def LWC1 : LW_FT<"lwc1", FGR32Opnd, IIFLoad, load>, LW_FM<0x31>; 362263509Sdim def SWC1 : SW_FT<"swc1", FGR32Opnd, IIFStore, store>, LW_FM<0x39>; 363226890Sdim} 364193323Sed 365263509Sdimlet Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { 366263509Sdim def LDC164 : LW_FT<"ldc1", FGR64Opnd, IIFLoad, load>, LW_FM<0x35>; 367263509Sdim def SDC164 : SW_FT<"sdc1", FGR64Opnd, IIFStore, store>, LW_FM<0x3d>; 368193323Sed} 369193323Sed 370263509Sdimlet Predicates = [NotFP64bit, HasStdEnc] in { 371263509Sdim def LDC1 : LW_FT<"ldc1", AFGR64Opnd, IIFLoad, load>, LW_FM<0x35>; 372263509Sdim def SDC1 : SW_FT<"sdc1", AFGR64Opnd, IIFStore, store>, LW_FM<0x3d>; 373235633Sdim} 374235633Sdim 375263509Sdim/// Cop2 Memory Instructions 376263509Sdimlet Predicates = [HasStdEnc] in { 377263509Sdim def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>; 378263509Sdim def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>; 379263509Sdim def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>; 380263509Sdim def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>; 381235633Sdim} 382235633Sdim 383235633Sdim// Indexed loads and stores. 384252723Sdimlet Predicates = [HasFPIdx, HasStdEnc] in { 385263509Sdim def LWXC1 : LWXC1_FT<"lwxc1", FGR32Opnd, IIFLoad, load>, LWXC1_FM<0>; 386263509Sdim def SWXC1 : SWXC1_FT<"swxc1", FGR32Opnd, IIFStore, store>, SWXC1_FM<8>; 387235633Sdim} 388235633Sdim 389263509Sdimlet Predicates = [HasFPIdx, NotFP64bit, HasStdEnc] in { 390263509Sdim def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, IIFLoad, load>, LWXC1_FM<1>; 391263509Sdim def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, IIFStore, store>, SWXC1_FM<9>; 392235633Sdim} 393235633Sdim 394263509Sdimlet Predicates = [HasFPIdx, IsFP64bit, HasStdEnc], 395263509Sdim DecoderNamespace="Mips64" in { 396263509Sdim def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, IIFLoad, load>, LWXC1_FM<1>; 397263509Sdim def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, IIFStore, store>, SWXC1_FM<9>; 398235633Sdim} 399235633Sdim 400245431Sdim// Load/store doubleword indexed unaligned. 401263509Sdimlet Predicates = [NotFP64bit, HasStdEnc] in { 402263509Sdim def LUXC1 : LWXC1_FT<"luxc1", AFGR64Opnd, IIFLoad>, LWXC1_FM<0x5>; 403263509Sdim def SUXC1 : SWXC1_FT<"suxc1", AFGR64Opnd, IIFStore>, SWXC1_FM<0xd>; 404245431Sdim} 405245431Sdim 406263509Sdimlet Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace="Mips64" in { 407263509Sdim def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, IIFLoad>, LWXC1_FM<0x5>; 408263509Sdim def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, IIFStore>, SWXC1_FM<0xd>; 409245431Sdim} 410245431Sdim 411193323Sed/// Floating-point Aritmetic 412263509Sdimdef FADD_S : ADDS_FT<"add.s", FGR32Opnd, IIFadd, 1, fadd>, 413263509Sdim ADDS_FM<0x00, 16>; 414263509Sdimdefm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>; 415263509Sdimdef FDIV_S : ADDS_FT<"div.s", FGR32Opnd, IIFdivSingle, 0, fdiv>, 416263509Sdim ADDS_FM<0x03, 16>; 417263509Sdimdefm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>; 418263509Sdimdef FMUL_S : ADDS_FT<"mul.s", FGR32Opnd, IIFmulSingle, 1, fmul>, 419263509Sdim ADDS_FM<0x02, 16>; 420263509Sdimdefm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>; 421263509Sdimdef FSUB_S : ADDS_FT<"sub.s", FGR32Opnd, IIFadd, 0, fsub>, 422263509Sdim ADDS_FM<0x01, 16>; 423263509Sdimdefm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>; 424193323Sed 425252723Sdimlet Predicates = [HasMips32r2, HasStdEnc] in { 426263509Sdim def MADD_S : MADDS_FT<"madd.s", FGR32Opnd, IIFmulSingle, fadd>, 427263509Sdim MADDS_FM<4, 0>; 428263509Sdim def MSUB_S : MADDS_FT<"msub.s", FGR32Opnd, IIFmulSingle, fsub>, 429263509Sdim MADDS_FM<5, 0>; 430235633Sdim} 431235633Sdim 432252723Sdimlet Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in { 433263509Sdim def NMADD_S : NMADDS_FT<"nmadd.s", FGR32Opnd, IIFmulSingle, fadd>, 434263509Sdim MADDS_FM<6, 0>; 435263509Sdim def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32Opnd, IIFmulSingle, fsub>, 436263509Sdim MADDS_FM<7, 0>; 437235633Sdim} 438235633Sdim 439252723Sdimlet Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in { 440263509Sdim def MADD_D32 : MADDS_FT<"madd.d", AFGR64Opnd, IIFmulDouble, fadd>, 441263509Sdim MADDS_FM<4, 1>; 442263509Sdim def MSUB_D32 : MADDS_FT<"msub.d", AFGR64Opnd, IIFmulDouble, fsub>, 443263509Sdim MADDS_FM<5, 1>; 444235633Sdim} 445235633Sdim 446252723Sdimlet Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in { 447263509Sdim def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64Opnd, IIFmulDouble, fadd>, 448252723Sdim MADDS_FM<6, 1>; 449263509Sdim def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64Opnd, IIFmulDouble, fsub>, 450252723Sdim MADDS_FM<7, 1>; 451235633Sdim} 452235633Sdim 453252723Sdimlet Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in { 454263509Sdim def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, IIFmulDouble, fadd>, 455263509Sdim MADDS_FM<4, 1>; 456263509Sdim def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, IIFmulDouble, fsub>, 457263509Sdim MADDS_FM<5, 1>; 458235633Sdim} 459235633Sdim 460252723Sdimlet Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc], 461245431Sdim isCodeGenOnly=1 in { 462263509Sdim def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, IIFmulDouble, fadd>, 463252723Sdim MADDS_FM<6, 1>; 464263509Sdim def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, IIFmulDouble, fsub>, 465252723Sdim MADDS_FM<7, 1>; 466235633Sdim} 467235633Sdim 468193323Sed//===----------------------------------------------------------------------===// 469193323Sed// Floating Point Branch Codes 470193323Sed//===----------------------------------------------------------------------===// 471221345Sdim// Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 472193323Sed// They must be kept in synch. 473193323Seddef MIPS_BRANCH_F : PatLeaf<(i32 0)>; 474193323Seddef MIPS_BRANCH_T : PatLeaf<(i32 1)>; 475193323Sed 476252723Sdimdef BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>; 477252723Sdimdef BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>; 478263509Sdim 479193323Sed//===----------------------------------------------------------------------===// 480193323Sed// Floating Point Flag Conditions 481193323Sed//===----------------------------------------------------------------------===// 482221345Sdim// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h. 483193323Sed// They must be kept in synch. 484193323Seddef MIPS_FCOND_F : PatLeaf<(i32 0)>; 485193323Seddef MIPS_FCOND_UN : PatLeaf<(i32 1)>; 486221345Sdimdef MIPS_FCOND_OEQ : PatLeaf<(i32 2)>; 487193323Seddef MIPS_FCOND_UEQ : PatLeaf<(i32 3)>; 488193323Seddef MIPS_FCOND_OLT : PatLeaf<(i32 4)>; 489193323Seddef MIPS_FCOND_ULT : PatLeaf<(i32 5)>; 490193323Seddef MIPS_FCOND_OLE : PatLeaf<(i32 6)>; 491193323Seddef MIPS_FCOND_ULE : PatLeaf<(i32 7)>; 492193323Seddef MIPS_FCOND_SF : PatLeaf<(i32 8)>; 493193323Seddef MIPS_FCOND_NGLE : PatLeaf<(i32 9)>; 494193323Seddef MIPS_FCOND_SEQ : PatLeaf<(i32 10)>; 495193323Seddef MIPS_FCOND_NGL : PatLeaf<(i32 11)>; 496193323Seddef MIPS_FCOND_LT : PatLeaf<(i32 12)>; 497193323Seddef MIPS_FCOND_NGE : PatLeaf<(i32 13)>; 498193323Seddef MIPS_FCOND_LE : PatLeaf<(i32 14)>; 499193323Seddef MIPS_FCOND_NGT : PatLeaf<(i32 15)>; 500193323Sed 501193323Sed/// Floating Point Compare 502252723Sdimdef FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>; 503252723Sdimdef FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, 504252723Sdim Requires<[NotFP64bit, HasStdEnc]>; 505252723Sdimlet DecoderNamespace = "Mips64" in 506252723Sdimdef FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>, 507252723Sdim Requires<[IsFP64bit, HasStdEnc]>; 508193323Sed 509193323Sed//===----------------------------------------------------------------------===// 510221345Sdim// Floating Point Pseudo-Instructions 511221345Sdim//===----------------------------------------------------------------------===// 512221345Sdim 513221345Sdim// This pseudo instr gets expanded into 2 mtc1 instrs after register 514221345Sdim// allocation. 515263509Sdimclass BuildPairF64Base<RegisterOperand RO> : 516263509Sdim PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi), 517263509Sdim [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>; 518221345Sdim 519263509Sdimdef BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, 520263509Sdim Requires<[NotFP64bit, HasStdEnc]>; 521263509Sdimdef BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, 522263509Sdim Requires<[IsFP64bit, HasStdEnc]>; 523263509Sdim 524221345Sdim// This pseudo instr gets expanded into 2 mfc1 instrs after register 525221345Sdim// allocation. 526221345Sdim// if n is 0, lower part of src is extracted. 527221345Sdim// if n is 1, higher part of src is extracted. 528263509Sdimclass ExtractElementF64Base<RegisterOperand RO> : 529263509Sdim PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n), 530263509Sdim [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>; 531221345Sdim 532263509Sdimdef ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, 533263509Sdim Requires<[NotFP64bit, HasStdEnc]>; 534263509Sdimdef ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, 535263509Sdim Requires<[IsFP64bit, HasStdEnc]>; 536263509Sdim 537221345Sdim//===----------------------------------------------------------------------===// 538263509Sdim// InstAliases. 539263509Sdim//===----------------------------------------------------------------------===// 540263509Sdimdef : InstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>; 541263509Sdimdef : InstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>; 542263509Sdim 543263509Sdim//===----------------------------------------------------------------------===// 544193323Sed// Floating Point Patterns 545193323Sed//===----------------------------------------------------------------------===// 546245431Sdimdef : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 547245431Sdimdef : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; 548193323Sed 549263509Sdimdef : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), 550263509Sdim (PseudoCVT_S_W GPR32Opnd:$src)>; 551263509Sdimdef : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 552263509Sdim (TRUNC_W_S FGR32Opnd:$src)>; 553193323Sed 554252723Sdimlet Predicates = [NotFP64bit, HasStdEnc] in { 555263509Sdim def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 556263509Sdim (PseudoCVT_D32_W GPR32Opnd:$src)>; 557263509Sdim def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), 558263509Sdim (TRUNC_W_D32 AFGR64Opnd:$src)>; 559263509Sdim def : MipsPat<(f32 (fround AFGR64Opnd:$src)), 560263509Sdim (CVT_S_D32 AFGR64Opnd:$src)>; 561263509Sdim def : MipsPat<(f64 (fextend FGR32Opnd:$src)), 562263509Sdim (CVT_D32_S FGR32Opnd:$src)>; 563193323Sed} 564193323Sed 565252723Sdimlet Predicates = [IsFP64bit, HasStdEnc] in { 566245431Sdim def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>; 567245431Sdim def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>; 568235633Sdim 569263509Sdim def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 570263509Sdim (PseudoCVT_D64_W GPR32Opnd:$src)>; 571263509Sdim def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)), 572263509Sdim (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>; 573263509Sdim def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), 574263509Sdim (PseudoCVT_D64_L GPR64Opnd:$src)>; 575235633Sdim 576263509Sdim def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 577263509Sdim (TRUNC_W_D64 FGR64Opnd:$src)>; 578263509Sdim def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 579263509Sdim (TRUNC_L_S FGR32Opnd:$src)>; 580263509Sdim def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 581263509Sdim (TRUNC_L_D64 FGR64Opnd:$src)>; 582235633Sdim 583263509Sdim def : MipsPat<(f32 (fround FGR64Opnd:$src)), 584263509Sdim (CVT_S_D64 FGR64Opnd:$src)>; 585263509Sdim def : MipsPat<(f64 (fextend FGR32Opnd:$src)), 586263509Sdim (CVT_D64_S FGR32Opnd:$src)>; 587235633Sdim} 588252723Sdim 589252723Sdim// Patterns for loads/stores with a reg+imm operand. 590252723Sdimlet AddedComplexity = 40 in { 591263509Sdim let Predicates = [HasStdEnc] in { 592252723Sdim def : LoadRegImmPat<LWC1, f32, load>; 593252723Sdim def : StoreRegImmPat<SWC1, f32>; 594252723Sdim } 595252723Sdim 596263509Sdim let Predicates = [IsFP64bit, HasStdEnc] in { 597252723Sdim def : LoadRegImmPat<LDC164, f64, load>; 598252723Sdim def : StoreRegImmPat<SDC164, f64>; 599252723Sdim } 600252723Sdim 601263509Sdim let Predicates = [NotFP64bit, HasStdEnc] in { 602252723Sdim def : LoadRegImmPat<LDC1, f64, load>; 603252723Sdim def : StoreRegImmPat<SDC1, f64>; 604252723Sdim } 605252723Sdim} 606