1235633Sdim//===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===// 2221345Sdim// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7221345Sdim// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// This describes the calling conventions for Mips architecture. 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed 12193323Sed/// CCIfSubtarget - Match if the current subtarget has a feature F. 13221345Sdimclass CCIfSubtarget<string F, CCAction A>: 14193323Sed CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>; 15193323Sed 16193323Sed//===----------------------------------------------------------------------===// 17193323Sed// Mips O32 Calling Convention 18193323Sed//===----------------------------------------------------------------------===// 19193323Sed 20221345Sdim// Only the return rules are defined here for O32. The rules for argument 21193323Sed// passing are defined in MipsISelLowering.cpp. 22193323Seddef RetCC_MipsO32 : CallingConv<[ 23224145Sdim // i32 are returned in registers V0, V1, A0, A1 24224145Sdim CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>, 25193323Sed 26202878Srdivacky // f32 are returned in registers F0, F2 27202878Srdivacky CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 28193323Sed 29263509Sdim // f64 arguments are returned in D0_64 and D1_64 in FP64bit mode or 30263509Sdim // in D0 and D1 in FP32bit mode. 31263509Sdim CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D1_64]>>>, 32263509Sdim CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()", CCAssignToReg<[D0, D1]>>> 33193323Sed]>; 34193323Sed 35193323Sed//===----------------------------------------------------------------------===// 36226890Sdim// Mips N32/64 Calling Convention 37226890Sdim//===----------------------------------------------------------------------===// 38226890Sdim 39226890Sdimdef CC_MipsN : CallingConv<[ 40235633Sdim // Promote i8/i16 arguments to i32. 41235633Sdim CCIfType<[i8, i16], CCPromoteToType<i32>>, 42226890Sdim 43226890Sdim // Integer arguments are passed in integer registers. 44235633Sdim CCIfType<[i32], CCAssignToRegWithShadow<[A0, A1, A2, A3, 45235633Sdim T0, T1, T2, T3], 46235633Sdim [F12, F13, F14, F15, 47235633Sdim F16, F17, F18, F19]>>, 48235633Sdim 49226890Sdim CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64, 50226890Sdim T0_64, T1_64, T2_64, T3_64], 51226890Sdim [D12_64, D13_64, D14_64, D15_64, 52226890Sdim D16_64, D17_64, D18_64, D19_64]>>, 53226890Sdim 54226890Sdim // f32 arguments are passed in single precision FP registers. 55226890Sdim CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15, 56226890Sdim F16, F17, F18, F19], 57226890Sdim [A0_64, A1_64, A2_64, A3_64, 58226890Sdim T0_64, T1_64, T2_64, T3_64]>>, 59226890Sdim 60226890Sdim // f64 arguments are passed in double precision FP registers. 61226890Sdim CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64, 62226890Sdim D16_64, D17_64, D18_64, D19_64], 63226890Sdim [A0_64, A1_64, A2_64, A3_64, 64226890Sdim T0_64, T1_64, T2_64, T3_64]>>, 65226890Sdim 66226890Sdim // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. 67235633Sdim CCIfType<[i32, f32], CCAssignToStack<4, 8>>, 68235633Sdim CCIfType<[i64, f64], CCAssignToStack<8, 8>> 69226890Sdim]>; 70226890Sdim 71235633Sdim// N32/64 variable arguments. 72235633Sdim// All arguments are passed in integer registers. 73235633Sdimdef CC_MipsN_VarArg : CallingConv<[ 74235633Sdim // Promote i8/i16 arguments to i32. 75235633Sdim CCIfType<[i8, i16], CCPromoteToType<i32>>, 76235633Sdim 77235633Sdim CCIfType<[i32, f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, 78235633Sdim 79235633Sdim CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, 80235633Sdim T0_64, T1_64, T2_64, T3_64]>>, 81235633Sdim 82235633Sdim // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. 83235633Sdim CCIfType<[i32, f32], CCAssignToStack<4, 8>>, 84235633Sdim CCIfType<[i64, f64], CCAssignToStack<8, 8>> 85235633Sdim]>; 86235633Sdim 87226890Sdimdef RetCC_MipsN : CallingConv<[ 88226890Sdim // i32 are returned in registers V0, V1 89226890Sdim CCIfType<[i32], CCAssignToReg<[V0, V1]>>, 90226890Sdim 91226890Sdim // i64 are returned in registers V0_64, V1_64 92226890Sdim CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>, 93226890Sdim 94226890Sdim // f32 are returned in registers F0, F2 95226890Sdim CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 96226890Sdim 97226890Sdim // f64 are returned in registers D0, D2 98226890Sdim CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>> 99226890Sdim]>; 100226890Sdim 101252723Sdim// In soft-mode, register A0_64, instead of V1_64, is used to return a long 102252723Sdim// double value. 103252723Sdimdef RetCC_F128Soft : CallingConv<[ 104252723Sdim CCIfType<[i64], CCAssignToReg<[V0_64, A0_64]>> 105252723Sdim]>; 106252723Sdim 107226890Sdim//===----------------------------------------------------------------------===// 108193323Sed// Mips EABI Calling Convention 109193323Sed//===----------------------------------------------------------------------===// 110193323Sed 111193323Seddef CC_MipsEABI : CallingConv<[ 112193323Sed // Promote i8/i16 arguments to i32. 113193323Sed CCIfType<[i8, i16], CCPromoteToType<i32>>, 114193323Sed 115193323Sed // Integer arguments are passed in integer registers. 116193323Sed CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, 117193323Sed 118221345Sdim // Single fp arguments are passed in pairs within 32-bit mode 119221345Sdim CCIfType<[f32], CCIfSubtarget<"isSingleFloat()", 120193323Sed CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>, 121193323Sed 122221345Sdim CCIfType<[f32], CCIfSubtarget<"isNotSingleFloat()", 123193323Sed CCAssignToReg<[F12, F14, F16, F18]>>>, 124193323Sed 125221345Sdim // The first 4 double fp arguments are passed in single fp registers. 126221345Sdim CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", 127193323Sed CCAssignToReg<[D6, D7, D8, D9]>>>, 128193323Sed 129193323Sed // Integer values get stored in stack slots that are 4 bytes in 130193323Sed // size and 4-byte aligned. 131193323Sed CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 132193323Sed 133193323Sed // Integer values get stored in stack slots that are 8 bytes in 134193323Sed // size and 8-byte aligned. 135193323Sed CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToStack<8, 8>>> 136193323Sed]>; 137193323Sed 138193323Seddef RetCC_MipsEABI : CallingConv<[ 139193323Sed // i32 are returned in registers V0, V1 140193323Sed CCIfType<[i32], CCAssignToReg<[V0, V1]>>, 141193323Sed 142193323Sed // f32 are returned in registers F0, F1 143193323Sed CCIfType<[f32], CCAssignToReg<[F0, F1]>>, 144193323Sed 145193323Sed // f64 are returned in register D0 146193323Sed CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>> 147193323Sed]>; 148193323Sed 149193323Sed//===----------------------------------------------------------------------===// 150245431Sdim// Mips FastCC Calling Convention 151245431Sdim//===----------------------------------------------------------------------===// 152245431Sdimdef CC_MipsO32_FastCC : CallingConv<[ 153245431Sdim // f64 arguments are passed in double-precision floating pointer registers. 154263509Sdim CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()", 155263509Sdim CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7, 156263509Sdim D8, D9]>>>, 157263509Sdim CCIfType<[f64], CCIfSubtarget<"isFP64bit()", 158263509Sdim CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, 159263509Sdim D4_64, D5_64, D6_64, D7_64, 160263509Sdim D8_64, D9_64, D10_64, D11_64, 161263509Sdim D12_64, D13_64, D14_64, D15_64, 162263509Sdim D16_64, D17_64, D18_64, 163263509Sdim D19_64]>>>, 164245431Sdim 165245431Sdim // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned. 166245431Sdim CCIfType<[f64], CCAssignToStack<8, 8>> 167245431Sdim]>; 168245431Sdim 169245431Sdimdef CC_MipsN_FastCC : CallingConv<[ 170245431Sdim // Integer arguments are passed in integer registers. 171245431Sdim CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64, 172245431Sdim T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 173245431Sdim T8_64, V1_64]>>, 174245431Sdim 175245431Sdim // f64 arguments are passed in double-precision floating pointer registers. 176245431Sdim CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64, 177245431Sdim D6_64, D7_64, D8_64, D9_64, D10_64, D11_64, 178245431Sdim D12_64, D13_64, D14_64, D15_64, D16_64, D17_64, 179245431Sdim D18_64, D19_64]>>, 180245431Sdim 181245431Sdim // Stack parameter slots for i64 and f64 are 64-bit doublewords and 182245431Sdim // 8-byte aligned. 183245431Sdim CCIfType<[i64, f64], CCAssignToStack<8, 8>> 184245431Sdim]>; 185245431Sdim 186245431Sdimdef CC_Mips_FastCC : CallingConv<[ 187245431Sdim // Handles byval parameters. 188245431Sdim CCIfByVal<CCPassByVal<4, 4>>, 189245431Sdim 190245431Sdim // Promote i8/i16 arguments to i32. 191245431Sdim CCIfType<[i8, i16], CCPromoteToType<i32>>, 192245431Sdim 193245431Sdim // Integer arguments are passed in integer registers. All scratch registers, 194245431Sdim // except for AT, V0 and T9, are available to be used as argument registers. 195245431Sdim CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, 196245431Sdim T7, T8, V1]>>, 197245431Sdim 198245431Sdim // f32 arguments are passed in single-precision floating pointer registers. 199245431Sdim CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, 200245431Sdim F11, F12, F13, F14, F15, F16, F17, F18, F19]>>, 201245431Sdim 202245431Sdim // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned. 203245431Sdim CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 204245431Sdim 205226890Sdim CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>, 206245431Sdim CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>, 207245431Sdim CCDelegateTo<CC_MipsN_FastCC> 208193323Sed]>; 209193323Sed 210263509Sdim//== 211263509Sdim 212263509Sdimdef CC_Mips16RetHelper : CallingConv<[ 213263509Sdim // Integer arguments are passed in integer registers. 214263509Sdim CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>> 215263509Sdim]>; 216263509Sdim 217245431Sdim//===----------------------------------------------------------------------===// 218245431Sdim// Mips Calling Convention Dispatch 219245431Sdim//===----------------------------------------------------------------------===// 220245431Sdim 221193323Seddef RetCC_Mips : CallingConv<[ 222193323Sed CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>, 223226890Sdim CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>, 224226890Sdim CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>, 225193323Sed CCDelegateTo<RetCC_MipsO32> 226193323Sed]>; 227235633Sdim 228235633Sdim//===----------------------------------------------------------------------===// 229235633Sdim// Callee-saved register lists. 230235633Sdim//===----------------------------------------------------------------------===// 231235633Sdim 232235633Sdimdef CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP, 233235633Sdim (sequence "S%u", 7, 0))>; 234235633Sdim 235235633Sdimdef CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, 236235633Sdim (sequence "S%u", 7, 0))>; 237235633Sdim 238263509Sdimdef CSR_O32_FP64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 20), RA, FP, 239263509Sdim (sequence "S%u", 7, 0))>; 240263509Sdim 241235633Sdimdef CSR_N32 : CalleeSavedRegs<(add D31_64, D29_64, D27_64, D25_64, D24_64, 242235633Sdim D23_64, D22_64, D21_64, RA_64, FP_64, GP_64, 243235633Sdim (sequence "S%u_64", 7, 0))>; 244235633Sdim 245235633Sdimdef CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64, 246235633Sdim GP_64, (sequence "S%u_64", 7, 0))>; 247263509Sdim 248263509Sdimdef CSR_Mips16RetHelper : 249263509Sdim CalleeSavedRegs<(add V0, V1, (sequence "A%u", 3, 0), S0, S1)>; 250