1235633Sdim//===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===// 2235633Sdim// 3235633Sdim// The LLVM Compiler Infrastructure 4235633Sdim// 5235633Sdim// This file is distributed under the University of Illinois Open Source 6235633Sdim// License. See LICENSE.TXT for details. 7235633Sdim// 8235633Sdim//===----------------------------------------------------------------------===// 9235633Sdim// 10235633Sdim// This file implements the MipsAsmBackend and MipsELFObjectWriter classes. 11235633Sdim// 12235633Sdim//===----------------------------------------------------------------------===// 13235633Sdim// 14235633Sdim 15235633Sdim#include "MipsFixupKinds.h" 16226584Sdim#include "MCTargetDesc/MipsMCTargetDesc.h" 17235633Sdim#include "llvm/MC/MCAsmBackend.h" 18226584Sdim#include "llvm/MC/MCAssembler.h" 19226584Sdim#include "llvm/MC/MCDirectives.h" 20226584Sdim#include "llvm/MC/MCELFObjectWriter.h" 21235633Sdim#include "llvm/MC/MCFixupKindInfo.h" 22226584Sdim#include "llvm/MC/MCObjectWriter.h" 23226584Sdim#include "llvm/MC/MCSubtargetInfo.h" 24226584Sdim#include "llvm/Support/ErrorHandling.h" 25226584Sdim#include "llvm/Support/raw_ostream.h" 26235633Sdim 27226584Sdimusing namespace llvm; 28226584Sdim 29235633Sdim// Prepare value for the target space for it 30235633Sdimstatic unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 31235633Sdim 32235633Sdim // Add/subtract and shift 33235633Sdim switch (Kind) { 34235633Sdim default: 35235633Sdim return 0; 36235633Sdim case FK_GPRel_4: 37235633Sdim case FK_Data_4: 38245431Sdim case FK_Data_8: 39235633Sdim case Mips::fixup_Mips_LO16: 40252723Sdim case Mips::fixup_Mips_GPREL16: 41245431Sdim case Mips::fixup_Mips_GPOFF_HI: 42245431Sdim case Mips::fixup_Mips_GPOFF_LO: 43245431Sdim case Mips::fixup_Mips_GOT_PAGE: 44245431Sdim case Mips::fixup_Mips_GOT_OFST: 45245431Sdim case Mips::fixup_Mips_GOT_DISP: 46245431Sdim case Mips::fixup_Mips_GOT_LO16: 47245431Sdim case Mips::fixup_Mips_CALL_LO16: 48263509Sdim case Mips::fixup_MICROMIPS_LO16: 49263509Sdim case Mips::fixup_MICROMIPS_GOT_PAGE: 50263509Sdim case Mips::fixup_MICROMIPS_GOT_OFST: 51263509Sdim case Mips::fixup_MICROMIPS_GOT_DISP: 52235633Sdim break; 53235633Sdim case Mips::fixup_Mips_PC16: 54235633Sdim // So far we are only using this type for branches. 55235633Sdim // For branches we start 1 instruction after the branch 56235633Sdim // so the displacement will be one instruction size less. 57235633Sdim Value -= 4; 58235633Sdim // The displacement is then divided by 4 to give us an 18 bit 59235633Sdim // address range. 60235633Sdim Value >>= 2; 61235633Sdim break; 62235633Sdim case Mips::fixup_Mips_26: 63235633Sdim // So far we are only using this type for jumps. 64235633Sdim // The displacement is then divided by 4 to give us an 28 bit 65235633Sdim // address range. 66235633Sdim Value >>= 2; 67235633Sdim break; 68235633Sdim case Mips::fixup_Mips_HI16: 69235633Sdim case Mips::fixup_Mips_GOT_Local: 70245431Sdim case Mips::fixup_Mips_GOT_HI16: 71245431Sdim case Mips::fixup_Mips_CALL_HI16: 72263509Sdim case Mips::fixup_MICROMIPS_HI16: 73245431Sdim // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. 74235633Sdim Value = ((Value + 0x8000) >> 16) & 0xffff; 75235633Sdim break; 76245431Sdim case Mips::fixup_Mips_HIGHER: 77245431Sdim // Get the 3rd 16-bits. 78245431Sdim Value = ((Value + 0x80008000LL) >> 32) & 0xffff; 79245431Sdim break; 80245431Sdim case Mips::fixup_Mips_HIGHEST: 81245431Sdim // Get the 4th 16-bits. 82245431Sdim Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; 83245431Sdim break; 84263509Sdim case Mips::fixup_MICROMIPS_26_S1: 85263509Sdim Value >>= 1; 86263509Sdim break; 87263509Sdim case Mips::fixup_MICROMIPS_PC16_S1: 88263509Sdim Value -= 4; 89263509Sdim Value >>= 1; 90263509Sdim break; 91235633Sdim } 92235633Sdim 93235633Sdim return Value; 94235633Sdim} 95235633Sdim 96226584Sdimnamespace { 97235633Sdimclass MipsAsmBackend : public MCAsmBackend { 98235633Sdim Triple::OSType OSType; 99235633Sdim bool IsLittle; // Big or little endian 100235633Sdim bool Is64Bit; // 32 or 64 bit words 101226584Sdim 102226584Sdimpublic: 103235633Sdim MipsAsmBackend(const Target &T, Triple::OSType _OSType, 104235633Sdim bool _isLittle, bool _is64Bit) 105235633Sdim :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {} 106226584Sdim 107235633Sdim MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 108245431Sdim return createMipsELFObjectWriter(OS, 109245431Sdim MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); 110226584Sdim } 111226584Sdim 112245431Sdim /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided 113226584Sdim /// data fragment, at the offset specified by the fixup and following the 114226584Sdim /// fixup kind as appropriate. 115235633Sdim void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 116226584Sdim uint64_t Value) const { 117235633Sdim MCFixupKind Kind = Fixup.getKind(); 118235633Sdim Value = adjustFixupValue((unsigned)Kind, Value); 119235633Sdim 120235633Sdim if (!Value) 121235633Sdim return; // Doesn't change encoding. 122235633Sdim 123235633Sdim // Where do we start in the object 124235633Sdim unsigned Offset = Fixup.getOffset(); 125235633Sdim // Number of bytes we need to fixup 126235633Sdim unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 127235633Sdim // Used to point to big endian bytes 128235633Sdim unsigned FullSize; 129235633Sdim 130235633Sdim switch ((unsigned)Kind) { 131235633Sdim case Mips::fixup_Mips_16: 132235633Sdim FullSize = 2; 133235633Sdim break; 134235633Sdim case Mips::fixup_Mips_64: 135235633Sdim FullSize = 8; 136235633Sdim break; 137235633Sdim default: 138235633Sdim FullSize = 4; 139235633Sdim break; 140235633Sdim } 141235633Sdim 142235633Sdim // Grab current value, if any, from bits. 143235633Sdim uint64_t CurVal = 0; 144235633Sdim 145235633Sdim for (unsigned i = 0; i != NumBytes; ++i) { 146235633Sdim unsigned Idx = IsLittle ? i : (FullSize - 1 - i); 147235633Sdim CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 148235633Sdim } 149235633Sdim 150245431Sdim uint64_t Mask = ((uint64_t)(-1) >> 151245431Sdim (64 - getFixupKindInfo(Kind).TargetSize)); 152235633Sdim CurVal |= Value & Mask; 153235633Sdim 154235633Sdim // Write out the fixed up bytes back to the code/data bits. 155235633Sdim for (unsigned i = 0; i != NumBytes; ++i) { 156235633Sdim unsigned Idx = IsLittle ? i : (FullSize - 1 - i); 157235633Sdim Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 158235633Sdim } 159226584Sdim } 160226584Sdim 161235633Sdim unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; } 162235633Sdim 163235633Sdim const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 164235633Sdim const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = { 165235633Sdim // This table *must* be in same the order of fixup_* kinds in 166235633Sdim // MipsFixupKinds.h. 167235633Sdim // 168235633Sdim // name offset bits flags 169235633Sdim { "fixup_Mips_16", 0, 16, 0 }, 170235633Sdim { "fixup_Mips_32", 0, 32, 0 }, 171235633Sdim { "fixup_Mips_REL32", 0, 32, 0 }, 172235633Sdim { "fixup_Mips_26", 0, 26, 0 }, 173235633Sdim { "fixup_Mips_HI16", 0, 16, 0 }, 174235633Sdim { "fixup_Mips_LO16", 0, 16, 0 }, 175235633Sdim { "fixup_Mips_GPREL16", 0, 16, 0 }, 176235633Sdim { "fixup_Mips_LITERAL", 0, 16, 0 }, 177235633Sdim { "fixup_Mips_GOT_Global", 0, 16, 0 }, 178235633Sdim { "fixup_Mips_GOT_Local", 0, 16, 0 }, 179235633Sdim { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 180235633Sdim { "fixup_Mips_CALL16", 0, 16, 0 }, 181235633Sdim { "fixup_Mips_GPREL32", 0, 32, 0 }, 182235633Sdim { "fixup_Mips_SHIFT5", 6, 5, 0 }, 183235633Sdim { "fixup_Mips_SHIFT6", 6, 5, 0 }, 184235633Sdim { "fixup_Mips_64", 0, 64, 0 }, 185235633Sdim { "fixup_Mips_TLSGD", 0, 16, 0 }, 186235633Sdim { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 187235633Sdim { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 188235633Sdim { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 189235633Sdim { "fixup_Mips_TLSLDM", 0, 16, 0 }, 190235633Sdim { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 191235633Sdim { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 192245431Sdim { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 193245431Sdim { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 194245431Sdim { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 195245431Sdim { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 196245431Sdim { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 197245431Sdim { "fixup_Mips_GOT_DISP", 0, 16, 0 }, 198245431Sdim { "fixup_Mips_HIGHER", 0, 16, 0 }, 199245431Sdim { "fixup_Mips_HIGHEST", 0, 16, 0 }, 200245431Sdim { "fixup_Mips_GOT_HI16", 0, 16, 0 }, 201245431Sdim { "fixup_Mips_GOT_LO16", 0, 16, 0 }, 202245431Sdim { "fixup_Mips_CALL_HI16", 0, 16, 0 }, 203263509Sdim { "fixup_Mips_CALL_LO16", 0, 16, 0 }, 204263509Sdim { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, 205263509Sdim { "fixup_MICROMIPS_HI16", 0, 16, 0 }, 206263509Sdim { "fixup_MICROMIPS_LO16", 0, 16, 0 }, 207263509Sdim { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, 208263509Sdim { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 209263509Sdim { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, 210263509Sdim { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, 211263509Sdim { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, 212263509Sdim { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, 213263509Sdim { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, 214263509Sdim { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, 215263509Sdim { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, 216263509Sdim { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 } 217235633Sdim }; 218235633Sdim 219235633Sdim if (Kind < FirstTargetFixupKind) 220235633Sdim return MCAsmBackend::getFixupKindInfo(Kind); 221235633Sdim 222235633Sdim assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 223235633Sdim "Invalid kind!"); 224235633Sdim return Infos[Kind - FirstTargetFixupKind]; 225235633Sdim } 226235633Sdim 227226584Sdim /// @name Target Relaxation Interfaces 228226584Sdim /// @{ 229226584Sdim 230226584Sdim /// MayNeedRelaxation - Check whether the given instruction may need 231226584Sdim /// relaxation. 232226584Sdim /// 233226584Sdim /// \param Inst - The instruction to test. 234235633Sdim bool mayNeedRelaxation(const MCInst &Inst) const { 235226584Sdim return false; 236226584Sdim } 237226584Sdim 238235633Sdim /// fixupNeedsRelaxation - Target specific predicate for whether a given 239235633Sdim /// fixup requires the associated instruction to be relaxed. 240235633Sdim bool fixupNeedsRelaxation(const MCFixup &Fixup, 241235633Sdim uint64_t Value, 242252723Sdim const MCRelaxableFragment *DF, 243235633Sdim const MCAsmLayout &Layout) const { 244235633Sdim // FIXME. 245235633Sdim assert(0 && "RelaxInstruction() unimplemented"); 246235633Sdim return false; 247235633Sdim } 248235633Sdim 249235633Sdim /// RelaxInstruction - Relax the instruction in the given fragment 250235633Sdim /// to the next wider instruction. 251226584Sdim /// 252235633Sdim /// \param Inst - The instruction to relax, which may be the same 253235633Sdim /// as the output. 254245431Sdim /// \param [out] Res On return, the relaxed instruction. 255235633Sdim void relaxInstruction(const MCInst &Inst, MCInst &Res) const { 256226584Sdim } 257235633Sdim 258226584Sdim /// @} 259226584Sdim 260235633Sdim /// WriteNopData - Write an (optimal) nop sequence of Count bytes 261235633Sdim /// to the given output. If the target cannot generate such a sequence, 262235633Sdim /// it should return an error. 263226584Sdim /// 264226584Sdim /// \return - True on success. 265235633Sdim bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { 266245431Sdim // Check for a less than instruction size number of bytes 267245431Sdim // FIXME: 16 bit instructions are not handled yet here. 268245431Sdim // We shouldn't be using a hard coded number for instruction size. 269245431Sdim if (Count % 4) return false; 270245431Sdim 271245431Sdim uint64_t NumNops = Count / 4; 272245431Sdim for (uint64_t i = 0; i != NumNops; ++i) 273245431Sdim OW->Write32(0); 274235633Sdim return true; 275226584Sdim } 276235633Sdim}; // class MipsAsmBackend 277226584Sdim 278235633Sdim} // namespace 279226584Sdim 280235633Sdim// MCAsmBackend 281263509SdimMCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, 282263509Sdim const MCRegisterInfo &MRI, 283263509Sdim StringRef TT, 284241506Sdim StringRef CPU) { 285235633Sdim return new MipsAsmBackend(T, Triple(TT).getOS(), 286235633Sdim /*IsLittle*/true, /*Is64Bit*/false); 287235633Sdim} 288226584Sdim 289263509SdimMCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, 290263509Sdim const MCRegisterInfo &MRI, 291263509Sdim StringRef TT, 292241506Sdim StringRef CPU) { 293235633Sdim return new MipsAsmBackend(T, Triple(TT).getOS(), 294235633Sdim /*IsLittle*/false, /*Is64Bit*/false); 295235633Sdim} 296226584Sdim 297263509SdimMCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, 298263509Sdim const MCRegisterInfo &MRI, 299263509Sdim StringRef TT, 300241506Sdim StringRef CPU) { 301235633Sdim return new MipsAsmBackend(T, Triple(TT).getOS(), 302235633Sdim /*IsLittle*/true, /*Is64Bit*/true); 303235633Sdim} 304226584Sdim 305263509SdimMCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, 306263509Sdim const MCRegisterInfo &MRI, 307263509Sdim StringRef TT, 308241506Sdim StringRef CPU) { 309235633Sdim return new MipsAsmBackend(T, Triple(TT).getOS(), 310235633Sdim /*IsLittle*/false, /*Is64Bit*/true); 311226584Sdim} 312226584Sdim 313