1235633Sdim//===-- MSP430InstrInfo.h - MSP430 Instruction Information ------*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the MSP430 implementation of the TargetInstrInfo class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#ifndef LLVM_TARGET_MSP430INSTRINFO_H 15193323Sed#define LLVM_TARGET_MSP430INSTRINFO_H 16193323Sed 17235633Sdim#include "MSP430RegisterInfo.h" 18193323Sed#include "llvm/Target/TargetInstrInfo.h" 19193323Sed 20224145Sdim#define GET_INSTRINFO_HEADER 21224145Sdim#include "MSP430GenInstrInfo.inc" 22224145Sdim 23193323Sednamespace llvm { 24193323Sed 25193323Sedclass MSP430TargetMachine; 26193323Sed 27202878Srdivacky/// MSP430II - This namespace holds all of the target specific flags that 28202878Srdivacky/// instruction info tracks. 29202878Srdivacky/// 30202878Srdivackynamespace MSP430II { 31202878Srdivacky enum { 32202878Srdivacky SizeShift = 2, 33202878Srdivacky SizeMask = 7 << SizeShift, 34202878Srdivacky 35202878Srdivacky SizeUnknown = 0 << SizeShift, 36202878Srdivacky SizeSpecial = 1 << SizeShift, 37202878Srdivacky Size2Bytes = 2 << SizeShift, 38202878Srdivacky Size4Bytes = 3 << SizeShift, 39202878Srdivacky Size6Bytes = 4 << SizeShift 40202878Srdivacky }; 41202878Srdivacky} 42202878Srdivacky 43224145Sdimclass MSP430InstrInfo : public MSP430GenInstrInfo { 44193323Sed const MSP430RegisterInfo RI; 45263509Sdim virtual void anchor(); 46193323Sedpublic: 47193323Sed explicit MSP430InstrInfo(MSP430TargetMachine &TM); 48193323Sed 49193323Sed /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 50193323Sed /// such, whenever a client has an instance of instruction info, it should 51193323Sed /// always be able to get register info as well (through this method). 52193323Sed /// 53193323Sed virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } 54193323Sed 55210299Sed void copyPhysReg(MachineBasicBlock &MBB, 56210299Sed MachineBasicBlock::iterator I, DebugLoc DL, 57210299Sed unsigned DestReg, unsigned SrcReg, 58210299Sed bool KillSrc) const; 59193323Sed 60193323Sed virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 61193323Sed MachineBasicBlock::iterator MI, 62193323Sed unsigned SrcReg, bool isKill, 63193323Sed int FrameIndex, 64208599Srdivacky const TargetRegisterClass *RC, 65208599Srdivacky const TargetRegisterInfo *TRI) const; 66193323Sed virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 67193323Sed MachineBasicBlock::iterator MI, 68193323Sed unsigned DestReg, int FrameIdx, 69208599Srdivacky const TargetRegisterClass *RC, 70208599Srdivacky const TargetRegisterInfo *TRI) const; 71193323Sed 72202878Srdivacky unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 73202878Srdivacky 74198396Srdivacky // Branch folding goodness 75198396Srdivacky bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 76198396Srdivacky bool isUnpredicatedTerminator(const MachineInstr *MI) const; 77198396Srdivacky bool AnalyzeBranch(MachineBasicBlock &MBB, 78198396Srdivacky MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 79198396Srdivacky SmallVectorImpl<MachineOperand> &Cond, 80198396Srdivacky bool AllowModify) const; 81193323Sed 82198396Srdivacky unsigned RemoveBranch(MachineBasicBlock &MBB) const; 83198396Srdivacky unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 84198396Srdivacky MachineBasicBlock *FBB, 85210299Sed const SmallVectorImpl<MachineOperand> &Cond, 86210299Sed DebugLoc DL) const; 87198396Srdivacky 88193323Sed}; 89193323Sed 90193323Sed} 91193323Sed 92193323Sed#endif 93