HexagonTargetMachine.cpp revision 245431 
1//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Implements the info about Hexagon target spec.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonTargetMachine.h"
15#include "Hexagon.h"
16#include "HexagonISelLowering.h"
17#include "HexagonMachineScheduler.h"
18#include "llvm/Module.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/PassManager.h"
21#include "llvm/Transforms/IPO/PassManagerBuilder.h"
22#include "llvm/Transforms/Scalar.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/TargetRegistry.h"
25
26using namespace llvm;
27
28static cl::
29opt<bool> DisableHardwareLoops(
30                        "disable-hexagon-hwloops", cl::Hidden,
31                        cl::desc("Disable Hardware Loops for Hexagon target"));
32
33static cl::
34opt<bool> DisableHexagonMISched("disable-hexagon-misched",
35                                cl::Hidden, cl::ZeroOrMore, cl::init(false),
36                                cl::desc("Disable Hexagon MI Scheduling"));
37
38/// HexagonTargetMachineModule - Note that this is used on hosts that
39/// cannot link in a library unless there are references into the
40/// library.  In particular, it seems that it is not possible to get
41/// things to work on Win32 without this.  Though it is unused, do not
42/// remove it.
43extern "C" int HexagonTargetMachineModule;
44int HexagonTargetMachineModule = 0;
45
46extern "C" void LLVMInitializeHexagonTarget() {
47  // Register the target.
48  RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
49}
50
51static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
52  return new VLIWMachineScheduler(C, new ConvergingVLIWScheduler());
53}
54
55static MachineSchedRegistry
56SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
57                    createVLIWMachineSched);
58
59/// HexagonTargetMachine ctor - Create an ILP32 architecture model.
60///
61
62/// Hexagon_TODO: Do I need an aggregate alignment?
63///
64HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
65                                           StringRef CPU, StringRef FS,
66                                           const TargetOptions &Options,
67                                           Reloc::Model RM,
68                                           CodeModel::Model CM,
69                                           CodeGenOpt::Level OL)
70  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
71    DL("e-p:32:32:32-"
72                "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
73                "f64:64:64-f32:32:32-a0:0-n32") ,
74    Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
75    TSInfo(*this),
76    FrameLowering(Subtarget),
77    InstrItins(&Subtarget.getInstrItineraryData()),
78    STTI(&TLInfo), VTTI(&TLInfo) {
79  setMCUseCFI(false);
80}
81
82// addPassesForOptimizations - Allow the backend (target) to add Target
83// Independent Optimization passes to the Pass Manager.
84bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
85
86  PM.add(createConstantPropagationPass());
87  PM.add(createLoopSimplifyPass());
88  PM.add(createDeadCodeEliminationPass());
89  PM.add(createConstantPropagationPass());
90  PM.add(createLoopUnrollPass());
91  PM.add(createLoopStrengthReducePass());
92  return true;
93}
94
95namespace {
96/// Hexagon Code Generator Pass Configuration Options.
97class HexagonPassConfig : public TargetPassConfig {
98public:
99  HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
100    : TargetPassConfig(TM, PM) {
101    // Enable MI scheduler.
102    if (!DisableHexagonMISched) {
103      enablePass(&MachineSchedulerID);
104      MachineSchedRegistry::setDefault(createVLIWMachineSched);
105    }
106  }
107
108  HexagonTargetMachine &getHexagonTargetMachine() const {
109    return getTM<HexagonTargetMachine>();
110  }
111
112  virtual bool addInstSelector();
113  virtual bool addPreRegAlloc();
114  virtual bool addPostRegAlloc();
115  virtual bool addPreSched2();
116  virtual bool addPreEmitPass();
117};
118} // namespace
119
120TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
121  return new HexagonPassConfig(this, PM);
122}
123
124bool HexagonPassConfig::addInstSelector() {
125  addPass(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
126  addPass(createHexagonISelDag(getHexagonTargetMachine()));
127  addPass(createHexagonPeephole());
128  return false;
129}
130
131
132bool HexagonPassConfig::addPreRegAlloc() {
133  if (!DisableHardwareLoops) {
134    addPass(createHexagonHardwareLoops());
135  }
136  return false;
137}
138
139bool HexagonPassConfig::addPostRegAlloc() {
140  addPass(createHexagonCFGOptimizer(getHexagonTargetMachine()));
141  return true;
142}
143
144
145bool HexagonPassConfig::addPreSched2() {
146  addPass(&IfConverterID);
147  return true;
148}
149
150bool HexagonPassConfig::addPreEmitPass() {
151
152  if (!DisableHardwareLoops) {
153    addPass(createHexagonFixupHwLoops());
154  }
155
156  addPass(createHexagonNewValueJump());
157
158  // Expand Spill code for predicate registers.
159  addPass(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
160
161  // Split up TFRcondsets into conditional transfers.
162  addPass(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
163
164  // Create Packets.
165  addPass(createHexagonPacketizer());
166
167  return false;
168}
169