HexagonRegisterInfo.h revision 263509
1159720Syar//==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==// 2159720Syar// 3159720Syar// The LLVM Compiler Infrastructure 4159720Syar// 5159720Syar// This file is distributed under the University of Illinois Open Source 6159720Syar// License. See LICENSE.TXT for details. 7159720Syar// 8159720Syar//===----------------------------------------------------------------------===// 9159720Syar// 10159720Syar// This file contains the Hexagon implementation of the TargetRegisterInfo 11159720Syar// class. 12159720Syar// 13159720Syar//===----------------------------------------------------------------------===// 14159720Syar 15159720Syar#ifndef HexagonREGISTERINFO_H 16159720Syar#define HexagonREGISTERINFO_H 17159720Syar 18159720Syar#include "llvm/MC/MachineLocation.h" 19159720Syar#include "llvm/Target/TargetRegisterInfo.h" 20159720Syar 21159720Syar#define GET_REGINFO_HEADER 22159720Syar#include "HexagonGenRegisterInfo.inc" 23159720Syar 24159720Syar// 25159720Syar// We try not to hard code the reserved registers in our code, 26159720Syar// so the following two macros were defined. However, there 27159720Syar// are still a few places that R11 and R10 are hard wired. 28159720Syar// See below. If, in the future, we decided to change the reserved 29159720Syar// register. Don't forget changing the following places. 30159720Syar// 31159720Syar// 1. the "Defs" set of STriw_pred in HexagonInstrInfo.td 32159720Syar// 2. the "Defs" set of LDri_pred in HexagonInstrInfo.td 33159720Syar// 3. the definition of "IntRegs" in HexagonRegisterInfo.td 34159720Syar// 4. the definition of "DoubleRegs" in HexagonRegisterInfo.td 35159720Syar// 36159720Syar#define HEXAGON_RESERVED_REG_1 Hexagon::R10 37159720Syar#define HEXAGON_RESERVED_REG_2 Hexagon::R11 38159720Syar 39159720Syarnamespace llvm { 40159720Syar 41159720Syarclass HexagonSubtarget; 42159720Syarclass HexagonInstrInfo; 43159720Syarclass Type; 44159720Syar 45159720Syarstruct HexagonRegisterInfo : public HexagonGenRegisterInfo { 46159720Syar HexagonSubtarget &Subtarget; 47159720Syar 48159720Syar HexagonRegisterInfo(HexagonSubtarget &st); 49159720Syar 50159720Syar /// Code Generation virtual methods... 51159720Syar const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const; 52159720Syar 53159720Syar const TargetRegisterClass* const* getCalleeSavedRegClasses( 54159720Syar const MachineFunction *MF = 0) const; 55159720Syar 56159720Syar BitVector getReservedRegs(const MachineFunction &MF) const; 57159720Syar 58159720Syar void eliminateFrameIndex(MachineBasicBlock::iterator II, 59159720Syar int SPAdj, unsigned FIOperandNum, 60159720Syar RegScavenger *RS = NULL) const; 61159720Syar 62159720Syar /// determineFrameLayout - Determine the size of the frame and maximum call 63159720Syar /// frame size. 64159720Syar void determineFrameLayout(MachineFunction &MF) const; 65159720Syar 66159720Syar /// requiresRegisterScavenging - returns true since we may need scavenging for 67159720Syar /// a temporary register when generating hardware loop instructions. 68159720Syar bool requiresRegisterScavenging(const MachineFunction &MF) const { 69159720Syar return true; 70159720Syar } 71159720Syar 72159720Syar bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 73159720Syar return true; 74 } 75 76 // Debug information queries. 77 unsigned getRARegister() const; 78 unsigned getFrameRegister(const MachineFunction &MF) const; 79 unsigned getFrameRegister() const; 80 unsigned getStackRegister() const; 81}; 82 83} // end namespace llvm 84 85#endif 86