1207618Srdivacky//=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=// 2210299Sed// 3207618Srdivacky// The LLVM Compiler Infrastructure 4207618Srdivacky// 5207618Srdivacky// This file is distributed under the University of Illinois Open Source 6207618Srdivacky// License. See LICENSE.TXT for details. 7210299Sed// 8207618Srdivacky//===----------------------------------------------------------------------===// 9207618Srdivacky// 10207618Srdivacky// This file defines the itinerary class data for the ARM Cortex A8 processors. 11207618Srdivacky// 12207618Srdivacky//===----------------------------------------------------------------------===// 13207618Srdivacky 14207618Srdivacky// 15207618Srdivacky// Scheduling information derived from "Cortex-A8 Technical Reference Manual". 16207618Srdivacky// Functional Units. 17207618Srdivackydef A8_Pipe0 : FuncUnit; // pipeline 0 18207618Srdivackydef A8_Pipe1 : FuncUnit; // pipeline 1 19218893Sdimdef A8_LSPipe : FuncUnit; // Load / store pipeline 20207618Srdivackydef A8_NPipe : FuncUnit; // NEON ALU/MUL pipe 21207618Srdivackydef A8_NLSPipe : FuncUnit; // NEON LS pipe 22207618Srdivacky// 23207618Srdivacky// Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1 24207618Srdivacky// 25207618Srdivackydef CortexA8Itineraries : ProcessorItineraries< 26218893Sdim [A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe], 27218893Sdim [], [ 28207618Srdivacky // Two fully-pipelined integer ALU pipelines 29207618Srdivacky // 30207618Srdivacky // No operand cycles 31207618Srdivacky InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>, 32207618Srdivacky // 33207618Srdivacky // Binary Instructions that produce a result 34210299Sed InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 35210299Sed InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>, 36210299Sed InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, 37218893Sdim InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>, 38210299Sed InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>, 39207618Srdivacky // 40218893Sdim // Bitwise Instructions that produce a result 41218893Sdim InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 42218893Sdim InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>, 43218893Sdim InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, 44218893Sdim InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>, 45218893Sdim // 46207618Srdivacky // Unary Instructions that produce a result 47210299Sed InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 48210299Sed InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, 49207618Srdivacky // 50218893Sdim // Zero and sign extension instructions 51218893Sdim InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, 52218893Sdim InstrItinData<IIC_iEXTAr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, 53218893Sdim InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>],[2, 2, 1, 1]>, 54218893Sdim // 55207618Srdivacky // Compare instructions 56210299Sed InstrItinData<IIC_iCMPi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>, 57210299Sed InstrItinData<IIC_iCMPr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 58210299Sed InstrItinData<IIC_iCMPsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, 59210299Sed InstrItinData<IIC_iCMPsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>, 60207618Srdivacky // 61218893Sdim // Test instructions 62218893Sdim InstrItinData<IIC_iTSTi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>, 63218893Sdim InstrItinData<IIC_iTSTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 64218893Sdim InstrItinData<IIC_iTSTsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, 65218893Sdim InstrItinData<IIC_iTSTsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>, 66218893Sdim // 67207618Srdivacky // Move instructions, unconditional 68210299Sed InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>, 69210299Sed InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, 70210299Sed InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, 71210299Sed InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>, 72218893Sdim InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 73218893Sdim InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>, 74218893Sdim InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 75218893Sdim InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 76218893Sdim InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [3]>, 77218893Sdim InstrItinData<IIC_iMOVix2ld,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 78218893Sdim InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 79218893Sdim InstrStage<1, [A8_LSPipe]>], [5]>, 80207618Srdivacky // 81207618Srdivacky // Move instructions, conditional 82210299Sed InstrItinData<IIC_iCMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2]>, 83210299Sed InstrItinData<IIC_iCMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, 84210299Sed InstrItinData<IIC_iCMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, 85210299Sed InstrItinData<IIC_iCMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>, 86218893Sdim InstrItinData<IIC_iCMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 87218893Sdim InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [3, 1]>, 88218893Sdim // 89218893Sdim // MVN instructions 90218893Sdim InstrItinData<IIC_iMVNi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>, 91218893Sdim InstrItinData<IIC_iMVNr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, 92218893Sdim InstrItinData<IIC_iMVNsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, 93218893Sdim InstrItinData<IIC_iMVNsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>, 94207618Srdivacky 95207618Srdivacky // Integer multiply pipeline 96207618Srdivacky // Result written in E5, but that is relative to the last cycle of multicycle, 97207618Srdivacky // so we use 6 for those cases 98207618Srdivacky // 99207618Srdivacky InstrItinData<IIC_iMUL16 , [InstrStage<1, [A8_Pipe0]>], [5, 1, 1]>, 100218893Sdim InstrItinData<IIC_iMAC16 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>, 101218893Sdim InstrItinData<IIC_iMUL32 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1]>, 102218893Sdim InstrItinData<IIC_iMAC32 , [InstrStage<2, [A8_Pipe0]>], [6, 1, 1, 4]>, 103218893Sdim InstrItinData<IIC_iMUL64 , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>, 104218893Sdim InstrItinData<IIC_iMAC64 , [InstrStage<3, [A8_Pipe0]>], [6, 6, 1, 1]>, 105210299Sed 106207618Srdivacky // Integer load pipeline 107207618Srdivacky // 108207618Srdivacky // Immediate offset 109218893Sdim InstrItinData<IIC_iLoad_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 110218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 1]>, 111218893Sdim InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 112218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 1]>, 113218893Sdim InstrItinData<IIC_iLoad_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 114218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 1]>, 115207618Srdivacky // 116207618Srdivacky // Register offset 117218893Sdim InstrItinData<IIC_iLoad_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 118218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, 119218893Sdim InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 120218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, 121218893Sdim InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 122218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, 123207618Srdivacky // 124207618Srdivacky // Scaled register offset, issues over 2 cycles 125218893Sdim // FIXME: lsl by 2 takes 1 cycle. 126218893Sdim InstrItinData<IIC_iLoad_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 127218893Sdim InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>, 128218893Sdim InstrItinData<IIC_iLoad_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 129218893Sdim InstrStage<1, [A8_LSPipe]>], [4, 1, 1]>, 130207618Srdivacky // 131207618Srdivacky // Immediate offset with update 132218893Sdim InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 133218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>, 134218893Sdim InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 135218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 2, 1]>, 136207618Srdivacky // 137207618Srdivacky // Register offset with update 138218893Sdim InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 139218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>, 140218893Sdim InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 141218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>, 142218893Sdim InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 143218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 2, 1, 1]>, 144207618Srdivacky // 145207618Srdivacky // Scaled register offset with update, issues over 2 cycles 146218893Sdim InstrItinData<IIC_iLoad_siu , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 147218893Sdim InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>, 148218893Sdim InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 149218893Sdim InstrStage<2, [A8_LSPipe]>], [4, 3, 1, 1]>, 150207618Srdivacky // 151218893Sdim // Load multiple, def is the 5th operand. Pipeline 0 only. 152218893Sdim // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers. 153218893Sdim InstrItinData<IIC_iLoad_m , [InstrStage<2, [A8_Pipe0], 0>, 154245431Sdim InstrStage<2, [A8_LSPipe]>], 155245431Sdim [1, 1, 1, 1, 3], [], -1>, // dynamic uops 156218893Sdim // 157218893Sdim // Load multiple + update, defs are the 1st and 5th operands. 158218893Sdim InstrItinData<IIC_iLoad_mu , [InstrStage<3, [A8_Pipe0], 0>, 159245431Sdim InstrStage<3, [A8_LSPipe]>], 160245431Sdim [2, 1, 1, 1, 3], [], -1>, // dynamic uops 161218893Sdim // 162218893Sdim // Load multiple plus branch 163218893Sdim InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [A8_Pipe0], 0>, 164218893Sdim InstrStage<3, [A8_LSPipe]>, 165218893Sdim InstrStage<1, [A8_Pipe0, A8_Pipe1]>], 166245431Sdim [1, 2, 1, 1, 3], [], -1>, // dynamic uops 167218893Sdim // 168218893Sdim // Pop, def is the 3rd operand. 169218893Sdim InstrItinData<IIC_iPop , [InstrStage<3, [A8_Pipe0], 0>, 170245431Sdim InstrStage<3, [A8_LSPipe]>], 171245431Sdim [1, 1, 3], [], -1>, // dynamic uops 172218893Sdim // 173218893Sdim // Push, def is the 3th operand. 174218893Sdim InstrItinData<IIC_iPop_Br, [InstrStage<3, [A8_Pipe0], 0>, 175218893Sdim InstrStage<3, [A8_LSPipe]>, 176218893Sdim InstrStage<1, [A8_Pipe0, A8_Pipe1]>], 177245431Sdim [1, 1, 3], [], -1>, // dynamic uops 178218893Sdim // 179218893Sdim // iLoadi + iALUr for t2LDRpci_pic. 180218893Sdim InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 181218893Sdim InstrStage<1, [A8_LSPipe]>, 182218893Sdim InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [4, 1]>, 183218893Sdim 184218893Sdim 185207618Srdivacky // Integer store pipeline 186207618Srdivacky // 187207618Srdivacky // Immediate offset 188218893Sdim InstrItinData<IIC_iStore_i , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 189218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 1]>, 190218893Sdim InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 191218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 1]>, 192218893Sdim InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 193218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 1]>, 194207618Srdivacky // 195207618Srdivacky // Register offset 196218893Sdim InstrItinData<IIC_iStore_r , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 197218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, 198218893Sdim InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 199218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, 200218893Sdim InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 201218893Sdim InstrStage<1, [A8_LSPipe]>], [3, 1, 1]>, 202207618Srdivacky // 203207618Srdivacky // Scaled register offset, issues over 2 cycles 204218893Sdim InstrItinData<IIC_iStore_si , [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 205218893Sdim InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>, 206218893Sdim InstrItinData<IIC_iStore_bh_si,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 207218893Sdim InstrStage<2, [A8_LSPipe]>], [3, 1, 1]>, 208207618Srdivacky // 209207618Srdivacky // Immediate offset with update 210218893Sdim InstrItinData<IIC_iStore_iu , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 211218893Sdim InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>, 212218893Sdim InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 213218893Sdim InstrStage<1, [A8_LSPipe]>], [2, 3, 1]>, 214207618Srdivacky // 215207618Srdivacky // Register offset with update 216218893Sdim InstrItinData<IIC_iStore_ru , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 217218893Sdim InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>, 218218893Sdim InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 219218893Sdim InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>, 220218893Sdim InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 221218893Sdim InstrStage<1, [A8_LSPipe]>], [2, 3, 1, 1]>, 222207618Srdivacky // 223207618Srdivacky // Scaled register offset with update, issues over 2 cycles 224218893Sdim InstrItinData<IIC_iStore_siu, [InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 225218893Sdim InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>, 226218893Sdim InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [A8_Pipe0, A8_Pipe1], 0>, 227218893Sdim InstrStage<2, [A8_LSPipe]>], [3, 3, 1, 1]>, 228207618Srdivacky // 229218893Sdim // Store multiple. Pipeline 0 only. 230218893Sdim // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers. 231218893Sdim InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Pipe0], 0>, 232245431Sdim InstrStage<2, [A8_LSPipe]>], 233245431Sdim [], [], -1>, // dynamic uops 234218893Sdim // 235218893Sdim // Store multiple + update 236218893Sdim InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Pipe0], 0>, 237245431Sdim InstrStage<2, [A8_LSPipe]>], 238245431Sdim [2], [], -1>, // dynamic uops 239218893Sdim // 240218893Sdim // Preload 241218893Sdim InstrItinData<IIC_Preload, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 242218893Sdim 243207618Srdivacky // Branch 244207618Srdivacky // 245207618Srdivacky // no delay slots, so the latency of a branch is unimportant 246207618Srdivacky InstrItinData<IIC_Br , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>, 247207618Srdivacky 248207618Srdivacky // VFP 249207618Srdivacky // Issue through integer pipeline, and execute in NEON unit. We assume 250207618Srdivacky // RunFast mode so that NFP pipeline is used for single-precision when 251207618Srdivacky // possible. 252207618Srdivacky // 253207618Srdivacky // FP Special Register to Integer Register File Move 254218893Sdim InstrItinData<IIC_fpSTAT , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 255218893Sdim InstrStage<1, [A8_NLSPipe]>], [20]>, 256207618Srdivacky // 257207618Srdivacky // Single-precision FP Unary 258218893Sdim InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 259207618Srdivacky InstrStage<1, [A8_NPipe]>], [7, 1]>, 260207618Srdivacky // 261207618Srdivacky // Double-precision FP Unary 262218893Sdim InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 263207618Srdivacky InstrStage<4, [A8_NPipe], 0>, 264207618Srdivacky InstrStage<4, [A8_NLSPipe]>], [4, 1]>, 265207618Srdivacky // 266207618Srdivacky // Single-precision FP Compare 267218893Sdim InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 268207618Srdivacky InstrStage<1, [A8_NPipe]>], [1, 1]>, 269207618Srdivacky // 270207618Srdivacky // Double-precision FP Compare 271218893Sdim InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 272207618Srdivacky InstrStage<4, [A8_NPipe], 0>, 273207618Srdivacky InstrStage<4, [A8_NLSPipe]>], [4, 1]>, 274207618Srdivacky // 275207618Srdivacky // Single to Double FP Convert 276218893Sdim InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 277207618Srdivacky InstrStage<7, [A8_NPipe], 0>, 278207618Srdivacky InstrStage<7, [A8_NLSPipe]>], [7, 1]>, 279207618Srdivacky // 280207618Srdivacky // Double to Single FP Convert 281218893Sdim InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 282207618Srdivacky InstrStage<5, [A8_NPipe], 0>, 283207618Srdivacky InstrStage<5, [A8_NLSPipe]>], [5, 1]>, 284207618Srdivacky // 285207618Srdivacky // Single-Precision FP to Integer Convert 286218893Sdim InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 287207618Srdivacky InstrStage<1, [A8_NPipe]>], [7, 1]>, 288207618Srdivacky // 289207618Srdivacky // Double-Precision FP to Integer Convert 290218893Sdim InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 291207618Srdivacky InstrStage<8, [A8_NPipe], 0>, 292207618Srdivacky InstrStage<8, [A8_NLSPipe]>], [8, 1]>, 293207618Srdivacky // 294207618Srdivacky // Integer to Single-Precision FP Convert 295218893Sdim InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 296207618Srdivacky InstrStage<1, [A8_NPipe]>], [7, 1]>, 297207618Srdivacky // 298207618Srdivacky // Integer to Double-Precision FP Convert 299218893Sdim InstrItinData<IIC_fpCVTID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 300207618Srdivacky InstrStage<8, [A8_NPipe], 0>, 301207618Srdivacky InstrStage<8, [A8_NLSPipe]>], [8, 1]>, 302207618Srdivacky // 303207618Srdivacky // Single-precision FP ALU 304218893Sdim InstrItinData<IIC_fpALU32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 305207618Srdivacky InstrStage<1, [A8_NPipe]>], [7, 1, 1]>, 306207618Srdivacky // 307207618Srdivacky // Double-precision FP ALU 308218893Sdim InstrItinData<IIC_fpALU64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 309207618Srdivacky InstrStage<9, [A8_NPipe], 0>, 310207618Srdivacky InstrStage<9, [A8_NLSPipe]>], [9, 1, 1]>, 311207618Srdivacky // 312207618Srdivacky // Single-precision FP Multiply 313218893Sdim InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 314207618Srdivacky InstrStage<1, [A8_NPipe]>], [7, 1, 1]>, 315207618Srdivacky // 316207618Srdivacky // Double-precision FP Multiply 317218893Sdim InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 318207618Srdivacky InstrStage<11, [A8_NPipe], 0>, 319207618Srdivacky InstrStage<11, [A8_NLSPipe]>], [11, 1, 1]>, 320207618Srdivacky // 321207618Srdivacky // Single-precision FP MAC 322218893Sdim InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 323207618Srdivacky InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>, 324207618Srdivacky // 325207618Srdivacky // Double-precision FP MAC 326218893Sdim InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 327207618Srdivacky InstrStage<19, [A8_NPipe], 0>, 328207618Srdivacky InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>, 329207618Srdivacky // 330235633Sdim // Single-precision Fused FP MAC 331235633Sdim InstrItinData<IIC_fpFMAC32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 332235633Sdim InstrStage<1, [A8_NPipe]>], [7, 2, 1, 1]>, 333235633Sdim // 334235633Sdim // Double-precision Fused FP MAC 335235633Sdim InstrItinData<IIC_fpFMAC64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 336235633Sdim InstrStage<19, [A8_NPipe], 0>, 337235633Sdim InstrStage<19, [A8_NLSPipe]>], [19, 2, 1, 1]>, 338235633Sdim // 339207618Srdivacky // Single-precision FP DIV 340218893Sdim InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 341207618Srdivacky InstrStage<20, [A8_NPipe], 0>, 342207618Srdivacky InstrStage<20, [A8_NLSPipe]>], [20, 1, 1]>, 343207618Srdivacky // 344207618Srdivacky // Double-precision FP DIV 345218893Sdim InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 346207618Srdivacky InstrStage<29, [A8_NPipe], 0>, 347207618Srdivacky InstrStage<29, [A8_NLSPipe]>], [29, 1, 1]>, 348207618Srdivacky // 349207618Srdivacky // Single-precision FP SQRT 350218893Sdim InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 351207618Srdivacky InstrStage<19, [A8_NPipe], 0>, 352207618Srdivacky InstrStage<19, [A8_NLSPipe]>], [19, 1]>, 353207618Srdivacky // 354207618Srdivacky // Double-precision FP SQRT 355218893Sdim InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 356207618Srdivacky InstrStage<29, [A8_NPipe], 0>, 357207618Srdivacky InstrStage<29, [A8_NLSPipe]>], [29, 1]>, 358218893Sdim 359207618Srdivacky // 360218893Sdim // Integer to Single-precision Move 361218893Sdim InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 362218893Sdim InstrStage<1, [A8_NPipe]>], 363218893Sdim [2, 1]>, 364218893Sdim // 365218893Sdim // Integer to Double-precision Move 366218893Sdim InstrItinData<IIC_fpMOVID, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 367218893Sdim InstrStage<1, [A8_NPipe]>], 368218893Sdim [2, 1, 1]>, 369218893Sdim // 370218893Sdim // Single-precision to Integer Move 371218893Sdim InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 372218893Sdim InstrStage<1, [A8_NPipe]>], 373218893Sdim [20, 1]>, 374218893Sdim // 375218893Sdim // Double-precision to Integer Move 376218893Sdim InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 377218893Sdim InstrStage<1, [A8_NPipe]>], 378218893Sdim [20, 20, 1]>, 379218893Sdim 380218893Sdim // 381207618Srdivacky // Single-precision FP Load 382218893Sdim InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 383218893Sdim InstrStage<1, [A8_NLSPipe], 0>, 384218893Sdim InstrStage<1, [A8_LSPipe]>], 385218893Sdim [2, 1]>, 386207618Srdivacky // 387207618Srdivacky // Double-precision FP Load 388218893Sdim InstrItinData<IIC_fpLoad64, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 389218893Sdim InstrStage<1, [A8_NLSPipe], 0>, 390218893Sdim InstrStage<1, [A8_LSPipe]>], 391218893Sdim [2, 1]>, 392207618Srdivacky // 393207618Srdivacky // FP Load Multiple 394218893Sdim // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers. 395218893Sdim InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 396218893Sdim InstrStage<1, [A8_NLSPipe], 0>, 397218893Sdim InstrStage<1, [A8_LSPipe]>, 398218893Sdim InstrStage<1, [A8_NLSPipe], 0>, 399245431Sdim InstrStage<1, [A8_LSPipe]>], 400245431Sdim [1, 1, 1, 2], [], -1>, // dynamic uops 401207618Srdivacky // 402218893Sdim // FP Load Multiple + update 403218893Sdim InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 404218893Sdim InstrStage<1, [A8_NLSPipe], 0>, 405218893Sdim InstrStage<1, [A8_LSPipe]>, 406218893Sdim InstrStage<1, [A8_NLSPipe], 0>, 407245431Sdim InstrStage<1, [A8_LSPipe]>], 408245431Sdim [2, 1, 1, 1, 2], [], -1>, // dynamic uops 409218893Sdim // 410207618Srdivacky // Single-precision FP Store 411218893Sdim InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 412218893Sdim InstrStage<1, [A8_NLSPipe], 0>, 413218893Sdim InstrStage<1, [A8_LSPipe]>], 414218893Sdim [1, 1]>, 415207618Srdivacky // 416207618Srdivacky // Double-precision FP Store 417218893Sdim InstrItinData<IIC_fpStore64,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 418218893Sdim InstrStage<1, [A8_NLSPipe], 0>, 419218893Sdim InstrStage<1, [A8_LSPipe]>], 420218893Sdim [1, 1]>, 421207618Srdivacky // 422207618Srdivacky // FP Store Multiple 423218893Sdim InstrItinData<IIC_fpStore_m,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 424218893Sdim InstrStage<1, [A8_NLSPipe], 0>, 425218893Sdim InstrStage<1, [A8_LSPipe]>, 426218893Sdim InstrStage<1, [A8_NLSPipe], 0>, 427245431Sdim InstrStage<1, [A8_LSPipe]>], 428245431Sdim [1, 1, 1, 1], [], -1>, // dynamic uops 429218893Sdim // 430218893Sdim // FP Store Multiple + update 431218893Sdim InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 432218893Sdim InstrStage<1, [A8_NLSPipe], 0>, 433218893Sdim InstrStage<1, [A8_LSPipe]>, 434218893Sdim InstrStage<1, [A8_NLSPipe], 0>, 435245431Sdim InstrStage<1, [A8_LSPipe]>], 436245431Sdim [2, 1, 1, 1, 1], [], -1>, // dynamic uops 437207618Srdivacky // NEON 438207618Srdivacky // Issue through integer pipeline, and execute in NEON unit. 439207618Srdivacky // 440207618Srdivacky // VLD1 441218893Sdim InstrItinData<IIC_VLD1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 442218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 443218893Sdim InstrStage<2, [A8_LSPipe]>], 444218893Sdim [2, 1]>, 445218893Sdim // VLD1x2 446218893Sdim InstrItinData<IIC_VLD1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 447218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 448218893Sdim InstrStage<2, [A8_LSPipe]>], 449218893Sdim [2, 2, 1]>, 450207618Srdivacky // 451218893Sdim // VLD1x3 452218893Sdim InstrItinData<IIC_VLD1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 453218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 454218893Sdim InstrStage<3, [A8_LSPipe]>], 455218893Sdim [2, 2, 3, 1]>, 456218893Sdim // 457218893Sdim // VLD1x4 458218893Sdim InstrItinData<IIC_VLD1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 459218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 460218893Sdim InstrStage<3, [A8_LSPipe]>], 461218893Sdim [2, 2, 3, 3, 1]>, 462218893Sdim // 463218893Sdim // VLD1u 464218893Sdim InstrItinData<IIC_VLD1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 465218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 466218893Sdim InstrStage<2, [A8_LSPipe]>], 467218893Sdim [2, 2, 1]>, 468218893Sdim // 469218893Sdim // VLD1x2u 470218893Sdim InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 471218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 472218893Sdim InstrStage<2, [A8_LSPipe]>], 473218893Sdim [2, 2, 2, 1]>, 474218893Sdim // 475218893Sdim // VLD1x3u 476218893Sdim InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 477218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 478218893Sdim InstrStage<3, [A8_LSPipe]>], 479218893Sdim [2, 2, 3, 2, 1]>, 480218893Sdim // 481218893Sdim // VLD1x4u 482218893Sdim InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 483218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 484218893Sdim InstrStage<3, [A8_LSPipe]>], 485218893Sdim [2, 2, 3, 3, 2, 1]>, 486218893Sdim // 487218893Sdim // VLD1ln 488218893Sdim InstrItinData<IIC_VLD1ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 489218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 490218893Sdim InstrStage<3, [A8_LSPipe]>], 491218893Sdim [3, 1, 1, 1]>, 492218893Sdim // 493218893Sdim // VLD1lnu 494218893Sdim InstrItinData<IIC_VLD1lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 495218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 496218893Sdim InstrStage<3, [A8_LSPipe]>], 497218893Sdim [3, 2, 1, 1, 1, 1]>, 498218893Sdim // 499218893Sdim // VLD1dup 500218893Sdim InstrItinData<IIC_VLD1dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 501218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 502218893Sdim InstrStage<2, [A8_LSPipe]>], 503218893Sdim [2, 1]>, 504218893Sdim // 505218893Sdim // VLD1dupu 506218893Sdim InstrItinData<IIC_VLD1dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 507218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 508218893Sdim InstrStage<2, [A8_LSPipe]>], 509218893Sdim [2, 2, 1, 1]>, 510218893Sdim // 511207618Srdivacky // VLD2 512218893Sdim InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 513218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 514218893Sdim InstrStage<2, [A8_LSPipe]>], 515218893Sdim [2, 2, 1]>, 516207618Srdivacky // 517218893Sdim // VLD2x2 518218893Sdim InstrItinData<IIC_VLD2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 519218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 520218893Sdim InstrStage<3, [A8_LSPipe]>], 521218893Sdim [2, 2, 3, 3, 1]>, 522218893Sdim // 523218893Sdim // VLD2ln 524218893Sdim InstrItinData<IIC_VLD2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 525218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 526218893Sdim InstrStage<3, [A8_LSPipe]>], 527218893Sdim [3, 3, 1, 1, 1, 1]>, 528218893Sdim // 529218893Sdim // VLD2u 530218893Sdim InstrItinData<IIC_VLD2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 531218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 532218893Sdim InstrStage<2, [A8_LSPipe]>], 533218893Sdim [2, 2, 2, 1, 1, 1]>, 534218893Sdim // 535218893Sdim // VLD2x2u 536218893Sdim InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 537218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 538218893Sdim InstrStage<3, [A8_LSPipe]>], 539218893Sdim [2, 2, 3, 3, 2, 1]>, 540218893Sdim // 541218893Sdim // VLD2lnu 542218893Sdim InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 543218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 544218893Sdim InstrStage<3, [A8_LSPipe]>], 545218893Sdim [3, 3, 2, 1, 1, 1, 1, 1]>, 546218893Sdim // 547218893Sdim // VLD2dup 548218893Sdim InstrItinData<IIC_VLD2dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 549218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 550218893Sdim InstrStage<2, [A8_LSPipe]>], 551218893Sdim [2, 2, 1]>, 552218893Sdim // 553218893Sdim // VLD2dupu 554218893Sdim InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 555218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 556218893Sdim InstrStage<2, [A8_LSPipe]>], 557218893Sdim [2, 2, 2, 1, 1]>, 558218893Sdim // 559207618Srdivacky // VLD3 560218893Sdim InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 561218893Sdim InstrStage<4, [A8_NLSPipe], 0>, 562218893Sdim InstrStage<4, [A8_LSPipe]>], 563218893Sdim [3, 3, 4, 1]>, 564207618Srdivacky // 565218893Sdim // VLD3ln 566218893Sdim InstrItinData<IIC_VLD3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 567218893Sdim InstrStage<5, [A8_NLSPipe], 0>, 568218893Sdim InstrStage<5, [A8_LSPipe]>], 569218893Sdim [4, 4, 5, 1, 1, 1, 1, 2]>, 570218893Sdim // 571218893Sdim // VLD3u 572218893Sdim InstrItinData<IIC_VLD3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 573218893Sdim InstrStage<4, [A8_NLSPipe], 0>, 574218893Sdim InstrStage<4, [A8_LSPipe]>], 575218893Sdim [3, 3, 4, 2, 1]>, 576218893Sdim // 577218893Sdim // VLD3lnu 578218893Sdim InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 579218893Sdim InstrStage<5, [A8_NLSPipe], 0>, 580218893Sdim InstrStage<5, [A8_LSPipe]>], 581218893Sdim [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>, 582218893Sdim // 583218893Sdim // VLD3dup 584218893Sdim InstrItinData<IIC_VLD3dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 585218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 586218893Sdim InstrStage<3, [A8_LSPipe]>], 587218893Sdim [2, 2, 3, 1]>, 588218893Sdim // 589218893Sdim // VLD3dupu 590218893Sdim InstrItinData<IIC_VLD3dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 591218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 592218893Sdim InstrStage<3, [A8_LSPipe]>], 593218893Sdim [2, 2, 3, 2, 1, 1]>, 594218893Sdim // 595207618Srdivacky // VLD4 596218893Sdim InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 597218893Sdim InstrStage<4, [A8_NLSPipe], 0>, 598218893Sdim InstrStage<4, [A8_LSPipe]>], 599218893Sdim [3, 3, 4, 4, 1]>, 600207618Srdivacky // 601218893Sdim // VLD4ln 602218893Sdim InstrItinData<IIC_VLD4ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 603218893Sdim InstrStage<5, [A8_NLSPipe], 0>, 604218893Sdim InstrStage<5, [A8_LSPipe]>], 605218893Sdim [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>, 606207618Srdivacky // 607218893Sdim // VLD4u 608218893Sdim InstrItinData<IIC_VLD4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 609218893Sdim InstrStage<4, [A8_NLSPipe], 0>, 610218893Sdim InstrStage<4, [A8_LSPipe]>], 611218893Sdim [3, 3, 4, 4, 2, 1]>, 612218893Sdim // 613218893Sdim // VLD4lnu 614218893Sdim InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 615218893Sdim InstrStage<5, [A8_NLSPipe], 0>, 616218893Sdim InstrStage<5, [A8_LSPipe]>], 617218893Sdim [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>, 618218893Sdim // 619218893Sdim // VLD4dup 620218893Sdim InstrItinData<IIC_VLD4dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 621218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 622218893Sdim InstrStage<3, [A8_LSPipe]>], 623218893Sdim [2, 2, 3, 3, 1]>, 624218893Sdim // 625218893Sdim // VLD4dupu 626218893Sdim InstrItinData<IIC_VLD4dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 627218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 628218893Sdim InstrStage<3, [A8_LSPipe]>], 629218893Sdim [2, 2, 3, 3, 2, 1, 1]>, 630218893Sdim // 631218893Sdim // VST1 632218893Sdim InstrItinData<IIC_VST1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 633218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 634218893Sdim InstrStage<2, [A8_LSPipe]>], 635218893Sdim [1, 1, 1]>, 636218893Sdim // 637218893Sdim // VST1x2 638218893Sdim InstrItinData<IIC_VST1x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 639218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 640218893Sdim InstrStage<2, [A8_LSPipe]>], 641218893Sdim [1, 1, 1, 1]>, 642218893Sdim // 643218893Sdim // VST1x3 644218893Sdim InstrItinData<IIC_VST1x3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 645218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 646218893Sdim InstrStage<3, [A8_LSPipe]>], 647218893Sdim [1, 1, 1, 1, 2]>, 648218893Sdim // 649218893Sdim // VST1x4 650218893Sdim InstrItinData<IIC_VST1x4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 651218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 652218893Sdim InstrStage<3, [A8_LSPipe]>], 653218893Sdim [1, 1, 1, 1, 2, 2]>, 654218893Sdim // 655218893Sdim // VST1u 656218893Sdim InstrItinData<IIC_VST1u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 657218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 658218893Sdim InstrStage<2, [A8_LSPipe]>], 659218893Sdim [2, 1, 1, 1, 1]>, 660218893Sdim // 661218893Sdim // VST1x2u 662218893Sdim InstrItinData<IIC_VST1x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 663218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 664218893Sdim InstrStage<2, [A8_LSPipe]>], 665218893Sdim [2, 1, 1, 1, 1, 1]>, 666218893Sdim // 667218893Sdim // VST1x3u 668218893Sdim InstrItinData<IIC_VST1x3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 669218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 670218893Sdim InstrStage<3, [A8_LSPipe]>], 671218893Sdim [2, 1, 1, 1, 1, 1, 2]>, 672218893Sdim // 673218893Sdim // VST1x4u 674218893Sdim InstrItinData<IIC_VST1x4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 675218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 676218893Sdim InstrStage<3, [A8_LSPipe]>], 677218893Sdim [2, 1, 1, 1, 1, 1, 2, 2]>, 678218893Sdim // 679218893Sdim // VST1ln 680218893Sdim InstrItinData<IIC_VST1ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 681218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 682218893Sdim InstrStage<2, [A8_LSPipe]>], 683218893Sdim [1, 1, 1]>, 684218893Sdim // 685218893Sdim // VST1lnu 686218893Sdim InstrItinData<IIC_VST1lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>, 687218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 688218893Sdim InstrStage<2, [A8_LSPipe]>], 689218893Sdim [2, 1, 1, 1, 1]>, 690218893Sdim // 691218893Sdim // VST2 692218893Sdim InstrItinData<IIC_VST2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 693218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 694218893Sdim InstrStage<2, [A8_LSPipe]>], 695218893Sdim [1, 1, 1, 1]>, 696218893Sdim // 697218893Sdim // VST2x2 698218893Sdim InstrItinData<IIC_VST2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 699218893Sdim InstrStage<4, [A8_NLSPipe], 0>, 700218893Sdim InstrStage<4, [A8_LSPipe]>], 701218893Sdim [1, 1, 1, 1, 2, 2]>, 702218893Sdim // 703218893Sdim // VST2u 704218893Sdim InstrItinData<IIC_VST2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 705218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 706218893Sdim InstrStage<2, [A8_LSPipe]>], 707218893Sdim [2, 1, 1, 1, 1, 1]>, 708218893Sdim // 709218893Sdim // VST2x2u 710218893Sdim InstrItinData<IIC_VST2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 711218893Sdim InstrStage<4, [A8_NLSPipe], 0>, 712218893Sdim InstrStage<4, [A8_LSPipe]>], 713218893Sdim [2, 1, 1, 1, 1, 1, 2, 2]>, 714218893Sdim // 715218893Sdim // VST2ln 716218893Sdim InstrItinData<IIC_VST2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 717218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 718218893Sdim InstrStage<2, [A8_LSPipe]>], 719218893Sdim [1, 1, 1, 1]>, 720218893Sdim // 721218893Sdim // VST2lnu 722218893Sdim InstrItinData<IIC_VST2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 723218893Sdim InstrStage<2, [A8_NLSPipe], 0>, 724218893Sdim InstrStage<2, [A8_LSPipe]>], 725218893Sdim [2, 1, 1, 1, 1, 1]>, 726218893Sdim // 727218893Sdim // VST3 728218893Sdim InstrItinData<IIC_VST3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 729218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 730218893Sdim InstrStage<3, [A8_LSPipe]>], 731218893Sdim [1, 1, 1, 1, 2]>, 732218893Sdim // 733218893Sdim // VST3u 734218893Sdim InstrItinData<IIC_VST3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 735218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 736218893Sdim InstrStage<3, [A8_LSPipe]>], 737218893Sdim [2, 1, 1, 1, 1, 1, 2]>, 738218893Sdim // 739218893Sdim // VST3ln 740218893Sdim InstrItinData<IIC_VST3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 741218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 742218893Sdim InstrStage<3, [A8_LSPipe]>], 743218893Sdim [1, 1, 1, 1, 2]>, 744218893Sdim // 745218893Sdim // VST3lnu 746218893Sdim InstrItinData<IIC_VST3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 747218893Sdim InstrStage<3, [A8_NLSPipe], 0>, 748218893Sdim InstrStage<3, [A8_LSPipe]>], 749218893Sdim [2, 1, 1, 1, 1, 1, 2]>, 750218893Sdim // 751218893Sdim // VST4 752218893Sdim InstrItinData<IIC_VST4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 753218893Sdim InstrStage<4, [A8_NLSPipe], 0>, 754218893Sdim InstrStage<4, [A8_LSPipe]>], 755218893Sdim [1, 1, 1, 1, 2, 2]>, 756218893Sdim // 757218893Sdim // VST4u 758218893Sdim InstrItinData<IIC_VST4u, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 759218893Sdim InstrStage<4, [A8_NLSPipe], 0>, 760218893Sdim InstrStage<4, [A8_LSPipe]>], 761218893Sdim [2, 1, 1, 1, 1, 1, 2, 2]>, 762218893Sdim // 763218893Sdim // VST4ln 764218893Sdim InstrItinData<IIC_VST4ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 765218893Sdim InstrStage<4, [A8_NLSPipe], 0>, 766218893Sdim InstrStage<4, [A8_LSPipe]>], 767218893Sdim [1, 1, 1, 1, 2, 2]>, 768218893Sdim // 769218893Sdim // VST4lnu 770218893Sdim InstrItinData<IIC_VST4lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 771218893Sdim InstrStage<4, [A8_NLSPipe], 0>, 772218893Sdim InstrStage<4, [A8_LSPipe]>], 773218893Sdim [2, 1, 1, 1, 1, 1, 2, 2]>, 774218893Sdim // 775207618Srdivacky // Double-register FP Unary 776218893Sdim InstrItinData<IIC_VUNAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 777207618Srdivacky InstrStage<1, [A8_NPipe]>], [5, 2]>, 778207618Srdivacky // 779207618Srdivacky // Quad-register FP Unary 780207618Srdivacky // Result written in N5, but that is relative to the last cycle of multicycle, 781207618Srdivacky // so we use 6 for those cases 782218893Sdim InstrItinData<IIC_VUNAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 783207618Srdivacky InstrStage<2, [A8_NPipe]>], [6, 2]>, 784207618Srdivacky // 785207618Srdivacky // Double-register FP Binary 786218893Sdim InstrItinData<IIC_VBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 787207618Srdivacky InstrStage<1, [A8_NPipe]>], [5, 2, 2]>, 788207618Srdivacky // 789218893Sdim // VPADD, etc. 790218893Sdim InstrItinData<IIC_VPBIND, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 791218893Sdim InstrStage<1, [A8_NPipe]>], [5, 2, 2]>, 792218893Sdim // 793218893Sdim // Double-register FP VMUL 794218893Sdim InstrItinData<IIC_VFMULD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 795218893Sdim InstrStage<1, [A8_NPipe]>], [5, 2, 1]>, 796218893Sdim 797218893Sdim // 798207618Srdivacky // Quad-register FP Binary 799207618Srdivacky // Result written in N5, but that is relative to the last cycle of multicycle, 800207618Srdivacky // so we use 6 for those cases 801218893Sdim InstrItinData<IIC_VBINQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 802207618Srdivacky InstrStage<2, [A8_NPipe]>], [6, 2, 2]>, 803207618Srdivacky // 804218893Sdim // Quad-register FP VMUL 805218893Sdim InstrItinData<IIC_VFMULQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 806218893Sdim InstrStage<1, [A8_NPipe]>], [6, 2, 1]>, 807218893Sdim // 808218893Sdim // Move 809218893Sdim InstrItinData<IIC_VMOV, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 810218893Sdim InstrStage<1, [A8_NPipe]>], [1, 1]>, 811218893Sdim // 812207618Srdivacky // Move Immediate 813218893Sdim InstrItinData<IIC_VMOVImm, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 814207618Srdivacky InstrStage<1, [A8_NPipe]>], [3]>, 815207618Srdivacky // 816207618Srdivacky // Double-register Permute Move 817218893Sdim InstrItinData<IIC_VMOVD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 818207618Srdivacky InstrStage<1, [A8_NLSPipe]>], [2, 1]>, 819207618Srdivacky // 820207618Srdivacky // Quad-register Permute Move 821207618Srdivacky // Result written in N2, but that is relative to the last cycle of multicycle, 822207618Srdivacky // so we use 3 for those cases 823218893Sdim InstrItinData<IIC_VMOVQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 824207618Srdivacky InstrStage<2, [A8_NLSPipe]>], [3, 1]>, 825207618Srdivacky // 826207618Srdivacky // Integer to Single-precision Move 827218893Sdim InstrItinData<IIC_VMOVIS , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 828207618Srdivacky InstrStage<1, [A8_NLSPipe]>], [2, 1]>, 829207618Srdivacky // 830207618Srdivacky // Integer to Double-precision Move 831218893Sdim InstrItinData<IIC_VMOVID , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 832207618Srdivacky InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>, 833207618Srdivacky // 834207618Srdivacky // Single-precision to Integer Move 835218893Sdim InstrItinData<IIC_VMOVSI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 836207618Srdivacky InstrStage<1, [A8_NLSPipe]>], [20, 1]>, 837207618Srdivacky // 838207618Srdivacky // Double-precision to Integer Move 839218893Sdim InstrItinData<IIC_VMOVDI , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 840207618Srdivacky InstrStage<1, [A8_NLSPipe]>], [20, 20, 1]>, 841207618Srdivacky // 842207618Srdivacky // Integer to Lane Move 843218893Sdim InstrItinData<IIC_VMOVISL , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 844207618Srdivacky InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>, 845207618Srdivacky // 846218893Sdim // Vector narrow move 847218893Sdim InstrItinData<IIC_VMOVN , [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 848218893Sdim InstrStage<1, [A8_NPipe]>], [2, 1]>, 849218893Sdim // 850207618Srdivacky // Double-register Permute 851218893Sdim InstrItinData<IIC_VPERMD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 852207618Srdivacky InstrStage<1, [A8_NLSPipe]>], [2, 2, 1, 1]>, 853207618Srdivacky // 854207618Srdivacky // Quad-register Permute 855207618Srdivacky // Result written in N2, but that is relative to the last cycle of multicycle, 856207618Srdivacky // so we use 3 for those cases 857218893Sdim InstrItinData<IIC_VPERMQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 858207618Srdivacky InstrStage<2, [A8_NLSPipe]>], [3, 3, 1, 1]>, 859207618Srdivacky // 860207618Srdivacky // Quad-register Permute (3 cycle issue) 861207618Srdivacky // Result written in N2, but that is relative to the last cycle of multicycle, 862207618Srdivacky // so we use 4 for those cases 863218893Sdim InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 864207618Srdivacky InstrStage<1, [A8_NLSPipe]>, 865207618Srdivacky InstrStage<1, [A8_NPipe], 0>, 866207618Srdivacky InstrStage<2, [A8_NLSPipe]>], [4, 4, 1, 1]>, 867207618Srdivacky // 868207618Srdivacky // Double-register FP Multiple-Accumulate 869218893Sdim InstrItinData<IIC_VMACD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 870207618Srdivacky InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>, 871207618Srdivacky // 872207618Srdivacky // Quad-register FP Multiple-Accumulate 873207618Srdivacky // Result written in N9, but that is relative to the last cycle of multicycle, 874207618Srdivacky // so we use 10 for those cases 875218893Sdim InstrItinData<IIC_VMACQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 876207618Srdivacky InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>, 877207618Srdivacky // 878235633Sdim // Double-register Fused FP Multiple-Accumulate 879235633Sdim InstrItinData<IIC_VFMACD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 880235633Sdim InstrStage<1, [A8_NPipe]>], [9, 3, 2, 2]>, 881235633Sdim // 882235633Sdim // Quad-register Fused FP Multiple-Accumulate 883235633Sdim // Result written in N9, but that is relative to the last cycle of multicycle, 884235633Sdim // so we use 10 for those cases 885235633Sdim InstrItinData<IIC_VFMACQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 886235633Sdim InstrStage<2, [A8_NPipe]>], [10, 3, 2, 2]>, 887235633Sdim // 888207618Srdivacky // Double-register Reciprical Step 889218893Sdim InstrItinData<IIC_VRECSD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 890207618Srdivacky InstrStage<1, [A8_NPipe]>], [9, 2, 2]>, 891207618Srdivacky // 892207618Srdivacky // Quad-register Reciprical Step 893218893Sdim InstrItinData<IIC_VRECSQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 894207618Srdivacky InstrStage<2, [A8_NPipe]>], [10, 2, 2]>, 895207618Srdivacky // 896207618Srdivacky // Double-register Integer Count 897218893Sdim InstrItinData<IIC_VCNTiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 898207618Srdivacky InstrStage<1, [A8_NPipe]>], [3, 2, 2]>, 899207618Srdivacky // 900207618Srdivacky // Quad-register Integer Count 901207618Srdivacky // Result written in N3, but that is relative to the last cycle of multicycle, 902207618Srdivacky // so we use 4 for those cases 903218893Sdim InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 904207618Srdivacky InstrStage<2, [A8_NPipe]>], [4, 2, 2]>, 905207618Srdivacky // 906207618Srdivacky // Double-register Integer Unary 907218893Sdim InstrItinData<IIC_VUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 908207618Srdivacky InstrStage<1, [A8_NPipe]>], [4, 2]>, 909207618Srdivacky // 910207618Srdivacky // Quad-register Integer Unary 911218893Sdim InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 912207618Srdivacky InstrStage<1, [A8_NPipe]>], [4, 2]>, 913207618Srdivacky // 914207618Srdivacky // Double-register Integer Q-Unary 915218893Sdim InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 916207618Srdivacky InstrStage<1, [A8_NPipe]>], [4, 1]>, 917207618Srdivacky // 918207618Srdivacky // Quad-register Integer CountQ-Unary 919218893Sdim InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 920207618Srdivacky InstrStage<1, [A8_NPipe]>], [4, 1]>, 921207618Srdivacky // 922207618Srdivacky // Double-register Integer Binary 923218893Sdim InstrItinData<IIC_VBINiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 924207618Srdivacky InstrStage<1, [A8_NPipe]>], [3, 2, 2]>, 925207618Srdivacky // 926207618Srdivacky // Quad-register Integer Binary 927218893Sdim InstrItinData<IIC_VBINiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 928207618Srdivacky InstrStage<1, [A8_NPipe]>], [3, 2, 2]>, 929207618Srdivacky // 930207618Srdivacky // Double-register Integer Binary (4 cycle) 931218893Sdim InstrItinData<IIC_VBINi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 932207618Srdivacky InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, 933207618Srdivacky // 934207618Srdivacky // Quad-register Integer Binary (4 cycle) 935218893Sdim InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 936207618Srdivacky InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, 937207618Srdivacky 938207618Srdivacky // 939207618Srdivacky // Double-register Integer Subtract 940218893Sdim InstrItinData<IIC_VSUBiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 941207618Srdivacky InstrStage<1, [A8_NPipe]>], [3, 2, 1]>, 942207618Srdivacky // 943207618Srdivacky // Quad-register Integer Subtract 944218893Sdim InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 945207618Srdivacky InstrStage<1, [A8_NPipe]>], [3, 2, 1]>, 946207618Srdivacky // 947207618Srdivacky // Double-register Integer Subtract 948218893Sdim InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 949207618Srdivacky InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, 950207618Srdivacky // 951207618Srdivacky // Quad-register Integer Subtract 952218893Sdim InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 953207618Srdivacky InstrStage<1, [A8_NPipe]>], [4, 2, 1]>, 954207618Srdivacky // 955207618Srdivacky // Double-register Integer Shift 956218893Sdim InstrItinData<IIC_VSHLiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 957207618Srdivacky InstrStage<1, [A8_NPipe]>], [3, 1, 1]>, 958207618Srdivacky // 959207618Srdivacky // Quad-register Integer Shift 960218893Sdim InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 961207618Srdivacky InstrStage<2, [A8_NPipe]>], [4, 1, 1]>, 962207618Srdivacky // 963207618Srdivacky // Double-register Integer Shift (4 cycle) 964218893Sdim InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 965207618Srdivacky InstrStage<1, [A8_NPipe]>], [4, 1, 1]>, 966207618Srdivacky // 967207618Srdivacky // Quad-register Integer Shift (4 cycle) 968218893Sdim InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 969207618Srdivacky InstrStage<2, [A8_NPipe]>], [5, 1, 1]>, 970207618Srdivacky // 971207618Srdivacky // Double-register Integer Pair Add Long 972218893Sdim InstrItinData<IIC_VPALiD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 973207618Srdivacky InstrStage<1, [A8_NPipe]>], [6, 3, 1]>, 974207618Srdivacky // 975207618Srdivacky // Quad-register Integer Pair Add Long 976218893Sdim InstrItinData<IIC_VPALiQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 977207618Srdivacky InstrStage<2, [A8_NPipe]>], [7, 3, 1]>, 978207618Srdivacky // 979207618Srdivacky // Double-register Absolute Difference and Accumulate 980218893Sdim InstrItinData<IIC_VABAD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 981207618Srdivacky InstrStage<1, [A8_NPipe]>], [6, 3, 2, 1]>, 982207618Srdivacky // 983207618Srdivacky // Quad-register Absolute Difference and Accumulate 984218893Sdim InstrItinData<IIC_VABAQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 985207618Srdivacky InstrStage<2, [A8_NPipe]>], [6, 3, 2, 1]>, 986207618Srdivacky 987207618Srdivacky // 988207618Srdivacky // Double-register Integer Multiply (.8, .16) 989218893Sdim InstrItinData<IIC_VMULi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 990207618Srdivacky InstrStage<1, [A8_NPipe]>], [6, 2, 2]>, 991207618Srdivacky // 992207618Srdivacky // Double-register Integer Multiply (.32) 993218893Sdim InstrItinData<IIC_VMULi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 994207618Srdivacky InstrStage<2, [A8_NPipe]>], [7, 2, 1]>, 995207618Srdivacky // 996207618Srdivacky // Quad-register Integer Multiply (.8, .16) 997218893Sdim InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 998207618Srdivacky InstrStage<2, [A8_NPipe]>], [7, 2, 2]>, 999207618Srdivacky // 1000207618Srdivacky // Quad-register Integer Multiply (.32) 1001218893Sdim InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1002207618Srdivacky InstrStage<1, [A8_NPipe]>, 1003207618Srdivacky InstrStage<2, [A8_NLSPipe], 0>, 1004207618Srdivacky InstrStage<3, [A8_NPipe]>], [9, 2, 1]>, 1005207618Srdivacky // 1006207618Srdivacky // Double-register Integer Multiply-Accumulate (.8, .16) 1007218893Sdim InstrItinData<IIC_VMACi16D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1008207618Srdivacky InstrStage<1, [A8_NPipe]>], [6, 3, 2, 2]>, 1009207618Srdivacky // 1010207618Srdivacky // Double-register Integer Multiply-Accumulate (.32) 1011218893Sdim InstrItinData<IIC_VMACi32D, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1012207618Srdivacky InstrStage<2, [A8_NPipe]>], [7, 3, 2, 1]>, 1013207618Srdivacky // 1014207618Srdivacky // Quad-register Integer Multiply-Accumulate (.8, .16) 1015218893Sdim InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1016207618Srdivacky InstrStage<2, [A8_NPipe]>], [7, 3, 2, 2]>, 1017207618Srdivacky // 1018207618Srdivacky // Quad-register Integer Multiply-Accumulate (.32) 1019218893Sdim InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1020207618Srdivacky InstrStage<1, [A8_NPipe]>, 1021207618Srdivacky InstrStage<2, [A8_NLSPipe], 0>, 1022207618Srdivacky InstrStage<3, [A8_NPipe]>], [9, 3, 2, 1]>, 1023207618Srdivacky // 1024207618Srdivacky // Double-register VEXT 1025218893Sdim InstrItinData<IIC_VEXTD, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1026207618Srdivacky InstrStage<1, [A8_NLSPipe]>], [2, 1, 1]>, 1027207618Srdivacky // 1028207618Srdivacky // Quad-register VEXT 1029218893Sdim InstrItinData<IIC_VEXTQ, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1030207618Srdivacky InstrStage<2, [A8_NLSPipe]>], [3, 1, 1]>, 1031207618Srdivacky // 1032207618Srdivacky // VTB 1033218893Sdim InstrItinData<IIC_VTB1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1034207618Srdivacky InstrStage<2, [A8_NLSPipe]>], [3, 2, 1]>, 1035218893Sdim InstrItinData<IIC_VTB2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1036207618Srdivacky InstrStage<2, [A8_NLSPipe]>], [3, 2, 2, 1]>, 1037218893Sdim InstrItinData<IIC_VTB3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1038207618Srdivacky InstrStage<1, [A8_NLSPipe]>, 1039207618Srdivacky InstrStage<1, [A8_NPipe], 0>, 1040207618Srdivacky InstrStage<2, [A8_NLSPipe]>], [4, 2, 2, 3, 1]>, 1041218893Sdim InstrItinData<IIC_VTB4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1042207618Srdivacky InstrStage<1, [A8_NLSPipe]>, 1043207618Srdivacky InstrStage<1, [A8_NPipe], 0>, 1044210299Sed InstrStage<2, [A8_NLSPipe]>],[4, 2, 2, 3, 3, 1]>, 1045207618Srdivacky // 1046207618Srdivacky // VTBX 1047218893Sdim InstrItinData<IIC_VTBX1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1048207618Srdivacky InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 1]>, 1049218893Sdim InstrItinData<IIC_VTBX2, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1050207618Srdivacky InstrStage<2, [A8_NLSPipe]>], [3, 1, 2, 2, 1]>, 1051218893Sdim InstrItinData<IIC_VTBX3, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1052207618Srdivacky InstrStage<1, [A8_NLSPipe]>, 1053207618Srdivacky InstrStage<1, [A8_NPipe], 0>, 1054210299Sed InstrStage<2, [A8_NLSPipe]>],[4, 1, 2, 2, 3, 1]>, 1055218893Sdim InstrItinData<IIC_VTBX4, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, 1056207618Srdivacky InstrStage<1, [A8_NLSPipe]>, 1057207618Srdivacky InstrStage<1, [A8_NPipe], 0>, 1058210299Sed InstrStage<2, [A8_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]> 1059207618Srdivacky]>; 1060245431Sdim 1061245431Sdim// ===---------------------------------------------------------------------===// 1062245431Sdim// This following definitions describe the simple machine model which 1063245431Sdim// will replace itineraries. 1064245431Sdim 1065245431Sdim// Cortex-A8 machine model for scheduling and other instruction cost heuristics. 1066245431Sdimdef CortexA8Model : SchedMachineModel { 1067245431Sdim let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. 1068245431Sdim let MinLatency = -1; // OperandCycles are interpreted as MinLatency. 1069245431Sdim let LoadLatency = 2; // Optimistic load latency assuming bypass. 1070245431Sdim // This is overriden by OperandCycles if the 1071245431Sdim // Itineraries are queried instead. 1072245431Sdim let MispredictPenalty = 13; // Based on estimate of pipeline depth. 1073245431Sdim 1074245431Sdim let Itineraries = CortexA8Itineraries; 1075245431Sdim} 1076