1235633Sdim//===-- ARMSchedule.td - ARM Scheduling Definitions --------*- tablegen -*-===// 2235633Sdim// 3194612Sed// The LLVM Compiler Infrastructure 4194612Sed// 5194612Sed// This file is distributed under the University of Illinois Open Source 6194612Sed// License. See LICENSE.TXT for details. 7235633Sdim// 8194612Sed//===----------------------------------------------------------------------===// 9252723Sdim//===----------------------------------------------------------------------===// 10252723Sdim// Instruction scheduling annotations for out-of-order CPUs. 11252723Sdim// These annotations are independent of the itinerary class defined below. 12252723Sdim// Here we define the subtarget independent read/write per-operand resources. 13252723Sdim// The subtarget schedule definitions will then map these to the subtarget's 14252723Sdim// resource usages. 15252723Sdim// For example: 16252723Sdim// The instruction cycle timings table might contain an entry for an operation 17252723Sdim// like the following: 18252723Sdim// Rd <- ADD Rn, Rm, <shift> Rs 19252723Sdim// Uops | Latency from register | Uops - resource requirements - latency 20252723Sdim// 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3 21252723Sdim// | | uopc Rd, Rn, T0 - P01 - 1 22252723Sdim// This is telling us that the result will be available in destination register 23252723Sdim// Rd after a minimum of three cycles after the result in Rm and Rs is available 24252723Sdim// and one cycle after the result in Rn is available. The micro-ops can execute 25252723Sdim// on resource P01. 26252723Sdim// To model this, we need to express that we need to dispatch two micro-ops, 27252723Sdim// that the resource P01 is needed and that the latency to Rn is different than 28252723Sdim// the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by 29252723Sdim// two. 30252723Sdim// We will do this by assigning (abstract) resources to register defs/uses. 31252723Sdim// ARMSchedule.td: 32252723Sdim// def WriteALUsr : SchedWrite; 33252723Sdim// def ReadAdvanceALUsr : ScheRead; 34252723Sdim// 35252723Sdim// ARMInstrInfo.td: 36252723Sdim// def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault, 37252723Sdim// ReadDefault]> { ...} 38252723Sdim// ReadAdvance read resources allow us to define "pipeline by-passes" or 39252723Sdim// shorter latencies to certain registers as needed in the example above. 40252723Sdim// The "ReadDefault" can be omitted. 41252723Sdim// Next, the subtarget td file assigns resources to the abstract resources 42252723Sdim// defined here. 43252723Sdim// ARMScheduleSubtarget.td: 44252723Sdim// // Resources. 45252723Sdim// def P01 : ProcResource<3>; // ALU unit (3 of it). 46252723Sdim// ... 47252723Sdim// // Resource usages. 48252723Sdim// def : WriteRes<WriteALUsr, [P01, P01]> { 49252723Sdim// Latency = 4; // Latency of 4. 50252723Sdim// NumMicroOps = 2; // Dispatch 2 micro-ops. 51252723Sdim// // The two instances of resource P01 are occupied for one cycle. It is one 52252723Sdim// // cycle because these resources happen to be pipelined. 53252723Sdim// ResourceCycles = [1, 1]; 54252723Sdim// } 55252723Sdim// def : ReadAdvance<ReadAdvanceALUsr, 3>; 56194612Sed 57252723Sdim// Basic ALU operation. 58252723Sdimdef WriteALU : SchedWrite; 59252723Sdimdef ReadALU : SchedRead; 60252723Sdim 61252723Sdim// Basic ALU with shifts. 62252723Sdimdef WriteALUsi : SchedWrite; // Shift by immediate. 63252723Sdimdef WriteALUsr : SchedWrite; // Shift by register. 64252723Sdimdef WriteALUSsr : SchedWrite; // Shift by register (flag setting). 65252723Sdimdef ReadALUsr : SchedRead; // Some operands are read later. 66252723Sdim 67252723Sdim// Compares. 68252723Sdimdef WriteCMP : SchedWrite; 69252723Sdimdef WriteCMPsi : SchedWrite; 70252723Sdimdef WriteCMPsr : SchedWrite; 71252723Sdim 72263509Sdim// Division. 73263509Sdimdef WriteDiv : SchedWrite; 74263509Sdim 75263509Sdim// Loads. 76263509Sdimdef WriteLd : SchedWrite; 77263509Sdimdef WritePreLd : SchedWrite; 78263509Sdim 79263509Sdim// Branches. 80263509Sdimdef WriteBr : SchedWrite; 81263509Sdimdef WriteBrL : SchedWrite; 82263509Sdimdef WriteBrTbl : SchedWrite; 83263509Sdim 84263509Sdim// Fixpoint conversions. 85263509Sdimdef WriteCvtFP : SchedWrite; 86263509Sdim 87263509Sdim// Noop. 88263509Sdimdef WriteNoop : SchedWrite; 89263509Sdim 90252723Sdim// Define TII for use in SchedVariant Predicates. 91252723Sdimdef : PredicateProlog<[{ 92252723Sdim const ARMBaseInstrInfo *TII = 93252723Sdim static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo()); 94252723Sdim (void)TII; 95252723Sdim}]>; 96252723Sdim 97252723Sdimdef IsPredicatedPred : SchedPredicate<[{TII->isPredicated(MI)}]>; 98252723Sdim 99194612Sed//===----------------------------------------------------------------------===// 100194612Sed// Instruction Itinerary classes used for ARM 101194612Sed// 102198090Srdivackydef IIC_iALUx : InstrItinClass; 103198090Srdivackydef IIC_iALUi : InstrItinClass; 104198090Srdivackydef IIC_iALUr : InstrItinClass; 105198090Srdivackydef IIC_iALUsi : InstrItinClass; 106218893Sdimdef IIC_iALUsir : InstrItinClass; 107198090Srdivackydef IIC_iALUsr : InstrItinClass; 108218893Sdimdef IIC_iBITi : InstrItinClass; 109218893Sdimdef IIC_iBITr : InstrItinClass; 110218893Sdimdef IIC_iBITsi : InstrItinClass; 111218893Sdimdef IIC_iBITsr : InstrItinClass; 112198090Srdivackydef IIC_iUNAr : InstrItinClass; 113198090Srdivackydef IIC_iUNAsi : InstrItinClass; 114218893Sdimdef IIC_iEXTr : InstrItinClass; 115218893Sdimdef IIC_iEXTAr : InstrItinClass; 116218893Sdimdef IIC_iEXTAsr : InstrItinClass; 117198090Srdivackydef IIC_iCMPi : InstrItinClass; 118198090Srdivackydef IIC_iCMPr : InstrItinClass; 119198090Srdivackydef IIC_iCMPsi : InstrItinClass; 120198090Srdivackydef IIC_iCMPsr : InstrItinClass; 121218893Sdimdef IIC_iTSTi : InstrItinClass; 122218893Sdimdef IIC_iTSTr : InstrItinClass; 123218893Sdimdef IIC_iTSTsi : InstrItinClass; 124218893Sdimdef IIC_iTSTsr : InstrItinClass; 125198090Srdivackydef IIC_iMOVi : InstrItinClass; 126198090Srdivackydef IIC_iMOVr : InstrItinClass; 127198090Srdivackydef IIC_iMOVsi : InstrItinClass; 128198090Srdivackydef IIC_iMOVsr : InstrItinClass; 129218893Sdimdef IIC_iMOVix2 : InstrItinClass; 130218893Sdimdef IIC_iMOVix2addpc : InstrItinClass; 131218893Sdimdef IIC_iMOVix2ld : InstrItinClass; 132218893Sdimdef IIC_iMVNi : InstrItinClass; 133218893Sdimdef IIC_iMVNr : InstrItinClass; 134218893Sdimdef IIC_iMVNsi : InstrItinClass; 135218893Sdimdef IIC_iMVNsr : InstrItinClass; 136198090Srdivackydef IIC_iCMOVi : InstrItinClass; 137198090Srdivackydef IIC_iCMOVr : InstrItinClass; 138198090Srdivackydef IIC_iCMOVsi : InstrItinClass; 139198090Srdivackydef IIC_iCMOVsr : InstrItinClass; 140218893Sdimdef IIC_iCMOVix2 : InstrItinClass; 141198090Srdivackydef IIC_iMUL16 : InstrItinClass; 142198090Srdivackydef IIC_iMAC16 : InstrItinClass; 143198090Srdivackydef IIC_iMUL32 : InstrItinClass; 144198090Srdivackydef IIC_iMAC32 : InstrItinClass; 145198090Srdivackydef IIC_iMUL64 : InstrItinClass; 146198090Srdivackydef IIC_iMAC64 : InstrItinClass; 147245431Sdimdef IIC_iDIV : InstrItinClass; 148218893Sdimdef IIC_iLoad_i : InstrItinClass; 149218893Sdimdef IIC_iLoad_r : InstrItinClass; 150218893Sdimdef IIC_iLoad_si : InstrItinClass; 151218893Sdimdef IIC_iLoad_iu : InstrItinClass; 152218893Sdimdef IIC_iLoad_ru : InstrItinClass; 153218893Sdimdef IIC_iLoad_siu : InstrItinClass; 154218893Sdimdef IIC_iLoad_bh_i : InstrItinClass; 155218893Sdimdef IIC_iLoad_bh_r : InstrItinClass; 156218893Sdimdef IIC_iLoad_bh_si : InstrItinClass; 157218893Sdimdef IIC_iLoad_bh_iu : InstrItinClass; 158218893Sdimdef IIC_iLoad_bh_ru : InstrItinClass; 159218893Sdimdef IIC_iLoad_bh_siu : InstrItinClass; 160218893Sdimdef IIC_iLoad_d_i : InstrItinClass; 161218893Sdimdef IIC_iLoad_d_r : InstrItinClass; 162218893Sdimdef IIC_iLoad_d_ru : InstrItinClass; 163245431Sdimdef IIC_iLoad_m : InstrItinClass; 164245431Sdimdef IIC_iLoad_mu : InstrItinClass; 165245431Sdimdef IIC_iLoad_mBr : InstrItinClass; 166245431Sdimdef IIC_iPop : InstrItinClass; 167245431Sdimdef IIC_iPop_Br : InstrItinClass; 168218893Sdimdef IIC_iLoadiALU : InstrItinClass; 169218893Sdimdef IIC_iStore_i : InstrItinClass; 170218893Sdimdef IIC_iStore_r : InstrItinClass; 171218893Sdimdef IIC_iStore_si : InstrItinClass; 172218893Sdimdef IIC_iStore_iu : InstrItinClass; 173218893Sdimdef IIC_iStore_ru : InstrItinClass; 174218893Sdimdef IIC_iStore_siu : InstrItinClass; 175218893Sdimdef IIC_iStore_bh_i : InstrItinClass; 176218893Sdimdef IIC_iStore_bh_r : InstrItinClass; 177218893Sdimdef IIC_iStore_bh_si : InstrItinClass; 178218893Sdimdef IIC_iStore_bh_iu : InstrItinClass; 179218893Sdimdef IIC_iStore_bh_ru : InstrItinClass; 180218893Sdimdef IIC_iStore_bh_siu : InstrItinClass; 181218893Sdimdef IIC_iStore_d_i : InstrItinClass; 182218893Sdimdef IIC_iStore_d_r : InstrItinClass; 183218893Sdimdef IIC_iStore_d_ru : InstrItinClass; 184245431Sdimdef IIC_iStore_m : InstrItinClass; 185245431Sdimdef IIC_iStore_mu : InstrItinClass; 186218893Sdimdef IIC_Preload : InstrItinClass; 187198090Srdivackydef IIC_Br : InstrItinClass; 188198090Srdivackydef IIC_fpSTAT : InstrItinClass; 189198090Srdivackydef IIC_fpUNA32 : InstrItinClass; 190198090Srdivackydef IIC_fpUNA64 : InstrItinClass; 191198090Srdivackydef IIC_fpCMP32 : InstrItinClass; 192198090Srdivackydef IIC_fpCMP64 : InstrItinClass; 193198090Srdivackydef IIC_fpCVTSD : InstrItinClass; 194198090Srdivackydef IIC_fpCVTDS : InstrItinClass; 195207618Srdivackydef IIC_fpCVTSH : InstrItinClass; 196207618Srdivackydef IIC_fpCVTHS : InstrItinClass; 197198090Srdivackydef IIC_fpCVTIS : InstrItinClass; 198198090Srdivackydef IIC_fpCVTID : InstrItinClass; 199198090Srdivackydef IIC_fpCVTSI : InstrItinClass; 200198090Srdivackydef IIC_fpCVTDI : InstrItinClass; 201207618Srdivackydef IIC_fpMOVIS : InstrItinClass; 202207618Srdivackydef IIC_fpMOVID : InstrItinClass; 203207618Srdivackydef IIC_fpMOVSI : InstrItinClass; 204207618Srdivackydef IIC_fpMOVDI : InstrItinClass; 205198090Srdivackydef IIC_fpALU32 : InstrItinClass; 206198090Srdivackydef IIC_fpALU64 : InstrItinClass; 207198090Srdivackydef IIC_fpMUL32 : InstrItinClass; 208198090Srdivackydef IIC_fpMUL64 : InstrItinClass; 209198090Srdivackydef IIC_fpMAC32 : InstrItinClass; 210198090Srdivackydef IIC_fpMAC64 : InstrItinClass; 211235633Sdimdef IIC_fpFMAC32 : InstrItinClass; 212235633Sdimdef IIC_fpFMAC64 : InstrItinClass; 213198090Srdivackydef IIC_fpDIV32 : InstrItinClass; 214198090Srdivackydef IIC_fpDIV64 : InstrItinClass; 215198090Srdivackydef IIC_fpSQRT32 : InstrItinClass; 216198090Srdivackydef IIC_fpSQRT64 : InstrItinClass; 217198090Srdivackydef IIC_fpLoad32 : InstrItinClass; 218198090Srdivackydef IIC_fpLoad64 : InstrItinClass; 219245431Sdimdef IIC_fpLoad_m : InstrItinClass; 220245431Sdimdef IIC_fpLoad_mu : InstrItinClass; 221198090Srdivackydef IIC_fpStore32 : InstrItinClass; 222198090Srdivackydef IIC_fpStore64 : InstrItinClass; 223245431Sdimdef IIC_fpStore_m : InstrItinClass; 224245431Sdimdef IIC_fpStore_mu : InstrItinClass; 225198090Srdivackydef IIC_VLD1 : InstrItinClass; 226218893Sdimdef IIC_VLD1x2 : InstrItinClass; 227218893Sdimdef IIC_VLD1x3 : InstrItinClass; 228218893Sdimdef IIC_VLD1x4 : InstrItinClass; 229218893Sdimdef IIC_VLD1u : InstrItinClass; 230218893Sdimdef IIC_VLD1x2u : InstrItinClass; 231218893Sdimdef IIC_VLD1x3u : InstrItinClass; 232218893Sdimdef IIC_VLD1x4u : InstrItinClass; 233218893Sdimdef IIC_VLD1ln : InstrItinClass; 234218893Sdimdef IIC_VLD1lnu : InstrItinClass; 235218893Sdimdef IIC_VLD1dup : InstrItinClass; 236218893Sdimdef IIC_VLD1dupu : InstrItinClass; 237198090Srdivackydef IIC_VLD2 : InstrItinClass; 238218893Sdimdef IIC_VLD2x2 : InstrItinClass; 239218893Sdimdef IIC_VLD2u : InstrItinClass; 240218893Sdimdef IIC_VLD2x2u : InstrItinClass; 241218893Sdimdef IIC_VLD2ln : InstrItinClass; 242218893Sdimdef IIC_VLD2lnu : InstrItinClass; 243218893Sdimdef IIC_VLD2dup : InstrItinClass; 244218893Sdimdef IIC_VLD2dupu : InstrItinClass; 245198090Srdivackydef IIC_VLD3 : InstrItinClass; 246218893Sdimdef IIC_VLD3ln : InstrItinClass; 247218893Sdimdef IIC_VLD3u : InstrItinClass; 248218893Sdimdef IIC_VLD3lnu : InstrItinClass; 249218893Sdimdef IIC_VLD3dup : InstrItinClass; 250218893Sdimdef IIC_VLD3dupu : InstrItinClass; 251198090Srdivackydef IIC_VLD4 : InstrItinClass; 252218893Sdimdef IIC_VLD4ln : InstrItinClass; 253218893Sdimdef IIC_VLD4u : InstrItinClass; 254218893Sdimdef IIC_VLD4lnu : InstrItinClass; 255218893Sdimdef IIC_VLD4dup : InstrItinClass; 256218893Sdimdef IIC_VLD4dupu : InstrItinClass; 257218893Sdimdef IIC_VST1 : InstrItinClass; 258218893Sdimdef IIC_VST1x2 : InstrItinClass; 259218893Sdimdef IIC_VST1x3 : InstrItinClass; 260218893Sdimdef IIC_VST1x4 : InstrItinClass; 261218893Sdimdef IIC_VST1u : InstrItinClass; 262218893Sdimdef IIC_VST1x2u : InstrItinClass; 263218893Sdimdef IIC_VST1x3u : InstrItinClass; 264218893Sdimdef IIC_VST1x4u : InstrItinClass; 265218893Sdimdef IIC_VST1ln : InstrItinClass; 266218893Sdimdef IIC_VST1lnu : InstrItinClass; 267218893Sdimdef IIC_VST2 : InstrItinClass; 268218893Sdimdef IIC_VST2x2 : InstrItinClass; 269218893Sdimdef IIC_VST2u : InstrItinClass; 270218893Sdimdef IIC_VST2x2u : InstrItinClass; 271218893Sdimdef IIC_VST2ln : InstrItinClass; 272218893Sdimdef IIC_VST2lnu : InstrItinClass; 273218893Sdimdef IIC_VST3 : InstrItinClass; 274218893Sdimdef IIC_VST3u : InstrItinClass; 275218893Sdimdef IIC_VST3ln : InstrItinClass; 276218893Sdimdef IIC_VST3lnu : InstrItinClass; 277218893Sdimdef IIC_VST4 : InstrItinClass; 278218893Sdimdef IIC_VST4u : InstrItinClass; 279218893Sdimdef IIC_VST4ln : InstrItinClass; 280218893Sdimdef IIC_VST4lnu : InstrItinClass; 281198090Srdivackydef IIC_VUNAD : InstrItinClass; 282198090Srdivackydef IIC_VUNAQ : InstrItinClass; 283198090Srdivackydef IIC_VBIND : InstrItinClass; 284198090Srdivackydef IIC_VBINQ : InstrItinClass; 285218893Sdimdef IIC_VPBIND : InstrItinClass; 286218893Sdimdef IIC_VFMULD : InstrItinClass; 287218893Sdimdef IIC_VFMULQ : InstrItinClass; 288218893Sdimdef IIC_VMOV : InstrItinClass; 289198090Srdivackydef IIC_VMOVImm : InstrItinClass; 290198090Srdivackydef IIC_VMOVD : InstrItinClass; 291198090Srdivackydef IIC_VMOVQ : InstrItinClass; 292198090Srdivackydef IIC_VMOVIS : InstrItinClass; 293198090Srdivackydef IIC_VMOVID : InstrItinClass; 294198090Srdivackydef IIC_VMOVISL : InstrItinClass; 295198090Srdivackydef IIC_VMOVSI : InstrItinClass; 296198090Srdivackydef IIC_VMOVDI : InstrItinClass; 297218893Sdimdef IIC_VMOVN : InstrItinClass; 298198090Srdivackydef IIC_VPERMD : InstrItinClass; 299198090Srdivackydef IIC_VPERMQ : InstrItinClass; 300198090Srdivackydef IIC_VPERMQ3 : InstrItinClass; 301198090Srdivackydef IIC_VMACD : InstrItinClass; 302198090Srdivackydef IIC_VMACQ : InstrItinClass; 303235633Sdimdef IIC_VFMACD : InstrItinClass; 304235633Sdimdef IIC_VFMACQ : InstrItinClass; 305198090Srdivackydef IIC_VRECSD : InstrItinClass; 306198090Srdivackydef IIC_VRECSQ : InstrItinClass; 307198090Srdivackydef IIC_VCNTiD : InstrItinClass; 308198090Srdivackydef IIC_VCNTiQ : InstrItinClass; 309198090Srdivackydef IIC_VUNAiD : InstrItinClass; 310198090Srdivackydef IIC_VUNAiQ : InstrItinClass; 311198090Srdivackydef IIC_VQUNAiD : InstrItinClass; 312198090Srdivackydef IIC_VQUNAiQ : InstrItinClass; 313198090Srdivackydef IIC_VBINiD : InstrItinClass; 314198090Srdivackydef IIC_VBINiQ : InstrItinClass; 315198090Srdivackydef IIC_VSUBiD : InstrItinClass; 316198090Srdivackydef IIC_VSUBiQ : InstrItinClass; 317198090Srdivackydef IIC_VBINi4D : InstrItinClass; 318198090Srdivackydef IIC_VBINi4Q : InstrItinClass; 319207618Srdivackydef IIC_VSUBi4D : InstrItinClass; 320207618Srdivackydef IIC_VSUBi4Q : InstrItinClass; 321207618Srdivackydef IIC_VABAD : InstrItinClass; 322207618Srdivackydef IIC_VABAQ : InstrItinClass; 323198090Srdivackydef IIC_VSHLiD : InstrItinClass; 324198090Srdivackydef IIC_VSHLiQ : InstrItinClass; 325198090Srdivackydef IIC_VSHLi4D : InstrItinClass; 326198090Srdivackydef IIC_VSHLi4Q : InstrItinClass; 327198090Srdivackydef IIC_VPALiD : InstrItinClass; 328198090Srdivackydef IIC_VPALiQ : InstrItinClass; 329198090Srdivackydef IIC_VMULi16D : InstrItinClass; 330198090Srdivackydef IIC_VMULi32D : InstrItinClass; 331198090Srdivackydef IIC_VMULi16Q : InstrItinClass; 332198090Srdivackydef IIC_VMULi32Q : InstrItinClass; 333198090Srdivackydef IIC_VMACi16D : InstrItinClass; 334198090Srdivackydef IIC_VMACi32D : InstrItinClass; 335198090Srdivackydef IIC_VMACi16Q : InstrItinClass; 336198090Srdivackydef IIC_VMACi32Q : InstrItinClass; 337198090Srdivackydef IIC_VEXTD : InstrItinClass; 338198090Srdivackydef IIC_VEXTQ : InstrItinClass; 339198090Srdivackydef IIC_VTB1 : InstrItinClass; 340198090Srdivackydef IIC_VTB2 : InstrItinClass; 341198090Srdivackydef IIC_VTB3 : InstrItinClass; 342198090Srdivackydef IIC_VTB4 : InstrItinClass; 343198090Srdivackydef IIC_VTBX1 : InstrItinClass; 344198090Srdivackydef IIC_VTBX2 : InstrItinClass; 345198090Srdivackydef IIC_VTBX3 : InstrItinClass; 346198090Srdivackydef IIC_VTBX4 : InstrItinClass; 347194612Sed 348194612Sed//===----------------------------------------------------------------------===// 349194612Sed// Processor instruction itineraries. 350194612Sed 351194612Sedinclude "ARMScheduleV6.td" 352207618Srdivackyinclude "ARMScheduleA8.td" 353207618Srdivackyinclude "ARMScheduleA9.td" 354245431Sdiminclude "ARMScheduleSwift.td" 355