ARMRegisterInfo.td revision 194710
150479Speter//===- ARMRegisterInfo.td - ARM Register defs -------------------*- C++ -*-===// 22656Srgrimes// 32656Srgrimes// The LLVM Compiler Infrastructure 4124033Simp// 5124033Simp// This file is distributed under the University of Illinois Open Source 6124033Simp// License. See LICENSE.TXT for details. 7276465Sbz// 8124033Simp//===----------------------------------------------------------------------===// 9124033Simp 10124033Simp//===----------------------------------------------------------------------===// 11124033Simp// Declarations that describe the ARM register file 12124033Simp//===----------------------------------------------------------------------===// 13124033Simp 14124033Simp// Registers are identified with 4-bit ID numbers. 15124033Simpclass ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> { 16124033Simp field bits<4> Num; 17124033Simp let Namespace = "ARM"; 18185403Simp let SubRegs = subregs; 19124033Simp} 20124033Simp 21185403Simpclass ARMFReg<bits<5> num, string n> : Register<n> { 22124033Simp field bits<5> Num; 23124033Simp let Namespace = "ARM"; 24124033Simp} 25124033Simp 26124033Simp// Integer registers 27124033Simpdef R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; 28124033Simpdef R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; 29124033Simpdef R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>; 30124033Simpdef R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>; 31124033Simpdef R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>; 32124033Simpdef R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>; 332656Srgrimesdef R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>; 342656Srgrimesdef R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>; 352656Srgrimesdef R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>; 362656Srgrimesdef R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>; 372656Srgrimesdef R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>; 382656Srgrimesdef R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>; 392656Srgrimesdef R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>; 402656Srgrimesdef SP : ARMReg<13, "sp">, DwarfRegNum<[13]>; 412656Srgrimesdef LR : ARMReg<14, "lr">, DwarfRegNum<[14]>; 422656Srgrimesdef PC : ARMReg<15, "pc">, DwarfRegNum<[15]>; 432656Srgrimes 442656Srgrimes// Float registers 452656Srgrimesdef S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">; 462656Srgrimesdef S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">; 472656Srgrimesdef S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">; 482656Srgrimesdef S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">; 492656Srgrimesdef S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">; 502656Srgrimesdef S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">; 512656Srgrimesdef S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">; 522656Srgrimesdef S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">; 532656Srgrimesdef S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">; 542656Srgrimesdef S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">; 552656Srgrimesdef S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">; 562656Srgrimesdef S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">; 572656Srgrimesdef S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">; 582656Srgrimesdef S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">; 592656Srgrimesdef S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">; 602656Srgrimesdef S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">; 612656Srgrimes 622656Srgrimes// Aliases of the F* registers used to hold 64-bit fp values (doubles) 632656Srgrimesdef D0 : ARMReg< 0, "d0", [S0, S1]>; 642656Srgrimesdef D1 : ARMReg< 1, "d1", [S2, S3]>; 652656Srgrimesdef D2 : ARMReg< 2, "d2", [S4, S5]>; 662656Srgrimesdef D3 : ARMReg< 3, "d3", [S6, S7]>; 672656Srgrimesdef D4 : ARMReg< 4, "d4", [S8, S9]>; 682656Srgrimesdef D5 : ARMReg< 5, "d5", [S10, S11]>; 692656Srgrimesdef D6 : ARMReg< 6, "d6", [S12, S13]>; 702656Srgrimesdef D7 : ARMReg< 7, "d7", [S14, S15]>; 712656Srgrimesdef D8 : ARMReg< 8, "d8", [S16, S17]>; 722656Srgrimesdef D9 : ARMReg< 9, "d9", [S18, S19]>; 732656Srgrimesdef D10 : ARMReg<10, "d10", [S20, S21]>; 742656Srgrimesdef D11 : ARMReg<11, "d11", [S22, S23]>; 752656Srgrimesdef D12 : ARMReg<12, "d12", [S24, S25]>; 762656Srgrimesdef D13 : ARMReg<13, "d13", [S26, S27]>; 772656Srgrimesdef D14 : ARMReg<14, "d14", [S28, S29]>; 782656Srgrimesdef D15 : ARMReg<15, "d15", [S30, S31]>; 792656Srgrimes 802656Srgrimes// VFP3 defines 16 additional double registers 812656Srgrimesdef D16 : ARMFReg<16, "d16">; def D17 : ARMFReg<17, "d16">; 822656Srgrimesdef D18 : ARMFReg<18, "d16">; def D19 : ARMFReg<19, "d16">; 832656Srgrimesdef D20 : ARMFReg<20, "d16">; def D21 : ARMFReg<21, "d16">; 842656Srgrimesdef D22 : ARMFReg<22, "d16">; def D23 : ARMFReg<23, "d16">; 852656Srgrimesdef D24 : ARMFReg<24, "d16">; def D25 : ARMFReg<25, "d16">; 862656Srgrimesdef D26 : ARMFReg<26, "d16">; def D27 : ARMFReg<27, "d16">; 872656Srgrimesdef D28 : ARMFReg<28, "d16">; def D29 : ARMFReg<29, "d16">; 882656Srgrimesdef D30 : ARMFReg<30, "d16">; def D31 : ARMFReg<31, "d16">; 892656Srgrimes 902656Srgrimes// Advanced SIMD (NEON) defines 16 quad-word aliases 912656Srgrimesdef Q0 : ARMReg< 0, "q0", [D0, D1]>; 922656Srgrimesdef Q1 : ARMReg< 1, "q1", [D2, D3]>; 932656Srgrimesdef Q2 : ARMReg< 2, "q2", [D4, D5]>; 942656Srgrimesdef Q3 : ARMReg< 3, "q3", [D6, D7]>; 9550978Sobriendef Q4 : ARMReg< 4, "q4", [D8, D9]>; 9650978Sobriendef Q5 : ARMReg< 5, "q5", [D10, D11]>; 9750978Sobriendef Q6 : ARMReg< 6, "q6", [D12, D13]>; 9850978Sobriendef Q7 : ARMReg< 7, "q7", [D14, D15]>; 9950978Sobriendef Q8 : ARMReg< 8, "q8", [D16, D17]>; 10050978Sobriendef Q9 : ARMReg< 9, "q9", [D18, D19]>; 10150978Sobriendef Q10 : ARMReg<10, "q10", [D20, D21]>; 10250978Sobriendef Q11 : ARMReg<11, "q11", [D22, D23]>; 10350978Sobriendef Q12 : ARMReg<12, "q12", [D24, D25]>; 10450978Sobriendef Q13 : ARMReg<13, "q13", [D26, D27]>; 10550978Sobriendef Q14 : ARMReg<14, "q14", [D28, D29]>; 10650978Sobriendef Q15 : ARMReg<15, "q15", [D30, D31]>; 10750978Sobrien 10850978Sobrien// Current Program Status Register. 10950978Sobriendef CPSR : ARMReg<0, "cpsr">; 11050978Sobrien 11150978Sobrien// Register classes. 11250978Sobrien// 11350978Sobrien// pc == Program Counter 11450978Sobrien// lr == Link Register 11550978Sobrien// sp == Stack Pointer 11650978Sobrien// r12 == ip (scratch) 11750978Sobrien// r7 == Frame Pointer (thumb-style backtraces) 11850978Sobrien// r9 == May be reserved as Thread Register 11950978Sobrien// r11 == Frame Pointer (arm-style backtraces) 12050978Sobrien// r10 == Stack Limit 12150978Sobrien// 12250978Sobriendef GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, 12350978Sobrien R7, R8, R9, R10, R12, R11, 12450978Sobrien LR, SP, PC]> { 12550978Sobrien let MethodProtos = [{ 12650978Sobrien iterator allocation_order_begin(const MachineFunction &MF) const; 127 iterator allocation_order_end(const MachineFunction &MF) const; 128 }]; 129 // FIXME: We are reserving r12 in case the PEI needs to use it to 130 // generate large stack offset. Make it available once we have register 131 // scavenging. Similarly r3 is reserved in Thumb mode for now. 132 let MethodBodies = [{ 133 // FP is R11, R9 is available. 134 static const unsigned ARM_GPR_AO_1[] = { 135 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 136 ARM::R12,ARM::LR, 137 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 138 ARM::R8, ARM::R9, ARM::R10, 139 ARM::R11 }; 140 // FP is R11, R9 is not available. 141 static const unsigned ARM_GPR_AO_2[] = { 142 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 143 ARM::R12,ARM::LR, 144 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 145 ARM::R8, ARM::R10, 146 ARM::R11 }; 147 // FP is R7, R9 is available as non-callee-saved register. 148 // This is used by Darwin. 149 static const unsigned ARM_GPR_AO_3[] = { 150 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 151 ARM::R9, ARM::R12,ARM::LR, 152 ARM::R4, ARM::R5, ARM::R6, 153 ARM::R8, ARM::R10,ARM::R11,ARM::R7 }; 154 // FP is R7, R9 is not available. 155 static const unsigned ARM_GPR_AO_4[] = { 156 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 157 ARM::R12,ARM::LR, 158 ARM::R4, ARM::R5, ARM::R6, 159 ARM::R8, ARM::R10,ARM::R11, 160 ARM::R7 }; 161 162 GPRClass::iterator 163 GPRClass::allocation_order_begin(const MachineFunction &MF) const { 164 const TargetMachine &TM = MF.getTarget(); 165 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); 166 if (Subtarget.isTargetDarwin()) { 167 if (Subtarget.isR9Reserved()) 168 return ARM_GPR_AO_4; 169 else 170 return ARM_GPR_AO_3; 171 } else { 172 if (Subtarget.isR9Reserved()) 173 return ARM_GPR_AO_2; 174 else 175 return ARM_GPR_AO_1; 176 } 177 } 178 179 GPRClass::iterator 180 GPRClass::allocation_order_end(const MachineFunction &MF) const { 181 const TargetMachine &TM = MF.getTarget(); 182 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 183 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); 184 GPRClass::iterator I; 185 186 if (Subtarget.isTargetDarwin()) { 187 if (Subtarget.isR9Reserved()) 188 I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned)); 189 else 190 I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned)); 191 } else { 192 if (Subtarget.isR9Reserved()) 193 I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned)); 194 else 195 I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned)); 196 } 197 198 // Mac OS X requires FP not to be clobbered for backtracing purpose. 199 return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I; 200 } 201 }]; 202} 203 204// Thumb registers are R0-R7 normally. Some instructions can still use 205// the general GPR register class above (MOV, e.g.) 206def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> { 207 let MethodProtos = [{ 208 iterator allocation_order_begin(const MachineFunction &MF) const; 209 iterator allocation_order_end(const MachineFunction &MF) const; 210 }]; 211 // FIXME: We are reserving r3 in Thumb mode in case the PEI needs to use it 212 // to generate large stack offset. Make it available once we have register 213 // scavenging. 214 let MethodBodies = [{ 215 static const unsigned THUMB_tGPR_AO[] = { 216 ARM::R0, ARM::R1, ARM::R2, 217 ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; 218 219 // FP is R7, only low registers available. 220 tGPRClass::iterator 221 tGPRClass::allocation_order_begin(const MachineFunction &MF) const { 222 return THUMB_tGPR_AO; 223 } 224 225 tGPRClass::iterator 226 tGPRClass::allocation_order_end(const MachineFunction &MF) const { 227 const TargetMachine &TM = MF.getTarget(); 228 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 229 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); 230 tGPRClass::iterator I = 231 THUMB_tGPR_AO + (sizeof(THUMB_tGPR_AO)/sizeof(unsigned)); 232 // Mac OS X requires FP not to be clobbered for backtracing purpose. 233 return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I; 234 } 235 }]; 236} 237 238// Scalar single precision floating point register class.. 239def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8, 240 S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, 241 S23, S24, S25, S26, S27, S28, S29, S30, S31]>; 242 243// Scalar double precision floating point / generic 64-bit vector register 244// class. 245// ARM requires only word alignment for double. It's more performant if it 246// is double-word alignment though. 247def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64, 248 [D0, D1, D2, D3, D4, D5, D6, D7, 249 D8, D9, D10, D11, D12, D13, D14, D15]> { 250 let SubRegClassList = [SPR, SPR]; 251 let MethodProtos = [{ 252 iterator allocation_order_begin(const MachineFunction &MF) const; 253 iterator allocation_order_end(const MachineFunction &MF) const; 254 }]; 255 let MethodBodies = [{ 256 // VFP2 257 static const unsigned ARM_DPR_VFP2[] = { 258 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 259 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 260 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 261 ARM::D12, ARM::D13, ARM::D14, ARM::D15 }; 262 // VFP3 263 static const unsigned ARM_DPR_VFP3[] = { 264 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 265 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 266 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 267 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 268 ARM::D16, ARM::D17, ARM::D18, ARM::D15, 269 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 270 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 271 ARM::D28, ARM::D29, ARM::D30, ARM::D31 }; 272 DPRClass::iterator 273 DPRClass::allocation_order_begin(const MachineFunction &MF) const { 274 const TargetMachine &TM = MF.getTarget(); 275 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); 276 if (Subtarget.hasVFP3()) 277 return ARM_DPR_VFP3; 278 return ARM_DPR_VFP2; 279 } 280 281 DPRClass::iterator 282 DPRClass::allocation_order_end(const MachineFunction &MF) const { 283 const TargetMachine &TM = MF.getTarget(); 284 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); 285 if (Subtarget.hasVFP3()) 286 return ARM_DPR_VFP3 + (sizeof(ARM_DPR_VFP3)/sizeof(unsigned)); 287 else 288 return ARM_DPR_VFP2 + (sizeof(ARM_DPR_VFP2)/sizeof(unsigned)); 289 } 290 }]; 291} 292 293// Generic 128-bit vector register class. 294def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128, 295 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, 296 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15]> { 297 let SubRegClassList = [SPR, SPR, SPR, SPR, DPR, DPR]; 298} 299 300// Condition code registers. 301def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>; 302 303//===----------------------------------------------------------------------===// 304// Subregister Set Definitions... now that we have all of the pieces, define the 305// sub registers for each register. 306// 307 308def arm_ssubreg_0 : PatLeaf<(i32 1)>; 309def arm_ssubreg_1 : PatLeaf<(i32 2)>; 310def arm_ssubreg_2 : PatLeaf<(i32 3)>; 311def arm_ssubreg_3 : PatLeaf<(i32 4)>; 312def arm_dsubreg_0 : PatLeaf<(i32 5)>; 313def arm_dsubreg_1 : PatLeaf<(i32 6)>; 314 315// S sub-registers of D registers. 316def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7, 317 D8, D9, D10, D11, D12, D13, D14, D15], 318 [S0, S2, S4, S6, S8, S10, S12, S14, 319 S16, S18, S20, S22, S24, S26, S28, S30]>; 320def : SubRegSet<2, [D0, D1, D2, D3, D4, D5, D6, D7, 321 D8, D9, D10, D11, D12, D13, D14, D15], 322 [S1, S3, S5, S7, S9, S11, S13, S15, 323 S17, S19, S21, S23, S25, S27, S29, S31]>; 324 325// S sub-registers of Q registers. 326def : SubRegSet<1, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7], 327 [S0, S4, S8, S12, S16, S20, S24, S28]>; 328def : SubRegSet<2, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7], 329 [S1, S5, S9, S13, S17, S21, S25, S29]>; 330def : SubRegSet<3, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7], 331 [S2, S6, S10, S14, S18, S22, S26, S30]>; 332def : SubRegSet<4, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7], 333 [S3, S7, S11, S15, S19, S23, S27, S31]>; 334 335// D sub-registers of Q registers. 336def : SubRegSet<5, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, 337 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15], 338 [D0, D2, D4, D6, D8, D10, D12, D14, 339 D16, D18, D20, D22, D24, D26, D28, D30]>; 340def : SubRegSet<6, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, 341 Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15], 342 [D1, D3, D5, D7, D9, D11, D13, D15, 343 D17, D19, D21, D23, D25, D27, D29, D31]>; 344 345