ARMInstrInfo.h revision 194710 
1//===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMINSTRUCTIONINFO_H
15#define ARMINSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "ARMRegisterInfo.h"
19#include "ARM.h"
20
21namespace llvm {
22  class ARMSubtarget;
23
24/// ARMII - This namespace holds all of the target specific flags that
25/// instruction info tracks.
26///
27namespace ARMII {
28  enum {
29    //===------------------------------------------------------------------===//
30    // Instruction Flags.
31
32    //===------------------------------------------------------------------===//
33    // This four-bit field describes the addressing mode used.
34
35    AddrModeMask  = 0xf,
36    AddrModeNone  = 0,
37    AddrMode1     = 1,
38    AddrMode2     = 2,
39    AddrMode3     = 3,
40    AddrMode4     = 4,
41    AddrMode5     = 5,
42    AddrModeT1    = 6,
43    AddrModeT2    = 7,
44    AddrModeT4    = 8,
45    AddrModeTs    = 9,  // i8 * 4 for pc and sp relative data
46
47    // Size* - Flags to keep track of the size of an instruction.
48    SizeShift     = 4,
49    SizeMask      = 7 << SizeShift,
50    SizeSpecial   = 1,   // 0 byte pseudo or special case.
51    Size8Bytes    = 2,
52    Size4Bytes    = 3,
53    Size2Bytes    = 4,
54
55    // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
56    // and store ops
57    IndexModeShift = 7,
58    IndexModeMask  = 3 << IndexModeShift,
59    IndexModePre   = 1,
60    IndexModePost  = 2,
61
62    //===------------------------------------------------------------------===//
63    // Misc flags.
64
65    // UnaryDP - Indicates this is a unary data processing instruction, i.e.
66    // it doesn't have a Rn operand.
67    UnaryDP       = 1 << 9,
68
69    //===------------------------------------------------------------------===//
70    // Instruction encoding formats.
71    //
72    FormShift     = 10,
73    FormMask      = 0x1f << FormShift,
74
75    // Pseudo instructions
76    Pseudo        = 0  << FormShift,
77
78    // Multiply instructions
79    MulFrm        = 1  << FormShift,
80
81    // Branch instructions
82    BrFrm         = 2  << FormShift,
83    BrMiscFrm     = 3  << FormShift,
84
85    // Data Processing instructions
86    DPFrm         = 4  << FormShift,
87    DPSoRegFrm    = 5  << FormShift,
88
89    // Load and Store
90    LdFrm         = 6  << FormShift,
91    StFrm         = 7  << FormShift,
92    LdMiscFrm     = 8  << FormShift,
93    StMiscFrm     = 9  << FormShift,
94    LdStMulFrm    = 10 << FormShift,
95
96    // Miscellaneous arithmetic instructions
97    ArithMiscFrm  = 11 << FormShift,
98
99    // Extend instructions
100    ExtFrm        = 12 << FormShift,
101
102    // VFP formats
103    VFPUnaryFrm   = 13 << FormShift,
104    VFPBinaryFrm  = 14 << FormShift,
105    VFPConv1Frm   = 15 << FormShift,
106    VFPConv2Frm   = 16 << FormShift,
107    VFPConv3Frm   = 17 << FormShift,
108    VFPConv4Frm   = 18 << FormShift,
109    VFPConv5Frm   = 19 << FormShift,
110    VFPLdStFrm    = 20 << FormShift,
111    VFPLdStMulFrm = 21 << FormShift,
112    VFPMiscFrm    = 22 << FormShift,
113
114    // Thumb format
115    ThumbFrm      = 23 << FormShift,
116
117    // NEON format
118    NEONFrm       = 24 << FormShift,
119    NEONGetLnFrm  = 25 << FormShift,
120    NEONSetLnFrm  = 26 << FormShift,
121    NEONDupFrm    = 27 << FormShift,
122
123    //===------------------------------------------------------------------===//
124    // Field shifts - such shifts are used to set field while generating
125    // machine instructions.
126    M_BitShift     = 5,
127    ShiftImmShift  = 5,
128    ShiftShift     = 7,
129    N_BitShift     = 7,
130    ImmHiShift     = 8,
131    SoRotImmShift  = 8,
132    RegRsShift     = 8,
133    ExtRotImmShift = 10,
134    RegRdLoShift   = 12,
135    RegRdShift     = 12,
136    RegRdHiShift   = 16,
137    RegRnShift     = 16,
138    S_BitShift     = 20,
139    W_BitShift     = 21,
140    AM3_I_BitShift = 22,
141    D_BitShift     = 22,
142    U_BitShift     = 23,
143    P_BitShift     = 24,
144    I_BitShift     = 25,
145    CondShift      = 28
146  };
147}
148
149class ARMInstrInfo : public TargetInstrInfoImpl {
150  const ARMRegisterInfo RI;
151public:
152  explicit ARMInstrInfo(const ARMSubtarget &STI);
153
154  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
155  /// such, whenever a client has an instance of instruction info, it should
156  /// always be able to get register info as well (through this method).
157  ///
158  virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
159
160  /// Return true if the instruction is a register to register move and return
161  /// the source and dest operands and their sub-register indices by reference.
162  virtual bool isMoveInstr(const MachineInstr &MI,
163                           unsigned &SrcReg, unsigned &DstReg,
164                           unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
165
166  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
167                                       int &FrameIndex) const;
168  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
169                                      int &FrameIndex) const;
170
171  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
172                     unsigned DestReg, const MachineInstr *Orig) const;
173
174  virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
175                                              MachineBasicBlock::iterator &MBBI,
176                                              LiveVariables *LV) const;
177
178  // Branch analysis.
179  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
180                             MachineBasicBlock *&FBB,
181                             SmallVectorImpl<MachineOperand> &Cond,
182                             bool AllowModify) const;
183  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
184  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
185                                MachineBasicBlock *FBB,
186                            const SmallVectorImpl<MachineOperand> &Cond) const;
187  virtual bool copyRegToReg(MachineBasicBlock &MBB,
188                            MachineBasicBlock::iterator I,
189                            unsigned DestReg, unsigned SrcReg,
190                            const TargetRegisterClass *DestRC,
191                            const TargetRegisterClass *SrcRC) const;
192  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
193                                   MachineBasicBlock::iterator MBBI,
194                                   unsigned SrcReg, bool isKill, int FrameIndex,
195                                   const TargetRegisterClass *RC) const;
196
197  virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
198                              SmallVectorImpl<MachineOperand> &Addr,
199                              const TargetRegisterClass *RC,
200                              SmallVectorImpl<MachineInstr*> &NewMIs) const;
201
202  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
203                                    MachineBasicBlock::iterator MBBI,
204                                    unsigned DestReg, int FrameIndex,
205                                    const TargetRegisterClass *RC) const;
206
207  virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
208                               SmallVectorImpl<MachineOperand> &Addr,
209                               const TargetRegisterClass *RC,
210                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
211  virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
212                                         MachineBasicBlock::iterator MI,
213                                 const std::vector<CalleeSavedInfo> &CSI) const;
214  virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
215                                           MachineBasicBlock::iterator MI,
216                                 const std::vector<CalleeSavedInfo> &CSI) const;
217
218  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
219                                              MachineInstr* MI,
220                                           const SmallVectorImpl<unsigned> &Ops,
221                                              int FrameIndex) const;
222
223  virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
224                                              MachineInstr* MI,
225                                           const SmallVectorImpl<unsigned> &Ops,
226                                              MachineInstr* LoadMI) const {
227    return 0;
228  }
229
230  virtual bool canFoldMemoryOperand(const MachineInstr *MI,
231                                    const SmallVectorImpl<unsigned> &Ops) const;
232
233  virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
234  virtual
235  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
236
237  // Predication support.
238  virtual bool isPredicated(const MachineInstr *MI) const;
239
240  ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
241    int PIdx = MI->findFirstPredOperandIdx();
242    return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
243                      : ARMCC::AL;
244  }
245
246  virtual
247  bool PredicateInstruction(MachineInstr *MI,
248                            const SmallVectorImpl<MachineOperand> &Pred) const;
249
250  virtual
251  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
252                         const SmallVectorImpl<MachineOperand> &Pred2) const;
253
254  virtual bool DefinesPredicate(MachineInstr *MI,
255                                std::vector<MachineOperand> &Pred) const;
256
257  /// GetInstSize - Returns the size of the specified MachineInstr.
258  ///
259  virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
260};
261
262}
263
264#endif
265