ARMFastISel.cpp revision 212793
1//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the ARM-specific support for the FastISel class. Some 11// of the target-specific code is generated by tablegen in the file 12// ARMGenFastISel.inc, which is #included here. 13// 14//===----------------------------------------------------------------------===// 15 16#include "ARM.h" 17#include "ARMBaseInstrInfo.h" 18#include "ARMRegisterInfo.h" 19#include "ARMTargetMachine.h" 20#include "ARMSubtarget.h" 21#include "llvm/CallingConv.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/Instructions.h" 25#include "llvm/IntrinsicInst.h" 26#include "llvm/CodeGen/Analysis.h" 27#include "llvm/CodeGen/FastISel.h" 28#include "llvm/CodeGen/FunctionLoweringInfo.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/MachineModuleInfo.h" 31#include "llvm/CodeGen/MachineConstantPool.h" 32#include "llvm/CodeGen/MachineFrameInfo.h" 33#include "llvm/CodeGen/MachineRegisterInfo.h" 34#include "llvm/Support/CallSite.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/GetElementPtrTypeIterator.h" 38#include "llvm/Target/TargetData.h" 39#include "llvm/Target/TargetInstrInfo.h" 40#include "llvm/Target/TargetLowering.h" 41#include "llvm/Target/TargetMachine.h" 42#include "llvm/Target/TargetOptions.h" 43using namespace llvm; 44 45static cl::opt<bool> 46EnableARMFastISel("arm-fast-isel", 47 cl::desc("Turn on experimental ARM fast-isel support"), 48 cl::init(false), cl::Hidden); 49 50namespace { 51 52class ARMFastISel : public FastISel { 53 54 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 55 /// make the right decision when generating code for different targets. 56 const ARMSubtarget *Subtarget; 57 const TargetMachine &TM; 58 const TargetInstrInfo &TII; 59 const TargetLowering &TLI; 60 const ARMFunctionInfo *AFI; 61 62 // Convenience variable to avoid checking all the time. 63 bool isThumb; 64 65 public: 66 explicit ARMFastISel(FunctionLoweringInfo &funcInfo) 67 : FastISel(funcInfo), 68 TM(funcInfo.MF->getTarget()), 69 TII(*TM.getInstrInfo()), 70 TLI(*TM.getTargetLowering()) { 71 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 72 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>(); 73 isThumb = AFI->isThumbFunction(); 74 } 75 76 // Code from FastISel.cpp. 77 virtual unsigned FastEmitInst_(unsigned MachineInstOpcode, 78 const TargetRegisterClass *RC); 79 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode, 80 const TargetRegisterClass *RC, 81 unsigned Op0, bool Op0IsKill); 82 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode, 83 const TargetRegisterClass *RC, 84 unsigned Op0, bool Op0IsKill, 85 unsigned Op1, bool Op1IsKill); 86 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode, 87 const TargetRegisterClass *RC, 88 unsigned Op0, bool Op0IsKill, 89 uint64_t Imm); 90 virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode, 91 const TargetRegisterClass *RC, 92 unsigned Op0, bool Op0IsKill, 93 const ConstantFP *FPImm); 94 virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode, 95 const TargetRegisterClass *RC, 96 uint64_t Imm); 97 virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode, 98 const TargetRegisterClass *RC, 99 unsigned Op0, bool Op0IsKill, 100 unsigned Op1, bool Op1IsKill, 101 uint64_t Imm); 102 virtual unsigned FastEmitInst_extractsubreg(MVT RetVT, 103 unsigned Op0, bool Op0IsKill, 104 uint32_t Idx); 105 106 // Backend specific FastISel code. 107 virtual bool TargetSelectInstruction(const Instruction *I); 108 virtual unsigned TargetMaterializeConstant(const Constant *C); 109 110 #include "ARMGenFastISel.inc" 111 112 // Instruction selection routines. 113 virtual bool ARMSelectLoad(const Instruction *I); 114 virtual bool ARMSelectStore(const Instruction *I); 115 virtual bool ARMSelectBranch(const Instruction *I); 116 117 // Utility routines. 118 private: 119 bool isTypeLegal(const Type *Ty, EVT &VT); 120 bool isLoadTypeLegal(const Type *Ty, EVT &VT); 121 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset); 122 bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset); 123 bool ARMLoadAlloca(const Instruction *I); 124 bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg); 125 bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset); 126 bool ARMMaterializeConstant(const ConstantInt *Val, unsigned &Reg); 127 128 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); 129 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); 130}; 131 132} // end anonymous namespace 133 134// #include "ARMGenCallingConv.inc" 135 136// DefinesOptionalPredicate - This is different from DefinesPredicate in that 137// we don't care about implicit defs here, just places we'll need to add a 138// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR. 139bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { 140 const TargetInstrDesc &TID = MI->getDesc(); 141 if (!TID.hasOptionalDef()) 142 return false; 143 144 // Look to see if our OptionalDef is defining CPSR or CCR. 145 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 146 const MachineOperand &MO = MI->getOperand(i); 147 if (!MO.isReg() || !MO.isDef()) continue; 148 if (MO.getReg() == ARM::CPSR) 149 *CPSR = true; 150 } 151 return true; 152} 153 154// If the machine is predicable go ahead and add the predicate operands, if 155// it needs default CC operands add those. 156const MachineInstrBuilder & 157ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { 158 MachineInstr *MI = &*MIB; 159 160 // Do we use a predicate? 161 if (TII.isPredicable(MI)) 162 AddDefaultPred(MIB); 163 164 // Do we optionally set a predicate? Preds is size > 0 iff the predicate 165 // defines CPSR. All other OptionalDefines in ARM are the CCR register. 166 bool CPSR = false; 167 if (DefinesOptionalPredicate(MI, &CPSR)) { 168 if (CPSR) 169 AddDefaultT1CC(MIB); 170 else 171 AddDefaultCC(MIB); 172 } 173 return MIB; 174} 175 176unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode, 177 const TargetRegisterClass* RC) { 178 unsigned ResultReg = createResultReg(RC); 179 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 180 181 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)); 182 return ResultReg; 183} 184 185unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode, 186 const TargetRegisterClass *RC, 187 unsigned Op0, bool Op0IsKill) { 188 unsigned ResultReg = createResultReg(RC); 189 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 190 191 if (II.getNumDefs() >= 1) 192 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 193 .addReg(Op0, Op0IsKill * RegState::Kill)); 194 else { 195 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 196 .addReg(Op0, Op0IsKill * RegState::Kill)); 197 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 198 TII.get(TargetOpcode::COPY), ResultReg) 199 .addReg(II.ImplicitDefs[0])); 200 } 201 return ResultReg; 202} 203 204unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 205 const TargetRegisterClass *RC, 206 unsigned Op0, bool Op0IsKill, 207 unsigned Op1, bool Op1IsKill) { 208 unsigned ResultReg = createResultReg(RC); 209 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 210 211 if (II.getNumDefs() >= 1) 212 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 213 .addReg(Op0, Op0IsKill * RegState::Kill) 214 .addReg(Op1, Op1IsKill * RegState::Kill)); 215 else { 216 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 217 .addReg(Op0, Op0IsKill * RegState::Kill) 218 .addReg(Op1, Op1IsKill * RegState::Kill)); 219 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 220 TII.get(TargetOpcode::COPY), ResultReg) 221 .addReg(II.ImplicitDefs[0])); 222 } 223 return ResultReg; 224} 225 226unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 227 const TargetRegisterClass *RC, 228 unsigned Op0, bool Op0IsKill, 229 uint64_t Imm) { 230 unsigned ResultReg = createResultReg(RC); 231 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 232 233 if (II.getNumDefs() >= 1) 234 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 235 .addReg(Op0, Op0IsKill * RegState::Kill) 236 .addImm(Imm)); 237 else { 238 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 239 .addReg(Op0, Op0IsKill * RegState::Kill) 240 .addImm(Imm)); 241 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 242 TII.get(TargetOpcode::COPY), ResultReg) 243 .addReg(II.ImplicitDefs[0])); 244 } 245 return ResultReg; 246} 247 248unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 249 const TargetRegisterClass *RC, 250 unsigned Op0, bool Op0IsKill, 251 const ConstantFP *FPImm) { 252 unsigned ResultReg = createResultReg(RC); 253 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 254 255 if (II.getNumDefs() >= 1) 256 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 257 .addReg(Op0, Op0IsKill * RegState::Kill) 258 .addFPImm(FPImm)); 259 else { 260 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 261 .addReg(Op0, Op0IsKill * RegState::Kill) 262 .addFPImm(FPImm)); 263 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 264 TII.get(TargetOpcode::COPY), ResultReg) 265 .addReg(II.ImplicitDefs[0])); 266 } 267 return ResultReg; 268} 269 270unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 271 const TargetRegisterClass *RC, 272 unsigned Op0, bool Op0IsKill, 273 unsigned Op1, bool Op1IsKill, 274 uint64_t Imm) { 275 unsigned ResultReg = createResultReg(RC); 276 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 277 278 if (II.getNumDefs() >= 1) 279 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 280 .addReg(Op0, Op0IsKill * RegState::Kill) 281 .addReg(Op1, Op1IsKill * RegState::Kill) 282 .addImm(Imm)); 283 else { 284 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 285 .addReg(Op0, Op0IsKill * RegState::Kill) 286 .addReg(Op1, Op1IsKill * RegState::Kill) 287 .addImm(Imm)); 288 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 289 TII.get(TargetOpcode::COPY), ResultReg) 290 .addReg(II.ImplicitDefs[0])); 291 } 292 return ResultReg; 293} 294 295unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode, 296 const TargetRegisterClass *RC, 297 uint64_t Imm) { 298 unsigned ResultReg = createResultReg(RC); 299 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 300 301 if (II.getNumDefs() >= 1) 302 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 303 .addImm(Imm)); 304 else { 305 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 306 .addImm(Imm)); 307 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 308 TII.get(TargetOpcode::COPY), ResultReg) 309 .addReg(II.ImplicitDefs[0])); 310 } 311 return ResultReg; 312} 313 314unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT, 315 unsigned Op0, bool Op0IsKill, 316 uint32_t Idx) { 317 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 318 assert(TargetRegisterInfo::isVirtualRegister(Op0) && 319 "Cannot yet extract from physregs"); 320 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 321 DL, TII.get(TargetOpcode::COPY), ResultReg) 322 .addReg(Op0, getKillRegState(Op0IsKill), Idx)); 323 return ResultReg; 324} 325 326unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) { 327 EVT VT = TLI.getValueType(C->getType(), true); 328 329 // Only handle simple types. 330 if (!VT.isSimple()) return 0; 331 332 // TODO: This should be safe for fp because they're just bits from the 333 // Constant. 334 // TODO: Theoretically we could materialize fp constants with instructions 335 // from VFP3. 336 337 // MachineConstantPool wants an explicit alignment. 338 unsigned Align = TD.getPrefTypeAlignment(C->getType()); 339 if (Align == 0) { 340 // TODO: Figure out if this is correct. 341 Align = TD.getTypeAllocSize(C->getType()); 342 } 343 unsigned Idx = MCP.getConstantPoolIndex(C, Align); 344 345 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 346 // Different addressing modes between ARM/Thumb2 for constant pool loads. 347 if (isThumb) 348 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 349 TII.get(ARM::t2LDRpci)) 350 .addReg(DestReg).addConstantPoolIndex(Idx)); 351 else 352 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 353 TII.get(ARM::LDRcp)) 354 .addReg(DestReg).addConstantPoolIndex(Idx) 355 .addReg(0).addImm(0)); 356 357 return DestReg; 358} 359 360bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) { 361 VT = TLI.getValueType(Ty, true); 362 363 // Only handle simple types. 364 if (VT == MVT::Other || !VT.isSimple()) return false; 365 366 // Handle all legal types, i.e. a register that will directly hold this 367 // value. 368 return TLI.isTypeLegal(VT); 369} 370 371bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) { 372 if (isTypeLegal(Ty, VT)) return true; 373 374 // If this is a type than can be sign or zero-extended to a basic operation 375 // go ahead and accept it now. 376 if (VT == MVT::i8 || VT == MVT::i16) 377 return true; 378 379 return false; 380} 381 382// Computes the Reg+Offset to get to an object. 383bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg, 384 int &Offset) { 385 // Some boilerplate from the X86 FastISel. 386 const User *U = NULL; 387 unsigned Opcode = Instruction::UserOp1; 388 if (const Instruction *I = dyn_cast<Instruction>(Obj)) { 389 // Don't walk into other basic blocks; it's possible we haven't 390 // visited them yet, so the instructions may not yet be assigned 391 // virtual registers. 392 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB) 393 return false; 394 395 Opcode = I->getOpcode(); 396 U = I; 397 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) { 398 Opcode = C->getOpcode(); 399 U = C; 400 } 401 402 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType())) 403 if (Ty->getAddressSpace() > 255) 404 // Fast instruction selection doesn't support the special 405 // address spaces. 406 return false; 407 408 switch (Opcode) { 409 default: 410 //errs() << "Failing Opcode is: " << *Op1 << "\n"; 411 break; 412 case Instruction::Alloca: { 413 assert(false && "Alloca should have been handled earlier!"); 414 return false; 415 } 416 } 417 418 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) { 419 //errs() << "Failing GV is: " << GV << "\n"; 420 (void)GV; 421 return false; 422 } 423 424 // Try to get this in a register if nothing else has worked. 425 Reg = getRegForValue(Obj); 426 if (Reg == 0) return false; 427 428 // Since the offset may be too large for the load instruction 429 // get the reg+offset into a register. 430 // TODO: Verify the additions work, otherwise we'll need to add the 431 // offset instead of 0 to the instructions and do all sorts of operand 432 // munging. 433 // TODO: Optimize this somewhat. 434 if (Offset != 0) { 435 ARMCC::CondCodes Pred = ARMCC::AL; 436 unsigned PredReg = 0; 437 438 if (!isThumb) 439 emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 440 Reg, Reg, Offset, Pred, PredReg, 441 static_cast<const ARMBaseInstrInfo&>(TII)); 442 else { 443 assert(AFI->isThumb2Function()); 444 emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 445 Reg, Reg, Offset, Pred, PredReg, 446 static_cast<const ARMBaseInstrInfo&>(TII)); 447 } 448 } 449 450 return true; 451} 452 453bool ARMFastISel::ARMLoadAlloca(const Instruction *I) { 454 Value *Op0 = I->getOperand(0); 455 456 // Verify it's an alloca. 457 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) { 458 DenseMap<const AllocaInst*, int>::iterator SI = 459 FuncInfo.StaticAllocaMap.find(AI); 460 461 if (SI != FuncInfo.StaticAllocaMap.end()) { 462 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); 463 unsigned ResultReg = createResultReg(RC); 464 TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt, 465 ResultReg, SI->second, RC, 466 TM.getRegisterInfo()); 467 UpdateValueMap(I, ResultReg); 468 return true; 469 } 470 } 471 return false; 472} 473 474bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, 475 unsigned Reg, int Offset) { 476 477 assert(VT.isSimple() && "Non-simple types are invalid here!"); 478 unsigned Opc; 479 480 switch (VT.getSimpleVT().SimpleTy) { 481 default: 482 assert(false && "Trying to emit for an unhandled type!"); 483 return false; 484 case MVT::i16: 485 Opc = isThumb ? ARM::tLDRH : ARM::LDRH; 486 VT = MVT::i32; 487 break; 488 case MVT::i8: 489 Opc = isThumb ? ARM::tLDRB : ARM::LDRB; 490 VT = MVT::i32; 491 break; 492 case MVT::i32: 493 Opc = isThumb ? ARM::tLDR : ARM::LDR; 494 break; 495 } 496 497 ResultReg = createResultReg(TLI.getRegClassFor(VT)); 498 499 // TODO: Fix the Addressing modes so that these can share some code. 500 // Since this is a Thumb1 load this will work in Thumb1 or 2 mode. 501 if (isThumb) 502 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 503 TII.get(Opc), ResultReg) 504 .addReg(Reg).addImm(Offset).addReg(0)); 505 else 506 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 507 TII.get(Opc), ResultReg) 508 .addReg(Reg).addReg(0).addImm(Offset)); 509 510 return true; 511} 512 513bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg) { 514 Value *Op1 = I->getOperand(1); 515 516 // Verify it's an alloca. 517 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) { 518 DenseMap<const AllocaInst*, int>::iterator SI = 519 FuncInfo.StaticAllocaMap.find(AI); 520 521 if (SI != FuncInfo.StaticAllocaMap.end()) { 522 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); 523 assert(SrcReg != 0 && "Nothing to store!"); 524 TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt, 525 SrcReg, true /*isKill*/, SI->second, RC, 526 TM.getRegisterInfo()); 527 return true; 528 } 529 } 530 return false; 531} 532 533bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, 534 unsigned DstReg, int Offset) { 535 unsigned StrOpc; 536 switch (VT.getSimpleVT().SimpleTy) { 537 default: return false; 538 case MVT::i1: 539 case MVT::i8: StrOpc = isThumb ? ARM::tSTRB : ARM::STRB; break; 540 case MVT::i16: StrOpc = isThumb ? ARM::tSTRH : ARM::STRH; break; 541 case MVT::i32: StrOpc = isThumb ? ARM::tSTR : ARM::STR; break; 542 case MVT::f32: 543 if (!Subtarget->hasVFP2()) return false; 544 StrOpc = ARM::VSTRS; 545 break; 546 case MVT::f64: 547 if (!Subtarget->hasVFP2()) return false; 548 StrOpc = ARM::VSTRD; 549 break; 550 } 551 552 if (isThumb) 553 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 554 TII.get(StrOpc), SrcReg) 555 .addReg(DstReg).addImm(Offset).addReg(0)); 556 else 557 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 558 TII.get(StrOpc), SrcReg) 559 .addReg(DstReg).addReg(0).addImm(Offset)); 560 561 return true; 562} 563 564bool ARMFastISel::ARMSelectStore(const Instruction *I) { 565 Value *Op0 = I->getOperand(0); 566 unsigned SrcReg = 0; 567 568 // Yay type legalization 569 EVT VT; 570 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT)) 571 return false; 572 573 // Get the value to be stored into a register. 574 SrcReg = getRegForValue(Op0); 575 if (SrcReg == 0) 576 return false; 577 578 // If we're an alloca we know we have a frame index and can emit the store 579 // quickly. 580 if (ARMStoreAlloca(I, SrcReg)) 581 return true; 582 583 // Our register and offset with innocuous defaults. 584 unsigned Reg = 0; 585 int Offset = 0; 586 587 // See if we can handle this as Reg + Offset 588 if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset)) 589 return false; 590 591 if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false; 592 593 return false; 594 595} 596 597bool ARMFastISel::ARMSelectLoad(const Instruction *I) { 598 // If we're an alloca we know we have a frame index and can emit the load 599 // directly in short order. 600 if (ARMLoadAlloca(I)) 601 return true; 602 603 // Verify we have a legal type before going any further. 604 EVT VT; 605 if (!isLoadTypeLegal(I->getType(), VT)) 606 return false; 607 608 // Our register and offset with innocuous defaults. 609 unsigned Reg = 0; 610 int Offset = 0; 611 612 // See if we can handle this as Reg + Offset 613 if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset)) 614 return false; 615 616 unsigned ResultReg; 617 if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false; 618 619 UpdateValueMap(I, ResultReg); 620 return true; 621} 622 623bool ARMFastISel::ARMSelectBranch(const Instruction *I) { 624 const BranchInst *BI = cast<BranchInst>(I); 625 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; 626 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; 627 628 // Simple branch support. 629 unsigned CondReg = getRegForValue(BI->getCondition()); 630 if (CondReg == 0) return false; 631 632 unsigned CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr; 633 unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; 634 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) 635 .addReg(CondReg).addReg(CondReg)); 636 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) 637 .addMBB(TBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 638 FastEmitBranch(FBB, DL); 639 FuncInfo.MBB->addSuccessor(TBB); 640 return true; 641} 642 643// TODO: SoftFP support. 644bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { 645 // No Thumb-1 for now. 646 if (isThumb && !AFI->isThumb2Function()) return false; 647 648 switch (I->getOpcode()) { 649 case Instruction::Load: 650 return ARMSelectLoad(I); 651 case Instruction::Store: 652 return ARMSelectStore(I); 653 case Instruction::Br: 654 return ARMSelectBranch(I); 655 default: break; 656 } 657 return false; 658} 659 660namespace llvm { 661 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) { 662 if (EnableARMFastISel) return new ARMFastISel(funcInfo); 663 return 0; 664 } 665} 666