ARMBaseRegisterInfo.cpp revision 204792 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41using namespace llvm;
42
43static cl::opt<bool>
44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45          cl::desc("Reuse repeated frame index values"));
46
47unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
48                                                   bool *isSPVFP) {
49  if (isSPVFP)
50    *isSPVFP = false;
51
52  using namespace ARM;
53  switch (RegEnum) {
54  default:
55    llvm_unreachable("Unknown ARM register!");
56  case R0:  case D0:  case Q0:  return 0;
57  case R1:  case D1:  case Q1:  return 1;
58  case R2:  case D2:  case Q2:  return 2;
59  case R3:  case D3:  case Q3:  return 3;
60  case R4:  case D4:  case Q4:  return 4;
61  case R5:  case D5:  case Q5:  return 5;
62  case R6:  case D6:  case Q6:  return 6;
63  case R7:  case D7:  case Q7:  return 7;
64  case R8:  case D8:  case Q8:  return 8;
65  case R9:  case D9:  case Q9:  return 9;
66  case R10: case D10: case Q10: return 10;
67  case R11: case D11: case Q11: return 11;
68  case R12: case D12: case Q12: return 12;
69  case SP:  case D13: case Q13: return 13;
70  case LR:  case D14: case Q14: return 14;
71  case PC:  case D15: case Q15: return 15;
72
73  case D16: return 16;
74  case D17: return 17;
75  case D18: return 18;
76  case D19: return 19;
77  case D20: return 20;
78  case D21: return 21;
79  case D22: return 22;
80  case D23: return 23;
81  case D24: return 24;
82  case D25: return 25;
83  case D26: return 27;
84  case D27: return 27;
85  case D28: return 28;
86  case D29: return 29;
87  case D30: return 30;
88  case D31: return 31;
89
90  case S0: case S1: case S2: case S3:
91  case S4: case S5: case S6: case S7:
92  case S8: case S9: case S10: case S11:
93  case S12: case S13: case S14: case S15:
94  case S16: case S17: case S18: case S19:
95  case S20: case S21: case S22: case S23:
96  case S24: case S25: case S26: case S27:
97  case S28: case S29: case S30: case S31: {
98    if (isSPVFP)
99      *isSPVFP = true;
100    switch (RegEnum) {
101    default: return 0; // Avoid compile time warning.
102    case S0: return 0;
103    case S1: return 1;
104    case S2: return 2;
105    case S3: return 3;
106    case S4: return 4;
107    case S5: return 5;
108    case S6: return 6;
109    case S7: return 7;
110    case S8: return 8;
111    case S9: return 9;
112    case S10: return 10;
113    case S11: return 11;
114    case S12: return 12;
115    case S13: return 13;
116    case S14: return 14;
117    case S15: return 15;
118    case S16: return 16;
119    case S17: return 17;
120    case S18: return 18;
121    case S19: return 19;
122    case S20: return 20;
123    case S21: return 21;
124    case S22: return 22;
125    case S23: return 23;
126    case S24: return 24;
127    case S25: return 25;
128    case S26: return 26;
129    case S27: return 27;
130    case S28: return 28;
131    case S29: return 29;
132    case S30: return 30;
133    case S31: return 31;
134    }
135  }
136  }
137}
138
139ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
140                                         const ARMSubtarget &sti)
141  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
142    TII(tii), STI(sti),
143    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
144}
145
146const unsigned*
147ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
148  static const unsigned CalleeSavedRegs[] = {
149    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
150    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
151
152    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
153    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
154    0
155  };
156
157  static const unsigned DarwinCalleeSavedRegs[] = {
158    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
159    // register.
160    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
161    ARM::R11, ARM::R10, ARM::R8,
162
163    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
164    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
165    0
166  };
167  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
168}
169
170const TargetRegisterClass* const *
171ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
172  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
173    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
174    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
175    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
176
177    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
178    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
179    0
180  };
181
182  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
183    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
184    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
185    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
186
187    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
188    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
189    0
190  };
191
192  static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
193    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
194    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
195    &ARM::GPRRegClass, &ARM::GPRRegClass,
196
197    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
198    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
199    0
200  };
201
202  static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
203    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
204    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
205    &ARM::GPRRegClass,  &ARM::GPRRegClass,
206
207    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
208    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
209    0
210  };
211
212  if (STI.isThumb1Only()) {
213    return STI.isTargetDarwin()
214      ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
215  }
216  return STI.isTargetDarwin()
217    ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
218}
219
220BitVector ARMBaseRegisterInfo::
221getReservedRegs(const MachineFunction &MF) const {
222  // FIXME: avoid re-calculating this everytime.
223  BitVector Reserved(getNumRegs());
224  Reserved.set(ARM::SP);
225  Reserved.set(ARM::PC);
226  if (STI.isTargetDarwin() || hasFP(MF))
227    Reserved.set(FramePtr);
228  // Some targets reserve R9.
229  if (STI.isR9Reserved())
230    Reserved.set(ARM::R9);
231  return Reserved;
232}
233
234bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
235                                        unsigned Reg) const {
236  switch (Reg) {
237  default: break;
238  case ARM::SP:
239  case ARM::PC:
240    return true;
241  case ARM::R7:
242  case ARM::R11:
243    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
244      return true;
245    break;
246  case ARM::R9:
247    return STI.isR9Reserved();
248  }
249
250  return false;
251}
252
253const TargetRegisterClass *
254ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
255                                              const TargetRegisterClass *B,
256                                              unsigned SubIdx) const {
257  switch (SubIdx) {
258  default: return 0;
259  case 1:
260  case 2:
261  case 3:
262  case 4:
263    // S sub-registers.
264    if (A->getSize() == 8) {
265      if (B == &ARM::SPR_8RegClass)
266        return &ARM::DPR_8RegClass;
267      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
268      if (A == &ARM::DPR_8RegClass)
269        return A;
270      return &ARM::DPR_VFP2RegClass;
271    }
272
273    assert(A->getSize() == 16 && "Expecting a Q register class!");
274    if (B == &ARM::SPR_8RegClass)
275      return &ARM::QPR_8RegClass;
276    return &ARM::QPR_VFP2RegClass;
277  case 5:
278  case 6:
279    // D sub-registers.
280    if (B == &ARM::DPR_VFP2RegClass)
281      return &ARM::QPR_VFP2RegClass;
282    if (B == &ARM::DPR_8RegClass)
283      return &ARM::QPR_8RegClass;
284    return A;
285  }
286  return 0;
287}
288
289const TargetRegisterClass *
290ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
291  return ARM::GPRRegisterClass;
292}
293
294/// getAllocationOrder - Returns the register allocation order for a specified
295/// register class in the form of a pair of TargetRegisterClass iterators.
296std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
297ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
298                                        unsigned HintType, unsigned HintReg,
299                                        const MachineFunction &MF) const {
300  // Alternative register allocation orders when favoring even / odd registers
301  // of register pairs.
302
303  // No FP, R9 is available.
304  static const unsigned GPREven1[] = {
305    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
306    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
307    ARM::R9, ARM::R11
308  };
309  static const unsigned GPROdd1[] = {
310    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
311    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
312    ARM::R8, ARM::R10
313  };
314
315  // FP is R7, R9 is available.
316  static const unsigned GPREven2[] = {
317    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
318    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
319    ARM::R9, ARM::R11
320  };
321  static const unsigned GPROdd2[] = {
322    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
323    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
324    ARM::R8, ARM::R10
325  };
326
327  // FP is R11, R9 is available.
328  static const unsigned GPREven3[] = {
329    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
330    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
331    ARM::R9
332  };
333  static const unsigned GPROdd3[] = {
334    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
335    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
336    ARM::R8
337  };
338
339  // No FP, R9 is not available.
340  static const unsigned GPREven4[] = {
341    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
342    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
343    ARM::R11
344  };
345  static const unsigned GPROdd4[] = {
346    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
347    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
348    ARM::R10
349  };
350
351  // FP is R7, R9 is not available.
352  static const unsigned GPREven5[] = {
353    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
354    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
355    ARM::R11
356  };
357  static const unsigned GPROdd5[] = {
358    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
359    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
360    ARM::R10
361  };
362
363  // FP is R11, R9 is not available.
364  static const unsigned GPREven6[] = {
365    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
366    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
367  };
368  static const unsigned GPROdd6[] = {
369    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
370    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
371  };
372
373
374  if (HintType == ARMRI::RegPairEven) {
375    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
376      // It's no longer possible to fulfill this hint. Return the default
377      // allocation order.
378      return std::make_pair(RC->allocation_order_begin(MF),
379                            RC->allocation_order_end(MF));
380
381    if (!STI.isTargetDarwin() && !hasFP(MF)) {
382      if (!STI.isR9Reserved())
383        return std::make_pair(GPREven1,
384                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
385      else
386        return std::make_pair(GPREven4,
387                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
388    } else if (FramePtr == ARM::R7) {
389      if (!STI.isR9Reserved())
390        return std::make_pair(GPREven2,
391                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
392      else
393        return std::make_pair(GPREven5,
394                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
395    } else { // FramePtr == ARM::R11
396      if (!STI.isR9Reserved())
397        return std::make_pair(GPREven3,
398                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
399      else
400        return std::make_pair(GPREven6,
401                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
402    }
403  } else if (HintType == ARMRI::RegPairOdd) {
404    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
405      // It's no longer possible to fulfill this hint. Return the default
406      // allocation order.
407      return std::make_pair(RC->allocation_order_begin(MF),
408                            RC->allocation_order_end(MF));
409
410    if (!STI.isTargetDarwin() && !hasFP(MF)) {
411      if (!STI.isR9Reserved())
412        return std::make_pair(GPROdd1,
413                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
414      else
415        return std::make_pair(GPROdd4,
416                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
417    } else if (FramePtr == ARM::R7) {
418      if (!STI.isR9Reserved())
419        return std::make_pair(GPROdd2,
420                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
421      else
422        return std::make_pair(GPROdd5,
423                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
424    } else { // FramePtr == ARM::R11
425      if (!STI.isR9Reserved())
426        return std::make_pair(GPROdd3,
427                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
428      else
429        return std::make_pair(GPROdd6,
430                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
431    }
432  }
433  return std::make_pair(RC->allocation_order_begin(MF),
434                        RC->allocation_order_end(MF));
435}
436
437/// ResolveRegAllocHint - Resolves the specified register allocation hint
438/// to a physical register. Returns the physical register if it is successful.
439unsigned
440ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
441                                         const MachineFunction &MF) const {
442  if (Reg == 0 || !isPhysicalRegister(Reg))
443    return 0;
444  if (Type == 0)
445    return Reg;
446  else if (Type == (unsigned)ARMRI::RegPairOdd)
447    // Odd register.
448    return getRegisterPairOdd(Reg, MF);
449  else if (Type == (unsigned)ARMRI::RegPairEven)
450    // Even register.
451    return getRegisterPairEven(Reg, MF);
452  return 0;
453}
454
455void
456ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
457                                        MachineFunction &MF) const {
458  MachineRegisterInfo *MRI = &MF.getRegInfo();
459  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
460  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
461       Hint.first == (unsigned)ARMRI::RegPairEven) &&
462      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
463    // If 'Reg' is one of the even / odd register pair and it's now changed
464    // (e.g. coalesced) into a different register. The other register of the
465    // pair allocation hint must be updated to reflect the relationship
466    // change.
467    unsigned OtherReg = Hint.second;
468    Hint = MRI->getRegAllocationHint(OtherReg);
469    if (Hint.second == Reg)
470      // Make sure the pair has not already divorced.
471      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
472  }
473}
474
475/// hasFP - Return true if the specified function should have a dedicated frame
476/// pointer register.  This is true if the function has variable sized allocas
477/// or if frame pointer elimination is disabled.
478///
479bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
480  const MachineFrameInfo *MFI = MF.getFrameInfo();
481  return ((NoFramePointerElim && MFI->hasCalls())||
482          needsStackRealignment(MF) ||
483          MFI->hasVarSizedObjects() ||
484          MFI->isFrameAddressTaken());
485}
486
487bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
488  const MachineFrameInfo *MFI = MF.getFrameInfo();
489  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
490  return (RealignStack &&
491          !AFI->isThumb1OnlyFunction() &&
492          !MFI->hasVarSizedObjects());
493}
494
495bool ARMBaseRegisterInfo::
496needsStackRealignment(const MachineFunction &MF) const {
497  const MachineFrameInfo *MFI = MF.getFrameInfo();
498  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
499  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
500  return (RealignStack &&
501          !AFI->isThumb1OnlyFunction() &&
502          (MFI->getMaxAlignment() > StackAlign) &&
503          !MFI->hasVarSizedObjects());
504}
505
506bool ARMBaseRegisterInfo::
507cannotEliminateFrame(const MachineFunction &MF) const {
508  const MachineFrameInfo *MFI = MF.getFrameInfo();
509  if (NoFramePointerElim && MFI->hasCalls())
510    return true;
511  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
512    || needsStackRealignment(MF);
513}
514
515/// estimateStackSize - Estimate and return the size of the frame.
516static unsigned estimateStackSize(MachineFunction &MF) {
517  const MachineFrameInfo *FFI = MF.getFrameInfo();
518  int Offset = 0;
519  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
520    int FixedOff = -FFI->getObjectOffset(i);
521    if (FixedOff > Offset) Offset = FixedOff;
522  }
523  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
524    if (FFI->isDeadObjectIndex(i))
525      continue;
526    Offset += FFI->getObjectSize(i);
527    unsigned Align = FFI->getObjectAlignment(i);
528    // Adjust to alignment boundary
529    Offset = (Offset+Align-1)/Align*Align;
530  }
531  return (unsigned)Offset;
532}
533
534/// estimateRSStackSizeLimit - Look at each instruction that references stack
535/// frames and return the stack size limit beyond which some of these
536/// instructions will require a scratch register during their expansion later.
537unsigned
538ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
539  unsigned Limit = (1 << 12) - 1;
540  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
541    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
542         I != E; ++I) {
543      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
544        if (!I->getOperand(i).isFI()) continue;
545
546        const TargetInstrDesc &Desc = TII.get(I->getOpcode());
547        unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
548        if (AddrMode == ARMII::AddrMode3 ||
549            AddrMode == ARMII::AddrModeT2_i8)
550          return (1 << 8) - 1;
551
552        if (AddrMode == ARMII::AddrMode5 ||
553            AddrMode == ARMII::AddrModeT2_i8s4)
554          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
555
556        if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
557          // When the stack offset is negative, we will end up using
558          // the i8 instructions instead.
559          return (1 << 8) - 1;
560
561        if (AddrMode == ARMII::AddrMode6)
562          return 0;
563        break; // At most one FI per instruction
564      }
565    }
566  }
567
568  return Limit;
569}
570
571void
572ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
573                                                       RegScavenger *RS) const {
574  // This tells PEI to spill the FP as if it is any other callee-save register
575  // to take advantage the eliminateFrameIndex machinery. This also ensures it
576  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
577  // to combine multiple loads / stores.
578  bool CanEliminateFrame = true;
579  bool CS1Spilled = false;
580  bool LRSpilled = false;
581  unsigned NumGPRSpills = 0;
582  SmallVector<unsigned, 4> UnspilledCS1GPRs;
583  SmallVector<unsigned, 4> UnspilledCS2GPRs;
584  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
585
586  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
587  // scratch register.
588  // FIXME: It will be better just to find spare register here.
589  if (needsStackRealignment(MF) &&
590      AFI->isThumb2Function())
591    MF.getRegInfo().setPhysRegUsed(ARM::R4);
592
593  // Don't spill FP if the frame can be eliminated. This is determined
594  // by scanning the callee-save registers to see if any is used.
595  const unsigned *CSRegs = getCalleeSavedRegs();
596  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
597  for (unsigned i = 0; CSRegs[i]; ++i) {
598    unsigned Reg = CSRegs[i];
599    bool Spilled = false;
600    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
601      AFI->setCSRegisterIsSpilled(Reg);
602      Spilled = true;
603      CanEliminateFrame = false;
604    } else {
605      // Check alias registers too.
606      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
607        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
608          Spilled = true;
609          CanEliminateFrame = false;
610        }
611      }
612    }
613
614    if (CSRegClasses[i] == ARM::GPRRegisterClass ||
615        CSRegClasses[i] == ARM::tGPRRegisterClass) {
616      if (Spilled) {
617        NumGPRSpills++;
618
619        if (!STI.isTargetDarwin()) {
620          if (Reg == ARM::LR)
621            LRSpilled = true;
622          CS1Spilled = true;
623          continue;
624        }
625
626        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
627        switch (Reg) {
628        case ARM::LR:
629          LRSpilled = true;
630          // Fallthrough
631        case ARM::R4:
632        case ARM::R5:
633        case ARM::R6:
634        case ARM::R7:
635          CS1Spilled = true;
636          break;
637        default:
638          break;
639        }
640      } else {
641        if (!STI.isTargetDarwin()) {
642          UnspilledCS1GPRs.push_back(Reg);
643          continue;
644        }
645
646        switch (Reg) {
647        case ARM::R4:
648        case ARM::R5:
649        case ARM::R6:
650        case ARM::R7:
651        case ARM::LR:
652          UnspilledCS1GPRs.push_back(Reg);
653          break;
654        default:
655          UnspilledCS2GPRs.push_back(Reg);
656          break;
657        }
658      }
659    }
660  }
661
662  bool ForceLRSpill = false;
663  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
664    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
665    // Force LR to be spilled if the Thumb function size is > 2048. This enables
666    // use of BL to implement far jump. If it turns out that it's not needed
667    // then the branch fix up path will undo it.
668    if (FnSize >= (1 << 11)) {
669      CanEliminateFrame = false;
670      ForceLRSpill = true;
671    }
672  }
673
674  // If any of the stack slot references may be out of range of an immediate
675  // offset, make sure a register (or a spill slot) is available for the
676  // register scavenger. Note that if we're indexing off the frame pointer, the
677  // effective stack size is 4 bytes larger since the FP points to the stack
678  // slot of the previous FP.
679  bool BigStack = RS &&
680    estimateStackSize(MF) + (hasFP(MF) ? 4 : 0) >= estimateRSStackSizeLimit(MF);
681
682  bool ExtraCSSpill = false;
683  if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
684    AFI->setHasStackFrame(true);
685
686    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
687    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
688    if (!LRSpilled && CS1Spilled) {
689      MF.getRegInfo().setPhysRegUsed(ARM::LR);
690      AFI->setCSRegisterIsSpilled(ARM::LR);
691      NumGPRSpills++;
692      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
693                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
694      ForceLRSpill = false;
695      ExtraCSSpill = true;
696    }
697
698    // Darwin ABI requires FP to point to the stack slot that contains the
699    // previous FP.
700    if (STI.isTargetDarwin() || hasFP(MF)) {
701      MF.getRegInfo().setPhysRegUsed(FramePtr);
702      NumGPRSpills++;
703    }
704
705    // If stack and double are 8-byte aligned and we are spilling an odd number
706    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
707    // the integer and double callee save areas.
708    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
709    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
710      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
711        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
712          unsigned Reg = UnspilledCS1GPRs[i];
713          // Don't spill high register if the function is thumb1
714          if (!AFI->isThumb1OnlyFunction() ||
715              isARMLowRegister(Reg) || Reg == ARM::LR) {
716            MF.getRegInfo().setPhysRegUsed(Reg);
717            AFI->setCSRegisterIsSpilled(Reg);
718            if (!isReservedReg(MF, Reg))
719              ExtraCSSpill = true;
720            break;
721          }
722        }
723      } else if (!UnspilledCS2GPRs.empty() &&
724                 !AFI->isThumb1OnlyFunction()) {
725        unsigned Reg = UnspilledCS2GPRs.front();
726        MF.getRegInfo().setPhysRegUsed(Reg);
727        AFI->setCSRegisterIsSpilled(Reg);
728        if (!isReservedReg(MF, Reg))
729          ExtraCSSpill = true;
730      }
731    }
732
733    // Estimate if we might need to scavenge a register at some point in order
734    // to materialize a stack offset. If so, either spill one additional
735    // callee-saved register or reserve a special spill slot to facilitate
736    // register scavenging. Thumb1 needs a spill slot for stack pointer
737    // adjustments also, even when the frame itself is small.
738    if (BigStack && !ExtraCSSpill) {
739      // If any non-reserved CS register isn't spilled, just spill one or two
740      // extra. That should take care of it!
741      unsigned NumExtras = TargetAlign / 4;
742      SmallVector<unsigned, 2> Extras;
743      while (NumExtras && !UnspilledCS1GPRs.empty()) {
744        unsigned Reg = UnspilledCS1GPRs.back();
745        UnspilledCS1GPRs.pop_back();
746        if (!isReservedReg(MF, Reg)) {
747          Extras.push_back(Reg);
748          NumExtras--;
749        }
750      }
751      // For non-Thumb1 functions, also check for hi-reg CS registers
752      if (!AFI->isThumb1OnlyFunction()) {
753        while (NumExtras && !UnspilledCS2GPRs.empty()) {
754          unsigned Reg = UnspilledCS2GPRs.back();
755          UnspilledCS2GPRs.pop_back();
756          if (!isReservedReg(MF, Reg)) {
757            Extras.push_back(Reg);
758            NumExtras--;
759          }
760        }
761      }
762      if (Extras.size() && NumExtras == 0) {
763        for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
764          MF.getRegInfo().setPhysRegUsed(Extras[i]);
765          AFI->setCSRegisterIsSpilled(Extras[i]);
766        }
767      } else if (!AFI->isThumb1OnlyFunction()) {
768        // note: Thumb1 functions spill to R12, not the stack.  Reserve a slot
769        // closest to SP or frame pointer.
770        const TargetRegisterClass *RC = ARM::GPRRegisterClass;
771        MachineFrameInfo *MFI = MF.getFrameInfo();
772        RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
773                                                           RC->getAlignment(),
774                                                           false));
775      }
776    }
777  }
778
779  if (ForceLRSpill) {
780    MF.getRegInfo().setPhysRegUsed(ARM::LR);
781    AFI->setCSRegisterIsSpilled(ARM::LR);
782    AFI->setLRIsSpilledForFarJump(true);
783  }
784}
785
786unsigned ARMBaseRegisterInfo::getRARegister() const {
787  return ARM::LR;
788}
789
790unsigned
791ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
792  if (STI.isTargetDarwin() || hasFP(MF))
793    return FramePtr;
794  return ARM::SP;
795}
796
797int
798ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
799                                            unsigned &FrameReg) const {
800  const MachineFrameInfo *MFI = MF.getFrameInfo();
801  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
802  int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
803  bool isFixed = MFI->isFixedObjectIndex(FI);
804
805  FrameReg = ARM::SP;
806  if (AFI->isGPRCalleeSavedArea1Frame(FI))
807    Offset -= AFI->getGPRCalleeSavedArea1Offset();
808  else if (AFI->isGPRCalleeSavedArea2Frame(FI))
809    Offset -= AFI->getGPRCalleeSavedArea2Offset();
810  else if (AFI->isDPRCalleeSavedAreaFrame(FI))
811    Offset -= AFI->getDPRCalleeSavedAreaOffset();
812  else if (needsStackRealignment(MF)) {
813    // When dynamically realigning the stack, use the frame pointer for
814    // parameters, and the stack pointer for locals.
815    assert (hasFP(MF) && "dynamic stack realignment without a FP!");
816    if (isFixed) {
817      FrameReg = getFrameRegister(MF);
818      Offset -= AFI->getFramePtrSpillOffset();
819    }
820  } else if (hasFP(MF) && AFI->hasStackFrame()) {
821    if (isFixed || MFI->hasVarSizedObjects()) {
822      // Use frame pointer to reference fixed objects unless this is a
823      // frameless function.
824      FrameReg = getFrameRegister(MF);
825      Offset -= AFI->getFramePtrSpillOffset();
826    } else if (AFI->isThumb2Function()) {
827      // In Thumb2 mode, the negative offset is very limited.
828      int FPOffset = Offset - AFI->getFramePtrSpillOffset();
829      if (FPOffset >= -255 && FPOffset < 0) {
830        FrameReg = getFrameRegister(MF);
831        Offset = FPOffset;
832      }
833    }
834  }
835  return Offset;
836}
837
838
839int
840ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
841                                         int FI) const {
842  unsigned FrameReg;
843  return getFrameIndexReference(MF, FI, FrameReg);
844}
845
846unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
847  llvm_unreachable("What is the exception register");
848  return 0;
849}
850
851unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
852  llvm_unreachable("What is the exception handler register");
853  return 0;
854}
855
856int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
857  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
858}
859
860unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
861                                              const MachineFunction &MF) const {
862  switch (Reg) {
863  default: break;
864  // Return 0 if either register of the pair is a special register.
865  // So no R12, etc.
866  case ARM::R1:
867    return ARM::R0;
868  case ARM::R3:
869    return ARM::R2;
870  case ARM::R5:
871    return ARM::R4;
872  case ARM::R7:
873    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
874  case ARM::R9:
875    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
876  case ARM::R11:
877    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
878
879  case ARM::S1:
880    return ARM::S0;
881  case ARM::S3:
882    return ARM::S2;
883  case ARM::S5:
884    return ARM::S4;
885  case ARM::S7:
886    return ARM::S6;
887  case ARM::S9:
888    return ARM::S8;
889  case ARM::S11:
890    return ARM::S10;
891  case ARM::S13:
892    return ARM::S12;
893  case ARM::S15:
894    return ARM::S14;
895  case ARM::S17:
896    return ARM::S16;
897  case ARM::S19:
898    return ARM::S18;
899  case ARM::S21:
900    return ARM::S20;
901  case ARM::S23:
902    return ARM::S22;
903  case ARM::S25:
904    return ARM::S24;
905  case ARM::S27:
906    return ARM::S26;
907  case ARM::S29:
908    return ARM::S28;
909  case ARM::S31:
910    return ARM::S30;
911
912  case ARM::D1:
913    return ARM::D0;
914  case ARM::D3:
915    return ARM::D2;
916  case ARM::D5:
917    return ARM::D4;
918  case ARM::D7:
919    return ARM::D6;
920  case ARM::D9:
921    return ARM::D8;
922  case ARM::D11:
923    return ARM::D10;
924  case ARM::D13:
925    return ARM::D12;
926  case ARM::D15:
927    return ARM::D14;
928  case ARM::D17:
929    return ARM::D16;
930  case ARM::D19:
931    return ARM::D18;
932  case ARM::D21:
933    return ARM::D20;
934  case ARM::D23:
935    return ARM::D22;
936  case ARM::D25:
937    return ARM::D24;
938  case ARM::D27:
939    return ARM::D26;
940  case ARM::D29:
941    return ARM::D28;
942  case ARM::D31:
943    return ARM::D30;
944  }
945
946  return 0;
947}
948
949unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
950                                             const MachineFunction &MF) const {
951  switch (Reg) {
952  default: break;
953  // Return 0 if either register of the pair is a special register.
954  // So no R12, etc.
955  case ARM::R0:
956    return ARM::R1;
957  case ARM::R2:
958    return ARM::R3;
959  case ARM::R4:
960    return ARM::R5;
961  case ARM::R6:
962    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
963  case ARM::R8:
964    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
965  case ARM::R10:
966    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
967
968  case ARM::S0:
969    return ARM::S1;
970  case ARM::S2:
971    return ARM::S3;
972  case ARM::S4:
973    return ARM::S5;
974  case ARM::S6:
975    return ARM::S7;
976  case ARM::S8:
977    return ARM::S9;
978  case ARM::S10:
979    return ARM::S11;
980  case ARM::S12:
981    return ARM::S13;
982  case ARM::S14:
983    return ARM::S15;
984  case ARM::S16:
985    return ARM::S17;
986  case ARM::S18:
987    return ARM::S19;
988  case ARM::S20:
989    return ARM::S21;
990  case ARM::S22:
991    return ARM::S23;
992  case ARM::S24:
993    return ARM::S25;
994  case ARM::S26:
995    return ARM::S27;
996  case ARM::S28:
997    return ARM::S29;
998  case ARM::S30:
999    return ARM::S31;
1000
1001  case ARM::D0:
1002    return ARM::D1;
1003  case ARM::D2:
1004    return ARM::D3;
1005  case ARM::D4:
1006    return ARM::D5;
1007  case ARM::D6:
1008    return ARM::D7;
1009  case ARM::D8:
1010    return ARM::D9;
1011  case ARM::D10:
1012    return ARM::D11;
1013  case ARM::D12:
1014    return ARM::D13;
1015  case ARM::D14:
1016    return ARM::D15;
1017  case ARM::D16:
1018    return ARM::D17;
1019  case ARM::D18:
1020    return ARM::D19;
1021  case ARM::D20:
1022    return ARM::D21;
1023  case ARM::D22:
1024    return ARM::D23;
1025  case ARM::D24:
1026    return ARM::D25;
1027  case ARM::D26:
1028    return ARM::D27;
1029  case ARM::D28:
1030    return ARM::D29;
1031  case ARM::D30:
1032    return ARM::D31;
1033  }
1034
1035  return 0;
1036}
1037
1038/// emitLoadConstPool - Emits a load from constpool to materialize the
1039/// specified immediate.
1040void ARMBaseRegisterInfo::
1041emitLoadConstPool(MachineBasicBlock &MBB,
1042                  MachineBasicBlock::iterator &MBBI,
1043                  DebugLoc dl,
1044                  unsigned DestReg, unsigned SubIdx, int Val,
1045                  ARMCC::CondCodes Pred,
1046                  unsigned PredReg) const {
1047  MachineFunction &MF = *MBB.getParent();
1048  MachineConstantPool *ConstantPool = MF.getConstantPool();
1049  Constant *C =
1050        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1051  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1052
1053  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1054    .addReg(DestReg, getDefRegState(true), SubIdx)
1055    .addConstantPoolIndex(Idx)
1056    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1057}
1058
1059bool ARMBaseRegisterInfo::
1060requiresRegisterScavenging(const MachineFunction &MF) const {
1061  return true;
1062}
1063
1064bool ARMBaseRegisterInfo::
1065requiresFrameIndexScavenging(const MachineFunction &MF) const {
1066  return true;
1067}
1068
1069// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1070// not required, we reserve argument space for call sites in the function
1071// immediately on entry to the current function. This eliminates the need for
1072// add/sub sp brackets around call sites. Returns true if the call frame is
1073// included as part of the stack frame.
1074bool ARMBaseRegisterInfo::
1075hasReservedCallFrame(MachineFunction &MF) const {
1076  const MachineFrameInfo *FFI = MF.getFrameInfo();
1077  unsigned CFSize = FFI->getMaxCallFrameSize();
1078  // It's not always a good idea to include the call frame as part of the
1079  // stack frame. ARM (especially Thumb) has small immediate offset to
1080  // address the stack frame. So a large call frame can cause poor codegen
1081  // and may even makes it impossible to scavenge a register.
1082  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
1083    return false;
1084
1085  return !MF.getFrameInfo()->hasVarSizedObjects();
1086}
1087
1088// canSimplifyCallFramePseudos - If there is a reserved call frame, the
1089// call frame pseudos can be simplified. Unlike most targets, having a FP
1090// is not sufficient here since we still may reference some objects via SP
1091// even when FP is available in Thumb2 mode.
1092bool ARMBaseRegisterInfo::
1093canSimplifyCallFramePseudos(MachineFunction &MF) const {
1094  return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1095}
1096
1097static void
1098emitSPUpdate(bool isARM,
1099             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1100             DebugLoc dl, const ARMBaseInstrInfo &TII,
1101             int NumBytes,
1102             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1103  if (isARM)
1104    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1105                            Pred, PredReg, TII);
1106  else
1107    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1108                           Pred, PredReg, TII);
1109}
1110
1111
1112void ARMBaseRegisterInfo::
1113eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1114                              MachineBasicBlock::iterator I) const {
1115  if (!hasReservedCallFrame(MF)) {
1116    // If we have alloca, convert as follows:
1117    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1118    // ADJCALLSTACKUP   -> add, sp, sp, amount
1119    MachineInstr *Old = I;
1120    DebugLoc dl = Old->getDebugLoc();
1121    unsigned Amount = Old->getOperand(0).getImm();
1122    if (Amount != 0) {
1123      // We need to keep the stack aligned properly.  To do this, we round the
1124      // amount of space needed for the outgoing arguments up to the next
1125      // alignment boundary.
1126      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1127      Amount = (Amount+Align-1)/Align*Align;
1128
1129      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1130      assert(!AFI->isThumb1OnlyFunction() &&
1131             "This eliminateCallFramePseudoInstr does not support Thumb1!");
1132      bool isARM = !AFI->isThumbFunction();
1133
1134      // Replace the pseudo instruction with a new instruction...
1135      unsigned Opc = Old->getOpcode();
1136      int PIdx = Old->findFirstPredOperandIdx();
1137      ARMCC::CondCodes Pred = (PIdx == -1)
1138        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1139      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1140        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1141        unsigned PredReg = Old->getOperand(2).getReg();
1142        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1143      } else {
1144        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1145        unsigned PredReg = Old->getOperand(3).getReg();
1146        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1147        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1148      }
1149    }
1150  }
1151  MBB.erase(I);
1152}
1153
1154unsigned
1155ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1156                                         int SPAdj, int *Value,
1157                                         RegScavenger *RS) const {
1158  unsigned i = 0;
1159  MachineInstr &MI = *II;
1160  MachineBasicBlock &MBB = *MI.getParent();
1161  MachineFunction &MF = *MBB.getParent();
1162  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1163  assert(!AFI->isThumb1OnlyFunction() &&
1164         "This eliminateFrameIndex does not support Thumb1!");
1165
1166  while (!MI.getOperand(i).isFI()) {
1167    ++i;
1168    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1169  }
1170
1171  int FrameIndex = MI.getOperand(i).getIndex();
1172  unsigned FrameReg;
1173
1174  int Offset = getFrameIndexReference(MF, FrameIndex, FrameReg);
1175  if (FrameReg != ARM::SP)
1176    SPAdj = 0;
1177  Offset += SPAdj;
1178
1179  // Modify MI as necessary to handle as much of 'Offset' as possible
1180  bool Done = false;
1181  if (!AFI->isThumbFunction())
1182    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1183  else {
1184    assert(AFI->isThumb2Function());
1185    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1186  }
1187  if (Done)
1188    return 0;
1189
1190  // If we get here, the immediate doesn't fit into the instruction.  We folded
1191  // as much as possible above, handle the rest, providing a register that is
1192  // SP+LargeImm.
1193  assert((Offset ||
1194          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1195          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1196         "This code isn't needed if offset already handled!");
1197
1198  unsigned ScratchReg = 0;
1199  int PIdx = MI.findFirstPredOperandIdx();
1200  ARMCC::CondCodes Pred = (PIdx == -1)
1201    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1202  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1203  if (Offset == 0)
1204    // Must be addrmode4/6.
1205    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1206  else {
1207    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1208    if (Value) *Value = Offset;
1209    if (!AFI->isThumbFunction())
1210      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1211                              Offset, Pred, PredReg, TII);
1212    else {
1213      assert(AFI->isThumb2Function());
1214      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1215                             Offset, Pred, PredReg, TII);
1216    }
1217    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1218    if (!ReuseFrameIndexVals)
1219      ScratchReg = 0;
1220  }
1221  return ScratchReg;
1222}
1223
1224/// Move iterator past the next bunch of callee save load / store ops for
1225/// the particular spill area (1: integer area 1, 2: integer area 2,
1226/// 3: fp area, 0: don't care).
1227static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1228                                   MachineBasicBlock::iterator &MBBI,
1229                                   int Opc1, int Opc2, unsigned Area,
1230                                   const ARMSubtarget &STI) {
1231  while (MBBI != MBB.end() &&
1232         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1233         MBBI->getOperand(1).isFI()) {
1234    if (Area != 0) {
1235      bool Done = false;
1236      unsigned Category = 0;
1237      switch (MBBI->getOperand(0).getReg()) {
1238      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1239      case ARM::LR:
1240        Category = 1;
1241        break;
1242      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1243        Category = STI.isTargetDarwin() ? 2 : 1;
1244        break;
1245      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1246      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1247        Category = 3;
1248        break;
1249      default:
1250        Done = true;
1251        break;
1252      }
1253      if (Done || Category != Area)
1254        break;
1255    }
1256
1257    ++MBBI;
1258  }
1259}
1260
1261void ARMBaseRegisterInfo::
1262emitPrologue(MachineFunction &MF) const {
1263  MachineBasicBlock &MBB = MF.front();
1264  MachineBasicBlock::iterator MBBI = MBB.begin();
1265  MachineFrameInfo  *MFI = MF.getFrameInfo();
1266  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1267  assert(!AFI->isThumb1OnlyFunction() &&
1268         "This emitPrologue does not support Thumb1!");
1269  bool isARM = !AFI->isThumbFunction();
1270  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1271  unsigned NumBytes = MFI->getStackSize();
1272  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1273  DebugLoc dl = (MBBI != MBB.end() ?
1274                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1275
1276  // Determine the sizes of each callee-save spill areas and record which frame
1277  // belongs to which callee-save spill areas.
1278  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1279  int FramePtrSpillFI = 0;
1280
1281  // Allocate the vararg register save area. This is not counted in NumBytes.
1282  if (VARegSaveSize)
1283    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1284
1285  if (!AFI->hasStackFrame()) {
1286    if (NumBytes != 0)
1287      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1288    return;
1289  }
1290
1291  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1292    unsigned Reg = CSI[i].getReg();
1293    int FI = CSI[i].getFrameIdx();
1294    switch (Reg) {
1295    case ARM::R4:
1296    case ARM::R5:
1297    case ARM::R6:
1298    case ARM::R7:
1299    case ARM::LR:
1300      if (Reg == FramePtr)
1301        FramePtrSpillFI = FI;
1302      AFI->addGPRCalleeSavedArea1Frame(FI);
1303      GPRCS1Size += 4;
1304      break;
1305    case ARM::R8:
1306    case ARM::R9:
1307    case ARM::R10:
1308    case ARM::R11:
1309      if (Reg == FramePtr)
1310        FramePtrSpillFI = FI;
1311      if (STI.isTargetDarwin()) {
1312        AFI->addGPRCalleeSavedArea2Frame(FI);
1313        GPRCS2Size += 4;
1314      } else {
1315        AFI->addGPRCalleeSavedArea1Frame(FI);
1316        GPRCS1Size += 4;
1317      }
1318      break;
1319    default:
1320      AFI->addDPRCalleeSavedAreaFrame(FI);
1321      DPRCSSize += 8;
1322    }
1323  }
1324
1325  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1326  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1327  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1328
1329  // Set FP to point to the stack slot that contains the previous FP.
1330  // For Darwin, FP is R7, which has now been stored in spill area 1.
1331  // Otherwise, if this is not Darwin, all the callee-saved registers go
1332  // into spill area 1, including the FP in R11.  In either case, it is
1333  // now safe to emit this assignment.
1334  if (STI.isTargetDarwin() || hasFP(MF)) {
1335    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1336    MachineInstrBuilder MIB =
1337      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1338      .addFrameIndex(FramePtrSpillFI).addImm(0);
1339    AddDefaultCC(AddDefaultPred(MIB));
1340  }
1341
1342  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1343  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1344
1345  // Build the new SUBri to adjust SP for FP callee-save spill area.
1346  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1347  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1348
1349  // Determine starting offsets of spill areas.
1350  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1351  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1352  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1353  if (STI.isTargetDarwin() || hasFP(MF))
1354    AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1355                                NumBytes);
1356  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1357  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1358  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1359
1360  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1361  NumBytes = DPRCSOffset;
1362  if (NumBytes) {
1363    // Adjust SP after all the callee-save spills.
1364    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1365  }
1366
1367  if (STI.isTargetELF() && hasFP(MF)) {
1368    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1369                             AFI->getFramePtrSpillOffset());
1370  }
1371
1372  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1373  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1374  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1375
1376  // If we need dynamic stack realignment, do it here.
1377  if (needsStackRealignment(MF)) {
1378    unsigned MaxAlign = MFI->getMaxAlignment();
1379    assert (!AFI->isThumb1OnlyFunction());
1380    if (!AFI->isThumbFunction()) {
1381      // Emit bic sp, sp, MaxAlign
1382      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1383                                          TII.get(ARM::BICri), ARM::SP)
1384                                  .addReg(ARM::SP, RegState::Kill)
1385                                  .addImm(MaxAlign-1)));
1386    } else {
1387      // We cannot use sp as source/dest register here, thus we're emitting the
1388      // following sequence:
1389      // mov r4, sp
1390      // bic r4, r4, MaxAlign
1391      // mov sp, r4
1392      // FIXME: It will be better just to find spare register here.
1393      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1394        .addReg(ARM::SP, RegState::Kill);
1395      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1396                                          TII.get(ARM::t2BICri), ARM::R4)
1397                                  .addReg(ARM::R4, RegState::Kill)
1398                                  .addImm(MaxAlign-1)));
1399      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1400        .addReg(ARM::R4, RegState::Kill);
1401    }
1402  }
1403}
1404
1405static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1406  for (unsigned i = 0; CSRegs[i]; ++i)
1407    if (Reg == CSRegs[i])
1408      return true;
1409  return false;
1410}
1411
1412static bool isCSRestore(MachineInstr *MI,
1413                        const ARMBaseInstrInfo &TII,
1414                        const unsigned *CSRegs) {
1415  return ((MI->getOpcode() == (int)ARM::VLDRD ||
1416           MI->getOpcode() == (int)ARM::LDR ||
1417           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1418          MI->getOperand(1).isFI() &&
1419          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1420}
1421
1422void ARMBaseRegisterInfo::
1423emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1424  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1425  assert(MBBI->getDesc().isReturn() &&
1426         "Can only insert epilog into returning blocks");
1427  DebugLoc dl = MBBI->getDebugLoc();
1428  MachineFrameInfo *MFI = MF.getFrameInfo();
1429  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1430  assert(!AFI->isThumb1OnlyFunction() &&
1431         "This emitEpilogue does not support Thumb1!");
1432  bool isARM = !AFI->isThumbFunction();
1433
1434  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1435  int NumBytes = (int)MFI->getStackSize();
1436
1437  if (!AFI->hasStackFrame()) {
1438    if (NumBytes != 0)
1439      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1440  } else {
1441    // Unwind MBBI to point to first LDR / VLDRD.
1442    const unsigned *CSRegs = getCalleeSavedRegs();
1443    if (MBBI != MBB.begin()) {
1444      do
1445        --MBBI;
1446      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1447      if (!isCSRestore(MBBI, TII, CSRegs))
1448        ++MBBI;
1449    }
1450
1451    // Move SP to start of FP callee save spill area.
1452    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1453                 AFI->getGPRCalleeSavedArea2Size() +
1454                 AFI->getDPRCalleeSavedAreaSize());
1455
1456    // Darwin ABI requires FP to point to the stack slot that contains the
1457    // previous FP.
1458    bool HasFP = hasFP(MF);
1459    if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1460      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1461      // Reset SP based on frame pointer only if the stack frame extends beyond
1462      // frame pointer stack slot or target is ELF and the function has FP.
1463      if (HasFP ||
1464          AFI->getGPRCalleeSavedArea2Size() ||
1465          AFI->getDPRCalleeSavedAreaSize()  ||
1466          AFI->getDPRCalleeSavedAreaOffset()) {
1467        if (NumBytes) {
1468          if (isARM)
1469            emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1470                                    ARMCC::AL, 0, TII);
1471          else
1472            emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1473                                    ARMCC::AL, 0, TII);
1474        } else {
1475          // Thumb2 or ARM.
1476          if (isARM)
1477            BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1478              .addReg(FramePtr)
1479              .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1480          else
1481            BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1482              .addReg(FramePtr);
1483        }
1484      }
1485    } else if (NumBytes)
1486      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1487
1488    // Move SP to start of integer callee save spill area 2.
1489    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1490    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1491
1492    // Move SP to start of integer callee save spill area 1.
1493    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1494    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1495
1496    // Move SP to SP upon entry to the function.
1497    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1498    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1499  }
1500
1501  if (VARegSaveSize)
1502    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1503}
1504
1505#include "ARMGenRegisterInfo.inc"
1506