ARMBaseRegisterInfo.cpp revision 202375 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41using namespace llvm;
42
43static cl::opt<bool>
44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45          cl::desc("Reuse repeated frame index values"));
46
47unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
48                                                   bool *isSPVFP) {
49  if (isSPVFP)
50    *isSPVFP = false;
51
52  using namespace ARM;
53  switch (RegEnum) {
54  default:
55    llvm_unreachable("Unknown ARM register!");
56  case R0:  case D0:  case Q0:  return 0;
57  case R1:  case D1:  case Q1:  return 1;
58  case R2:  case D2:  case Q2:  return 2;
59  case R3:  case D3:  case Q3:  return 3;
60  case R4:  case D4:  case Q4:  return 4;
61  case R5:  case D5:  case Q5:  return 5;
62  case R6:  case D6:  case Q6:  return 6;
63  case R7:  case D7:  case Q7:  return 7;
64  case R8:  case D8:  case Q8:  return 8;
65  case R9:  case D9:  case Q9:  return 9;
66  case R10: case D10: case Q10: return 10;
67  case R11: case D11: case Q11: return 11;
68  case R12: case D12: case Q12: return 12;
69  case SP:  case D13: case Q13: return 13;
70  case LR:  case D14: case Q14: return 14;
71  case PC:  case D15: case Q15: return 15;
72
73  case D16: return 16;
74  case D17: return 17;
75  case D18: return 18;
76  case D19: return 19;
77  case D20: return 20;
78  case D21: return 21;
79  case D22: return 22;
80  case D23: return 23;
81  case D24: return 24;
82  case D25: return 25;
83  case D26: return 27;
84  case D27: return 27;
85  case D28: return 28;
86  case D29: return 29;
87  case D30: return 30;
88  case D31: return 31;
89
90  case S0: case S1: case S2: case S3:
91  case S4: case S5: case S6: case S7:
92  case S8: case S9: case S10: case S11:
93  case S12: case S13: case S14: case S15:
94  case S16: case S17: case S18: case S19:
95  case S20: case S21: case S22: case S23:
96  case S24: case S25: case S26: case S27:
97  case S28: case S29: case S30: case S31: {
98    if (isSPVFP)
99      *isSPVFP = true;
100    switch (RegEnum) {
101    default: return 0; // Avoid compile time warning.
102    case S0: return 0;
103    case S1: return 1;
104    case S2: return 2;
105    case S3: return 3;
106    case S4: return 4;
107    case S5: return 5;
108    case S6: return 6;
109    case S7: return 7;
110    case S8: return 8;
111    case S9: return 9;
112    case S10: return 10;
113    case S11: return 11;
114    case S12: return 12;
115    case S13: return 13;
116    case S14: return 14;
117    case S15: return 15;
118    case S16: return 16;
119    case S17: return 17;
120    case S18: return 18;
121    case S19: return 19;
122    case S20: return 20;
123    case S21: return 21;
124    case S22: return 22;
125    case S23: return 23;
126    case S24: return 24;
127    case S25: return 25;
128    case S26: return 26;
129    case S27: return 27;
130    case S28: return 28;
131    case S29: return 29;
132    case S30: return 30;
133    case S31: return 31;
134    }
135  }
136  }
137}
138
139ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
140                                         const ARMSubtarget &sti)
141  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
142    TII(tii), STI(sti),
143    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
144}
145
146const unsigned*
147ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
148  static const unsigned CalleeSavedRegs[] = {
149    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
150    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
151
152    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
153    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
154    0
155  };
156
157  static const unsigned DarwinCalleeSavedRegs[] = {
158    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
159    // register.
160    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
161    ARM::R11, ARM::R10, ARM::R8,
162
163    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
164    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
165    0
166  };
167  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
168}
169
170const TargetRegisterClass* const *
171ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
172  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
173    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
174    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
175    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
176
177    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
178    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
179    0
180  };
181
182  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
183    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
184    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
185    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
186
187    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
188    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
189    0
190  };
191
192  static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
193    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
194    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
195    &ARM::GPRRegClass, &ARM::GPRRegClass,
196
197    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
198    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
199    0
200  };
201
202  static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
203    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
204    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
205    &ARM::GPRRegClass,  &ARM::GPRRegClass,
206
207    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
208    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
209    0
210  };
211
212  if (STI.isThumb1Only()) {
213    return STI.isTargetDarwin()
214      ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
215  }
216  return STI.isTargetDarwin()
217    ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
218}
219
220BitVector ARMBaseRegisterInfo::
221getReservedRegs(const MachineFunction &MF) const {
222  // FIXME: avoid re-calculating this everytime.
223  BitVector Reserved(getNumRegs());
224  Reserved.set(ARM::SP);
225  Reserved.set(ARM::PC);
226  if (STI.isTargetDarwin() || hasFP(MF))
227    Reserved.set(FramePtr);
228  // Some targets reserve R9.
229  if (STI.isR9Reserved())
230    Reserved.set(ARM::R9);
231  return Reserved;
232}
233
234bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
235                                        unsigned Reg) const {
236  switch (Reg) {
237  default: break;
238  case ARM::SP:
239  case ARM::PC:
240    return true;
241  case ARM::R7:
242  case ARM::R11:
243    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
244      return true;
245    break;
246  case ARM::R9:
247    return STI.isR9Reserved();
248  }
249
250  return false;
251}
252
253const TargetRegisterClass *
254ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
255                                              const TargetRegisterClass *B,
256                                              unsigned SubIdx) const {
257  switch (SubIdx) {
258  default: return 0;
259  case 1:
260  case 2:
261  case 3:
262  case 4:
263    // S sub-registers.
264    if (A->getSize() == 8) {
265      if (B == &ARM::SPR_8RegClass)
266        return &ARM::DPR_8RegClass;
267      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
268      if (A == &ARM::DPR_8RegClass)
269        return A;
270      return &ARM::DPR_VFP2RegClass;
271    }
272
273    assert(A->getSize() == 16 && "Expecting a Q register class!");
274    if (B == &ARM::SPR_8RegClass)
275      return &ARM::QPR_8RegClass;
276    return &ARM::QPR_VFP2RegClass;
277  case 5:
278  case 6:
279    // D sub-registers.
280    if (B == &ARM::DPR_VFP2RegClass)
281      return &ARM::QPR_VFP2RegClass;
282    if (B == &ARM::DPR_8RegClass)
283      return &ARM::QPR_8RegClass;
284    return A;
285  }
286  return 0;
287}
288
289const TargetRegisterClass *
290ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
291  return ARM::GPRRegisterClass;
292}
293
294/// getAllocationOrder - Returns the register allocation order for a specified
295/// register class in the form of a pair of TargetRegisterClass iterators.
296std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
297ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
298                                        unsigned HintType, unsigned HintReg,
299                                        const MachineFunction &MF) const {
300  // Alternative register allocation orders when favoring even / odd registers
301  // of register pairs.
302
303  // No FP, R9 is available.
304  static const unsigned GPREven1[] = {
305    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
306    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
307    ARM::R9, ARM::R11
308  };
309  static const unsigned GPROdd1[] = {
310    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
311    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
312    ARM::R8, ARM::R10
313  };
314
315  // FP is R7, R9 is available.
316  static const unsigned GPREven2[] = {
317    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
318    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
319    ARM::R9, ARM::R11
320  };
321  static const unsigned GPROdd2[] = {
322    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
323    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
324    ARM::R8, ARM::R10
325  };
326
327  // FP is R11, R9 is available.
328  static const unsigned GPREven3[] = {
329    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
330    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
331    ARM::R9
332  };
333  static const unsigned GPROdd3[] = {
334    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
335    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
336    ARM::R8
337  };
338
339  // No FP, R9 is not available.
340  static const unsigned GPREven4[] = {
341    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
342    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
343    ARM::R11
344  };
345  static const unsigned GPROdd4[] = {
346    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
347    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
348    ARM::R10
349  };
350
351  // FP is R7, R9 is not available.
352  static const unsigned GPREven5[] = {
353    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
354    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
355    ARM::R11
356  };
357  static const unsigned GPROdd5[] = {
358    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
359    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
360    ARM::R10
361  };
362
363  // FP is R11, R9 is not available.
364  static const unsigned GPREven6[] = {
365    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
366    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
367  };
368  static const unsigned GPROdd6[] = {
369    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
370    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
371  };
372
373
374  if (HintType == ARMRI::RegPairEven) {
375    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
376      // It's no longer possible to fulfill this hint. Return the default
377      // allocation order.
378      return std::make_pair(RC->allocation_order_begin(MF),
379                            RC->allocation_order_end(MF));
380
381    if (!STI.isTargetDarwin() && !hasFP(MF)) {
382      if (!STI.isR9Reserved())
383        return std::make_pair(GPREven1,
384                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
385      else
386        return std::make_pair(GPREven4,
387                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
388    } else if (FramePtr == ARM::R7) {
389      if (!STI.isR9Reserved())
390        return std::make_pair(GPREven2,
391                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
392      else
393        return std::make_pair(GPREven5,
394                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
395    } else { // FramePtr == ARM::R11
396      if (!STI.isR9Reserved())
397        return std::make_pair(GPREven3,
398                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
399      else
400        return std::make_pair(GPREven6,
401                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
402    }
403  } else if (HintType == ARMRI::RegPairOdd) {
404    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
405      // It's no longer possible to fulfill this hint. Return the default
406      // allocation order.
407      return std::make_pair(RC->allocation_order_begin(MF),
408                            RC->allocation_order_end(MF));
409
410    if (!STI.isTargetDarwin() && !hasFP(MF)) {
411      if (!STI.isR9Reserved())
412        return std::make_pair(GPROdd1,
413                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
414      else
415        return std::make_pair(GPROdd4,
416                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
417    } else if (FramePtr == ARM::R7) {
418      if (!STI.isR9Reserved())
419        return std::make_pair(GPROdd2,
420                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
421      else
422        return std::make_pair(GPROdd5,
423                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
424    } else { // FramePtr == ARM::R11
425      if (!STI.isR9Reserved())
426        return std::make_pair(GPROdd3,
427                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
428      else
429        return std::make_pair(GPROdd6,
430                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
431    }
432  }
433  return std::make_pair(RC->allocation_order_begin(MF),
434                        RC->allocation_order_end(MF));
435}
436
437/// ResolveRegAllocHint - Resolves the specified register allocation hint
438/// to a physical register. Returns the physical register if it is successful.
439unsigned
440ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
441                                         const MachineFunction &MF) const {
442  if (Reg == 0 || !isPhysicalRegister(Reg))
443    return 0;
444  if (Type == 0)
445    return Reg;
446  else if (Type == (unsigned)ARMRI::RegPairOdd)
447    // Odd register.
448    return getRegisterPairOdd(Reg, MF);
449  else if (Type == (unsigned)ARMRI::RegPairEven)
450    // Even register.
451    return getRegisterPairEven(Reg, MF);
452  return 0;
453}
454
455void
456ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
457                                        MachineFunction &MF) const {
458  MachineRegisterInfo *MRI = &MF.getRegInfo();
459  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
460  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
461       Hint.first == (unsigned)ARMRI::RegPairEven) &&
462      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
463    // If 'Reg' is one of the even / odd register pair and it's now changed
464    // (e.g. coalesced) into a different register. The other register of the
465    // pair allocation hint must be updated to reflect the relationship
466    // change.
467    unsigned OtherReg = Hint.second;
468    Hint = MRI->getRegAllocationHint(OtherReg);
469    if (Hint.second == Reg)
470      // Make sure the pair has not already divorced.
471      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
472  }
473}
474
475/// hasFP - Return true if the specified function should have a dedicated frame
476/// pointer register.  This is true if the function has variable sized allocas
477/// or if frame pointer elimination is disabled.
478///
479bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
480  const MachineFrameInfo *MFI = MF.getFrameInfo();
481  return (NoFramePointerElim ||
482          needsStackRealignment(MF) ||
483          MFI->hasVarSizedObjects() ||
484          MFI->isFrameAddressTaken());
485}
486
487bool ARMBaseRegisterInfo::
488needsStackRealignment(const MachineFunction &MF) const {
489  const MachineFrameInfo *MFI = MF.getFrameInfo();
490  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
491  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
492  return (RealignStack &&
493          !AFI->isThumb1OnlyFunction() &&
494          (MFI->getMaxAlignment() > StackAlign) &&
495          !MFI->hasVarSizedObjects());
496}
497
498bool ARMBaseRegisterInfo::
499cannotEliminateFrame(const MachineFunction &MF) const {
500  const MachineFrameInfo *MFI = MF.getFrameInfo();
501  if (NoFramePointerElim && MFI->hasCalls())
502    return true;
503  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
504    || needsStackRealignment(MF);
505}
506
507/// estimateStackSize - Estimate and return the size of the frame.
508static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
509  const MachineFrameInfo *FFI = MF.getFrameInfo();
510  int Offset = 0;
511  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
512    int FixedOff = -FFI->getObjectOffset(i);
513    if (FixedOff > Offset) Offset = FixedOff;
514  }
515  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
516    if (FFI->isDeadObjectIndex(i))
517      continue;
518    Offset += FFI->getObjectSize(i);
519    unsigned Align = FFI->getObjectAlignment(i);
520    // Adjust to alignment boundary
521    Offset = (Offset+Align-1)/Align*Align;
522  }
523  return (unsigned)Offset;
524}
525
526/// estimateRSStackSizeLimit - Look at each instruction that references stack
527/// frames and return the stack size limit beyond which some of these
528/// instructions will require a scratch register during their expansion later.
529unsigned
530ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
531  unsigned Limit = (1 << 12) - 1;
532  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
533    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
534         I != E; ++I) {
535      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
536        if (!I->getOperand(i).isFI()) continue;
537
538        const TargetInstrDesc &Desc = TII.get(I->getOpcode());
539        unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
540        if (AddrMode == ARMII::AddrMode3 ||
541            AddrMode == ARMII::AddrModeT2_i8)
542          return (1 << 8) - 1;
543
544        if (AddrMode == ARMII::AddrMode5 ||
545            AddrMode == ARMII::AddrModeT2_i8s4)
546          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
547
548        if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
549          // When the stack offset is negative, we will end up using
550          // the i8 instructions instead.
551          return (1 << 8) - 1;
552
553        if (AddrMode == ARMII::AddrMode6)
554          return 0;
555        break; // At most one FI per instruction
556      }
557    }
558  }
559
560  return Limit;
561}
562
563void
564ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
565                                                       RegScavenger *RS) const {
566  // This tells PEI to spill the FP as if it is any other callee-save register
567  // to take advantage the eliminateFrameIndex machinery. This also ensures it
568  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
569  // to combine multiple loads / stores.
570  bool CanEliminateFrame = true;
571  bool CS1Spilled = false;
572  bool LRSpilled = false;
573  unsigned NumGPRSpills = 0;
574  SmallVector<unsigned, 4> UnspilledCS1GPRs;
575  SmallVector<unsigned, 4> UnspilledCS2GPRs;
576  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
577
578
579  // Calculate and set max stack object alignment early, so we can decide
580  // whether we will need stack realignment (and thus FP).
581  if (RealignStack) {
582    MachineFrameInfo *MFI = MF.getFrameInfo();
583    MFI->calculateMaxStackAlignment();
584  }
585
586  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
587  // scratch register.
588  // FIXME: It will be better just to find spare register here.
589  if (needsStackRealignment(MF) &&
590      AFI->isThumb2Function())
591    MF.getRegInfo().setPhysRegUsed(ARM::R4);
592
593  // Don't spill FP if the frame can be eliminated. This is determined
594  // by scanning the callee-save registers to see if any is used.
595  const unsigned *CSRegs = getCalleeSavedRegs();
596  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
597  for (unsigned i = 0; CSRegs[i]; ++i) {
598    unsigned Reg = CSRegs[i];
599    bool Spilled = false;
600    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
601      AFI->setCSRegisterIsSpilled(Reg);
602      Spilled = true;
603      CanEliminateFrame = false;
604    } else {
605      // Check alias registers too.
606      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
607        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
608          Spilled = true;
609          CanEliminateFrame = false;
610        }
611      }
612    }
613
614    if (CSRegClasses[i] == ARM::GPRRegisterClass ||
615        CSRegClasses[i] == ARM::tGPRRegisterClass) {
616      if (Spilled) {
617        NumGPRSpills++;
618
619        if (!STI.isTargetDarwin()) {
620          if (Reg == ARM::LR)
621            LRSpilled = true;
622          CS1Spilled = true;
623          continue;
624        }
625
626        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
627        switch (Reg) {
628        case ARM::LR:
629          LRSpilled = true;
630          // Fallthrough
631        case ARM::R4:
632        case ARM::R5:
633        case ARM::R6:
634        case ARM::R7:
635          CS1Spilled = true;
636          break;
637        default:
638          break;
639        }
640      } else {
641        if (!STI.isTargetDarwin()) {
642          UnspilledCS1GPRs.push_back(Reg);
643          continue;
644        }
645
646        switch (Reg) {
647        case ARM::R4:
648        case ARM::R5:
649        case ARM::R6:
650        case ARM::R7:
651        case ARM::LR:
652          UnspilledCS1GPRs.push_back(Reg);
653          break;
654        default:
655          UnspilledCS2GPRs.push_back(Reg);
656          break;
657        }
658      }
659    }
660  }
661
662  bool ForceLRSpill = false;
663  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
664    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
665    // Force LR to be spilled if the Thumb function size is > 2048. This enables
666    // use of BL to implement far jump. If it turns out that it's not needed
667    // then the branch fix up path will undo it.
668    if (FnSize >= (1 << 11)) {
669      CanEliminateFrame = false;
670      ForceLRSpill = true;
671    }
672  }
673
674  bool ExtraCSSpill = false;
675  if (!CanEliminateFrame || cannotEliminateFrame(MF)) {
676    AFI->setHasStackFrame(true);
677
678    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
679    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
680    if (!LRSpilled && CS1Spilled) {
681      MF.getRegInfo().setPhysRegUsed(ARM::LR);
682      AFI->setCSRegisterIsSpilled(ARM::LR);
683      NumGPRSpills++;
684      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
685                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
686      ForceLRSpill = false;
687      ExtraCSSpill = true;
688    }
689
690    // Darwin ABI requires FP to point to the stack slot that contains the
691    // previous FP.
692    if (STI.isTargetDarwin() || hasFP(MF)) {
693      MF.getRegInfo().setPhysRegUsed(FramePtr);
694      NumGPRSpills++;
695    }
696
697    // If stack and double are 8-byte aligned and we are spilling an odd number
698    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
699    // the integer and double callee save areas.
700    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
701    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
702      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
703        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
704          unsigned Reg = UnspilledCS1GPRs[i];
705          // Don't spill high register if the function is thumb1
706          if (!AFI->isThumb1OnlyFunction() ||
707              isARMLowRegister(Reg) || Reg == ARM::LR) {
708            MF.getRegInfo().setPhysRegUsed(Reg);
709            AFI->setCSRegisterIsSpilled(Reg);
710            if (!isReservedReg(MF, Reg))
711              ExtraCSSpill = true;
712            break;
713          }
714        }
715      } else if (!UnspilledCS2GPRs.empty() &&
716                 !AFI->isThumb1OnlyFunction()) {
717        unsigned Reg = UnspilledCS2GPRs.front();
718        MF.getRegInfo().setPhysRegUsed(Reg);
719        AFI->setCSRegisterIsSpilled(Reg);
720        if (!isReservedReg(MF, Reg))
721          ExtraCSSpill = true;
722      }
723    }
724
725    // Estimate if we might need to scavenge a register at some point in order
726    // to materialize a stack offset. If so, either spill one additional
727    // callee-saved register or reserve a special spill slot to facilitate
728    // register scavenging. Thumb1 needs a spill slot for stack pointer
729    // adjustments also, even when the frame itself is small.
730    if (RS && !ExtraCSSpill) {
731      MachineFrameInfo  *MFI = MF.getFrameInfo();
732      // If any of the stack slot references may be out of range of an
733      // immediate offset, make sure a register (or a spill slot) is
734      // available for the register scavenger. Note that if we're indexing
735      // off the frame pointer, the effective stack size is 4 bytes larger
736      // since the FP points to the stack slot of the previous FP.
737      if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0)
738          >= estimateRSStackSizeLimit(MF)) {
739        // If any non-reserved CS register isn't spilled, just spill one or two
740        // extra. That should take care of it!
741        unsigned NumExtras = TargetAlign / 4;
742        SmallVector<unsigned, 2> Extras;
743        while (NumExtras && !UnspilledCS1GPRs.empty()) {
744          unsigned Reg = UnspilledCS1GPRs.back();
745          UnspilledCS1GPRs.pop_back();
746          if (!isReservedReg(MF, Reg)) {
747            Extras.push_back(Reg);
748            NumExtras--;
749          }
750        }
751        // For non-Thumb1 functions, also check for hi-reg CS registers
752        if (!AFI->isThumb1OnlyFunction()) {
753          while (NumExtras && !UnspilledCS2GPRs.empty()) {
754            unsigned Reg = UnspilledCS2GPRs.back();
755            UnspilledCS2GPRs.pop_back();
756            if (!isReservedReg(MF, Reg)) {
757              Extras.push_back(Reg);
758              NumExtras--;
759            }
760          }
761        }
762        if (Extras.size() && NumExtras == 0) {
763          for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
764            MF.getRegInfo().setPhysRegUsed(Extras[i]);
765            AFI->setCSRegisterIsSpilled(Extras[i]);
766          }
767        } else if (!AFI->isThumb1OnlyFunction()) {
768          // note: Thumb1 functions spill to R12, not the stack.
769          // Reserve a slot closest to SP or frame pointer.
770          const TargetRegisterClass *RC = ARM::GPRRegisterClass;
771          RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
772                                                             RC->getAlignment(),
773                                                             false));
774        }
775      }
776    }
777  }
778
779  if (ForceLRSpill) {
780    MF.getRegInfo().setPhysRegUsed(ARM::LR);
781    AFI->setCSRegisterIsSpilled(ARM::LR);
782    AFI->setLRIsSpilledForFarJump(true);
783  }
784}
785
786unsigned ARMBaseRegisterInfo::getRARegister() const {
787  return ARM::LR;
788}
789
790unsigned
791ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
792  if (STI.isTargetDarwin() || hasFP(MF))
793    return FramePtr;
794  return ARM::SP;
795}
796
797int
798ARMBaseRegisterInfo::getFrameIndexReference(MachineFunction &MF, int FI,
799                                            unsigned &FrameReg) const {
800  const MachineFrameInfo *MFI = MF.getFrameInfo();
801  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
802  int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
803  bool isFixed = MFI->isFixedObjectIndex(FI);
804
805  FrameReg = ARM::SP;
806  if (AFI->isGPRCalleeSavedArea1Frame(FI))
807    Offset -= AFI->getGPRCalleeSavedArea1Offset();
808  else if (AFI->isGPRCalleeSavedArea2Frame(FI))
809    Offset -= AFI->getGPRCalleeSavedArea2Offset();
810  else if (AFI->isDPRCalleeSavedAreaFrame(FI))
811    Offset -= AFI->getDPRCalleeSavedAreaOffset();
812  else if (needsStackRealignment(MF)) {
813    // When dynamically realigning the stack, use the frame pointer for
814    // parameters, and the stack pointer for locals.
815    assert (hasFP(MF) && "dynamic stack realignment without a FP!");
816    if (isFixed) {
817      FrameReg = getFrameRegister(MF);
818      Offset -= AFI->getFramePtrSpillOffset();
819    }
820  } else if (hasFP(MF) && AFI->hasStackFrame()) {
821    if (isFixed || MFI->hasVarSizedObjects()) {
822      // Use frame pointer to reference fixed objects unless this is a
823      // frameless function.
824      FrameReg = getFrameRegister(MF);
825      Offset -= AFI->getFramePtrSpillOffset();
826    } else if (AFI->isThumb2Function()) {
827      // In Thumb2 mode, the negative offset is very limited.
828      int FPOffset = Offset - AFI->getFramePtrSpillOffset();
829      if (FPOffset >= -255 && FPOffset < 0) {
830        FrameReg = getFrameRegister(MF);
831        Offset = FPOffset;
832      }
833    }
834  }
835  return Offset;
836}
837
838
839int
840ARMBaseRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
841  unsigned FrameReg;
842  return getFrameIndexReference(MF, FI, FrameReg);
843}
844
845unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
846  llvm_unreachable("What is the exception register");
847  return 0;
848}
849
850unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
851  llvm_unreachable("What is the exception handler register");
852  return 0;
853}
854
855int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
856  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
857}
858
859unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
860                                              const MachineFunction &MF) const {
861  switch (Reg) {
862  default: break;
863  // Return 0 if either register of the pair is a special register.
864  // So no R12, etc.
865  case ARM::R1:
866    return ARM::R0;
867  case ARM::R3:
868    return ARM::R2;
869  case ARM::R5:
870    return ARM::R4;
871  case ARM::R7:
872    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
873  case ARM::R9:
874    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
875  case ARM::R11:
876    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
877
878  case ARM::S1:
879    return ARM::S0;
880  case ARM::S3:
881    return ARM::S2;
882  case ARM::S5:
883    return ARM::S4;
884  case ARM::S7:
885    return ARM::S6;
886  case ARM::S9:
887    return ARM::S8;
888  case ARM::S11:
889    return ARM::S10;
890  case ARM::S13:
891    return ARM::S12;
892  case ARM::S15:
893    return ARM::S14;
894  case ARM::S17:
895    return ARM::S16;
896  case ARM::S19:
897    return ARM::S18;
898  case ARM::S21:
899    return ARM::S20;
900  case ARM::S23:
901    return ARM::S22;
902  case ARM::S25:
903    return ARM::S24;
904  case ARM::S27:
905    return ARM::S26;
906  case ARM::S29:
907    return ARM::S28;
908  case ARM::S31:
909    return ARM::S30;
910
911  case ARM::D1:
912    return ARM::D0;
913  case ARM::D3:
914    return ARM::D2;
915  case ARM::D5:
916    return ARM::D4;
917  case ARM::D7:
918    return ARM::D6;
919  case ARM::D9:
920    return ARM::D8;
921  case ARM::D11:
922    return ARM::D10;
923  case ARM::D13:
924    return ARM::D12;
925  case ARM::D15:
926    return ARM::D14;
927  case ARM::D17:
928    return ARM::D16;
929  case ARM::D19:
930    return ARM::D18;
931  case ARM::D21:
932    return ARM::D20;
933  case ARM::D23:
934    return ARM::D22;
935  case ARM::D25:
936    return ARM::D24;
937  case ARM::D27:
938    return ARM::D26;
939  case ARM::D29:
940    return ARM::D28;
941  case ARM::D31:
942    return ARM::D30;
943  }
944
945  return 0;
946}
947
948unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
949                                             const MachineFunction &MF) const {
950  switch (Reg) {
951  default: break;
952  // Return 0 if either register of the pair is a special register.
953  // So no R12, etc.
954  case ARM::R0:
955    return ARM::R1;
956  case ARM::R2:
957    return ARM::R3;
958  case ARM::R4:
959    return ARM::R5;
960  case ARM::R6:
961    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
962  case ARM::R8:
963    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
964  case ARM::R10:
965    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
966
967  case ARM::S0:
968    return ARM::S1;
969  case ARM::S2:
970    return ARM::S3;
971  case ARM::S4:
972    return ARM::S5;
973  case ARM::S6:
974    return ARM::S7;
975  case ARM::S8:
976    return ARM::S9;
977  case ARM::S10:
978    return ARM::S11;
979  case ARM::S12:
980    return ARM::S13;
981  case ARM::S14:
982    return ARM::S15;
983  case ARM::S16:
984    return ARM::S17;
985  case ARM::S18:
986    return ARM::S19;
987  case ARM::S20:
988    return ARM::S21;
989  case ARM::S22:
990    return ARM::S23;
991  case ARM::S24:
992    return ARM::S25;
993  case ARM::S26:
994    return ARM::S27;
995  case ARM::S28:
996    return ARM::S29;
997  case ARM::S30:
998    return ARM::S31;
999
1000  case ARM::D0:
1001    return ARM::D1;
1002  case ARM::D2:
1003    return ARM::D3;
1004  case ARM::D4:
1005    return ARM::D5;
1006  case ARM::D6:
1007    return ARM::D7;
1008  case ARM::D8:
1009    return ARM::D9;
1010  case ARM::D10:
1011    return ARM::D11;
1012  case ARM::D12:
1013    return ARM::D13;
1014  case ARM::D14:
1015    return ARM::D15;
1016  case ARM::D16:
1017    return ARM::D17;
1018  case ARM::D18:
1019    return ARM::D19;
1020  case ARM::D20:
1021    return ARM::D21;
1022  case ARM::D22:
1023    return ARM::D23;
1024  case ARM::D24:
1025    return ARM::D25;
1026  case ARM::D26:
1027    return ARM::D27;
1028  case ARM::D28:
1029    return ARM::D29;
1030  case ARM::D30:
1031    return ARM::D31;
1032  }
1033
1034  return 0;
1035}
1036
1037/// emitLoadConstPool - Emits a load from constpool to materialize the
1038/// specified immediate.
1039void ARMBaseRegisterInfo::
1040emitLoadConstPool(MachineBasicBlock &MBB,
1041                  MachineBasicBlock::iterator &MBBI,
1042                  DebugLoc dl,
1043                  unsigned DestReg, unsigned SubIdx, int Val,
1044                  ARMCC::CondCodes Pred,
1045                  unsigned PredReg) const {
1046  MachineFunction &MF = *MBB.getParent();
1047  MachineConstantPool *ConstantPool = MF.getConstantPool();
1048  Constant *C =
1049        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1050  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1051
1052  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1053    .addReg(DestReg, getDefRegState(true), SubIdx)
1054    .addConstantPoolIndex(Idx)
1055    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1056}
1057
1058bool ARMBaseRegisterInfo::
1059requiresRegisterScavenging(const MachineFunction &MF) const {
1060  return true;
1061}
1062
1063bool ARMBaseRegisterInfo::
1064requiresFrameIndexScavenging(const MachineFunction &MF) const {
1065  return true;
1066}
1067
1068// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1069// not required, we reserve argument space for call sites in the function
1070// immediately on entry to the current function. This eliminates the need for
1071// add/sub sp brackets around call sites. Returns true if the call frame is
1072// included as part of the stack frame.
1073bool ARMBaseRegisterInfo::
1074hasReservedCallFrame(MachineFunction &MF) const {
1075  const MachineFrameInfo *FFI = MF.getFrameInfo();
1076  unsigned CFSize = FFI->getMaxCallFrameSize();
1077  // It's not always a good idea to include the call frame as part of the
1078  // stack frame. ARM (especially Thumb) has small immediate offset to
1079  // address the stack frame. So a large call frame can cause poor codegen
1080  // and may even makes it impossible to scavenge a register.
1081  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
1082    return false;
1083
1084  return !MF.getFrameInfo()->hasVarSizedObjects();
1085}
1086
1087static void
1088emitSPUpdate(bool isARM,
1089             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1090             DebugLoc dl, const ARMBaseInstrInfo &TII,
1091             int NumBytes,
1092             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1093  if (isARM)
1094    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1095                            Pred, PredReg, TII);
1096  else
1097    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1098                           Pred, PredReg, TII);
1099}
1100
1101
1102void ARMBaseRegisterInfo::
1103eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1104                              MachineBasicBlock::iterator I) const {
1105  if (!hasReservedCallFrame(MF)) {
1106    // If we have alloca, convert as follows:
1107    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1108    // ADJCALLSTACKUP   -> add, sp, sp, amount
1109    MachineInstr *Old = I;
1110    DebugLoc dl = Old->getDebugLoc();
1111    unsigned Amount = Old->getOperand(0).getImm();
1112    if (Amount != 0) {
1113      // We need to keep the stack aligned properly.  To do this, we round the
1114      // amount of space needed for the outgoing arguments up to the next
1115      // alignment boundary.
1116      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1117      Amount = (Amount+Align-1)/Align*Align;
1118
1119      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1120      assert(!AFI->isThumb1OnlyFunction() &&
1121             "This eliminateCallFramePseudoInstr does not suppor Thumb1!");
1122      bool isARM = !AFI->isThumbFunction();
1123
1124      // Replace the pseudo instruction with a new instruction...
1125      unsigned Opc = Old->getOpcode();
1126      ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
1127      // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN?
1128      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1129        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1130        unsigned PredReg = Old->getOperand(2).getReg();
1131        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1132      } else {
1133        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1134        unsigned PredReg = Old->getOperand(3).getReg();
1135        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1136        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1137      }
1138    }
1139  }
1140  MBB.erase(I);
1141}
1142
1143unsigned
1144ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1145                                         int SPAdj, int *Value,
1146                                         RegScavenger *RS) const {
1147  unsigned i = 0;
1148  MachineInstr &MI = *II;
1149  MachineBasicBlock &MBB = *MI.getParent();
1150  MachineFunction &MF = *MBB.getParent();
1151  const MachineFrameInfo *MFI = MF.getFrameInfo();
1152  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1153  assert(!AFI->isThumb1OnlyFunction() &&
1154         "This eliminateFrameIndex does not support Thumb1!");
1155
1156  while (!MI.getOperand(i).isFI()) {
1157    ++i;
1158    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1159  }
1160
1161  int FrameIndex = MI.getOperand(i).getIndex();
1162  int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj;
1163  unsigned FrameReg;
1164
1165  Offset = getFrameIndexReference(MF, FrameIndex, FrameReg);
1166  if (FrameReg != ARM::SP)
1167    SPAdj = 0;
1168
1169  // Modify MI as necessary to handle as much of 'Offset' as possible
1170  bool Done = false;
1171  if (!AFI->isThumbFunction())
1172    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1173  else {
1174    assert(AFI->isThumb2Function());
1175    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1176  }
1177  if (Done)
1178    return 0;
1179
1180  // If we get here, the immediate doesn't fit into the instruction.  We folded
1181  // as much as possible above, handle the rest, providing a register that is
1182  // SP+LargeImm.
1183  assert((Offset ||
1184          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1185          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1186         "This code isn't needed if offset already handled!");
1187
1188  unsigned ScratchReg = 0;
1189  int PIdx = MI.findFirstPredOperandIdx();
1190  ARMCC::CondCodes Pred = (PIdx == -1)
1191    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1192  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1193  if (Offset == 0)
1194    // Must be addrmode4/6.
1195    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1196  else {
1197    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1198    if (Value) *Value = Offset;
1199    if (!AFI->isThumbFunction())
1200      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1201                              Offset, Pred, PredReg, TII);
1202    else {
1203      assert(AFI->isThumb2Function());
1204      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1205                             Offset, Pred, PredReg, TII);
1206    }
1207    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1208    if (!ReuseFrameIndexVals)
1209      ScratchReg = 0;
1210  }
1211  return ScratchReg;
1212}
1213
1214/// Move iterator past the next bunch of callee save load / store ops for
1215/// the particular spill area (1: integer area 1, 2: integer area 2,
1216/// 3: fp area, 0: don't care).
1217static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1218                                   MachineBasicBlock::iterator &MBBI,
1219                                   int Opc1, int Opc2, unsigned Area,
1220                                   const ARMSubtarget &STI) {
1221  while (MBBI != MBB.end() &&
1222         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1223         MBBI->getOperand(1).isFI()) {
1224    if (Area != 0) {
1225      bool Done = false;
1226      unsigned Category = 0;
1227      switch (MBBI->getOperand(0).getReg()) {
1228      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1229      case ARM::LR:
1230        Category = 1;
1231        break;
1232      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1233        Category = STI.isTargetDarwin() ? 2 : 1;
1234        break;
1235      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1236      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1237        Category = 3;
1238        break;
1239      default:
1240        Done = true;
1241        break;
1242      }
1243      if (Done || Category != Area)
1244        break;
1245    }
1246
1247    ++MBBI;
1248  }
1249}
1250
1251void ARMBaseRegisterInfo::
1252emitPrologue(MachineFunction &MF) const {
1253  MachineBasicBlock &MBB = MF.front();
1254  MachineBasicBlock::iterator MBBI = MBB.begin();
1255  MachineFrameInfo  *MFI = MF.getFrameInfo();
1256  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1257  assert(!AFI->isThumb1OnlyFunction() &&
1258         "This emitPrologue does not suppor Thumb1!");
1259  bool isARM = !AFI->isThumbFunction();
1260  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1261  unsigned NumBytes = MFI->getStackSize();
1262  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1263  DebugLoc dl = (MBBI != MBB.end() ?
1264                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1265
1266  // Determine the sizes of each callee-save spill areas and record which frame
1267  // belongs to which callee-save spill areas.
1268  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1269  int FramePtrSpillFI = 0;
1270
1271  // Allocate the vararg register save area. This is not counted in NumBytes.
1272  if (VARegSaveSize)
1273    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1274
1275  if (!AFI->hasStackFrame()) {
1276    if (NumBytes != 0)
1277      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1278    return;
1279  }
1280
1281  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1282    unsigned Reg = CSI[i].getReg();
1283    int FI = CSI[i].getFrameIdx();
1284    switch (Reg) {
1285    case ARM::R4:
1286    case ARM::R5:
1287    case ARM::R6:
1288    case ARM::R7:
1289    case ARM::LR:
1290      if (Reg == FramePtr)
1291        FramePtrSpillFI = FI;
1292      AFI->addGPRCalleeSavedArea1Frame(FI);
1293      GPRCS1Size += 4;
1294      break;
1295    case ARM::R8:
1296    case ARM::R9:
1297    case ARM::R10:
1298    case ARM::R11:
1299      if (Reg == FramePtr)
1300        FramePtrSpillFI = FI;
1301      if (STI.isTargetDarwin()) {
1302        AFI->addGPRCalleeSavedArea2Frame(FI);
1303        GPRCS2Size += 4;
1304      } else {
1305        AFI->addGPRCalleeSavedArea1Frame(FI);
1306        GPRCS1Size += 4;
1307      }
1308      break;
1309    default:
1310      AFI->addDPRCalleeSavedAreaFrame(FI);
1311      DPRCSSize += 8;
1312    }
1313  }
1314
1315  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1316  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1317  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1318
1319  // Set FP to point to the stack slot that contains the previous FP.
1320  // For Darwin, FP is R7, which has now been stored in spill area 1.
1321  // Otherwise, if this is not Darwin, all the callee-saved registers go
1322  // into spill area 1, including the FP in R11.  In either case, it is
1323  // now safe to emit this assignment.
1324  if (STI.isTargetDarwin() || hasFP(MF)) {
1325    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1326    MachineInstrBuilder MIB =
1327      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1328      .addFrameIndex(FramePtrSpillFI).addImm(0);
1329    AddDefaultCC(AddDefaultPred(MIB));
1330  }
1331
1332  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1333  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1334
1335  // Build the new SUBri to adjust SP for FP callee-save spill area.
1336  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1337  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1338
1339  // Determine starting offsets of spill areas.
1340  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1341  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1342  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1343  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1344  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1345  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1346  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1347
1348  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1349  NumBytes = DPRCSOffset;
1350  if (NumBytes) {
1351    // Adjust SP after all the callee-save spills.
1352    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1353  }
1354
1355  if (STI.isTargetELF() && hasFP(MF)) {
1356    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1357                             AFI->getFramePtrSpillOffset());
1358  }
1359
1360  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1361  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1362  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1363
1364  // If we need dynamic stack realignment, do it here.
1365  if (needsStackRealignment(MF)) {
1366    unsigned MaxAlign = MFI->getMaxAlignment();
1367    assert (!AFI->isThumb1OnlyFunction());
1368    if (!AFI->isThumbFunction()) {
1369      // Emit bic sp, sp, MaxAlign
1370      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1371                                          TII.get(ARM::BICri), ARM::SP)
1372                                  .addReg(ARM::SP, RegState::Kill)
1373                                  .addImm(MaxAlign-1)));
1374    } else {
1375      // We cannot use sp as source/dest register here, thus we're emitting the
1376      // following sequence:
1377      // mov r4, sp
1378      // bic r4, r4, MaxAlign
1379      // mov sp, r4
1380      // FIXME: It will be better just to find spare register here.
1381      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1382        .addReg(ARM::SP, RegState::Kill);
1383      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1384                                          TII.get(ARM::t2BICri), ARM::R4)
1385                                  .addReg(ARM::R4, RegState::Kill)
1386                                  .addImm(MaxAlign-1)));
1387      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1388        .addReg(ARM::R4, RegState::Kill);
1389    }
1390  }
1391}
1392
1393static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1394  for (unsigned i = 0; CSRegs[i]; ++i)
1395    if (Reg == CSRegs[i])
1396      return true;
1397  return false;
1398}
1399
1400static bool isCSRestore(MachineInstr *MI,
1401                        const ARMBaseInstrInfo &TII,
1402                        const unsigned *CSRegs) {
1403  return ((MI->getOpcode() == (int)ARM::VLDRD ||
1404           MI->getOpcode() == (int)ARM::LDR ||
1405           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1406          MI->getOperand(1).isFI() &&
1407          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1408}
1409
1410void ARMBaseRegisterInfo::
1411emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1412  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1413  assert(MBBI->getDesc().isReturn() &&
1414         "Can only insert epilog into returning blocks");
1415  DebugLoc dl = MBBI->getDebugLoc();
1416  MachineFrameInfo *MFI = MF.getFrameInfo();
1417  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1418  assert(!AFI->isThumb1OnlyFunction() &&
1419         "This emitEpilogue does not suppor Thumb1!");
1420  bool isARM = !AFI->isThumbFunction();
1421
1422  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1423  int NumBytes = (int)MFI->getStackSize();
1424
1425  if (!AFI->hasStackFrame()) {
1426    if (NumBytes != 0)
1427      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1428  } else {
1429    // Unwind MBBI to point to first LDR / VLDRD.
1430    const unsigned *CSRegs = getCalleeSavedRegs();
1431    if (MBBI != MBB.begin()) {
1432      do
1433        --MBBI;
1434      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1435      if (!isCSRestore(MBBI, TII, CSRegs))
1436        ++MBBI;
1437    }
1438
1439    // Move SP to start of FP callee save spill area.
1440    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1441                 AFI->getGPRCalleeSavedArea2Size() +
1442                 AFI->getDPRCalleeSavedAreaSize());
1443
1444    // Darwin ABI requires FP to point to the stack slot that contains the
1445    // previous FP.
1446    bool HasFP = hasFP(MF);
1447    if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1448      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1449      // Reset SP based on frame pointer only if the stack frame extends beyond
1450      // frame pointer stack slot or target is ELF and the function has FP.
1451      if (HasFP ||
1452          AFI->getGPRCalleeSavedArea2Size() ||
1453          AFI->getDPRCalleeSavedAreaSize()  ||
1454          AFI->getDPRCalleeSavedAreaOffset()) {
1455        if (NumBytes) {
1456          if (isARM)
1457            emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1458                                    ARMCC::AL, 0, TII);
1459          else
1460            emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1461                                    ARMCC::AL, 0, TII);
1462        } else {
1463          // Thumb2 or ARM.
1464          if (isARM)
1465            BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1466              .addReg(FramePtr)
1467              .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1468          else
1469            BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1470              .addReg(FramePtr);
1471        }
1472      }
1473    } else if (NumBytes)
1474      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1475
1476    // Move SP to start of integer callee save spill area 2.
1477    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1478    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1479
1480    // Move SP to start of integer callee save spill area 1.
1481    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1482    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1483
1484    // Move SP to SP upon entry to the function.
1485    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1486    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1487  }
1488
1489  if (VARegSaveSize)
1490    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1491}
1492
1493#include "ARMGenRegisterInfo.inc"
1494