ARMBaseRegisterInfo.cpp revision 199989
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARM.h" 15#include "ARMAddressingModes.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMBaseRegisterInfo.h" 18#include "ARMInstrInfo.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMSubtarget.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/LLVMContext.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineInstrBuilder.h" 29#include "llvm/CodeGen/MachineLocation.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/RegisterScavenging.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetFrameInfo.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/BitVector.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/Support/CommandLine.h" 41using namespace llvm; 42 43static cl::opt<bool> 44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true), 45 cl::desc("Reuse repeated frame index values")); 46 47unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, 48 bool *isSPVFP) { 49 if (isSPVFP) 50 *isSPVFP = false; 51 52 using namespace ARM; 53 switch (RegEnum) { 54 default: 55 llvm_unreachable("Unknown ARM register!"); 56 case R0: case D0: case Q0: return 0; 57 case R1: case D1: case Q1: return 1; 58 case R2: case D2: case Q2: return 2; 59 case R3: case D3: case Q3: return 3; 60 case R4: case D4: case Q4: return 4; 61 case R5: case D5: case Q5: return 5; 62 case R6: case D6: case Q6: return 6; 63 case R7: case D7: case Q7: return 7; 64 case R8: case D8: case Q8: return 8; 65 case R9: case D9: case Q9: return 9; 66 case R10: case D10: case Q10: return 10; 67 case R11: case D11: case Q11: return 11; 68 case R12: case D12: case Q12: return 12; 69 case SP: case D13: case Q13: return 13; 70 case LR: case D14: case Q14: return 14; 71 case PC: case D15: case Q15: return 15; 72 73 case D16: return 16; 74 case D17: return 17; 75 case D18: return 18; 76 case D19: return 19; 77 case D20: return 20; 78 case D21: return 21; 79 case D22: return 22; 80 case D23: return 23; 81 case D24: return 24; 82 case D25: return 25; 83 case D26: return 27; 84 case D27: return 27; 85 case D28: return 28; 86 case D29: return 29; 87 case D30: return 30; 88 case D31: return 31; 89 90 case S0: case S1: case S2: case S3: 91 case S4: case S5: case S6: case S7: 92 case S8: case S9: case S10: case S11: 93 case S12: case S13: case S14: case S15: 94 case S16: case S17: case S18: case S19: 95 case S20: case S21: case S22: case S23: 96 case S24: case S25: case S26: case S27: 97 case S28: case S29: case S30: case S31: { 98 if (isSPVFP) 99 *isSPVFP = true; 100 switch (RegEnum) { 101 default: return 0; // Avoid compile time warning. 102 case S0: return 0; 103 case S1: return 1; 104 case S2: return 2; 105 case S3: return 3; 106 case S4: return 4; 107 case S5: return 5; 108 case S6: return 6; 109 case S7: return 7; 110 case S8: return 8; 111 case S9: return 9; 112 case S10: return 10; 113 case S11: return 11; 114 case S12: return 12; 115 case S13: return 13; 116 case S14: return 14; 117 case S15: return 15; 118 case S16: return 16; 119 case S17: return 17; 120 case S18: return 18; 121 case S19: return 19; 122 case S20: return 20; 123 case S21: return 21; 124 case S22: return 22; 125 case S23: return 23; 126 case S24: return 24; 127 case S25: return 25; 128 case S26: return 26; 129 case S27: return 27; 130 case S28: return 28; 131 case S29: return 29; 132 case S30: return 30; 133 case S31: return 31; 134 } 135 } 136 } 137} 138 139ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 140 const ARMSubtarget &sti) 141 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 142 TII(tii), STI(sti), 143 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 144} 145 146const unsigned* 147ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 148 static const unsigned CalleeSavedRegs[] = { 149 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 150 ARM::R7, ARM::R6, ARM::R5, ARM::R4, 151 152 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 153 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 154 0 155 }; 156 157 static const unsigned DarwinCalleeSavedRegs[] = { 158 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved 159 // register. 160 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 161 ARM::R11, ARM::R10, ARM::R8, 162 163 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 164 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 165 0 166 }; 167 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 168} 169 170const TargetRegisterClass* const * 171ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 172 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 173 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 174 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 175 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 176 177 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 178 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 179 0 180 }; 181 182 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = { 183 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 184 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass, 185 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass, 186 187 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 188 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 189 0 190 }; 191 192 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = { 193 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 194 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 195 &ARM::GPRRegClass, &ARM::GPRRegClass, 196 197 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 198 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 199 0 200 }; 201 202 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={ 203 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass, 204 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass, 205 &ARM::GPRRegClass, &ARM::GPRRegClass, 206 207 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 208 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 209 0 210 }; 211 212 if (STI.isThumb1Only()) { 213 return STI.isTargetDarwin() 214 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses; 215 } 216 return STI.isTargetDarwin() 217 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses; 218} 219 220BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 221 // FIXME: avoid re-calculating this everytime. 222 BitVector Reserved(getNumRegs()); 223 Reserved.set(ARM::SP); 224 Reserved.set(ARM::PC); 225 if (STI.isTargetDarwin() || hasFP(MF)) 226 Reserved.set(FramePtr); 227 // Some targets reserve R9. 228 if (STI.isR9Reserved()) 229 Reserved.set(ARM::R9); 230 return Reserved; 231} 232 233bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, 234 unsigned Reg) const { 235 switch (Reg) { 236 default: break; 237 case ARM::SP: 238 case ARM::PC: 239 return true; 240 case ARM::R7: 241 case ARM::R11: 242 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 243 return true; 244 break; 245 case ARM::R9: 246 return STI.isR9Reserved(); 247 } 248 249 return false; 250} 251 252const TargetRegisterClass * 253ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 254 const TargetRegisterClass *B, 255 unsigned SubIdx) const { 256 switch (SubIdx) { 257 default: return 0; 258 case 1: 259 case 2: 260 case 3: 261 case 4: 262 // S sub-registers. 263 if (A->getSize() == 8) { 264 if (B == &ARM::SPR_8RegClass) 265 return &ARM::DPR_8RegClass; 266 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!"); 267 if (A == &ARM::DPR_8RegClass) 268 return A; 269 return &ARM::DPR_VFP2RegClass; 270 } 271 272 assert(A->getSize() == 16 && "Expecting a Q register class!"); 273 if (B == &ARM::SPR_8RegClass) 274 return &ARM::QPR_8RegClass; 275 return &ARM::QPR_VFP2RegClass; 276 case 5: 277 case 6: 278 // D sub-registers. 279 if (B == &ARM::DPR_VFP2RegClass) 280 return &ARM::QPR_VFP2RegClass; 281 if (B == &ARM::DPR_8RegClass) 282 return &ARM::QPR_8RegClass; 283 return A; 284 } 285 return 0; 286} 287 288const TargetRegisterClass * 289ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { 290 return ARM::GPRRegisterClass; 291} 292 293/// getAllocationOrder - Returns the register allocation order for a specified 294/// register class in the form of a pair of TargetRegisterClass iterators. 295std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 296ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, 297 unsigned HintType, unsigned HintReg, 298 const MachineFunction &MF) const { 299 // Alternative register allocation orders when favoring even / odd registers 300 // of register pairs. 301 302 // No FP, R9 is available. 303 static const unsigned GPREven1[] = { 304 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 305 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 306 ARM::R9, ARM::R11 307 }; 308 static const unsigned GPROdd1[] = { 309 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 310 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 311 ARM::R8, ARM::R10 312 }; 313 314 // FP is R7, R9 is available. 315 static const unsigned GPREven2[] = { 316 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 317 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 318 ARM::R9, ARM::R11 319 }; 320 static const unsigned GPROdd2[] = { 321 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 322 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 323 ARM::R8, ARM::R10 324 }; 325 326 // FP is R11, R9 is available. 327 static const unsigned GPREven3[] = { 328 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 329 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 330 ARM::R9 331 }; 332 static const unsigned GPROdd3[] = { 333 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 334 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 335 ARM::R8 336 }; 337 338 // No FP, R9 is not available. 339 static const unsigned GPREven4[] = { 340 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 341 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 342 ARM::R11 343 }; 344 static const unsigned GPROdd4[] = { 345 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 346 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 347 ARM::R10 348 }; 349 350 // FP is R7, R9 is not available. 351 static const unsigned GPREven5[] = { 352 ARM::R0, ARM::R2, ARM::R4, ARM::R10, 353 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 354 ARM::R11 355 }; 356 static const unsigned GPROdd5[] = { 357 ARM::R1, ARM::R3, ARM::R5, ARM::R11, 358 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 359 ARM::R10 360 }; 361 362 // FP is R11, R9 is not available. 363 static const unsigned GPREven6[] = { 364 ARM::R0, ARM::R2, ARM::R4, ARM::R6, 365 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 366 }; 367 static const unsigned GPROdd6[] = { 368 ARM::R1, ARM::R3, ARM::R5, ARM::R7, 369 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 370 }; 371 372 373 if (HintType == ARMRI::RegPairEven) { 374 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 375 // It's no longer possible to fulfill this hint. Return the default 376 // allocation order. 377 return std::make_pair(RC->allocation_order_begin(MF), 378 RC->allocation_order_end(MF)); 379 380 if (!STI.isTargetDarwin() && !hasFP(MF)) { 381 if (!STI.isR9Reserved()) 382 return std::make_pair(GPREven1, 383 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned))); 384 else 385 return std::make_pair(GPREven4, 386 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned))); 387 } else if (FramePtr == ARM::R7) { 388 if (!STI.isR9Reserved()) 389 return std::make_pair(GPREven2, 390 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned))); 391 else 392 return std::make_pair(GPREven5, 393 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned))); 394 } else { // FramePtr == ARM::R11 395 if (!STI.isR9Reserved()) 396 return std::make_pair(GPREven3, 397 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned))); 398 else 399 return std::make_pair(GPREven6, 400 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned))); 401 } 402 } else if (HintType == ARMRI::RegPairOdd) { 403 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 404 // It's no longer possible to fulfill this hint. Return the default 405 // allocation order. 406 return std::make_pair(RC->allocation_order_begin(MF), 407 RC->allocation_order_end(MF)); 408 409 if (!STI.isTargetDarwin() && !hasFP(MF)) { 410 if (!STI.isR9Reserved()) 411 return std::make_pair(GPROdd1, 412 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned))); 413 else 414 return std::make_pair(GPROdd4, 415 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned))); 416 } else if (FramePtr == ARM::R7) { 417 if (!STI.isR9Reserved()) 418 return std::make_pair(GPROdd2, 419 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned))); 420 else 421 return std::make_pair(GPROdd5, 422 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned))); 423 } else { // FramePtr == ARM::R11 424 if (!STI.isR9Reserved()) 425 return std::make_pair(GPROdd3, 426 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned))); 427 else 428 return std::make_pair(GPROdd6, 429 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned))); 430 } 431 } 432 return std::make_pair(RC->allocation_order_begin(MF), 433 RC->allocation_order_end(MF)); 434} 435 436/// ResolveRegAllocHint - Resolves the specified register allocation hint 437/// to a physical register. Returns the physical register if it is successful. 438unsigned 439ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 440 const MachineFunction &MF) const { 441 if (Reg == 0 || !isPhysicalRegister(Reg)) 442 return 0; 443 if (Type == 0) 444 return Reg; 445 else if (Type == (unsigned)ARMRI::RegPairOdd) 446 // Odd register. 447 return getRegisterPairOdd(Reg, MF); 448 else if (Type == (unsigned)ARMRI::RegPairEven) 449 // Even register. 450 return getRegisterPairEven(Reg, MF); 451 return 0; 452} 453 454void 455ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 456 MachineFunction &MF) const { 457 MachineRegisterInfo *MRI = &MF.getRegInfo(); 458 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 459 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 460 Hint.first == (unsigned)ARMRI::RegPairEven) && 461 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) { 462 // If 'Reg' is one of the even / odd register pair and it's now changed 463 // (e.g. coalesced) into a different register. The other register of the 464 // pair allocation hint must be updated to reflect the relationship 465 // change. 466 unsigned OtherReg = Hint.second; 467 Hint = MRI->getRegAllocationHint(OtherReg); 468 if (Hint.second == Reg) 469 // Make sure the pair has not already divorced. 470 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 471 } 472} 473 474static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) { 475 unsigned MaxAlign = 0; 476 477 for (int i = FFI->getObjectIndexBegin(), 478 e = FFI->getObjectIndexEnd(); i != e; ++i) { 479 if (FFI->isDeadObjectIndex(i)) 480 continue; 481 482 unsigned Align = FFI->getObjectAlignment(i); 483 MaxAlign = std::max(MaxAlign, Align); 484 } 485 486 return MaxAlign; 487} 488 489/// hasFP - Return true if the specified function should have a dedicated frame 490/// pointer register. This is true if the function has variable sized allocas 491/// or if frame pointer elimination is disabled. 492/// 493bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { 494 const MachineFrameInfo *MFI = MF.getFrameInfo(); 495 return (NoFramePointerElim || 496 needsStackRealignment(MF) || 497 MFI->hasVarSizedObjects() || 498 MFI->isFrameAddressTaken()); 499} 500 501bool ARMBaseRegisterInfo:: 502needsStackRealignment(const MachineFunction &MF) const { 503 const MachineFrameInfo *MFI = MF.getFrameInfo(); 504 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 505 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 506 return (RealignStack && 507 !AFI->isThumb1OnlyFunction() && 508 (MFI->getMaxAlignment() > StackAlign) && 509 !MFI->hasVarSizedObjects()); 510} 511 512bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const { 513 const MachineFrameInfo *MFI = MF.getFrameInfo(); 514 if (NoFramePointerElim && MFI->hasCalls()) 515 return true; 516 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 517 || needsStackRealignment(MF); 518} 519 520/// estimateStackSize - Estimate and return the size of the frame. 521static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 522 const MachineFrameInfo *FFI = MF.getFrameInfo(); 523 int Offset = 0; 524 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 525 int FixedOff = -FFI->getObjectOffset(i); 526 if (FixedOff > Offset) Offset = FixedOff; 527 } 528 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 529 if (FFI->isDeadObjectIndex(i)) 530 continue; 531 Offset += FFI->getObjectSize(i); 532 unsigned Align = FFI->getObjectAlignment(i); 533 // Adjust to alignment boundary 534 Offset = (Offset+Align-1)/Align*Align; 535 } 536 return (unsigned)Offset; 537} 538 539/// estimateRSStackSizeLimit - Look at each instruction that references stack 540/// frames and return the stack size limit beyond which some of these 541/// instructions will require scratch register during their expansion later. 542unsigned 543ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const { 544 unsigned Limit = (1 << 12) - 1; 545 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { 546 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); 547 I != E; ++I) { 548 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 549 if (!I->getOperand(i).isFI()) continue; 550 551 const TargetInstrDesc &Desc = TII.get(I->getOpcode()); 552 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 553 if (AddrMode == ARMII::AddrMode3 || 554 AddrMode == ARMII::AddrModeT2_i8) 555 return (1 << 8) - 1; 556 557 if (AddrMode == ARMII::AddrMode5 || 558 AddrMode == ARMII::AddrModeT2_i8s4) 559 Limit = std::min(Limit, ((1U << 8) - 1) * 4); 560 561 if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF)) 562 // When the stack offset is negative, we will end up using 563 // the i8 instructions instead. 564 return (1 << 8) - 1; 565 break; // At most one FI per instruction 566 } 567 } 568 } 569 570 return Limit; 571} 572 573void 574ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 575 RegScavenger *RS) const { 576 // This tells PEI to spill the FP as if it is any other callee-save register 577 // to take advantage the eliminateFrameIndex machinery. This also ensures it 578 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 579 // to combine multiple loads / stores. 580 bool CanEliminateFrame = true; 581 bool CS1Spilled = false; 582 bool LRSpilled = false; 583 unsigned NumGPRSpills = 0; 584 SmallVector<unsigned, 4> UnspilledCS1GPRs; 585 SmallVector<unsigned, 4> UnspilledCS2GPRs; 586 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 587 588 MachineFrameInfo *MFI = MF.getFrameInfo(); 589 590 // Calculate and set max stack object alignment early, so we can decide 591 // whether we will need stack realignment (and thus FP). 592 if (RealignStack) { 593 unsigned MaxAlign = std::max(MFI->getMaxAlignment(), 594 calculateMaxStackAlignment(MFI)); 595 MFI->setMaxAlignment(MaxAlign); 596 } 597 598 // Don't spill FP if the frame can be eliminated. This is determined 599 // by scanning the callee-save registers to see if any is used. 600 const unsigned *CSRegs = getCalleeSavedRegs(); 601 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 602 for (unsigned i = 0; CSRegs[i]; ++i) { 603 unsigned Reg = CSRegs[i]; 604 bool Spilled = false; 605 if (MF.getRegInfo().isPhysRegUsed(Reg)) { 606 AFI->setCSRegisterIsSpilled(Reg); 607 Spilled = true; 608 CanEliminateFrame = false; 609 } else { 610 // Check alias registers too. 611 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 612 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 613 Spilled = true; 614 CanEliminateFrame = false; 615 } 616 } 617 } 618 619 if (CSRegClasses[i] == ARM::GPRRegisterClass || 620 CSRegClasses[i] == ARM::tGPRRegisterClass) { 621 if (Spilled) { 622 NumGPRSpills++; 623 624 if (!STI.isTargetDarwin()) { 625 if (Reg == ARM::LR) 626 LRSpilled = true; 627 CS1Spilled = true; 628 continue; 629 } 630 631 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 632 switch (Reg) { 633 case ARM::LR: 634 LRSpilled = true; 635 // Fallthrough 636 case ARM::R4: 637 case ARM::R5: 638 case ARM::R6: 639 case ARM::R7: 640 CS1Spilled = true; 641 break; 642 default: 643 break; 644 } 645 } else { 646 if (!STI.isTargetDarwin()) { 647 UnspilledCS1GPRs.push_back(Reg); 648 continue; 649 } 650 651 switch (Reg) { 652 case ARM::R4: 653 case ARM::R5: 654 case ARM::R6: 655 case ARM::R7: 656 case ARM::LR: 657 UnspilledCS1GPRs.push_back(Reg); 658 break; 659 default: 660 UnspilledCS2GPRs.push_back(Reg); 661 break; 662 } 663 } 664 } 665 } 666 667 bool ForceLRSpill = false; 668 if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 669 unsigned FnSize = TII.GetFunctionSizeInBytes(MF); 670 // Force LR to be spilled if the Thumb function size is > 2048. This enables 671 // use of BL to implement far jump. If it turns out that it's not needed 672 // then the branch fix up path will undo it. 673 if (FnSize >= (1 << 11)) { 674 CanEliminateFrame = false; 675 ForceLRSpill = true; 676 } 677 } 678 679 bool ExtraCSSpill = false; 680 if (!CanEliminateFrame || cannotEliminateFrame(MF)) { 681 AFI->setHasStackFrame(true); 682 683 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 684 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 685 if (!LRSpilled && CS1Spilled) { 686 MF.getRegInfo().setPhysRegUsed(ARM::LR); 687 AFI->setCSRegisterIsSpilled(ARM::LR); 688 NumGPRSpills++; 689 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 690 UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 691 ForceLRSpill = false; 692 ExtraCSSpill = true; 693 } 694 695 // Darwin ABI requires FP to point to the stack slot that contains the 696 // previous FP. 697 if (STI.isTargetDarwin() || hasFP(MF)) { 698 MF.getRegInfo().setPhysRegUsed(FramePtr); 699 NumGPRSpills++; 700 } 701 702 // If stack and double are 8-byte aligned and we are spilling an odd number 703 // of GPRs. Spill one extra callee save GPR so we won't have to pad between 704 // the integer and double callee save areas. 705 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 706 if (TargetAlign == 8 && (NumGPRSpills & 1)) { 707 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 708 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 709 unsigned Reg = UnspilledCS1GPRs[i]; 710 // Don't spill high register if the function is thumb1 711 if (!AFI->isThumb1OnlyFunction() || 712 isARMLowRegister(Reg) || Reg == ARM::LR) { 713 MF.getRegInfo().setPhysRegUsed(Reg); 714 AFI->setCSRegisterIsSpilled(Reg); 715 if (!isReservedReg(MF, Reg)) 716 ExtraCSSpill = true; 717 break; 718 } 719 } 720 } else if (!UnspilledCS2GPRs.empty() && 721 !AFI->isThumb1OnlyFunction()) { 722 unsigned Reg = UnspilledCS2GPRs.front(); 723 MF.getRegInfo().setPhysRegUsed(Reg); 724 AFI->setCSRegisterIsSpilled(Reg); 725 if (!isReservedReg(MF, Reg)) 726 ExtraCSSpill = true; 727 } 728 } 729 730 // Estimate if we might need to scavenge a register at some point in order 731 // to materialize a stack offset. If so, either spill one additional 732 // callee-saved register or reserve a special spill slot to facilitate 733 // register scavenging. Thumb1 needs a spill slot for stack pointer 734 // adjustments also, even when the frame itself is small. 735 if (RS && !ExtraCSSpill) { 736 MachineFrameInfo *MFI = MF.getFrameInfo(); 737 // If any of the stack slot references may be out of range of an 738 // immediate offset, make sure a register (or a spill slot) is 739 // available for the register scavenger. Note that if we're indexing 740 // off the frame pointer, the effective stack size is 4 bytes larger 741 // since the FP points to the stack slot of the previous FP. 742 if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0) 743 >= estimateRSStackSizeLimit(MF)) { 744 // If any non-reserved CS register isn't spilled, just spill one or two 745 // extra. That should take care of it! 746 unsigned NumExtras = TargetAlign / 4; 747 SmallVector<unsigned, 2> Extras; 748 while (NumExtras && !UnspilledCS1GPRs.empty()) { 749 unsigned Reg = UnspilledCS1GPRs.back(); 750 UnspilledCS1GPRs.pop_back(); 751 if (!isReservedReg(MF, Reg)) { 752 Extras.push_back(Reg); 753 NumExtras--; 754 } 755 } 756 // For non-Thumb1 functions, also check for hi-reg CS registers 757 if (!AFI->isThumb1OnlyFunction()) { 758 while (NumExtras && !UnspilledCS2GPRs.empty()) { 759 unsigned Reg = UnspilledCS2GPRs.back(); 760 UnspilledCS2GPRs.pop_back(); 761 if (!isReservedReg(MF, Reg)) { 762 Extras.push_back(Reg); 763 NumExtras--; 764 } 765 } 766 } 767 if (Extras.size() && NumExtras == 0) { 768 for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 769 MF.getRegInfo().setPhysRegUsed(Extras[i]); 770 AFI->setCSRegisterIsSpilled(Extras[i]); 771 } 772 } else if (!AFI->isThumb1OnlyFunction()) { 773 // note: Thumb1 functions spill to R12, not the stack. 774 // Reserve a slot closest to SP or frame pointer. 775 const TargetRegisterClass *RC = ARM::GPRRegisterClass; 776 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 777 RC->getAlignment(), 778 false)); 779 } 780 } 781 } 782 } 783 784 if (ForceLRSpill) { 785 MF.getRegInfo().setPhysRegUsed(ARM::LR); 786 AFI->setCSRegisterIsSpilled(ARM::LR); 787 AFI->setLRIsSpilledForFarJump(true); 788 } 789} 790 791unsigned ARMBaseRegisterInfo::getRARegister() const { 792 return ARM::LR; 793} 794 795unsigned 796ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 797 if (STI.isTargetDarwin() || hasFP(MF)) 798 return FramePtr; 799 return ARM::SP; 800} 801 802int 803ARMBaseRegisterInfo::getFrameIndexReference(MachineFunction &MF, int FI, 804 unsigned &FrameReg) const { 805 const MachineFrameInfo *MFI = MF.getFrameInfo(); 806 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 807 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); 808 bool isFixed = MFI->isFixedObjectIndex(FI); 809 810 FrameReg = ARM::SP; 811 if (AFI->isGPRCalleeSavedArea1Frame(FI)) 812 Offset -= AFI->getGPRCalleeSavedArea1Offset(); 813 else if (AFI->isGPRCalleeSavedArea2Frame(FI)) 814 Offset -= AFI->getGPRCalleeSavedArea2Offset(); 815 else if (AFI->isDPRCalleeSavedAreaFrame(FI)) 816 Offset -= AFI->getDPRCalleeSavedAreaOffset(); 817 else if (needsStackRealignment(MF)) { 818 // When dynamically realigning the stack, use the frame pointer for 819 // parameters, and the stack pointer for locals. 820 assert (hasFP(MF) && "dynamic stack realignment without a FP!"); 821 if (isFixed) { 822 FrameReg = getFrameRegister(MF); 823 Offset -= AFI->getFramePtrSpillOffset(); 824 } 825 } else if (hasFP(MF) && AFI->hasStackFrame()) { 826 if (isFixed || MFI->hasVarSizedObjects()) { 827 // Use frame pointer to reference fixed objects unless this is a 828 // frameless function. 829 FrameReg = getFrameRegister(MF); 830 Offset -= AFI->getFramePtrSpillOffset(); 831 } else if (AFI->isThumb2Function()) { 832 // In Thumb2 mode, the negative offset is very limited. 833 int FPOffset = Offset - AFI->getFramePtrSpillOffset(); 834 if (FPOffset >= -255 && FPOffset < 0) { 835 FrameReg = getFrameRegister(MF); 836 Offset = FPOffset; 837 } 838 } 839 } 840 return Offset; 841} 842 843 844int 845ARMBaseRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const { 846 unsigned FrameReg; 847 return getFrameIndexReference(MF, FI, FrameReg); 848} 849 850unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 851 llvm_unreachable("What is the exception register"); 852 return 0; 853} 854 855unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 856 llvm_unreachable("What is the exception handler register"); 857 return 0; 858} 859 860int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 861 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 862} 863 864unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 865 const MachineFunction &MF) const { 866 switch (Reg) { 867 default: break; 868 // Return 0 if either register of the pair is a special register. 869 // So no R12, etc. 870 case ARM::R1: 871 return ARM::R0; 872 case ARM::R3: 873 return ARM::R2; 874 case ARM::R5: 875 return ARM::R4; 876 case ARM::R7: 877 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; 878 case ARM::R9: 879 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; 880 case ARM::R11: 881 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; 882 883 case ARM::S1: 884 return ARM::S0; 885 case ARM::S3: 886 return ARM::S2; 887 case ARM::S5: 888 return ARM::S4; 889 case ARM::S7: 890 return ARM::S6; 891 case ARM::S9: 892 return ARM::S8; 893 case ARM::S11: 894 return ARM::S10; 895 case ARM::S13: 896 return ARM::S12; 897 case ARM::S15: 898 return ARM::S14; 899 case ARM::S17: 900 return ARM::S16; 901 case ARM::S19: 902 return ARM::S18; 903 case ARM::S21: 904 return ARM::S20; 905 case ARM::S23: 906 return ARM::S22; 907 case ARM::S25: 908 return ARM::S24; 909 case ARM::S27: 910 return ARM::S26; 911 case ARM::S29: 912 return ARM::S28; 913 case ARM::S31: 914 return ARM::S30; 915 916 case ARM::D1: 917 return ARM::D0; 918 case ARM::D3: 919 return ARM::D2; 920 case ARM::D5: 921 return ARM::D4; 922 case ARM::D7: 923 return ARM::D6; 924 case ARM::D9: 925 return ARM::D8; 926 case ARM::D11: 927 return ARM::D10; 928 case ARM::D13: 929 return ARM::D12; 930 case ARM::D15: 931 return ARM::D14; 932 case ARM::D17: 933 return ARM::D16; 934 case ARM::D19: 935 return ARM::D18; 936 case ARM::D21: 937 return ARM::D20; 938 case ARM::D23: 939 return ARM::D22; 940 case ARM::D25: 941 return ARM::D24; 942 case ARM::D27: 943 return ARM::D26; 944 case ARM::D29: 945 return ARM::D28; 946 case ARM::D31: 947 return ARM::D30; 948 } 949 950 return 0; 951} 952 953unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 954 const MachineFunction &MF) const { 955 switch (Reg) { 956 default: break; 957 // Return 0 if either register of the pair is a special register. 958 // So no R12, etc. 959 case ARM::R0: 960 return ARM::R1; 961 case ARM::R2: 962 return ARM::R3; 963 case ARM::R4: 964 return ARM::R5; 965 case ARM::R6: 966 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; 967 case ARM::R8: 968 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; 969 case ARM::R10: 970 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; 971 972 case ARM::S0: 973 return ARM::S1; 974 case ARM::S2: 975 return ARM::S3; 976 case ARM::S4: 977 return ARM::S5; 978 case ARM::S6: 979 return ARM::S7; 980 case ARM::S8: 981 return ARM::S9; 982 case ARM::S10: 983 return ARM::S11; 984 case ARM::S12: 985 return ARM::S13; 986 case ARM::S14: 987 return ARM::S15; 988 case ARM::S16: 989 return ARM::S17; 990 case ARM::S18: 991 return ARM::S19; 992 case ARM::S20: 993 return ARM::S21; 994 case ARM::S22: 995 return ARM::S23; 996 case ARM::S24: 997 return ARM::S25; 998 case ARM::S26: 999 return ARM::S27; 1000 case ARM::S28: 1001 return ARM::S29; 1002 case ARM::S30: 1003 return ARM::S31; 1004 1005 case ARM::D0: 1006 return ARM::D1; 1007 case ARM::D2: 1008 return ARM::D3; 1009 case ARM::D4: 1010 return ARM::D5; 1011 case ARM::D6: 1012 return ARM::D7; 1013 case ARM::D8: 1014 return ARM::D9; 1015 case ARM::D10: 1016 return ARM::D11; 1017 case ARM::D12: 1018 return ARM::D13; 1019 case ARM::D14: 1020 return ARM::D15; 1021 case ARM::D16: 1022 return ARM::D17; 1023 case ARM::D18: 1024 return ARM::D19; 1025 case ARM::D20: 1026 return ARM::D21; 1027 case ARM::D22: 1028 return ARM::D23; 1029 case ARM::D24: 1030 return ARM::D25; 1031 case ARM::D26: 1032 return ARM::D27; 1033 case ARM::D28: 1034 return ARM::D29; 1035 case ARM::D30: 1036 return ARM::D31; 1037 } 1038 1039 return 0; 1040} 1041 1042/// emitLoadConstPool - Emits a load from constpool to materialize the 1043/// specified immediate. 1044void ARMBaseRegisterInfo:: 1045emitLoadConstPool(MachineBasicBlock &MBB, 1046 MachineBasicBlock::iterator &MBBI, 1047 DebugLoc dl, 1048 unsigned DestReg, unsigned SubIdx, int Val, 1049 ARMCC::CondCodes Pred, 1050 unsigned PredReg) const { 1051 MachineFunction &MF = *MBB.getParent(); 1052 MachineConstantPool *ConstantPool = MF.getConstantPool(); 1053 Constant *C = 1054 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 1055 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 1056 1057 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 1058 .addReg(DestReg, getDefRegState(true), SubIdx) 1059 .addConstantPoolIndex(Idx) 1060 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 1061} 1062 1063bool ARMBaseRegisterInfo:: 1064requiresRegisterScavenging(const MachineFunction &MF) const { 1065 return true; 1066} 1067 1068bool ARMBaseRegisterInfo:: 1069requiresFrameIndexScavenging(const MachineFunction &MF) const { 1070 return true; 1071} 1072 1073// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 1074// not required, we reserve argument space for call sites in the function 1075// immediately on entry to the current function. This eliminates the need for 1076// add/sub sp brackets around call sites. Returns true if the call frame is 1077// included as part of the stack frame. 1078bool ARMBaseRegisterInfo:: 1079hasReservedCallFrame(MachineFunction &MF) const { 1080 const MachineFrameInfo *FFI = MF.getFrameInfo(); 1081 unsigned CFSize = FFI->getMaxCallFrameSize(); 1082 // It's not always a good idea to include the call frame as part of the 1083 // stack frame. ARM (especially Thumb) has small immediate offset to 1084 // address the stack frame. So a large call frame can cause poor codegen 1085 // and may even makes it impossible to scavenge a register. 1086 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 1087 return false; 1088 1089 return !MF.getFrameInfo()->hasVarSizedObjects(); 1090} 1091 1092static void 1093emitSPUpdate(bool isARM, 1094 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 1095 DebugLoc dl, const ARMBaseInstrInfo &TII, 1096 int NumBytes, 1097 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 1098 if (isARM) 1099 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 1100 Pred, PredReg, TII); 1101 else 1102 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 1103 Pred, PredReg, TII); 1104} 1105 1106 1107void ARMBaseRegisterInfo:: 1108eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1109 MachineBasicBlock::iterator I) const { 1110 if (!hasReservedCallFrame(MF)) { 1111 // If we have alloca, convert as follows: 1112 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 1113 // ADJCALLSTACKUP -> add, sp, sp, amount 1114 MachineInstr *Old = I; 1115 DebugLoc dl = Old->getDebugLoc(); 1116 unsigned Amount = Old->getOperand(0).getImm(); 1117 if (Amount != 0) { 1118 // We need to keep the stack aligned properly. To do this, we round the 1119 // amount of space needed for the outgoing arguments up to the next 1120 // alignment boundary. 1121 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1122 Amount = (Amount+Align-1)/Align*Align; 1123 1124 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1125 assert(!AFI->isThumb1OnlyFunction() && 1126 "This eliminateCallFramePseudoInstr does not suppor Thumb1!"); 1127 bool isARM = !AFI->isThumbFunction(); 1128 1129 // Replace the pseudo instruction with a new instruction... 1130 unsigned Opc = Old->getOpcode(); 1131 ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm(); 1132 // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN? 1133 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 1134 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 1135 unsigned PredReg = Old->getOperand(2).getReg(); 1136 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 1137 } else { 1138 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 1139 unsigned PredReg = Old->getOperand(3).getReg(); 1140 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 1141 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 1142 } 1143 } 1144 } 1145 MBB.erase(I); 1146} 1147 1148unsigned 1149ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 1150 int SPAdj, int *Value, 1151 RegScavenger *RS) const { 1152 unsigned i = 0; 1153 MachineInstr &MI = *II; 1154 MachineBasicBlock &MBB = *MI.getParent(); 1155 MachineFunction &MF = *MBB.getParent(); 1156 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1157 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1158 assert(!AFI->isThumb1OnlyFunction() && 1159 "This eliminateFrameIndex does not support Thumb1!"); 1160 1161 while (!MI.getOperand(i).isFI()) { 1162 ++i; 1163 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 1164 } 1165 1166 int FrameIndex = MI.getOperand(i).getIndex(); 1167 int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj; 1168 unsigned FrameReg; 1169 1170 Offset = getFrameIndexReference(MF, FrameIndex, FrameReg); 1171 if (FrameReg != ARM::SP) 1172 SPAdj = 0; 1173 1174 // Modify MI as necessary to handle as much of 'Offset' as possible 1175 bool Done = false; 1176 if (!AFI->isThumbFunction()) 1177 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 1178 else { 1179 assert(AFI->isThumb2Function()); 1180 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 1181 } 1182 if (Done) 1183 return 0; 1184 1185 // If we get here, the immediate doesn't fit into the instruction. We folded 1186 // as much as possible above, handle the rest, providing a register that is 1187 // SP+LargeImm. 1188 assert((Offset || 1189 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 1190 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 1191 "This code isn't needed if offset already handled!"); 1192 1193 unsigned ScratchReg = 0; 1194 int PIdx = MI.findFirstPredOperandIdx(); 1195 ARMCC::CondCodes Pred = (PIdx == -1) 1196 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1197 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1198 if (Offset == 0) 1199 // Must be addrmode4/6. 1200 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 1201 else { 1202 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass); 1203 if (Value) *Value = Offset; 1204 if (!AFI->isThumbFunction()) 1205 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1206 Offset, Pred, PredReg, TII); 1207 else { 1208 assert(AFI->isThumb2Function()); 1209 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1210 Offset, Pred, PredReg, TII); 1211 } 1212 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1213 if (!ReuseFrameIndexVals) 1214 ScratchReg = 0; 1215 } 1216 return ScratchReg; 1217} 1218 1219/// Move iterator past the next bunch of callee save load / store ops for 1220/// the particular spill area (1: integer area 1, 2: integer area 2, 1221/// 3: fp area, 0: don't care). 1222static void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1223 MachineBasicBlock::iterator &MBBI, 1224 int Opc1, int Opc2, unsigned Area, 1225 const ARMSubtarget &STI) { 1226 while (MBBI != MBB.end() && 1227 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) && 1228 MBBI->getOperand(1).isFI()) { 1229 if (Area != 0) { 1230 bool Done = false; 1231 unsigned Category = 0; 1232 switch (MBBI->getOperand(0).getReg()) { 1233 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1234 case ARM::LR: 1235 Category = 1; 1236 break; 1237 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1238 Category = STI.isTargetDarwin() ? 2 : 1; 1239 break; 1240 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 1241 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1242 Category = 3; 1243 break; 1244 default: 1245 Done = true; 1246 break; 1247 } 1248 if (Done || Category != Area) 1249 break; 1250 } 1251 1252 ++MBBI; 1253 } 1254} 1255 1256void ARMBaseRegisterInfo:: 1257emitPrologue(MachineFunction &MF) const { 1258 MachineBasicBlock &MBB = MF.front(); 1259 MachineBasicBlock::iterator MBBI = MBB.begin(); 1260 MachineFrameInfo *MFI = MF.getFrameInfo(); 1261 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1262 assert(!AFI->isThumb1OnlyFunction() && 1263 "This emitPrologue does not suppor Thumb1!"); 1264 bool isARM = !AFI->isThumbFunction(); 1265 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1266 unsigned NumBytes = MFI->getStackSize(); 1267 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1268 DebugLoc dl = (MBBI != MBB.end() ? 1269 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); 1270 1271 // Determine the sizes of each callee-save spill areas and record which frame 1272 // belongs to which callee-save spill areas. 1273 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1274 int FramePtrSpillFI = 0; 1275 1276 // Allocate the vararg register save area. This is not counted in NumBytes. 1277 if (VARegSaveSize) 1278 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize); 1279 1280 if (!AFI->hasStackFrame()) { 1281 if (NumBytes != 0) 1282 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1283 return; 1284 } 1285 1286 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1287 unsigned Reg = CSI[i].getReg(); 1288 int FI = CSI[i].getFrameIdx(); 1289 switch (Reg) { 1290 case ARM::R4: 1291 case ARM::R5: 1292 case ARM::R6: 1293 case ARM::R7: 1294 case ARM::LR: 1295 if (Reg == FramePtr) 1296 FramePtrSpillFI = FI; 1297 AFI->addGPRCalleeSavedArea1Frame(FI); 1298 GPRCS1Size += 4; 1299 break; 1300 case ARM::R8: 1301 case ARM::R9: 1302 case ARM::R10: 1303 case ARM::R11: 1304 if (Reg == FramePtr) 1305 FramePtrSpillFI = FI; 1306 if (STI.isTargetDarwin()) { 1307 AFI->addGPRCalleeSavedArea2Frame(FI); 1308 GPRCS2Size += 4; 1309 } else { 1310 AFI->addGPRCalleeSavedArea1Frame(FI); 1311 GPRCS1Size += 4; 1312 } 1313 break; 1314 default: 1315 AFI->addDPRCalleeSavedAreaFrame(FI); 1316 DPRCSSize += 8; 1317 } 1318 } 1319 1320 // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1321 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); 1322 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI); 1323 1324 // Set FP to point to the stack slot that contains the previous FP. 1325 // For Darwin, FP is R7, which has now been stored in spill area 1. 1326 // Otherwise, if this is not Darwin, all the callee-saved registers go 1327 // into spill area 1, including the FP in R11. In either case, it is 1328 // now safe to emit this assignment. 1329 if (STI.isTargetDarwin() || hasFP(MF)) { 1330 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; 1331 MachineInstrBuilder MIB = 1332 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 1333 .addFrameIndex(FramePtrSpillFI).addImm(0); 1334 AddDefaultCC(AddDefaultPred(MIB)); 1335 } 1336 1337 // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1338 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); 1339 1340 // Build the new SUBri to adjust SP for FP callee-save spill area. 1341 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI); 1342 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); 1343 1344 // Determine starting offsets of spill areas. 1345 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1346 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1347 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1348 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1349 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1350 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1351 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1352 1353 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI); 1354 NumBytes = DPRCSOffset; 1355 if (NumBytes) { 1356 // Adjust SP after all the callee-save spills. 1357 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1358 } 1359 1360 if (STI.isTargetELF() && hasFP(MF)) { 1361 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1362 AFI->getFramePtrSpillOffset()); 1363 } 1364 1365 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1366 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1367 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1368 1369 // If we need dynamic stack realignment, do it here. 1370 if (needsStackRealignment(MF)) { 1371 unsigned Opc; 1372 unsigned MaxAlign = MFI->getMaxAlignment(); 1373 assert (!AFI->isThumb1OnlyFunction()); 1374 Opc = AFI->isThumbFunction() ? ARM::t2BICri : ARM::BICri; 1375 1376 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), ARM::SP) 1377 .addReg(ARM::SP, RegState::Kill) 1378 .addImm(MaxAlign-1))); 1379 } 1380} 1381 1382static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1383 for (unsigned i = 0; CSRegs[i]; ++i) 1384 if (Reg == CSRegs[i]) 1385 return true; 1386 return false; 1387} 1388 1389static bool isCSRestore(MachineInstr *MI, 1390 const ARMBaseInstrInfo &TII, 1391 const unsigned *CSRegs) { 1392 return ((MI->getOpcode() == (int)ARM::VLDRD || 1393 MI->getOpcode() == (int)ARM::LDR || 1394 MI->getOpcode() == (int)ARM::t2LDRi12) && 1395 MI->getOperand(1).isFI() && 1396 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 1397} 1398 1399void ARMBaseRegisterInfo:: 1400emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { 1401 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1402 assert(MBBI->getDesc().isReturn() && 1403 "Can only insert epilog into returning blocks"); 1404 DebugLoc dl = MBBI->getDebugLoc(); 1405 MachineFrameInfo *MFI = MF.getFrameInfo(); 1406 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1407 assert(!AFI->isThumb1OnlyFunction() && 1408 "This emitEpilogue does not suppor Thumb1!"); 1409 bool isARM = !AFI->isThumbFunction(); 1410 1411 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1412 int NumBytes = (int)MFI->getStackSize(); 1413 1414 if (!AFI->hasStackFrame()) { 1415 if (NumBytes != 0) 1416 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1417 } else { 1418 // Unwind MBBI to point to first LDR / VLDRD. 1419 const unsigned *CSRegs = getCalleeSavedRegs(); 1420 if (MBBI != MBB.begin()) { 1421 do 1422 --MBBI; 1423 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 1424 if (!isCSRestore(MBBI, TII, CSRegs)) 1425 ++MBBI; 1426 } 1427 1428 // Move SP to start of FP callee save spill area. 1429 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1430 AFI->getGPRCalleeSavedArea2Size() + 1431 AFI->getDPRCalleeSavedAreaSize()); 1432 1433 // Darwin ABI requires FP to point to the stack slot that contains the 1434 // previous FP. 1435 bool HasFP = hasFP(MF); 1436 if ((STI.isTargetDarwin() && NumBytes) || HasFP) { 1437 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1438 // Reset SP based on frame pointer only if the stack frame extends beyond 1439 // frame pointer stack slot or target is ELF and the function has FP. 1440 if (HasFP || 1441 AFI->getGPRCalleeSavedArea2Size() || 1442 AFI->getDPRCalleeSavedAreaSize() || 1443 AFI->getDPRCalleeSavedAreaOffset()) { 1444 if (NumBytes) { 1445 if (isARM) 1446 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1447 ARMCC::AL, 0, TII); 1448 else 1449 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1450 ARMCC::AL, 0, TII); 1451 } else { 1452 // Thumb2 or ARM. 1453 if (isARM) 1454 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 1455 .addReg(FramePtr) 1456 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1457 else 1458 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP) 1459 .addReg(FramePtr); 1460 } 1461 } 1462 } else if (NumBytes) 1463 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1464 1465 // Move SP to start of integer callee save spill area 2. 1466 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI); 1467 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); 1468 1469 // Move SP to start of integer callee save spill area 1. 1470 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI); 1471 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); 1472 1473 // Move SP to SP upon entry to the function. 1474 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI); 1475 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); 1476 } 1477 1478 if (VARegSaveSize) 1479 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); 1480} 1481 1482namespace { 1483 struct MaximalStackAlignmentCalculator : public MachineFunctionPass { 1484 static char ID; 1485 MaximalStackAlignmentCalculator() : MachineFunctionPass(&ID) {} 1486 1487 virtual bool runOnMachineFunction(MachineFunction &MF) { 1488 MachineFrameInfo *FFI = MF.getFrameInfo(); 1489 MachineRegisterInfo &RI = MF.getRegInfo(); 1490 1491 // Calculate max stack alignment of all already allocated stack objects. 1492 unsigned MaxAlign = calculateMaxStackAlignment(FFI); 1493 1494 // Be over-conservative: scan over all vreg defs and find, whether vector 1495 // registers are used. If yes - there is probability, that vector register 1496 // will be spilled and thus stack needs to be aligned properly. 1497 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister; 1498 RegNum < RI.getLastVirtReg(); ++RegNum) 1499 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment()); 1500 1501 if (FFI->getMaxAlignment() == MaxAlign) 1502 return false; 1503 1504 FFI->setMaxAlignment(MaxAlign); 1505 return true; 1506 } 1507 1508 virtual const char *getPassName() const { 1509 return "ARM Stack Required Alignment Auto-Detector"; 1510 } 1511 1512 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 1513 AU.setPreservesCFG(); 1514 MachineFunctionPass::getAnalysisUsage(AU); 1515 } 1516 }; 1517 1518 char MaximalStackAlignmentCalculator::ID = 0; 1519} 1520 1521FunctionPass* 1522llvm::createARMMaxStackAlignmentCalculatorPass() { 1523 return new MaximalStackAlignmentCalculator(); 1524} 1525 1526#include "ARMGenRegisterInfo.inc" 1527