ARMBaseRegisterInfo.cpp revision 198396 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/raw_ostream.h"
34#include "llvm/Target/TargetFrameInfo.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37#include "llvm/ADT/BitVector.h"
38#include "llvm/ADT/SmallVector.h"
39#include "llvm/Support/CommandLine.h"
40using namespace llvm;
41
42static cl::opt<bool>
43ScavengeFrameIndexVals("arm-virtual-frame-index-vals", cl::Hidden,
44          cl::init(false),
45          cl::desc("Resolve frame index values via scavenging in PEI"));
46
47static cl::opt<bool>
48ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(false),
49          cl::desc("Reuse repeated frame index values"));
50
51unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
52                                                   bool *isSPVFP) {
53  if (isSPVFP)
54    *isSPVFP = false;
55
56  using namespace ARM;
57  switch (RegEnum) {
58  default:
59    llvm_unreachable("Unknown ARM register!");
60  case R0:  case D0:  case Q0:  return 0;
61  case R1:  case D1:  case Q1:  return 1;
62  case R2:  case D2:  case Q2:  return 2;
63  case R3:  case D3:  case Q3:  return 3;
64  case R4:  case D4:  case Q4:  return 4;
65  case R5:  case D5:  case Q5:  return 5;
66  case R6:  case D6:  case Q6:  return 6;
67  case R7:  case D7:  case Q7:  return 7;
68  case R8:  case D8:  case Q8:  return 8;
69  case R9:  case D9:  case Q9:  return 9;
70  case R10: case D10: case Q10: return 10;
71  case R11: case D11: case Q11: return 11;
72  case R12: case D12: case Q12: return 12;
73  case SP:  case D13: case Q13: return 13;
74  case LR:  case D14: case Q14: return 14;
75  case PC:  case D15: case Q15: return 15;
76
77  case D16: return 16;
78  case D17: return 17;
79  case D18: return 18;
80  case D19: return 19;
81  case D20: return 20;
82  case D21: return 21;
83  case D22: return 22;
84  case D23: return 23;
85  case D24: return 24;
86  case D25: return 25;
87  case D26: return 27;
88  case D27: return 27;
89  case D28: return 28;
90  case D29: return 29;
91  case D30: return 30;
92  case D31: return 31;
93
94  case S0: case S1: case S2: case S3:
95  case S4: case S5: case S6: case S7:
96  case S8: case S9: case S10: case S11:
97  case S12: case S13: case S14: case S15:
98  case S16: case S17: case S18: case S19:
99  case S20: case S21: case S22: case S23:
100  case S24: case S25: case S26: case S27:
101  case S28: case S29: case S30: case S31: {
102    if (isSPVFP)
103      *isSPVFP = true;
104    switch (RegEnum) {
105    default: return 0; // Avoid compile time warning.
106    case S0: return 0;
107    case S1: return 1;
108    case S2: return 2;
109    case S3: return 3;
110    case S4: return 4;
111    case S5: return 5;
112    case S6: return 6;
113    case S7: return 7;
114    case S8: return 8;
115    case S9: return 9;
116    case S10: return 10;
117    case S11: return 11;
118    case S12: return 12;
119    case S13: return 13;
120    case S14: return 14;
121    case S15: return 15;
122    case S16: return 16;
123    case S17: return 17;
124    case S18: return 18;
125    case S19: return 19;
126    case S20: return 20;
127    case S21: return 21;
128    case S22: return 22;
129    case S23: return 23;
130    case S24: return 24;
131    case S25: return 25;
132    case S26: return 26;
133    case S27: return 27;
134    case S28: return 28;
135    case S29: return 29;
136    case S30: return 30;
137    case S31: return 31;
138    }
139  }
140  }
141}
142
143ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
144                                         const ARMSubtarget &sti)
145  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
146    TII(tii), STI(sti),
147    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
148}
149
150const unsigned*
151ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
152  static const unsigned CalleeSavedRegs[] = {
153    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
154    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
155
156    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
157    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
158    0
159  };
160
161  static const unsigned DarwinCalleeSavedRegs[] = {
162    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
163    // register.
164    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
165    ARM::R11, ARM::R10, ARM::R8,
166
167    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
168    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
169    0
170  };
171  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
172}
173
174const TargetRegisterClass* const *
175ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
176  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
177    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
178    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
179    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
180
181    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
182    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
183    0
184  };
185
186  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
187    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
188    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
189    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
190
191    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
192    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
193    0
194  };
195
196  static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
197    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
198    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
199    &ARM::GPRRegClass, &ARM::GPRRegClass,
200
201    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
202    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
203    0
204  };
205
206  static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
207    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
208    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
209    &ARM::GPRRegClass,  &ARM::GPRRegClass,
210
211    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
212    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
213    0
214  };
215
216  if (STI.isThumb1Only()) {
217    return STI.isTargetDarwin()
218      ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
219  }
220  return STI.isTargetDarwin()
221    ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
222}
223
224BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
225  // FIXME: avoid re-calculating this everytime.
226  BitVector Reserved(getNumRegs());
227  Reserved.set(ARM::SP);
228  Reserved.set(ARM::PC);
229  if (STI.isTargetDarwin() || hasFP(MF))
230    Reserved.set(FramePtr);
231  // Some targets reserve R9.
232  if (STI.isR9Reserved())
233    Reserved.set(ARM::R9);
234  return Reserved;
235}
236
237bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
238                                        unsigned Reg) const {
239  switch (Reg) {
240  default: break;
241  case ARM::SP:
242  case ARM::PC:
243    return true;
244  case ARM::R7:
245  case ARM::R11:
246    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
247      return true;
248    break;
249  case ARM::R9:
250    return STI.isR9Reserved();
251  }
252
253  return false;
254}
255
256const TargetRegisterClass *
257ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
258  return ARM::GPRRegisterClass;
259}
260
261/// getAllocationOrder - Returns the register allocation order for a specified
262/// register class in the form of a pair of TargetRegisterClass iterators.
263std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
264ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
265                                        unsigned HintType, unsigned HintReg,
266                                        const MachineFunction &MF) const {
267  // Alternative register allocation orders when favoring even / odd registers
268  // of register pairs.
269
270  // No FP, R9 is available.
271  static const unsigned GPREven1[] = {
272    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
273    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
274    ARM::R9, ARM::R11
275  };
276  static const unsigned GPROdd1[] = {
277    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
278    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
279    ARM::R8, ARM::R10
280  };
281
282  // FP is R7, R9 is available.
283  static const unsigned GPREven2[] = {
284    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
285    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
286    ARM::R9, ARM::R11
287  };
288  static const unsigned GPROdd2[] = {
289    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
290    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
291    ARM::R8, ARM::R10
292  };
293
294  // FP is R11, R9 is available.
295  static const unsigned GPREven3[] = {
296    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
297    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
298    ARM::R9
299  };
300  static const unsigned GPROdd3[] = {
301    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
302    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
303    ARM::R8
304  };
305
306  // No FP, R9 is not available.
307  static const unsigned GPREven4[] = {
308    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
309    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
310    ARM::R11
311  };
312  static const unsigned GPROdd4[] = {
313    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
314    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
315    ARM::R10
316  };
317
318  // FP is R7, R9 is not available.
319  static const unsigned GPREven5[] = {
320    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
321    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
322    ARM::R11
323  };
324  static const unsigned GPROdd5[] = {
325    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
326    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
327    ARM::R10
328  };
329
330  // FP is R11, R9 is not available.
331  static const unsigned GPREven6[] = {
332    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
333    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
334  };
335  static const unsigned GPROdd6[] = {
336    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
337    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
338  };
339
340
341  if (HintType == ARMRI::RegPairEven) {
342    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
343      // It's no longer possible to fulfill this hint. Return the default
344      // allocation order.
345      return std::make_pair(RC->allocation_order_begin(MF),
346                            RC->allocation_order_end(MF));
347
348    if (!STI.isTargetDarwin() && !hasFP(MF)) {
349      if (!STI.isR9Reserved())
350        return std::make_pair(GPREven1,
351                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
352      else
353        return std::make_pair(GPREven4,
354                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
355    } else if (FramePtr == ARM::R7) {
356      if (!STI.isR9Reserved())
357        return std::make_pair(GPREven2,
358                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
359      else
360        return std::make_pair(GPREven5,
361                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
362    } else { // FramePtr == ARM::R11
363      if (!STI.isR9Reserved())
364        return std::make_pair(GPREven3,
365                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
366      else
367        return std::make_pair(GPREven6,
368                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
369    }
370  } else if (HintType == ARMRI::RegPairOdd) {
371    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
372      // It's no longer possible to fulfill this hint. Return the default
373      // allocation order.
374      return std::make_pair(RC->allocation_order_begin(MF),
375                            RC->allocation_order_end(MF));
376
377    if (!STI.isTargetDarwin() && !hasFP(MF)) {
378      if (!STI.isR9Reserved())
379        return std::make_pair(GPROdd1,
380                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
381      else
382        return std::make_pair(GPROdd4,
383                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
384    } else if (FramePtr == ARM::R7) {
385      if (!STI.isR9Reserved())
386        return std::make_pair(GPROdd2,
387                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
388      else
389        return std::make_pair(GPROdd5,
390                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
391    } else { // FramePtr == ARM::R11
392      if (!STI.isR9Reserved())
393        return std::make_pair(GPROdd3,
394                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
395      else
396        return std::make_pair(GPROdd6,
397                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
398    }
399  }
400  return std::make_pair(RC->allocation_order_begin(MF),
401                        RC->allocation_order_end(MF));
402}
403
404/// ResolveRegAllocHint - Resolves the specified register allocation hint
405/// to a physical register. Returns the physical register if it is successful.
406unsigned
407ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
408                                         const MachineFunction &MF) const {
409  if (Reg == 0 || !isPhysicalRegister(Reg))
410    return 0;
411  if (Type == 0)
412    return Reg;
413  else if (Type == (unsigned)ARMRI::RegPairOdd)
414    // Odd register.
415    return getRegisterPairOdd(Reg, MF);
416  else if (Type == (unsigned)ARMRI::RegPairEven)
417    // Even register.
418    return getRegisterPairEven(Reg, MF);
419  return 0;
420}
421
422void
423ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
424                                        MachineFunction &MF) const {
425  MachineRegisterInfo *MRI = &MF.getRegInfo();
426  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
427  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
428       Hint.first == (unsigned)ARMRI::RegPairEven) &&
429      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
430    // If 'Reg' is one of the even / odd register pair and it's now changed
431    // (e.g. coalesced) into a different register. The other register of the
432    // pair allocation hint must be updated to reflect the relationship
433    // change.
434    unsigned OtherReg = Hint.second;
435    Hint = MRI->getRegAllocationHint(OtherReg);
436    if (Hint.second == Reg)
437      // Make sure the pair has not already divorced.
438      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
439  }
440}
441
442/// hasFP - Return true if the specified function should have a dedicated frame
443/// pointer register.  This is true if the function has variable sized allocas
444/// or if frame pointer elimination is disabled.
445///
446bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
447  const MachineFrameInfo *MFI = MF.getFrameInfo();
448  return (NoFramePointerElim ||
449          MFI->hasVarSizedObjects() ||
450          MFI->isFrameAddressTaken());
451}
452
453bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
454  const MachineFrameInfo *MFI = MF.getFrameInfo();
455  if (NoFramePointerElim && MFI->hasCalls())
456    return true;
457  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
458}
459
460/// estimateStackSize - Estimate and return the size of the frame.
461static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
462  const MachineFrameInfo *FFI = MF.getFrameInfo();
463  int Offset = 0;
464  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
465    int FixedOff = -FFI->getObjectOffset(i);
466    if (FixedOff > Offset) Offset = FixedOff;
467  }
468  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
469    if (FFI->isDeadObjectIndex(i))
470      continue;
471    Offset += FFI->getObjectSize(i);
472    unsigned Align = FFI->getObjectAlignment(i);
473    // Adjust to alignment boundary
474    Offset = (Offset+Align-1)/Align*Align;
475  }
476  return (unsigned)Offset;
477}
478
479/// estimateRSStackSizeLimit - Look at each instruction that references stack
480/// frames and return the stack size limit beyond which some of these
481/// instructions will require scratch register during their expansion later.
482unsigned
483ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
484  unsigned Limit = (1 << 12) - 1;
485  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
486    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
487         I != E; ++I) {
488      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
489        if (!I->getOperand(i).isFI()) continue;
490
491        const TargetInstrDesc &Desc = TII.get(I->getOpcode());
492        unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
493        if (AddrMode == ARMII::AddrMode3 ||
494            AddrMode == ARMII::AddrModeT2_i8)
495          return (1 << 8) - 1;
496
497        if (AddrMode == ARMII::AddrMode5 ||
498            AddrMode == ARMII::AddrModeT2_i8s4)
499          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
500
501        if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
502          // When the stack offset is negative, we will end up using
503          // the i8 instructions instead.
504          return (1 << 8) - 1;
505        break; // At most one FI per instruction
506      }
507    }
508  }
509
510  return Limit;
511}
512
513void
514ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
515                                                          RegScavenger *RS) const {
516  // This tells PEI to spill the FP as if it is any other callee-save register
517  // to take advantage the eliminateFrameIndex machinery. This also ensures it
518  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
519  // to combine multiple loads / stores.
520  bool CanEliminateFrame = true;
521  bool CS1Spilled = false;
522  bool LRSpilled = false;
523  unsigned NumGPRSpills = 0;
524  SmallVector<unsigned, 4> UnspilledCS1GPRs;
525  SmallVector<unsigned, 4> UnspilledCS2GPRs;
526  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
527
528  // Don't spill FP if the frame can be eliminated. This is determined
529  // by scanning the callee-save registers to see if any is used.
530  const unsigned *CSRegs = getCalleeSavedRegs();
531  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
532  for (unsigned i = 0; CSRegs[i]; ++i) {
533    unsigned Reg = CSRegs[i];
534    bool Spilled = false;
535    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
536      AFI->setCSRegisterIsSpilled(Reg);
537      Spilled = true;
538      CanEliminateFrame = false;
539    } else {
540      // Check alias registers too.
541      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
542        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
543          Spilled = true;
544          CanEliminateFrame = false;
545        }
546      }
547    }
548
549    if (CSRegClasses[i] == ARM::GPRRegisterClass ||
550        CSRegClasses[i] == ARM::tGPRRegisterClass) {
551      if (Spilled) {
552        NumGPRSpills++;
553
554        if (!STI.isTargetDarwin()) {
555          if (Reg == ARM::LR)
556            LRSpilled = true;
557          CS1Spilled = true;
558          continue;
559        }
560
561        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
562        switch (Reg) {
563        case ARM::LR:
564          LRSpilled = true;
565          // Fallthrough
566        case ARM::R4:
567        case ARM::R5:
568        case ARM::R6:
569        case ARM::R7:
570          CS1Spilled = true;
571          break;
572        default:
573          break;
574        }
575      } else {
576        if (!STI.isTargetDarwin()) {
577          UnspilledCS1GPRs.push_back(Reg);
578          continue;
579        }
580
581        switch (Reg) {
582        case ARM::R4:
583        case ARM::R5:
584        case ARM::R6:
585        case ARM::R7:
586        case ARM::LR:
587          UnspilledCS1GPRs.push_back(Reg);
588          break;
589        default:
590          UnspilledCS2GPRs.push_back(Reg);
591          break;
592        }
593      }
594    }
595  }
596
597  bool ForceLRSpill = false;
598  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
599    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
600    // Force LR to be spilled if the Thumb function size is > 2048. This enables
601    // use of BL to implement far jump. If it turns out that it's not needed
602    // then the branch fix up path will undo it.
603    if (FnSize >= (1 << 11)) {
604      CanEliminateFrame = false;
605      ForceLRSpill = true;
606    }
607  }
608
609  bool ExtraCSSpill = false;
610  if (!CanEliminateFrame || cannotEliminateFrame(MF)) {
611    AFI->setHasStackFrame(true);
612
613    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
614    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
615    if (!LRSpilled && CS1Spilled) {
616      MF.getRegInfo().setPhysRegUsed(ARM::LR);
617      AFI->setCSRegisterIsSpilled(ARM::LR);
618      NumGPRSpills++;
619      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
620                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
621      ForceLRSpill = false;
622      ExtraCSSpill = true;
623    }
624
625    // Darwin ABI requires FP to point to the stack slot that contains the
626    // previous FP.
627    if (STI.isTargetDarwin() || hasFP(MF)) {
628      MF.getRegInfo().setPhysRegUsed(FramePtr);
629      NumGPRSpills++;
630    }
631
632    // If stack and double are 8-byte aligned and we are spilling an odd number
633    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
634    // the integer and double callee save areas.
635    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
636    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
637      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
638        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
639          unsigned Reg = UnspilledCS1GPRs[i];
640          // Don't spill high register if the function is thumb1
641          if (!AFI->isThumb1OnlyFunction() ||
642              isARMLowRegister(Reg) || Reg == ARM::LR) {
643            MF.getRegInfo().setPhysRegUsed(Reg);
644            AFI->setCSRegisterIsSpilled(Reg);
645            if (!isReservedReg(MF, Reg))
646              ExtraCSSpill = true;
647            break;
648          }
649        }
650      } else if (!UnspilledCS2GPRs.empty() &&
651                 !AFI->isThumb1OnlyFunction()) {
652        unsigned Reg = UnspilledCS2GPRs.front();
653        MF.getRegInfo().setPhysRegUsed(Reg);
654        AFI->setCSRegisterIsSpilled(Reg);
655        if (!isReservedReg(MF, Reg))
656          ExtraCSSpill = true;
657      }
658    }
659
660    // Estimate if we might need to scavenge a register at some point in order
661    // to materialize a stack offset. If so, either spill one additional
662    // callee-saved register or reserve a special spill slot to facilitate
663    // register scavenging. Thumb1 needs a spill slot for stack pointer
664    // adjustments also, even when the frame itself is small.
665    if (RS && !ExtraCSSpill) {
666      MachineFrameInfo  *MFI = MF.getFrameInfo();
667      // If any of the stack slot references may be out of range of an
668      // immediate offset, make sure a register (or a spill slot) is
669      // available for the register scavenger. Note that if we're indexing
670      // off the frame pointer, the effective stack size is 4 bytes larger
671      // since the FP points to the stack slot of the previous FP.
672      if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0)
673          >= estimateRSStackSizeLimit(MF)) {
674        // If any non-reserved CS register isn't spilled, just spill one or two
675        // extra. That should take care of it!
676        unsigned NumExtras = TargetAlign / 4;
677        SmallVector<unsigned, 2> Extras;
678        while (NumExtras && !UnspilledCS1GPRs.empty()) {
679          unsigned Reg = UnspilledCS1GPRs.back();
680          UnspilledCS1GPRs.pop_back();
681          if (!isReservedReg(MF, Reg)) {
682            Extras.push_back(Reg);
683            NumExtras--;
684          }
685        }
686        // For non-Thumb1 functions, also check for hi-reg CS registers
687        if (!AFI->isThumb1OnlyFunction()) {
688          while (NumExtras && !UnspilledCS2GPRs.empty()) {
689            unsigned Reg = UnspilledCS2GPRs.back();
690            UnspilledCS2GPRs.pop_back();
691            if (!isReservedReg(MF, Reg)) {
692              Extras.push_back(Reg);
693              NumExtras--;
694            }
695          }
696        }
697        if (Extras.size() && NumExtras == 0) {
698          for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
699            MF.getRegInfo().setPhysRegUsed(Extras[i]);
700            AFI->setCSRegisterIsSpilled(Extras[i]);
701          }
702        } else if (!AFI->isThumb1OnlyFunction()) {
703          // note: Thumb1 functions spill to R12, not the stack.
704          // Reserve a slot closest to SP or frame pointer.
705          const TargetRegisterClass *RC = ARM::GPRRegisterClass;
706          RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
707                                                           RC->getAlignment()));
708        }
709      }
710    }
711  }
712
713  if (ForceLRSpill) {
714    MF.getRegInfo().setPhysRegUsed(ARM::LR);
715    AFI->setCSRegisterIsSpilled(ARM::LR);
716    AFI->setLRIsSpilledForFarJump(true);
717  }
718}
719
720unsigned ARMBaseRegisterInfo::getRARegister() const {
721  return ARM::LR;
722}
723
724unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const {
725  if (STI.isTargetDarwin() || hasFP(MF))
726    return FramePtr;
727  return ARM::SP;
728}
729
730unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
731  llvm_unreachable("What is the exception register");
732  return 0;
733}
734
735unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
736  llvm_unreachable("What is the exception handler register");
737  return 0;
738}
739
740int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
741  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
742}
743
744unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
745                                               const MachineFunction &MF) const {
746  switch (Reg) {
747  default: break;
748  // Return 0 if either register of the pair is a special register.
749  // So no R12, etc.
750  case ARM::R1:
751    return ARM::R0;
752  case ARM::R3:
753    return ARM::R2;
754  case ARM::R5:
755    return ARM::R4;
756  case ARM::R7:
757    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
758  case ARM::R9:
759    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
760  case ARM::R11:
761    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
762
763  case ARM::S1:
764    return ARM::S0;
765  case ARM::S3:
766    return ARM::S2;
767  case ARM::S5:
768    return ARM::S4;
769  case ARM::S7:
770    return ARM::S6;
771  case ARM::S9:
772    return ARM::S8;
773  case ARM::S11:
774    return ARM::S10;
775  case ARM::S13:
776    return ARM::S12;
777  case ARM::S15:
778    return ARM::S14;
779  case ARM::S17:
780    return ARM::S16;
781  case ARM::S19:
782    return ARM::S18;
783  case ARM::S21:
784    return ARM::S20;
785  case ARM::S23:
786    return ARM::S22;
787  case ARM::S25:
788    return ARM::S24;
789  case ARM::S27:
790    return ARM::S26;
791  case ARM::S29:
792    return ARM::S28;
793  case ARM::S31:
794    return ARM::S30;
795
796  case ARM::D1:
797    return ARM::D0;
798  case ARM::D3:
799    return ARM::D2;
800  case ARM::D5:
801    return ARM::D4;
802  case ARM::D7:
803    return ARM::D6;
804  case ARM::D9:
805    return ARM::D8;
806  case ARM::D11:
807    return ARM::D10;
808  case ARM::D13:
809    return ARM::D12;
810  case ARM::D15:
811    return ARM::D14;
812  case ARM::D17:
813    return ARM::D16;
814  case ARM::D19:
815    return ARM::D18;
816  case ARM::D21:
817    return ARM::D20;
818  case ARM::D23:
819    return ARM::D22;
820  case ARM::D25:
821    return ARM::D24;
822  case ARM::D27:
823    return ARM::D26;
824  case ARM::D29:
825    return ARM::D28;
826  case ARM::D31:
827    return ARM::D30;
828  }
829
830  return 0;
831}
832
833unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
834                                             const MachineFunction &MF) const {
835  switch (Reg) {
836  default: break;
837  // Return 0 if either register of the pair is a special register.
838  // So no R12, etc.
839  case ARM::R0:
840    return ARM::R1;
841  case ARM::R2:
842    return ARM::R3;
843  case ARM::R4:
844    return ARM::R5;
845  case ARM::R6:
846    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
847  case ARM::R8:
848    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
849  case ARM::R10:
850    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
851
852  case ARM::S0:
853    return ARM::S1;
854  case ARM::S2:
855    return ARM::S3;
856  case ARM::S4:
857    return ARM::S5;
858  case ARM::S6:
859    return ARM::S7;
860  case ARM::S8:
861    return ARM::S9;
862  case ARM::S10:
863    return ARM::S11;
864  case ARM::S12:
865    return ARM::S13;
866  case ARM::S14:
867    return ARM::S15;
868  case ARM::S16:
869    return ARM::S17;
870  case ARM::S18:
871    return ARM::S19;
872  case ARM::S20:
873    return ARM::S21;
874  case ARM::S22:
875    return ARM::S23;
876  case ARM::S24:
877    return ARM::S25;
878  case ARM::S26:
879    return ARM::S27;
880  case ARM::S28:
881    return ARM::S29;
882  case ARM::S30:
883    return ARM::S31;
884
885  case ARM::D0:
886    return ARM::D1;
887  case ARM::D2:
888    return ARM::D3;
889  case ARM::D4:
890    return ARM::D5;
891  case ARM::D6:
892    return ARM::D7;
893  case ARM::D8:
894    return ARM::D9;
895  case ARM::D10:
896    return ARM::D11;
897  case ARM::D12:
898    return ARM::D13;
899  case ARM::D14:
900    return ARM::D15;
901  case ARM::D16:
902    return ARM::D17;
903  case ARM::D18:
904    return ARM::D19;
905  case ARM::D20:
906    return ARM::D21;
907  case ARM::D22:
908    return ARM::D23;
909  case ARM::D24:
910    return ARM::D25;
911  case ARM::D26:
912    return ARM::D27;
913  case ARM::D28:
914    return ARM::D29;
915  case ARM::D30:
916    return ARM::D31;
917  }
918
919  return 0;
920}
921
922/// emitLoadConstPool - Emits a load from constpool to materialize the
923/// specified immediate.
924void ARMBaseRegisterInfo::
925emitLoadConstPool(MachineBasicBlock &MBB,
926                  MachineBasicBlock::iterator &MBBI,
927                  DebugLoc dl,
928                  unsigned DestReg, unsigned SubIdx, int Val,
929                  ARMCC::CondCodes Pred,
930                  unsigned PredReg) const {
931  MachineFunction &MF = *MBB.getParent();
932  MachineConstantPool *ConstantPool = MF.getConstantPool();
933  Constant *C =
934        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
935  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
936
937  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
938    .addReg(DestReg, getDefRegState(true), SubIdx)
939    .addConstantPoolIndex(Idx)
940    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
941}
942
943bool ARMBaseRegisterInfo::
944requiresRegisterScavenging(const MachineFunction &MF) const {
945  return true;
946}
947
948bool ARMBaseRegisterInfo::
949requiresFrameIndexScavenging(const MachineFunction &MF) const {
950  return ScavengeFrameIndexVals;
951}
952
953// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
954// not required, we reserve argument space for call sites in the function
955// immediately on entry to the current function. This eliminates the need for
956// add/sub sp brackets around call sites. Returns true if the call frame is
957// included as part of the stack frame.
958bool ARMBaseRegisterInfo::
959hasReservedCallFrame(MachineFunction &MF) const {
960  const MachineFrameInfo *FFI = MF.getFrameInfo();
961  unsigned CFSize = FFI->getMaxCallFrameSize();
962  // It's not always a good idea to include the call frame as part of the
963  // stack frame. ARM (especially Thumb) has small immediate offset to
964  // address the stack frame. So a large call frame can cause poor codegen
965  // and may even makes it impossible to scavenge a register.
966  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
967    return false;
968
969  return !MF.getFrameInfo()->hasVarSizedObjects();
970}
971
972static void
973emitSPUpdate(bool isARM,
974             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
975             DebugLoc dl, const ARMBaseInstrInfo &TII,
976             int NumBytes,
977             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
978  if (isARM)
979    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
980                            Pred, PredReg, TII);
981  else
982    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
983                           Pred, PredReg, TII);
984}
985
986
987void ARMBaseRegisterInfo::
988eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
989                              MachineBasicBlock::iterator I) const {
990  if (!hasReservedCallFrame(MF)) {
991    // If we have alloca, convert as follows:
992    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
993    // ADJCALLSTACKUP   -> add, sp, sp, amount
994    MachineInstr *Old = I;
995    DebugLoc dl = Old->getDebugLoc();
996    unsigned Amount = Old->getOperand(0).getImm();
997    if (Amount != 0) {
998      // We need to keep the stack aligned properly.  To do this, we round the
999      // amount of space needed for the outgoing arguments up to the next
1000      // alignment boundary.
1001      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1002      Amount = (Amount+Align-1)/Align*Align;
1003
1004      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1005      assert(!AFI->isThumb1OnlyFunction() &&
1006             "This eliminateCallFramePseudoInstr does not suppor Thumb1!");
1007      bool isARM = !AFI->isThumbFunction();
1008
1009      // Replace the pseudo instruction with a new instruction...
1010      unsigned Opc = Old->getOpcode();
1011      ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
1012      // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN?
1013      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1014        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1015        unsigned PredReg = Old->getOperand(2).getReg();
1016        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1017      } else {
1018        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1019        unsigned PredReg = Old->getOperand(3).getReg();
1020        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1021        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1022      }
1023    }
1024  }
1025  MBB.erase(I);
1026}
1027
1028/// findScratchRegister - Find a 'free' ARM register. If register scavenger
1029/// is not being used, R12 is available. Otherwise, try for a call-clobbered
1030/// register first and then a spilled callee-saved register if that fails.
1031static
1032unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
1033                             ARMFunctionInfo *AFI) {
1034  unsigned Reg = RS ? RS->FindUnusedReg(RC) : (unsigned) ARM::R12;
1035  assert(!AFI->isThumb1OnlyFunction());
1036  return Reg;
1037}
1038
1039unsigned
1040ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1041                                         int SPAdj, int *Value,
1042                                         RegScavenger *RS) const {
1043  unsigned i = 0;
1044  MachineInstr &MI = *II;
1045  MachineBasicBlock &MBB = *MI.getParent();
1046  MachineFunction &MF = *MBB.getParent();
1047  const MachineFrameInfo *MFI = MF.getFrameInfo();
1048  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1049  assert(!AFI->isThumb1OnlyFunction() &&
1050         "This eliminateFrameIndex does not support Thumb1!");
1051
1052  while (!MI.getOperand(i).isFI()) {
1053    ++i;
1054    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1055  }
1056
1057  unsigned FrameReg = ARM::SP;
1058  int FrameIndex = MI.getOperand(i).getIndex();
1059  int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj;
1060
1061  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
1062    Offset -= AFI->getGPRCalleeSavedArea1Offset();
1063  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
1064    Offset -= AFI->getGPRCalleeSavedArea2Offset();
1065  else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
1066    Offset -= AFI->getDPRCalleeSavedAreaOffset();
1067  else if (hasFP(MF) && AFI->hasStackFrame()) {
1068    assert(SPAdj == 0 && "Unexpected stack offset!");
1069    // Use frame pointer to reference fixed objects unless this is a
1070    // frameless function,
1071    FrameReg = getFrameRegister(MF);
1072    Offset -= AFI->getFramePtrSpillOffset();
1073  }
1074
1075  // modify MI as necessary to handle as much of 'Offset' as possible
1076  bool Done = false;
1077  if (!AFI->isThumbFunction())
1078    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1079  else {
1080    assert(AFI->isThumb2Function());
1081    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1082  }
1083  if (Done)
1084    return 0;
1085
1086  // If we get here, the immediate doesn't fit into the instruction.  We folded
1087  // as much as possible above, handle the rest, providing a register that is
1088  // SP+LargeImm.
1089  assert((Offset ||
1090          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) &&
1091         "This code isn't needed if offset already handled!");
1092
1093  unsigned ScratchReg = 0;
1094  int PIdx = MI.findFirstPredOperandIdx();
1095  ARMCC::CondCodes Pred = (PIdx == -1)
1096    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1097  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1098  if (Offset == 0)
1099    // Must be addrmode4.
1100    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1101  else {
1102    if (!ScavengeFrameIndexVals) {
1103      // Insert a set of r12 with the full address: r12 = sp + offset
1104      // If the offset we have is too large to fit into the instruction, we need
1105      // to form it with a series of ADDri's.  Do this by taking 8-bit chunks
1106      // out of 'Offset'.
1107      ScratchReg = findScratchRegister(RS, ARM::GPRRegisterClass, AFI);
1108      if (ScratchReg == 0)
1109        // No register is "free". Scavenge a register.
1110        ScratchReg = RS->scavengeRegister(ARM::GPRRegisterClass, II, SPAdj);
1111    } else {
1112      ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1113      *Value = Offset;
1114    }
1115    if (!AFI->isThumbFunction())
1116      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1117                              Offset, Pred, PredReg, TII);
1118    else {
1119      assert(AFI->isThumb2Function());
1120      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1121                             Offset, Pred, PredReg, TII);
1122    }
1123    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1124    if (!ReuseFrameIndexVals || !ScavengeFrameIndexVals)
1125      ScratchReg = 0;
1126  }
1127  return ScratchReg;
1128}
1129
1130/// Move iterator pass the next bunch of callee save load / store ops for
1131/// the particular spill area (1: integer area 1, 2: integer area 2,
1132/// 3: fp area, 0: don't care).
1133static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1134                                   MachineBasicBlock::iterator &MBBI,
1135                                   int Opc1, int Opc2, unsigned Area,
1136                                   const ARMSubtarget &STI) {
1137  while (MBBI != MBB.end() &&
1138         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1139         MBBI->getOperand(1).isFI()) {
1140    if (Area != 0) {
1141      bool Done = false;
1142      unsigned Category = 0;
1143      switch (MBBI->getOperand(0).getReg()) {
1144      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1145      case ARM::LR:
1146        Category = 1;
1147        break;
1148      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1149        Category = STI.isTargetDarwin() ? 2 : 1;
1150        break;
1151      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1152      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1153        Category = 3;
1154        break;
1155      default:
1156        Done = true;
1157        break;
1158      }
1159      if (Done || Category != Area)
1160        break;
1161    }
1162
1163    ++MBBI;
1164  }
1165}
1166
1167void ARMBaseRegisterInfo::
1168emitPrologue(MachineFunction &MF) const {
1169  MachineBasicBlock &MBB = MF.front();
1170  MachineBasicBlock::iterator MBBI = MBB.begin();
1171  MachineFrameInfo  *MFI = MF.getFrameInfo();
1172  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1173  assert(!AFI->isThumb1OnlyFunction() &&
1174         "This emitPrologue does not suppor Thumb1!");
1175  bool isARM = !AFI->isThumbFunction();
1176  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1177  unsigned NumBytes = MFI->getStackSize();
1178  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1179  DebugLoc dl = (MBBI != MBB.end() ?
1180                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1181
1182  // Determine the sizes of each callee-save spill areas and record which frame
1183  // belongs to which callee-save spill areas.
1184  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1185  int FramePtrSpillFI = 0;
1186
1187  // Allocate the vararg register save area. This is not counted in NumBytes.
1188  if (VARegSaveSize)
1189    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1190
1191  if (!AFI->hasStackFrame()) {
1192    if (NumBytes != 0)
1193      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1194    return;
1195  }
1196
1197  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1198    unsigned Reg = CSI[i].getReg();
1199    int FI = CSI[i].getFrameIdx();
1200    switch (Reg) {
1201    case ARM::R4:
1202    case ARM::R5:
1203    case ARM::R6:
1204    case ARM::R7:
1205    case ARM::LR:
1206      if (Reg == FramePtr)
1207        FramePtrSpillFI = FI;
1208      AFI->addGPRCalleeSavedArea1Frame(FI);
1209      GPRCS1Size += 4;
1210      break;
1211    case ARM::R8:
1212    case ARM::R9:
1213    case ARM::R10:
1214    case ARM::R11:
1215      if (Reg == FramePtr)
1216        FramePtrSpillFI = FI;
1217      if (STI.isTargetDarwin()) {
1218        AFI->addGPRCalleeSavedArea2Frame(FI);
1219        GPRCS2Size += 4;
1220      } else {
1221        AFI->addGPRCalleeSavedArea1Frame(FI);
1222        GPRCS1Size += 4;
1223      }
1224      break;
1225    default:
1226      AFI->addDPRCalleeSavedAreaFrame(FI);
1227      DPRCSSize += 8;
1228    }
1229  }
1230
1231  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1232  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1233  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1234
1235  // Set FP to point to the stack slot that contains the previous FP.
1236  // For Darwin, FP is R7, which has now been stored in spill area 1.
1237  // Otherwise, if this is not Darwin, all the callee-saved registers go
1238  // into spill area 1, including the FP in R11.  In either case, it is
1239  // now safe to emit this assignment.
1240  if (STI.isTargetDarwin() || hasFP(MF)) {
1241    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1242    MachineInstrBuilder MIB =
1243      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1244      .addFrameIndex(FramePtrSpillFI).addImm(0);
1245    AddDefaultCC(AddDefaultPred(MIB));
1246  }
1247
1248  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1249  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1250
1251  // Build the new SUBri to adjust SP for FP callee-save spill area.
1252  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1253  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1254
1255  // Determine starting offsets of spill areas.
1256  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1257  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1258  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1259  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1260  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1261  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1262  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1263
1264  NumBytes = DPRCSOffset;
1265  if (NumBytes) {
1266    // Insert it after all the callee-save spills.
1267    movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI);
1268    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1269  }
1270
1271  if (STI.isTargetELF() && hasFP(MF)) {
1272    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1273                             AFI->getFramePtrSpillOffset());
1274  }
1275
1276  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1277  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1278  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1279}
1280
1281static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1282  for (unsigned i = 0; CSRegs[i]; ++i)
1283    if (Reg == CSRegs[i])
1284      return true;
1285  return false;
1286}
1287
1288static bool isCSRestore(MachineInstr *MI,
1289                        const ARMBaseInstrInfo &TII,
1290                        const unsigned *CSRegs) {
1291  return ((MI->getOpcode() == (int)ARM::FLDD ||
1292           MI->getOpcode() == (int)ARM::LDR ||
1293           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1294          MI->getOperand(1).isFI() &&
1295          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1296}
1297
1298void ARMBaseRegisterInfo::
1299emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1300  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1301  assert(MBBI->getDesc().isReturn() &&
1302         "Can only insert epilog into returning blocks");
1303  DebugLoc dl = MBBI->getDebugLoc();
1304  MachineFrameInfo *MFI = MF.getFrameInfo();
1305  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1306  assert(!AFI->isThumb1OnlyFunction() &&
1307         "This emitEpilogue does not suppor Thumb1!");
1308  bool isARM = !AFI->isThumbFunction();
1309
1310  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1311  int NumBytes = (int)MFI->getStackSize();
1312
1313  if (!AFI->hasStackFrame()) {
1314    if (NumBytes != 0)
1315      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1316  } else {
1317    // Unwind MBBI to point to first LDR / FLDD.
1318    const unsigned *CSRegs = getCalleeSavedRegs();
1319    if (MBBI != MBB.begin()) {
1320      do
1321        --MBBI;
1322      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1323      if (!isCSRestore(MBBI, TII, CSRegs))
1324        ++MBBI;
1325    }
1326
1327    // Move SP to start of FP callee save spill area.
1328    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1329                 AFI->getGPRCalleeSavedArea2Size() +
1330                 AFI->getDPRCalleeSavedAreaSize());
1331
1332    // Darwin ABI requires FP to point to the stack slot that contains the
1333    // previous FP.
1334    bool HasFP = hasFP(MF);
1335    if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1336      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1337      // Reset SP based on frame pointer only if the stack frame extends beyond
1338      // frame pointer stack slot or target is ELF and the function has FP.
1339      if (HasFP ||
1340          AFI->getGPRCalleeSavedArea2Size() ||
1341          AFI->getDPRCalleeSavedAreaSize()  ||
1342          AFI->getDPRCalleeSavedAreaOffset()) {
1343        if (NumBytes) {
1344          if (isARM)
1345            emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1346                                    ARMCC::AL, 0, TII);
1347          else
1348            emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1349                                    ARMCC::AL, 0, TII);
1350        } else {
1351          // Thumb2 or ARM.
1352          if (isARM)
1353            BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1354              .addReg(FramePtr)
1355              .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1356          else
1357            BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1358              .addReg(FramePtr);
1359        }
1360      }
1361    } else if (NumBytes)
1362      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1363
1364    // Move SP to start of integer callee save spill area 2.
1365    movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 0, 3, STI);
1366    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1367
1368    // Move SP to start of integer callee save spill area 1.
1369    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1370    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1371
1372    // Move SP to SP upon entry to the function.
1373    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1374    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1375  }
1376
1377  if (VARegSaveSize)
1378    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1379}
1380
1381#include "ARMGenRegisterInfo.inc"
1382