ScheduleDAGSDNodes.cpp revision 263509
1193323Sed//===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This implements the ScheduleDAG class, which is a base class used by 11193323Sed// scheduling implementation classes. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#define DEBUG_TYPE "pre-RA-sched" 16193323Sed#include "ScheduleDAGSDNodes.h" 17198090Srdivacky#include "InstrEmitter.h" 18252723Sdim#include "SDNodeDbgValue.h" 19202878Srdivacky#include "llvm/ADT/DenseMap.h" 20202878Srdivacky#include "llvm/ADT/SmallPtrSet.h" 21206083Srdivacky#include "llvm/ADT/SmallSet.h" 22202878Srdivacky#include "llvm/ADT/SmallVector.h" 23202878Srdivacky#include "llvm/ADT/Statistic.h" 24252723Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 25252723Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 26252723Sdim#include "llvm/CodeGen/SelectionDAG.h" 27252723Sdim#include "llvm/MC/MCInstrItineraries.h" 28221345Sdim#include "llvm/Support/CommandLine.h" 29193323Sed#include "llvm/Support/Debug.h" 30193323Sed#include "llvm/Support/raw_ostream.h" 31252723Sdim#include "llvm/Target/TargetInstrInfo.h" 32252723Sdim#include "llvm/Target/TargetLowering.h" 33252723Sdim#include "llvm/Target/TargetMachine.h" 34252723Sdim#include "llvm/Target/TargetRegisterInfo.h" 35252723Sdim#include "llvm/Target/TargetSubtargetInfo.h" 36193323Sedusing namespace llvm; 37193323Sed 38202878SrdivackySTATISTIC(LoadsClustered, "Number of loads clustered together"); 39202878Srdivacky 40221345Sdim// This allows latency based scheduler to notice high latency instructions 41221345Sdim// without a target itinerary. The choise if number here has more to do with 42221345Sdim// balancing scheduler heursitics than with the actual machine latency. 43221345Sdimstatic cl::opt<int> HighLatencyCycles( 44221345Sdim "sched-high-latency-cycles", cl::Hidden, cl::init(10), 45221345Sdim cl::desc("Roughly estimate the number of cycles that 'long latency'" 46221345Sdim "instructions take for targets with no itinerary")); 47221345Sdim 48193323SedScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf) 49235633Sdim : ScheduleDAG(mf), BB(0), DAG(0), 50218893Sdim InstrItins(mf.getTarget().getInstrItineraryData()) {} 51193323Sed 52193323Sed/// Run - perform scheduling. 53193323Sed/// 54235633Sdimvoid ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb) { 55235633Sdim BB = bb; 56193323Sed DAG = dag; 57235633Sdim 58235633Sdim // Clear the scheduler's SUnit DAG. 59235633Sdim ScheduleDAG::clearDAG(); 60235633Sdim Sequence.clear(); 61235633Sdim 62235633Sdim // Invoke the target's selection of scheduler. 63235633Sdim Schedule(); 64193323Sed} 65193323Sed 66208599Srdivacky/// NewSUnit - Creates a new SUnit and return a ptr to it. 67208599Srdivacky/// 68235633SdimSUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) { 69208599Srdivacky#ifndef NDEBUG 70208599Srdivacky const SUnit *Addr = 0; 71208599Srdivacky if (!SUnits.empty()) 72208599Srdivacky Addr = &SUnits[0]; 73208599Srdivacky#endif 74208599Srdivacky SUnits.push_back(SUnit(N, (unsigned)SUnits.size())); 75208599Srdivacky assert((Addr == 0 || Addr == &SUnits[0]) && 76208599Srdivacky "SUnits std::vector reallocated on the fly!"); 77208599Srdivacky SUnits.back().OrigNode = &SUnits.back(); 78208599Srdivacky SUnit *SU = &SUnits.back(); 79208599Srdivacky const TargetLowering &TLI = DAG->getTargetLoweringInfo(); 80212904Sdim if (!N || 81212904Sdim (N->isMachineOpcode() && 82212904Sdim N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)) 83210299Sed SU->SchedulingPref = Sched::None; 84210299Sed else 85210299Sed SU->SchedulingPref = TLI.getSchedulingPreference(N); 86208599Srdivacky return SU; 87208599Srdivacky} 88208599Srdivacky 89193323SedSUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) { 90235633Sdim SUnit *SU = newSUnit(Old->getNode()); 91193323Sed SU->OrigNode = Old->OrigNode; 92193323Sed SU->Latency = Old->Latency; 93221345Sdim SU->isVRegCycle = Old->isVRegCycle; 94218893Sdim SU->isCall = Old->isCall; 95221345Sdim SU->isCallOp = Old->isCallOp; 96193323Sed SU->isTwoAddress = Old->isTwoAddress; 97193323Sed SU->isCommutable = Old->isCommutable; 98193323Sed SU->hasPhysRegDefs = Old->hasPhysRegDefs; 99193323Sed SU->hasPhysRegClobbers = Old->hasPhysRegClobbers; 100221345Sdim SU->isScheduleHigh = Old->isScheduleHigh; 101221345Sdim SU->isScheduleLow = Old->isScheduleLow; 102208599Srdivacky SU->SchedulingPref = Old->SchedulingPref; 103193323Sed Old->isCloned = true; 104193323Sed return SU; 105193323Sed} 106193323Sed 107193323Sed/// CheckForPhysRegDependency - Check if the dependency between def and use of 108193323Sed/// a specified operand is a physical register dependency. If so, returns the 109193323Sed/// register and the cost of copying the register. 110193323Sedstatic void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, 111218893Sdim const TargetRegisterInfo *TRI, 112193323Sed const TargetInstrInfo *TII, 113193323Sed unsigned &PhysReg, int &Cost) { 114193323Sed if (Op != 2 || User->getOpcode() != ISD::CopyToReg) 115193323Sed return; 116193323Sed 117193323Sed unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 118193323Sed if (TargetRegisterInfo::isVirtualRegister(Reg)) 119193323Sed return; 120193323Sed 121193323Sed unsigned ResNo = User->getOperand(2).getResNo(); 122193323Sed if (Def->isMachineOpcode()) { 123224145Sdim const MCInstrDesc &II = TII->get(Def->getMachineOpcode()); 124193323Sed if (ResNo >= II.getNumDefs() && 125193323Sed II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { 126193323Sed PhysReg = Reg; 127193323Sed const TargetRegisterClass *RC = 128210299Sed TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo)); 129193323Sed Cost = RC->getCopyCost(); 130193323Sed } 131193323Sed } 132193323Sed} 133193323Sed 134236144Sdim// Helper for AddGlue to clone node operands. 135236144Sdimstatic void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, 136236144Sdim SmallVectorImpl<EVT> &VTs, 137236144Sdim SDValue ExtraOper = SDValue()) { 138202878Srdivacky SmallVector<SDValue, 4> Ops; 139210299Sed for (unsigned I = 0, E = N->getNumOperands(); I != E; ++I) 140210299Sed Ops.push_back(N->getOperand(I)); 141210299Sed 142236144Sdim if (ExtraOper.getNode()) 143236144Sdim Ops.push_back(ExtraOper); 144210299Sed 145202878Srdivacky SDVTList VTList = DAG->getVTList(&VTs[0], VTs.size()); 146210299Sed MachineSDNode::mmo_iterator Begin = 0, End = 0; 147210299Sed MachineSDNode *MN = dyn_cast<MachineSDNode>(N); 148210299Sed 149210299Sed // Store memory references. 150210299Sed if (MN) { 151210299Sed Begin = MN->memoperands_begin(); 152210299Sed End = MN->memoperands_end(); 153210299Sed } 154210299Sed 155202878Srdivacky DAG->MorphNodeTo(N, N->getOpcode(), VTList, &Ops[0], Ops.size()); 156210299Sed 157210299Sed // Reset the memory references 158210299Sed if (MN) 159210299Sed MN->setMemRefs(Begin, End); 160202878Srdivacky} 161202878Srdivacky 162236144Sdimstatic bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) { 163236144Sdim SmallVector<EVT, 4> VTs; 164236144Sdim SDNode *GlueDestNode = Glue.getNode(); 165236144Sdim 166236144Sdim // Don't add glue from a node to itself. 167236144Sdim if (GlueDestNode == N) return false; 168236144Sdim 169236144Sdim // Don't add a glue operand to something that already uses glue. 170236144Sdim if (GlueDestNode && 171236144Sdim N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) { 172236144Sdim return false; 173236144Sdim } 174236144Sdim // Don't add glue to something that already has a glue value. 175236144Sdim if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return false; 176236144Sdim 177236144Sdim for (unsigned I = 0, E = N->getNumValues(); I != E; ++I) 178236144Sdim VTs.push_back(N->getValueType(I)); 179236144Sdim 180236144Sdim if (AddGlue) 181236144Sdim VTs.push_back(MVT::Glue); 182236144Sdim 183236144Sdim CloneNodeWithValues(N, DAG, VTs, Glue); 184236144Sdim 185236144Sdim return true; 186236144Sdim} 187236144Sdim 188236144Sdim// Cleanup after unsuccessful AddGlue. Use the standard method of morphing the 189236144Sdim// node even though simply shrinking the value list is sufficient. 190236144Sdimstatic void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) { 191236144Sdim assert((N->getValueType(N->getNumValues() - 1) == MVT::Glue && 192236144Sdim !N->hasAnyUseOfValue(N->getNumValues() - 1)) && 193236144Sdim "expected an unused glue value"); 194236144Sdim 195236144Sdim SmallVector<EVT, 4> VTs; 196236144Sdim for (unsigned I = 0, E = N->getNumValues()-1; I != E; ++I) 197236144Sdim VTs.push_back(N->getValueType(I)); 198236144Sdim 199236144Sdim CloneNodeWithValues(N, DAG, VTs); 200236144Sdim} 201236144Sdim 202218893Sdim/// ClusterNeighboringLoads - Force nearby loads together by "gluing" them. 203202878Srdivacky/// This function finds loads of the same base and different offsets. If the 204218893Sdim/// offsets are not far apart (target specific), it add MVT::Glue inputs and 205202878Srdivacky/// outputs to ensure they are scheduled together and in order. This 206202878Srdivacky/// optimization may benefit some targets by improving cache locality. 207210299Sedvoid ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) { 208210299Sed SDNode *Chain = 0; 209210299Sed unsigned NumOps = Node->getNumOperands(); 210210299Sed if (Node->getOperand(NumOps-1).getValueType() == MVT::Other) 211210299Sed Chain = Node->getOperand(NumOps-1).getNode(); 212210299Sed if (!Chain) 213210299Sed return; 214210299Sed 215210299Sed // Look for other loads of the same chain. Find loads that are loading from 216210299Sed // the same base pointer and different offsets. 217202878Srdivacky SmallPtrSet<SDNode*, 16> Visited; 218202878Srdivacky SmallVector<int64_t, 4> Offsets; 219202878Srdivacky DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode. 220210299Sed bool Cluster = false; 221210299Sed SDNode *Base = Node; 222210299Sed for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end(); 223210299Sed I != E; ++I) { 224210299Sed SDNode *User = *I; 225210299Sed if (User == Node || !Visited.insert(User)) 226202878Srdivacky continue; 227210299Sed int64_t Offset1, Offset2; 228210299Sed if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || 229210299Sed Offset1 == Offset2) 230210299Sed // FIXME: Should be ok if they addresses are identical. But earlier 231210299Sed // optimizations really should have eliminated one of the loads. 232202878Srdivacky continue; 233210299Sed if (O2SMap.insert(std::make_pair(Offset1, Base)).second) 234210299Sed Offsets.push_back(Offset1); 235210299Sed O2SMap.insert(std::make_pair(Offset2, User)); 236210299Sed Offsets.push_back(Offset2); 237210299Sed if (Offset2 < Offset1) 238210299Sed Base = User; 239210299Sed Cluster = true; 240210299Sed } 241202878Srdivacky 242210299Sed if (!Cluster) 243210299Sed return; 244202878Srdivacky 245210299Sed // Sort them in increasing order. 246210299Sed std::sort(Offsets.begin(), Offsets.end()); 247202878Srdivacky 248210299Sed // Check if the loads are close enough. 249210299Sed SmallVector<SDNode*, 4> Loads; 250210299Sed unsigned NumLoads = 0; 251210299Sed int64_t BaseOff = Offsets[0]; 252210299Sed SDNode *BaseLoad = O2SMap[BaseOff]; 253210299Sed Loads.push_back(BaseLoad); 254210299Sed for (unsigned i = 1, e = Offsets.size(); i != e; ++i) { 255210299Sed int64_t Offset = Offsets[i]; 256210299Sed SDNode *Load = O2SMap[Offset]; 257210299Sed if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads)) 258210299Sed break; // Stop right here. Ignore loads that are further away. 259210299Sed Loads.push_back(Load); 260210299Sed ++NumLoads; 261210299Sed } 262202878Srdivacky 263210299Sed if (NumLoads == 0) 264210299Sed return; 265202878Srdivacky 266218893Sdim // Cluster loads by adding MVT::Glue outputs and inputs. This also 267210299Sed // ensure they are scheduled in order of increasing addresses. 268210299Sed SDNode *Lead = Loads[0]; 269236144Sdim SDValue InGlue = SDValue(0, 0); 270236144Sdim if (AddGlue(Lead, InGlue, true, DAG)) 271236144Sdim InGlue = SDValue(Lead, Lead->getNumValues() - 1); 272210299Sed for (unsigned I = 1, E = Loads.size(); I != E; ++I) { 273218893Sdim bool OutGlue = I < E - 1; 274210299Sed SDNode *Load = Loads[I]; 275210299Sed 276236144Sdim // If AddGlue fails, we could leave an unsused glue value. This should not 277236144Sdim // cause any 278236144Sdim if (AddGlue(Load, InGlue, OutGlue, DAG)) { 279236144Sdim if (OutGlue) 280236144Sdim InGlue = SDValue(Load, Load->getNumValues() - 1); 281210299Sed 282236144Sdim ++LoadsClustered; 283236144Sdim } 284236144Sdim else if (!OutGlue && InGlue.getNode()) 285236144Sdim RemoveUnusedGlue(InGlue.getNode(), DAG); 286210299Sed } 287210299Sed} 288210299Sed 289210299Sed/// ClusterNodes - Cluster certain nodes which should be scheduled together. 290210299Sed/// 291210299Sedvoid ScheduleDAGSDNodes::ClusterNodes() { 292210299Sed for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(), 293210299Sed E = DAG->allnodes_end(); NI != E; ++NI) { 294210299Sed SDNode *Node = &*NI; 295210299Sed if (!Node || !Node->isMachineOpcode()) 296202878Srdivacky continue; 297202878Srdivacky 298210299Sed unsigned Opc = Node->getMachineOpcode(); 299224145Sdim const MCInstrDesc &MCID = TII->get(Opc); 300224145Sdim if (MCID.mayLoad()) 301210299Sed // Cluster loads from "near" addresses into combined SUnits. 302210299Sed ClusterNeighboringLoads(Node); 303202878Srdivacky } 304202878Srdivacky} 305202878Srdivacky 306193323Sedvoid ScheduleDAGSDNodes::BuildSchedUnits() { 307193323Sed // During scheduling, the NodeId field of SDNode is used to map SDNodes 308193323Sed // to their associated SUnits by holding SUnits table indices. A value 309193323Sed // of -1 means the SDNode does not yet have an associated SUnit. 310193323Sed unsigned NumNodes = 0; 311193323Sed for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(), 312193323Sed E = DAG->allnodes_end(); NI != E; ++NI) { 313193323Sed NI->setNodeId(-1); 314193323Sed ++NumNodes; 315193323Sed } 316193323Sed 317193323Sed // Reserve entries in the vector for each of the SUnits we are creating. This 318193323Sed // ensure that reallocation of the vector won't happen, so SUnit*'s won't get 319193323Sed // invalidated. 320193323Sed // FIXME: Multiply by 2 because we may clone nodes during scheduling. 321193323Sed // This is a temporary workaround. 322193323Sed SUnits.reserve(NumNodes * 2); 323218893Sdim 324204642Srdivacky // Add all nodes in depth first order. 325204642Srdivacky SmallVector<SDNode*, 64> Worklist; 326204642Srdivacky SmallPtrSet<SDNode*, 64> Visited; 327204642Srdivacky Worklist.push_back(DAG->getRoot().getNode()); 328204642Srdivacky Visited.insert(DAG->getRoot().getNode()); 329218893Sdim 330221345Sdim SmallVector<SUnit*, 8> CallSUnits; 331204642Srdivacky while (!Worklist.empty()) { 332204642Srdivacky SDNode *NI = Worklist.pop_back_val(); 333218893Sdim 334204642Srdivacky // Add all operands to the worklist unless they've already been added. 335204642Srdivacky for (unsigned i = 0, e = NI->getNumOperands(); i != e; ++i) 336204642Srdivacky if (Visited.insert(NI->getOperand(i).getNode())) 337204642Srdivacky Worklist.push_back(NI->getOperand(i).getNode()); 338218893Sdim 339193323Sed if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate. 340193323Sed continue; 341218893Sdim 342193323Sed // If this node has already been processed, stop now. 343193323Sed if (NI->getNodeId() != -1) continue; 344218893Sdim 345235633Sdim SUnit *NodeSUnit = newSUnit(NI); 346218893Sdim 347218893Sdim // See if anything is glued to this node, if so, add them to glued 348218893Sdim // nodes. Nodes can have at most one glue input and one glue output. Glue 349218893Sdim // is required to be the last operand and result of a node. 350218893Sdim 351218893Sdim // Scan up to find glued preds. 352193323Sed SDNode *N = NI; 353193323Sed while (N->getNumOperands() && 354218893Sdim N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) { 355193323Sed N = N->getOperand(N->getNumOperands()-1).getNode(); 356193323Sed assert(N->getNodeId() == -1 && "Node already inserted!"); 357193323Sed N->setNodeId(NodeSUnit->NodeNum); 358218893Sdim if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) 359218893Sdim NodeSUnit->isCall = true; 360193323Sed } 361218893Sdim 362218893Sdim // Scan down to find any glued succs. 363193323Sed N = NI; 364218893Sdim while (N->getValueType(N->getNumValues()-1) == MVT::Glue) { 365218893Sdim SDValue GlueVal(N, N->getNumValues()-1); 366218893Sdim 367218893Sdim // There are either zero or one users of the Glue result. 368218893Sdim bool HasGlueUse = false; 369218893Sdim for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 370193323Sed UI != E; ++UI) 371218893Sdim if (GlueVal.isOperandOf(*UI)) { 372218893Sdim HasGlueUse = true; 373193323Sed assert(N->getNodeId() == -1 && "Node already inserted!"); 374193323Sed N->setNodeId(NodeSUnit->NodeNum); 375193323Sed N = *UI; 376218893Sdim if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) 377218893Sdim NodeSUnit->isCall = true; 378193323Sed break; 379193323Sed } 380218893Sdim if (!HasGlueUse) break; 381193323Sed } 382218893Sdim 383221345Sdim if (NodeSUnit->isCall) 384221345Sdim CallSUnits.push_back(NodeSUnit); 385221345Sdim 386221345Sdim // Schedule zero-latency TokenFactor below any nodes that may increase the 387221345Sdim // schedule height. Otherwise, ancestors of the TokenFactor may appear to 388221345Sdim // have false stalls. 389221345Sdim if (NI->getOpcode() == ISD::TokenFactor) 390221345Sdim NodeSUnit->isScheduleLow = true; 391221345Sdim 392218893Sdim // If there are glue operands involved, N is now the bottom-most node 393218893Sdim // of the sequence of nodes that are glued together. 394193323Sed // Update the SUnit. 395193323Sed NodeSUnit->setNode(N); 396193323Sed assert(N->getNodeId() == -1 && "Node already inserted!"); 397193323Sed N->setNodeId(NodeSUnit->NodeNum); 398193323Sed 399218893Sdim // Compute NumRegDefsLeft. This must be done before AddSchedEdges. 400218893Sdim InitNumRegDefsLeft(NodeSUnit); 401218893Sdim 402193323Sed // Assign the Latency field of NodeSUnit using target-provided information. 403235633Sdim computeLatency(NodeSUnit); 404193323Sed } 405221345Sdim 406221345Sdim // Find all call operands. 407221345Sdim while (!CallSUnits.empty()) { 408221345Sdim SUnit *SU = CallSUnits.pop_back_val(); 409221345Sdim for (const SDNode *SUNode = SU->getNode(); SUNode; 410221345Sdim SUNode = SUNode->getGluedNode()) { 411221345Sdim if (SUNode->getOpcode() != ISD::CopyToReg) 412221345Sdim continue; 413221345Sdim SDNode *SrcN = SUNode->getOperand(2).getNode(); 414221345Sdim if (isPassiveNode(SrcN)) continue; // Not scheduled. 415221345Sdim SUnit *SrcSU = &SUnits[SrcN->getNodeId()]; 416221345Sdim SrcSU->isCallOp = true; 417221345Sdim } 418221345Sdim } 419193323Sed} 420193323Sed 421193323Sedvoid ScheduleDAGSDNodes::AddSchedEdges() { 422224145Sdim const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>(); 423198090Srdivacky 424198090Srdivacky // Check to see if the scheduler cares about latencies. 425235633Sdim bool UnitLatencies = forceUnitLatencies(); 426198090Srdivacky 427193323Sed // Pass 2: add the preds, succs, etc. 428193323Sed for (unsigned su = 0, e = SUnits.size(); su != e; ++su) { 429193323Sed SUnit *SU = &SUnits[su]; 430193323Sed SDNode *MainNode = SU->getNode(); 431218893Sdim 432193323Sed if (MainNode->isMachineOpcode()) { 433193323Sed unsigned Opc = MainNode->getMachineOpcode(); 434224145Sdim const MCInstrDesc &MCID = TII->get(Opc); 435224145Sdim for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { 436224145Sdim if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { 437193323Sed SU->isTwoAddress = true; 438193323Sed break; 439193323Sed } 440193323Sed } 441224145Sdim if (MCID.isCommutable()) 442193323Sed SU->isCommutable = true; 443193323Sed } 444218893Sdim 445193323Sed // Find all predecessors and successors of the group. 446218893Sdim for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) { 447193323Sed if (N->isMachineOpcode() && 448193323Sed TII->get(N->getMachineOpcode()).getImplicitDefs()) { 449193323Sed SU->hasPhysRegClobbers = true; 450198090Srdivacky unsigned NumUsed = InstrEmitter::CountResults(N); 451193323Sed while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1)) 452193323Sed --NumUsed; // Skip over unused values at the end. 453193323Sed if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs()) 454193323Sed SU->hasPhysRegDefs = true; 455193323Sed } 456218893Sdim 457193323Sed for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 458193323Sed SDNode *OpN = N->getOperand(i).getNode(); 459193323Sed if (isPassiveNode(OpN)) continue; // Not scheduled. 460193323Sed SUnit *OpSU = &SUnits[OpN->getNodeId()]; 461193323Sed assert(OpSU && "Node has no SUnit!"); 462193323Sed if (OpSU == SU) continue; // In the same group. 463193323Sed 464198090Srdivacky EVT OpVT = N->getOperand(i).getValueType(); 465218893Sdim assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!"); 466193323Sed bool isChain = OpVT == MVT::Other; 467193323Sed 468193323Sed unsigned PhysReg = 0; 469193323Sed int Cost = 1; 470193323Sed // Determine if this is a physical register dependency. 471193323Sed CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); 472193323Sed assert((PhysReg == 0 || !isChain) && 473193323Sed "Chain dependence via physreg data?"); 474193323Sed // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler 475193323Sed // emits a copy from the physical register to a virtual register unless 476193323Sed // it requires a cross class copy (cost < 0). That means we are only 477193323Sed // treating "expensive to copy" register dependency as physical register 478193323Sed // dependency. This may change in the future though. 479224145Sdim if (Cost >= 0 && !StressSched) 480193323Sed PhysReg = 0; 481198090Srdivacky 482210299Sed // If this is a ctrl dep, latency is 1. 483210299Sed unsigned OpLatency = isChain ? 1 : OpSU->Latency; 484221345Sdim // Special-case TokenFactor chains as zero-latency. 485221345Sdim if(isChain && OpN->getOpcode() == ISD::TokenFactor) 486221345Sdim OpLatency = 0; 487221345Sdim 488245431Sdim SDep Dep = isChain ? SDep(OpSU, SDep::Barrier) 489245431Sdim : SDep(OpSU, SDep::Data, PhysReg); 490245431Sdim Dep.setLatency(OpLatency); 491198090Srdivacky if (!isChain && !UnitLatencies) { 492245431Sdim computeOperandLatency(OpN, N, i, Dep); 493245431Sdim ST.adjustSchedDependency(OpSU, SU, Dep); 494198090Srdivacky } 495198090Srdivacky 496245431Sdim if (!SU->addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) { 497218893Sdim // Multiple register uses are combined in the same SUnit. For example, 498218893Sdim // we could have a set of glued nodes with all their defs consumed by 499218893Sdim // another set of glued nodes. Register pressure tracking sees this as 500218893Sdim // a single use, so to keep pressure balanced we reduce the defs. 501221345Sdim // 502221345Sdim // We can't tell (without more book-keeping) if this results from 503221345Sdim // glued nodes or duplicate operands. As long as we don't reduce 504221345Sdim // NumRegDefsLeft to zero, we handle the common cases well. 505218893Sdim --OpSU->NumRegDefsLeft; 506218893Sdim } 507193323Sed } 508193323Sed } 509193323Sed } 510193323Sed} 511193323Sed 512193323Sed/// BuildSchedGraph - Build the SUnit graph from the selection dag that we 513193323Sed/// are input. This SUnit graph is similar to the SelectionDAG, but 514193323Sed/// excludes nodes that aren't interesting to scheduling, and represents 515218893Sdim/// glued together nodes with a single SUnit. 516198090Srdivackyvoid ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) { 517210299Sed // Cluster certain nodes which should be scheduled together. 518210299Sed ClusterNodes(); 519193323Sed // Populate the SUnits array. 520193323Sed BuildSchedUnits(); 521193323Sed // Compute all the scheduling dependencies between nodes. 522193323Sed AddSchedEdges(); 523193323Sed} 524193323Sed 525218893Sdim// Initialize NumNodeDefs for the current Node's opcode. 526218893Sdimvoid ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() { 527221345Sdim // Check for phys reg copy. 528221345Sdim if (!Node) 529221345Sdim return; 530221345Sdim 531218893Sdim if (!Node->isMachineOpcode()) { 532218893Sdim if (Node->getOpcode() == ISD::CopyFromReg) 533218893Sdim NodeNumDefs = 1; 534218893Sdim else 535218893Sdim NodeNumDefs = 0; 536218893Sdim return; 537218893Sdim } 538218893Sdim unsigned POpc = Node->getMachineOpcode(); 539218893Sdim if (POpc == TargetOpcode::IMPLICIT_DEF) { 540218893Sdim // No register need be allocated for this. 541218893Sdim NodeNumDefs = 0; 542218893Sdim return; 543218893Sdim } 544218893Sdim unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs(); 545218893Sdim // Some instructions define regs that are not represented in the selection DAG 546218893Sdim // (e.g. unused flags). See tMOVi8. Make sure we don't access past NumValues. 547218893Sdim NodeNumDefs = std::min(Node->getNumValues(), NRegDefs); 548218893Sdim DefIdx = 0; 549218893Sdim} 550218893Sdim 551218893Sdim// Construct a RegDefIter for this SUnit and find the first valid value. 552218893SdimScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU, 553218893Sdim const ScheduleDAGSDNodes *SD) 554218893Sdim : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { 555218893Sdim InitNodeNumDefs(); 556218893Sdim Advance(); 557218893Sdim} 558218893Sdim 559218893Sdim// Advance to the next valid value defined by the SUnit. 560218893Sdimvoid ScheduleDAGSDNodes::RegDefIter::Advance() { 561218893Sdim for (;Node;) { // Visit all glued nodes. 562218893Sdim for (;DefIdx < NodeNumDefs; ++DefIdx) { 563218893Sdim if (!Node->hasAnyUseOfValue(DefIdx)) 564218893Sdim continue; 565252723Sdim ValueType = Node->getSimpleValueType(DefIdx); 566218893Sdim ++DefIdx; 567218893Sdim return; // Found a normal regdef. 568218893Sdim } 569218893Sdim Node = Node->getGluedNode(); 570218893Sdim if (Node == NULL) { 571218893Sdim return; // No values left to visit. 572218893Sdim } 573218893Sdim InitNodeNumDefs(); 574218893Sdim } 575218893Sdim} 576218893Sdim 577218893Sdimvoid ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) { 578218893Sdim assert(SU->NumRegDefsLeft == 0 && "expect a new node"); 579218893Sdim for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) { 580218893Sdim assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected"); 581218893Sdim ++SU->NumRegDefsLeft; 582218893Sdim } 583218893Sdim} 584218893Sdim 585235633Sdimvoid ScheduleDAGSDNodes::computeLatency(SUnit *SU) { 586221345Sdim SDNode *N = SU->getNode(); 587221345Sdim 588221345Sdim // TokenFactor operands are considered zero latency, and some schedulers 589221345Sdim // (e.g. Top-Down list) may rely on the fact that operand latency is nonzero 590221345Sdim // whenever node latency is nonzero. 591221345Sdim if (N && N->getOpcode() == ISD::TokenFactor) { 592221345Sdim SU->Latency = 0; 593221345Sdim return; 594221345Sdim } 595221345Sdim 596208599Srdivacky // Check to see if the scheduler cares about latencies. 597235633Sdim if (forceUnitLatencies()) { 598208599Srdivacky SU->Latency = 1; 599208599Srdivacky return; 600208599Srdivacky } 601208599Srdivacky 602218893Sdim if (!InstrItins || InstrItins->isEmpty()) { 603221345Sdim if (N && N->isMachineOpcode() && 604221345Sdim TII->isHighLatencyDef(N->getMachineOpcode())) 605221345Sdim SU->Latency = HighLatencyCycles; 606221345Sdim else 607221345Sdim SU->Latency = 1; 608208599Srdivacky return; 609208599Srdivacky } 610218893Sdim 611193323Sed // Compute the latency for the node. We use the sum of the latencies for 612218893Sdim // all nodes glued together into this SUnit. 613193323Sed SU->Latency = 0; 614218893Sdim for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) 615218893Sdim if (N->isMachineOpcode()) 616218893Sdim SU->Latency += TII->getInstrLatency(InstrItins, N); 617193323Sed} 618193323Sed 619235633Sdimvoid ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use, 620208599Srdivacky unsigned OpIdx, SDep& dep) const{ 621208599Srdivacky // Check to see if the scheduler cares about latencies. 622235633Sdim if (forceUnitLatencies()) 623208599Srdivacky return; 624208599Srdivacky 625208599Srdivacky if (dep.getKind() != SDep::Data) 626208599Srdivacky return; 627208599Srdivacky 628208599Srdivacky unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); 629218893Sdim if (Use->isMachineOpcode()) 630218893Sdim // Adjust the use operand index by num of defs. 631218893Sdim OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); 632218893Sdim int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); 633218893Sdim if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg && 634218893Sdim !BB->succ_empty()) { 635218893Sdim unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg(); 636218893Sdim if (TargetRegisterInfo::isVirtualRegister(Reg)) 637218893Sdim // This copy is a liveout value. It is likely coalesced, so reduce the 638218893Sdim // latency so not to penalize the def. 639218893Sdim // FIXME: need target specific adjustment here? 640218893Sdim Latency = (Latency > 1) ? Latency - 1 : 1; 641208599Srdivacky } 642218893Sdim if (Latency >= 0) 643218893Sdim dep.setLatency(Latency); 644208599Srdivacky} 645208599Srdivacky 646193323Sedvoid ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const { 647245431Sdim#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 648193323Sed if (!SU->getNode()) { 649202375Srdivacky dbgs() << "PHYS REG COPY\n"; 650193323Sed return; 651193323Sed } 652193323Sed 653193323Sed SU->getNode()->dump(DAG); 654202375Srdivacky dbgs() << "\n"; 655218893Sdim SmallVector<SDNode *, 4> GluedNodes; 656218893Sdim for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode()) 657218893Sdim GluedNodes.push_back(N); 658218893Sdim while (!GluedNodes.empty()) { 659202375Srdivacky dbgs() << " "; 660218893Sdim GluedNodes.back()->dump(DAG); 661202375Srdivacky dbgs() << "\n"; 662218893Sdim GluedNodes.pop_back(); 663193323Sed } 664245431Sdim#endif 665193323Sed} 666198090Srdivacky 667245431Sdim#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 668235633Sdimvoid ScheduleDAGSDNodes::dumpSchedule() const { 669235633Sdim for (unsigned i = 0, e = Sequence.size(); i != e; i++) { 670235633Sdim if (SUnit *SU = Sequence[i]) 671235633Sdim SU->dump(this); 672235633Sdim else 673235633Sdim dbgs() << "**** NOOP ****\n"; 674235633Sdim } 675235633Sdim} 676245431Sdim#endif 677235633Sdim 678235633Sdim#ifndef NDEBUG 679235633Sdim/// VerifyScheduledSequence - Verify that all SUnits were scheduled and that 680235633Sdim/// their state is consistent with the nodes listed in Sequence. 681235633Sdim/// 682235633Sdimvoid ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) { 683235633Sdim unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp); 684235633Sdim unsigned Noops = 0; 685235633Sdim for (unsigned i = 0, e = Sequence.size(); i != e; ++i) 686235633Sdim if (!Sequence[i]) 687235633Sdim ++Noops; 688235633Sdim assert(Sequence.size() - Noops == ScheduledNodes && 689235633Sdim "The number of nodes scheduled doesn't match the expected number!"); 690235633Sdim} 691235633Sdim#endif // NDEBUG 692235633Sdim 693221345Sdim/// ProcessSDDbgValues - Process SDDbgValues associated with this node. 694263509Sdimstatic void 695263509SdimProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, 696263509Sdim SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, 697263509Sdim DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) { 698218893Sdim if (!N->getHasDebugValue()) 699206083Srdivacky return; 700206083Srdivacky 701206083Srdivacky // Opportunistically insert immediate dbg_value uses, i.e. those with source 702206083Srdivacky // order number right after the N. 703218893Sdim MachineBasicBlock *BB = Emitter.getBlock(); 704206083Srdivacky MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos(); 705224145Sdim ArrayRef<SDDbgValue*> DVs = DAG->GetDbgValues(N); 706206083Srdivacky for (unsigned i = 0, e = DVs.size(); i != e; ++i) { 707206083Srdivacky if (DVs[i]->isInvalidated()) 708206083Srdivacky continue; 709206083Srdivacky unsigned DVOrder = DVs[i]->getOrder(); 710218893Sdim if (!Order || DVOrder == ++Order) { 711207618Srdivacky MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap); 712207618Srdivacky if (DbgMI) { 713207618Srdivacky Orders.push_back(std::make_pair(DVOrder, DbgMI)); 714207618Srdivacky BB->insert(InsertPos, DbgMI); 715207618Srdivacky } 716206083Srdivacky DVs[i]->setIsInvalidated(); 717206083Srdivacky } 718206083Srdivacky } 719206083Srdivacky} 720206083Srdivacky 721218893Sdim// ProcessSourceNode - Process nodes with source order numbers. These are added 722218893Sdim// to a vector which EmitSchedule uses to determine how to insert dbg_value 723218893Sdim// instructions in the right order. 724263509Sdimstatic void 725263509SdimProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, 726263509Sdim DenseMap<SDValue, unsigned> &VRBaseMap, 727263509Sdim SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders, 728263509Sdim SmallSet<unsigned, 8> &Seen) { 729263509Sdim unsigned Order = N->getIROrder(); 730218893Sdim if (!Order || !Seen.insert(Order)) { 731218893Sdim // Process any valid SDDbgValues even if node does not have any order 732218893Sdim // assigned. 733218893Sdim ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0); 734218893Sdim return; 735218893Sdim } 736206083Srdivacky 737218893Sdim MachineBasicBlock *BB = Emitter.getBlock(); 738263509Sdim if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI() || 739263509Sdim // Fast-isel may have inserted some instructions, in which case the 740263509Sdim // BB->back().isPHI() test will not fire when we want it to. 741263509Sdim prior(Emitter.getInsertPos())->isPHI()) { 742218893Sdim // Did not insert any instruction. 743218893Sdim Orders.push_back(std::make_pair(Order, (MachineInstr*)0)); 744218893Sdim return; 745218893Sdim } 746218893Sdim 747218893Sdim Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos()))); 748218893Sdim ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); 749218893Sdim} 750218893Sdim 751235633Sdimvoid ScheduleDAGSDNodes:: 752235633SdimEmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap, 753235633Sdim MachineBasicBlock::iterator InsertPos) { 754235633Sdim for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 755235633Sdim I != E; ++I) { 756235633Sdim if (I->isCtrl()) continue; // ignore chain preds 757235633Sdim if (I->getSUnit()->CopyDstRC) { 758235633Sdim // Copy to physical register. 759235633Sdim DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit()); 760235633Sdim assert(VRI != VRBaseMap.end() && "Node emitted out of order - late"); 761235633Sdim // Find the destination physical register. 762235633Sdim unsigned Reg = 0; 763235633Sdim for (SUnit::const_succ_iterator II = SU->Succs.begin(), 764235633Sdim EE = SU->Succs.end(); II != EE; ++II) { 765235633Sdim if (II->isCtrl()) continue; // ignore chain preds 766235633Sdim if (II->getReg()) { 767235633Sdim Reg = II->getReg(); 768235633Sdim break; 769235633Sdim } 770235633Sdim } 771235633Sdim BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg) 772235633Sdim .addReg(VRI->second); 773235633Sdim } else { 774235633Sdim // Copy from physical register. 775235633Sdim assert(I->getReg() && "Unknown physical register!"); 776235633Sdim unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC); 777235633Sdim bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second; 778235633Sdim (void)isNew; // Silence compiler warning. 779235633Sdim assert(isNew && "Node emitted out of order - early"); 780235633Sdim BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase) 781235633Sdim .addReg(I->getReg()); 782235633Sdim } 783235633Sdim break; 784235633Sdim } 785235633Sdim} 786218893Sdim 787235633Sdim/// EmitSchedule - Emit the machine code in scheduled order. Return the new 788235633Sdim/// InsertPos and MachineBasicBlock that contains this insertion 789235633Sdim/// point. ScheduleDAGSDNodes holds a BB pointer for convenience, but this does 790235633Sdim/// not necessarily refer to returned BB. The emitter may split blocks. 791235633SdimMachineBasicBlock *ScheduleDAGSDNodes:: 792235633SdimEmitSchedule(MachineBasicBlock::iterator &InsertPos) { 793198090Srdivacky InstrEmitter Emitter(BB, InsertPos); 794198090Srdivacky DenseMap<SDValue, unsigned> VRBaseMap; 795198090Srdivacky DenseMap<SUnit*, unsigned> CopyVRBaseMap; 796206083Srdivacky SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; 797206083Srdivacky SmallSet<unsigned, 8> Seen; 798206083Srdivacky bool HasDbg = DAG->hasDebugValues(); 799205218Srdivacky 800207618Srdivacky // If this is the first BB, emit byval parameter dbg_value's. 801207618Srdivacky if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) { 802207618Srdivacky SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin(); 803207618Srdivacky SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd(); 804207618Srdivacky for (; PDI != PDE; ++PDI) { 805207618Srdivacky MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap); 806207618Srdivacky if (DbgMI) 807210299Sed BB->insert(InsertPos, DbgMI); 808207618Srdivacky } 809207618Srdivacky } 810207618Srdivacky 811198090Srdivacky for (unsigned i = 0, e = Sequence.size(); i != e; i++) { 812198090Srdivacky SUnit *SU = Sequence[i]; 813198090Srdivacky if (!SU) { 814198090Srdivacky // Null SUnit* is a noop. 815235633Sdim TII->insertNoop(*Emitter.getBlock(), InsertPos); 816198090Srdivacky continue; 817198090Srdivacky } 818198090Srdivacky 819198090Srdivacky // For pre-regalloc scheduling, create instructions corresponding to the 820218893Sdim // SDNode and any glued SDNodes and append them to the block. 821198090Srdivacky if (!SU->getNode()) { 822198090Srdivacky // Emit a copy. 823235633Sdim EmitPhysRegCopy(SU, CopyVRBaseMap, InsertPos); 824198090Srdivacky continue; 825198090Srdivacky } 826198090Srdivacky 827218893Sdim SmallVector<SDNode *, 4> GluedNodes; 828245431Sdim for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode()) 829218893Sdim GluedNodes.push_back(N); 830218893Sdim while (!GluedNodes.empty()) { 831218893Sdim SDNode *N = GluedNodes.back(); 832218893Sdim Emitter.EmitNode(GluedNodes.back(), SU->OrigNode != SU, SU->isCloned, 833207618Srdivacky VRBaseMap); 834207618Srdivacky // Remember the source order of the inserted instruction. 835206083Srdivacky if (HasDbg) 836207618Srdivacky ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen); 837218893Sdim GluedNodes.pop_back(); 838198090Srdivacky } 839198090Srdivacky Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, 840207618Srdivacky VRBaseMap); 841207618Srdivacky // Remember the source order of the inserted instruction. 842206083Srdivacky if (HasDbg) 843207618Srdivacky ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders, 844206083Srdivacky Seen); 845206083Srdivacky } 846206083Srdivacky 847207618Srdivacky // Insert all the dbg_values which have not already been inserted in source 848206083Srdivacky // order sequence. 849206083Srdivacky if (HasDbg) { 850210299Sed MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI(); 851206083Srdivacky 852206083Srdivacky // Sort the source order instructions and use the order to insert debug 853206083Srdivacky // values. 854263509Sdim std::sort(Orders.begin(), Orders.end(), less_first()); 855206083Srdivacky 856206083Srdivacky SDDbgInfo::DbgIterator DI = DAG->DbgBegin(); 857206083Srdivacky SDDbgInfo::DbgIterator DE = DAG->DbgEnd(); 858206083Srdivacky // Now emit the rest according to source order. 859206083Srdivacky unsigned LastOrder = 0; 860206083Srdivacky for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) { 861206083Srdivacky unsigned Order = Orders[i].first; 862206083Srdivacky MachineInstr *MI = Orders[i].second; 863206083Srdivacky // Insert all SDDbgValue's whose order(s) are before "Order". 864206083Srdivacky if (!MI) 865206083Srdivacky continue; 866206083Srdivacky for (; DI != DE && 867206083Srdivacky (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) { 868206083Srdivacky if ((*DI)->isInvalidated()) 869206083Srdivacky continue; 870207618Srdivacky MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap); 871207618Srdivacky if (DbgMI) { 872207618Srdivacky if (!LastOrder) 873207618Srdivacky // Insert to start of the BB (after PHIs). 874207618Srdivacky BB->insert(BBBegin, DbgMI); 875207618Srdivacky else { 876210299Sed // Insert at the instruction, which may be in a different 877210299Sed // block, if the block was split by a custom inserter. 878207618Srdivacky MachineBasicBlock::iterator Pos = MI; 879263509Sdim MI->getParent()->insert(Pos, DbgMI); 880207618Srdivacky } 881206083Srdivacky } 882205218Srdivacky } 883206083Srdivacky LastOrder = Order; 884206083Srdivacky } 885206083Srdivacky // Add trailing DbgValue's before the terminator. FIXME: May want to add 886206083Srdivacky // some of them before one or more conditional branches? 887235633Sdim SmallVector<MachineInstr*, 8> DbgMIs; 888206083Srdivacky while (DI != DE) { 889235633Sdim if (!(*DI)->isInvalidated()) 890235633Sdim if (MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap)) 891235633Sdim DbgMIs.push_back(DbgMI); 892206083Srdivacky ++DI; 893206083Srdivacky } 894235633Sdim 895235633Sdim MachineBasicBlock *InsertBB = Emitter.getBlock(); 896235633Sdim MachineBasicBlock::iterator Pos = InsertBB->getFirstTerminator(); 897235633Sdim InsertBB->insert(Pos, DbgMIs.begin(), DbgMIs.end()); 898198090Srdivacky } 899198090Srdivacky 900198090Srdivacky InsertPos = Emitter.getInsertPos(); 901235633Sdim return Emitter.getBlock(); 902198090Srdivacky} 903235633Sdim 904235633Sdim/// Return the basic block label. 905235633Sdimstd::string ScheduleDAGSDNodes::getDAGName() const { 906235633Sdim return "sunit-dag." + BB->getFullName(); 907235633Sdim} 908