FastISel.cpp revision 206274
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/Analysis/DebugInfo.h" 51#include "llvm/Target/TargetData.h" 52#include "llvm/Target/TargetInstrInfo.h" 53#include "llvm/Target/TargetLowering.h" 54#include "llvm/Target/TargetMachine.h" 55#include "FunctionLoweringInfo.h" 56using namespace llvm; 57 58unsigned FastISel::getRegForValue(Value *V) { 59 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 60 // Don't handle non-simple values in FastISel. 61 if (!RealVT.isSimple()) 62 return 0; 63 64 // Ignore illegal types. We must do this before looking up the value 65 // in ValueMap because Arguments are given virtual registers regardless 66 // of whether FastISel can handle them. 67 MVT VT = RealVT.getSimpleVT(); 68 if (!TLI.isTypeLegal(VT)) { 69 // Promote MVT::i1 to a legal type though, because it's common and easy. 70 if (VT == MVT::i1) 71 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 72 else 73 return 0; 74 } 75 76 // Look up the value to see if we already have a register for it. We 77 // cache values defined by Instructions across blocks, and other values 78 // only locally. This is because Instructions already have the SSA 79 // def-dominates-use requirement enforced. 80 if (ValueMap.count(V)) 81 return ValueMap[V]; 82 unsigned Reg = LocalValueMap[V]; 83 if (Reg != 0) 84 return Reg; 85 86 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 87 if (CI->getValue().getActiveBits() <= 64) 88 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 89 } else if (isa<AllocaInst>(V)) { 90 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 91 } else if (isa<ConstantPointerNull>(V)) { 92 // Translate this as an integer zero so that it can be 93 // local-CSE'd with actual integer zeros. 94 Reg = 95 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 96 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 97 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 98 99 if (!Reg) { 100 const APFloat &Flt = CF->getValueAPF(); 101 EVT IntVT = TLI.getPointerTy(); 102 103 uint64_t x[2]; 104 uint32_t IntBitWidth = IntVT.getSizeInBits(); 105 bool isExact; 106 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 107 APFloat::rmTowardZero, &isExact); 108 if (isExact) { 109 APInt IntVal(IntBitWidth, 2, x); 110 111 unsigned IntegerReg = 112 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 113 if (IntegerReg != 0) 114 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 115 } 116 } 117 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 118 if (!SelectOperator(CE, CE->getOpcode())) return 0; 119 Reg = LocalValueMap[CE]; 120 } else if (isa<UndefValue>(V)) { 121 Reg = createResultReg(TLI.getRegClassFor(VT)); 122 BuildMI(MBB, DL, TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 123 } 124 125 // If target-independent code couldn't handle the value, give target-specific 126 // code a try. 127 if (!Reg && isa<Constant>(V)) 128 Reg = TargetMaterializeConstant(cast<Constant>(V)); 129 130 // Don't cache constant materializations in the general ValueMap. 131 // To do so would require tracking what uses they dominate. 132 if (Reg != 0) 133 LocalValueMap[V] = Reg; 134 return Reg; 135} 136 137unsigned FastISel::lookUpRegForValue(Value *V) { 138 // Look up the value to see if we already have a register for it. We 139 // cache values defined by Instructions across blocks, and other values 140 // only locally. This is because Instructions already have the SSA 141 // def-dominatess-use requirement enforced. 142 if (ValueMap.count(V)) 143 return ValueMap[V]; 144 return LocalValueMap[V]; 145} 146 147/// UpdateValueMap - Update the value map to include the new mapping for this 148/// instruction, or insert an extra copy to get the result in a previous 149/// determined register. 150/// NOTE: This is only necessary because we might select a block that uses 151/// a value before we select the block that defines the value. It might be 152/// possible to fix this by selecting blocks in reverse postorder. 153unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) { 154 if (!isa<Instruction>(I)) { 155 LocalValueMap[I] = Reg; 156 return Reg; 157 } 158 159 unsigned &AssignedReg = ValueMap[I]; 160 if (AssignedReg == 0) 161 AssignedReg = Reg; 162 else if (Reg != AssignedReg) { 163 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 164 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 165 Reg, RegClass, RegClass); 166 } 167 return AssignedReg; 168} 169 170unsigned FastISel::getRegForGEPIndex(Value *Idx) { 171 unsigned IdxN = getRegForValue(Idx); 172 if (IdxN == 0) 173 // Unhandled operand. Halt "fast" selection and bail. 174 return 0; 175 176 // If the index is smaller or larger than intptr_t, truncate or extend it. 177 MVT PtrVT = TLI.getPointerTy(); 178 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 179 if (IdxVT.bitsLT(PtrVT)) 180 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN); 181 else if (IdxVT.bitsGT(PtrVT)) 182 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN); 183 return IdxN; 184} 185 186/// SelectBinaryOp - Select and emit code for a binary operator instruction, 187/// which has an opcode which directly corresponds to the given ISD opcode. 188/// 189bool FastISel::SelectBinaryOp(User *I, unsigned ISDOpcode) { 190 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 191 if (VT == MVT::Other || !VT.isSimple()) 192 // Unhandled type. Halt "fast" selection and bail. 193 return false; 194 195 // We only handle legal types. For example, on x86-32 the instruction 196 // selector contains all of the 64-bit instructions from x86-64, 197 // under the assumption that i64 won't be used if the target doesn't 198 // support it. 199 if (!TLI.isTypeLegal(VT)) { 200 // MVT::i1 is special. Allow AND, OR, or XOR because they 201 // don't require additional zeroing, which makes them easy. 202 if (VT == MVT::i1 && 203 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 204 ISDOpcode == ISD::XOR)) 205 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 206 else 207 return false; 208 } 209 210 unsigned Op0 = getRegForValue(I->getOperand(0)); 211 if (Op0 == 0) 212 // Unhandled operand. Halt "fast" selection and bail. 213 return false; 214 215 // Check if the second operand is a constant and handle it appropriately. 216 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 217 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 218 ISDOpcode, Op0, CI->getZExtValue()); 219 if (ResultReg != 0) { 220 // We successfully emitted code for the given LLVM Instruction. 221 UpdateValueMap(I, ResultReg); 222 return true; 223 } 224 } 225 226 // Check if the second operand is a constant float. 227 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 228 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 229 ISDOpcode, Op0, CF); 230 if (ResultReg != 0) { 231 // We successfully emitted code for the given LLVM Instruction. 232 UpdateValueMap(I, ResultReg); 233 return true; 234 } 235 } 236 237 unsigned Op1 = getRegForValue(I->getOperand(1)); 238 if (Op1 == 0) 239 // Unhandled operand. Halt "fast" selection and bail. 240 return false; 241 242 // Now we have both operands in registers. Emit the instruction. 243 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 244 ISDOpcode, Op0, Op1); 245 if (ResultReg == 0) 246 // Target-specific code wasn't able to find a machine opcode for 247 // the given ISD opcode and type. Halt "fast" selection and bail. 248 return false; 249 250 // We successfully emitted code for the given LLVM Instruction. 251 UpdateValueMap(I, ResultReg); 252 return true; 253} 254 255bool FastISel::SelectGetElementPtr(User *I) { 256 unsigned N = getRegForValue(I->getOperand(0)); 257 if (N == 0) 258 // Unhandled operand. Halt "fast" selection and bail. 259 return false; 260 261 const Type *Ty = I->getOperand(0)->getType(); 262 MVT VT = TLI.getPointerTy(); 263 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 264 OI != E; ++OI) { 265 Value *Idx = *OI; 266 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 267 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 268 if (Field) { 269 // N = N + Offset 270 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 271 // FIXME: This can be optimized by combining the add with a 272 // subsequent one. 273 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 274 if (N == 0) 275 // Unhandled operand. Halt "fast" selection and bail. 276 return false; 277 } 278 Ty = StTy->getElementType(Field); 279 } else { 280 Ty = cast<SequentialType>(Ty)->getElementType(); 281 282 // If this is a constant subscript, handle it quickly. 283 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 284 if (CI->getZExtValue() == 0) continue; 285 uint64_t Offs = 286 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 287 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 288 if (N == 0) 289 // Unhandled operand. Halt "fast" selection and bail. 290 return false; 291 continue; 292 } 293 294 // N = N + Idx * ElementSize; 295 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 296 unsigned IdxN = getRegForGEPIndex(Idx); 297 if (IdxN == 0) 298 // Unhandled operand. Halt "fast" selection and bail. 299 return false; 300 301 if (ElementSize != 1) { 302 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 303 if (IdxN == 0) 304 // Unhandled operand. Halt "fast" selection and bail. 305 return false; 306 } 307 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 308 if (N == 0) 309 // Unhandled operand. Halt "fast" selection and bail. 310 return false; 311 } 312 } 313 314 // We successfully emitted code for the given LLVM Instruction. 315 UpdateValueMap(I, N); 316 return true; 317} 318 319bool FastISel::SelectCall(User *I) { 320 Function *F = cast<CallInst>(I)->getCalledFunction(); 321 if (!F) return false; 322 323 unsigned IID = F->getIntrinsicID(); 324 switch (IID) { 325 default: break; 326 case Intrinsic::dbg_declare: { 327 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 328 if (!DIDescriptor::ValidDebugInfo(DI->getVariable(), CodeGenOpt::None) || 329 !MF.getMMI().hasDebugInfo()) 330 return true; 331 332 Value *Address = DI->getAddress(); 333 if (!Address) 334 return true; 335 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 336 // Don't handle byval struct arguments or VLAs, for example. 337 if (!AI) break; 338 DenseMap<const AllocaInst*, int>::iterator SI = 339 StaticAllocaMap.find(AI); 340 if (SI == StaticAllocaMap.end()) break; // VLAs. 341 int FI = SI->second; 342 if (!DI->getDebugLoc().isUnknown()) 343 MF.getMMI().setVariableDbgInfo(DI->getVariable(), FI, DI->getDebugLoc()); 344 345 // Building the map above is target independent. Generating DBG_VALUE 346 // inline is target dependent; do this now. 347 (void)TargetSelectInstruction(cast<Instruction>(I)); 348 return true; 349 } 350 case Intrinsic::dbg_value: { 351 // This requires target support, but right now X86 is the only Fast target. 352 DbgValueInst *DI = cast<DbgValueInst>(I); 353 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 354 Value *V = DI->getValue(); 355 if (!V) { 356 // Currently the optimizer can produce this; insert an undef to 357 // help debugging. Probably the optimizer should not do this. 358 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()). 359 addMetadata(DI->getVariable()); 360 } else if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 361 BuildMI(MBB, DL, II).addImm(CI->getZExtValue()).addImm(DI->getOffset()). 362 addMetadata(DI->getVariable()); 363 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 364 BuildMI(MBB, DL, II).addFPImm(CF).addImm(DI->getOffset()). 365 addMetadata(DI->getVariable()); 366 } else if (unsigned Reg = lookUpRegForValue(V)) { 367 BuildMI(MBB, DL, II).addReg(Reg, RegState::Debug).addImm(DI->getOffset()). 368 addMetadata(DI->getVariable()); 369 } else { 370 // We can't yet handle anything else here because it would require 371 // generating code, thus altering codegen because of debug info. 372 // Insert an undef so we can see what we dropped. 373 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()). 374 addMetadata(DI->getVariable()); 375 } 376 return true; 377 } 378 case Intrinsic::eh_exception: { 379 EVT VT = TLI.getValueType(I->getType()); 380 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 381 default: break; 382 case TargetLowering::Expand: { 383 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!"); 384 unsigned Reg = TLI.getExceptionAddressRegister(); 385 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 386 unsigned ResultReg = createResultReg(RC); 387 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 388 Reg, RC, RC); 389 assert(InsertedCopy && "Can't copy address registers!"); 390 InsertedCopy = InsertedCopy; 391 UpdateValueMap(I, ResultReg); 392 return true; 393 } 394 } 395 break; 396 } 397 case Intrinsic::eh_selector: { 398 EVT VT = TLI.getValueType(I->getType()); 399 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 400 default: break; 401 case TargetLowering::Expand: { 402 if (MBB->isLandingPad()) 403 AddCatchInfo(*cast<CallInst>(I), &MF.getMMI(), MBB); 404 else { 405#ifndef NDEBUG 406 CatchInfoLost.insert(cast<CallInst>(I)); 407#endif 408 // FIXME: Mark exception selector register as live in. Hack for PR1508. 409 unsigned Reg = TLI.getExceptionSelectorRegister(); 410 if (Reg) MBB->addLiveIn(Reg); 411 } 412 413 unsigned Reg = TLI.getExceptionSelectorRegister(); 414 EVT SrcVT = TLI.getPointerTy(); 415 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); 416 unsigned ResultReg = createResultReg(RC); 417 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg, 418 RC, RC); 419 assert(InsertedCopy && "Can't copy address registers!"); 420 InsertedCopy = InsertedCopy; 421 422 // Cast the register to the type of the selector. 423 if (SrcVT.bitsGT(MVT::i32)) 424 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, 425 ResultReg); 426 else if (SrcVT.bitsLT(MVT::i32)) 427 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, 428 ISD::SIGN_EXTEND, ResultReg); 429 if (ResultReg == 0) 430 // Unhandled operand. Halt "fast" selection and bail. 431 return false; 432 433 UpdateValueMap(I, ResultReg); 434 435 return true; 436 } 437 } 438 break; 439 } 440 } 441 return false; 442} 443 444bool FastISel::SelectCast(User *I, unsigned Opcode) { 445 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 446 EVT DstVT = TLI.getValueType(I->getType()); 447 448 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 449 DstVT == MVT::Other || !DstVT.isSimple()) 450 // Unhandled type. Halt "fast" selection and bail. 451 return false; 452 453 // Check if the destination type is legal. Or as a special case, 454 // it may be i1 if we're doing a truncate because that's 455 // easy and somewhat common. 456 if (!TLI.isTypeLegal(DstVT)) 457 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 458 // Unhandled type. Halt "fast" selection and bail. 459 return false; 460 461 // Check if the source operand is legal. Or as a special case, 462 // it may be i1 if we're doing zero-extension because that's 463 // easy and somewhat common. 464 if (!TLI.isTypeLegal(SrcVT)) 465 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 466 // Unhandled type. Halt "fast" selection and bail. 467 return false; 468 469 unsigned InputReg = getRegForValue(I->getOperand(0)); 470 if (!InputReg) 471 // Unhandled operand. Halt "fast" selection and bail. 472 return false; 473 474 // If the operand is i1, arrange for the high bits in the register to be zero. 475 if (SrcVT == MVT::i1) { 476 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT); 477 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 478 if (!InputReg) 479 return false; 480 } 481 // If the result is i1, truncate to the target's type for i1 first. 482 if (DstVT == MVT::i1) 483 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT); 484 485 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 486 DstVT.getSimpleVT(), 487 Opcode, 488 InputReg); 489 if (!ResultReg) 490 return false; 491 492 UpdateValueMap(I, ResultReg); 493 return true; 494} 495 496bool FastISel::SelectBitCast(User *I) { 497 // If the bitcast doesn't change the type, just use the operand value. 498 if (I->getType() == I->getOperand(0)->getType()) { 499 unsigned Reg = getRegForValue(I->getOperand(0)); 500 if (Reg == 0) 501 return false; 502 UpdateValueMap(I, Reg); 503 return true; 504 } 505 506 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 507 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 508 EVT DstVT = TLI.getValueType(I->getType()); 509 510 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 511 DstVT == MVT::Other || !DstVT.isSimple() || 512 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 513 // Unhandled type. Halt "fast" selection and bail. 514 return false; 515 516 unsigned Op0 = getRegForValue(I->getOperand(0)); 517 if (Op0 == 0) 518 // Unhandled operand. Halt "fast" selection and bail. 519 return false; 520 521 // First, try to perform the bitcast by inserting a reg-reg copy. 522 unsigned ResultReg = 0; 523 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 524 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 525 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 526 ResultReg = createResultReg(DstClass); 527 528 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 529 Op0, DstClass, SrcClass); 530 if (!InsertedCopy) 531 ResultReg = 0; 532 } 533 534 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 535 if (!ResultReg) 536 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 537 ISD::BIT_CONVERT, Op0); 538 539 if (!ResultReg) 540 return false; 541 542 UpdateValueMap(I, ResultReg); 543 return true; 544} 545 546bool 547FastISel::SelectInstruction(Instruction *I) { 548 // First, try doing target-independent selection. 549 if (SelectOperator(I, I->getOpcode())) 550 return true; 551 552 // Next, try calling the target to attempt to handle the instruction. 553 if (TargetSelectInstruction(I)) 554 return true; 555 556 return false; 557} 558 559/// FastEmitBranch - Emit an unconditional branch to the given block, 560/// unless it is the immediate (fall-through) successor, and update 561/// the CFG. 562void 563FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 564 if (MBB->isLayoutSuccessor(MSucc)) { 565 // The unconditional fall-through case, which needs no instructions. 566 } else { 567 // The unconditional branch case. 568 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 569 } 570 MBB->addSuccessor(MSucc); 571} 572 573/// SelectFNeg - Emit an FNeg operation. 574/// 575bool 576FastISel::SelectFNeg(User *I) { 577 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 578 if (OpReg == 0) return false; 579 580 // If the target has ISD::FNEG, use it. 581 EVT VT = TLI.getValueType(I->getType()); 582 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 583 ISD::FNEG, OpReg); 584 if (ResultReg != 0) { 585 UpdateValueMap(I, ResultReg); 586 return true; 587 } 588 589 // Bitcast the value to integer, twiddle the sign bit with xor, 590 // and then bitcast it back to floating-point. 591 if (VT.getSizeInBits() > 64) return false; 592 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 593 if (!TLI.isTypeLegal(IntVT)) 594 return false; 595 596 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 597 ISD::BIT_CONVERT, OpReg); 598 if (IntReg == 0) 599 return false; 600 601 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg, 602 UINT64_C(1) << (VT.getSizeInBits()-1), 603 IntVT.getSimpleVT()); 604 if (IntResultReg == 0) 605 return false; 606 607 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 608 ISD::BIT_CONVERT, IntResultReg); 609 if (ResultReg == 0) 610 return false; 611 612 UpdateValueMap(I, ResultReg); 613 return true; 614} 615 616bool 617FastISel::SelectOperator(User *I, unsigned Opcode) { 618 switch (Opcode) { 619 case Instruction::Add: 620 return SelectBinaryOp(I, ISD::ADD); 621 case Instruction::FAdd: 622 return SelectBinaryOp(I, ISD::FADD); 623 case Instruction::Sub: 624 return SelectBinaryOp(I, ISD::SUB); 625 case Instruction::FSub: 626 // FNeg is currently represented in LLVM IR as a special case of FSub. 627 if (BinaryOperator::isFNeg(I)) 628 return SelectFNeg(I); 629 return SelectBinaryOp(I, ISD::FSUB); 630 case Instruction::Mul: 631 return SelectBinaryOp(I, ISD::MUL); 632 case Instruction::FMul: 633 return SelectBinaryOp(I, ISD::FMUL); 634 case Instruction::SDiv: 635 return SelectBinaryOp(I, ISD::SDIV); 636 case Instruction::UDiv: 637 return SelectBinaryOp(I, ISD::UDIV); 638 case Instruction::FDiv: 639 return SelectBinaryOp(I, ISD::FDIV); 640 case Instruction::SRem: 641 return SelectBinaryOp(I, ISD::SREM); 642 case Instruction::URem: 643 return SelectBinaryOp(I, ISD::UREM); 644 case Instruction::FRem: 645 return SelectBinaryOp(I, ISD::FREM); 646 case Instruction::Shl: 647 return SelectBinaryOp(I, ISD::SHL); 648 case Instruction::LShr: 649 return SelectBinaryOp(I, ISD::SRL); 650 case Instruction::AShr: 651 return SelectBinaryOp(I, ISD::SRA); 652 case Instruction::And: 653 return SelectBinaryOp(I, ISD::AND); 654 case Instruction::Or: 655 return SelectBinaryOp(I, ISD::OR); 656 case Instruction::Xor: 657 return SelectBinaryOp(I, ISD::XOR); 658 659 case Instruction::GetElementPtr: 660 return SelectGetElementPtr(I); 661 662 case Instruction::Br: { 663 BranchInst *BI = cast<BranchInst>(I); 664 665 if (BI->isUnconditional()) { 666 BasicBlock *LLVMSucc = BI->getSuccessor(0); 667 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 668 FastEmitBranch(MSucc); 669 return true; 670 } 671 672 // Conditional branches are not handed yet. 673 // Halt "fast" selection and bail. 674 return false; 675 } 676 677 case Instruction::Unreachable: 678 // Nothing to emit. 679 return true; 680 681 case Instruction::PHI: 682 // PHI nodes are already emitted. 683 return true; 684 685 case Instruction::Alloca: 686 // FunctionLowering has the static-sized case covered. 687 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 688 return true; 689 690 // Dynamic-sized alloca is not handled yet. 691 return false; 692 693 case Instruction::Call: 694 return SelectCall(I); 695 696 case Instruction::BitCast: 697 return SelectBitCast(I); 698 699 case Instruction::FPToSI: 700 return SelectCast(I, ISD::FP_TO_SINT); 701 case Instruction::ZExt: 702 return SelectCast(I, ISD::ZERO_EXTEND); 703 case Instruction::SExt: 704 return SelectCast(I, ISD::SIGN_EXTEND); 705 case Instruction::Trunc: 706 return SelectCast(I, ISD::TRUNCATE); 707 case Instruction::SIToFP: 708 return SelectCast(I, ISD::SINT_TO_FP); 709 710 case Instruction::IntToPtr: // Deliberate fall-through. 711 case Instruction::PtrToInt: { 712 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 713 EVT DstVT = TLI.getValueType(I->getType()); 714 if (DstVT.bitsGT(SrcVT)) 715 return SelectCast(I, ISD::ZERO_EXTEND); 716 if (DstVT.bitsLT(SrcVT)) 717 return SelectCast(I, ISD::TRUNCATE); 718 unsigned Reg = getRegForValue(I->getOperand(0)); 719 if (Reg == 0) return false; 720 UpdateValueMap(I, Reg); 721 return true; 722 } 723 724 default: 725 // Unhandled instruction. Halt "fast" selection and bail. 726 return false; 727 } 728} 729 730FastISel::FastISel(MachineFunction &mf, 731 DenseMap<const Value *, unsigned> &vm, 732 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 733 DenseMap<const AllocaInst *, int> &am 734#ifndef NDEBUG 735 , SmallSet<Instruction*, 8> &cil 736#endif 737 ) 738 : MBB(0), 739 ValueMap(vm), 740 MBBMap(bm), 741 StaticAllocaMap(am), 742#ifndef NDEBUG 743 CatchInfoLost(cil), 744#endif 745 MF(mf), 746 MRI(MF.getRegInfo()), 747 MFI(*MF.getFrameInfo()), 748 MCP(*MF.getConstantPool()), 749 TM(MF.getTarget()), 750 TD(*TM.getTargetData()), 751 TII(*TM.getInstrInfo()), 752 TLI(*TM.getTargetLowering()) { 753} 754 755FastISel::~FastISel() {} 756 757unsigned FastISel::FastEmit_(MVT, MVT, 758 unsigned) { 759 return 0; 760} 761 762unsigned FastISel::FastEmit_r(MVT, MVT, 763 unsigned, unsigned /*Op0*/) { 764 return 0; 765} 766 767unsigned FastISel::FastEmit_rr(MVT, MVT, 768 unsigned, unsigned /*Op0*/, 769 unsigned /*Op0*/) { 770 return 0; 771} 772 773unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 774 return 0; 775} 776 777unsigned FastISel::FastEmit_f(MVT, MVT, 778 unsigned, ConstantFP * /*FPImm*/) { 779 return 0; 780} 781 782unsigned FastISel::FastEmit_ri(MVT, MVT, 783 unsigned, unsigned /*Op0*/, 784 uint64_t /*Imm*/) { 785 return 0; 786} 787 788unsigned FastISel::FastEmit_rf(MVT, MVT, 789 unsigned, unsigned /*Op0*/, 790 ConstantFP * /*FPImm*/) { 791 return 0; 792} 793 794unsigned FastISel::FastEmit_rri(MVT, MVT, 795 unsigned, 796 unsigned /*Op0*/, unsigned /*Op1*/, 797 uint64_t /*Imm*/) { 798 return 0; 799} 800 801/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 802/// to emit an instruction with an immediate operand using FastEmit_ri. 803/// If that fails, it materializes the immediate into a register and try 804/// FastEmit_rr instead. 805unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode, 806 unsigned Op0, uint64_t Imm, 807 MVT ImmType) { 808 // First check if immediate type is legal. If not, we can't use the ri form. 809 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 810 if (ResultReg != 0) 811 return ResultReg; 812 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 813 if (MaterialReg == 0) 814 return 0; 815 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 816} 817 818/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 819/// to emit an instruction with a floating-point immediate operand using 820/// FastEmit_rf. If that fails, it materializes the immediate into a register 821/// and try FastEmit_rr instead. 822unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode, 823 unsigned Op0, ConstantFP *FPImm, 824 MVT ImmType) { 825 // First check if immediate type is legal. If not, we can't use the rf form. 826 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 827 if (ResultReg != 0) 828 return ResultReg; 829 830 // Materialize the constant in a register. 831 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 832 if (MaterialReg == 0) { 833 // If the target doesn't have a way to directly enter a floating-point 834 // value into a register, use an alternate approach. 835 // TODO: The current approach only supports floating-point constants 836 // that can be constructed by conversion from integer values. This should 837 // be replaced by code that creates a load from a constant-pool entry, 838 // which will require some target-specific work. 839 const APFloat &Flt = FPImm->getValueAPF(); 840 EVT IntVT = TLI.getPointerTy(); 841 842 uint64_t x[2]; 843 uint32_t IntBitWidth = IntVT.getSizeInBits(); 844 bool isExact; 845 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 846 APFloat::rmTowardZero, &isExact); 847 if (!isExact) 848 return 0; 849 APInt IntVal(IntBitWidth, 2, x); 850 851 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 852 ISD::Constant, IntVal.getZExtValue()); 853 if (IntegerReg == 0) 854 return 0; 855 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 856 ISD::SINT_TO_FP, IntegerReg); 857 if (MaterialReg == 0) 858 return 0; 859 } 860 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 861} 862 863unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 864 return MRI.createVirtualRegister(RC); 865} 866 867unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 868 const TargetRegisterClass* RC) { 869 unsigned ResultReg = createResultReg(RC); 870 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 871 872 BuildMI(MBB, DL, II, ResultReg); 873 return ResultReg; 874} 875 876unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 877 const TargetRegisterClass *RC, 878 unsigned Op0) { 879 unsigned ResultReg = createResultReg(RC); 880 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 881 882 if (II.getNumDefs() >= 1) 883 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 884 else { 885 BuildMI(MBB, DL, II).addReg(Op0); 886 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 887 II.ImplicitDefs[0], RC, RC); 888 if (!InsertedCopy) 889 ResultReg = 0; 890 } 891 892 return ResultReg; 893} 894 895unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 896 const TargetRegisterClass *RC, 897 unsigned Op0, unsigned Op1) { 898 unsigned ResultReg = createResultReg(RC); 899 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 900 901 if (II.getNumDefs() >= 1) 902 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 903 else { 904 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 905 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 906 II.ImplicitDefs[0], RC, RC); 907 if (!InsertedCopy) 908 ResultReg = 0; 909 } 910 return ResultReg; 911} 912 913unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 914 const TargetRegisterClass *RC, 915 unsigned Op0, uint64_t Imm) { 916 unsigned ResultReg = createResultReg(RC); 917 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 918 919 if (II.getNumDefs() >= 1) 920 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 921 else { 922 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 923 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 924 II.ImplicitDefs[0], RC, RC); 925 if (!InsertedCopy) 926 ResultReg = 0; 927 } 928 return ResultReg; 929} 930 931unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 932 const TargetRegisterClass *RC, 933 unsigned Op0, ConstantFP *FPImm) { 934 unsigned ResultReg = createResultReg(RC); 935 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 936 937 if (II.getNumDefs() >= 1) 938 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 939 else { 940 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 941 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 942 II.ImplicitDefs[0], RC, RC); 943 if (!InsertedCopy) 944 ResultReg = 0; 945 } 946 return ResultReg; 947} 948 949unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 950 const TargetRegisterClass *RC, 951 unsigned Op0, unsigned Op1, uint64_t Imm) { 952 unsigned ResultReg = createResultReg(RC); 953 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 954 955 if (II.getNumDefs() >= 1) 956 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 957 else { 958 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 959 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 960 II.ImplicitDefs[0], RC, RC); 961 if (!InsertedCopy) 962 ResultReg = 0; 963 } 964 return ResultReg; 965} 966 967unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 968 const TargetRegisterClass *RC, 969 uint64_t Imm) { 970 unsigned ResultReg = createResultReg(RC); 971 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 972 973 if (II.getNumDefs() >= 1) 974 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 975 else { 976 BuildMI(MBB, DL, II).addImm(Imm); 977 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 978 II.ImplicitDefs[0], RC, RC); 979 if (!InsertedCopy) 980 ResultReg = 0; 981 } 982 return ResultReg; 983} 984 985unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 986 unsigned Op0, uint32_t Idx) { 987 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 988 989 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 990 const TargetInstrDesc &II = TII.get(TargetOpcode::EXTRACT_SUBREG); 991 992 if (II.getNumDefs() >= 1) 993 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 994 else { 995 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 996 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 997 II.ImplicitDefs[0], RC, RC); 998 if (!InsertedCopy) 999 ResultReg = 0; 1000 } 1001 return ResultReg; 1002} 1003 1004/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1005/// with all but the least significant bit set to zero. 1006unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) { 1007 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 1008} 1009