DAGCombiner.cpp revision 223017
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetLowering.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/raw_ostream.h" 38#include <algorithm> 39using namespace llvm; 40 41STATISTIC(NodesCombined , "Number of dag nodes combined"); 42STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 136 SDValue PromoteIntBinOp(SDValue Op); 137 SDValue PromoteIntShiftOp(SDValue Op); 138 SDValue PromoteExtend(SDValue Op); 139 bool PromoteLoad(SDValue Op); 140 141 /// combine - call the node-specific routine that knows how to fold each 142 /// particular type of node. If that doesn't do anything, try the 143 /// target-specific DAG combines. 144 SDValue combine(SDNode *N); 145 146 // Visitation implementation - Implement dag node combining for different 147 // node types. The semantics are as follows: 148 // Return Value: 149 // SDValue.getNode() == 0 - No change was made 150 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 151 // otherwise - N should be replaced by the returned Operand. 152 // 153 SDValue visitTokenFactor(SDNode *N); 154 SDValue visitMERGE_VALUES(SDNode *N); 155 SDValue visitADD(SDNode *N); 156 SDValue visitSUB(SDNode *N); 157 SDValue visitADDC(SDNode *N); 158 SDValue visitADDE(SDNode *N); 159 SDValue visitMUL(SDNode *N); 160 SDValue visitSDIV(SDNode *N); 161 SDValue visitUDIV(SDNode *N); 162 SDValue visitSREM(SDNode *N); 163 SDValue visitUREM(SDNode *N); 164 SDValue visitMULHU(SDNode *N); 165 SDValue visitMULHS(SDNode *N); 166 SDValue visitSMUL_LOHI(SDNode *N); 167 SDValue visitUMUL_LOHI(SDNode *N); 168 SDValue visitSMULO(SDNode *N); 169 SDValue visitUMULO(SDNode *N); 170 SDValue visitSDIVREM(SDNode *N); 171 SDValue visitUDIVREM(SDNode *N); 172 SDValue visitAND(SDNode *N); 173 SDValue visitOR(SDNode *N); 174 SDValue visitXOR(SDNode *N); 175 SDValue SimplifyVBinOp(SDNode *N); 176 SDValue visitSHL(SDNode *N); 177 SDValue visitSRA(SDNode *N); 178 SDValue visitSRL(SDNode *N); 179 SDValue visitCTLZ(SDNode *N); 180 SDValue visitCTTZ(SDNode *N); 181 SDValue visitCTPOP(SDNode *N); 182 SDValue visitSELECT(SDNode *N); 183 SDValue visitSELECT_CC(SDNode *N); 184 SDValue visitSETCC(SDNode *N); 185 SDValue visitSIGN_EXTEND(SDNode *N); 186 SDValue visitZERO_EXTEND(SDNode *N); 187 SDValue visitANY_EXTEND(SDNode *N); 188 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 189 SDValue visitTRUNCATE(SDNode *N); 190 SDValue visitBITCAST(SDNode *N); 191 SDValue visitBUILD_PAIR(SDNode *N); 192 SDValue visitFADD(SDNode *N); 193 SDValue visitFSUB(SDNode *N); 194 SDValue visitFMUL(SDNode *N); 195 SDValue visitFDIV(SDNode *N); 196 SDValue visitFREM(SDNode *N); 197 SDValue visitFCOPYSIGN(SDNode *N); 198 SDValue visitSINT_TO_FP(SDNode *N); 199 SDValue visitUINT_TO_FP(SDNode *N); 200 SDValue visitFP_TO_SINT(SDNode *N); 201 SDValue visitFP_TO_UINT(SDNode *N); 202 SDValue visitFP_ROUND(SDNode *N); 203 SDValue visitFP_ROUND_INREG(SDNode *N); 204 SDValue visitFP_EXTEND(SDNode *N); 205 SDValue visitFNEG(SDNode *N); 206 SDValue visitFABS(SDNode *N); 207 SDValue visitBRCOND(SDNode *N); 208 SDValue visitBR_CC(SDNode *N); 209 SDValue visitLOAD(SDNode *N); 210 SDValue visitSTORE(SDNode *N); 211 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 212 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 213 SDValue visitBUILD_VECTOR(SDNode *N); 214 SDValue visitCONCAT_VECTORS(SDNode *N); 215 SDValue visitVECTOR_SHUFFLE(SDNode *N); 216 SDValue visitMEMBARRIER(SDNode *N); 217 218 SDValue XformToShuffleWithZero(SDNode *N); 219 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 220 221 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 222 223 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 224 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 225 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 226 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 227 SDValue N3, ISD::CondCode CC, 228 bool NotExtCompare = false); 229 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 230 DebugLoc DL, bool foldBooleans = true); 231 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 232 unsigned HiOp); 233 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 234 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 235 SDValue BuildSDIV(SDNode *N); 236 SDValue BuildUDIV(SDNode *N); 237 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 238 SDValue ReduceLoadWidth(SDNode *N); 239 SDValue ReduceLoadOpStoreWidth(SDNode *N); 240 SDValue TransformFPLoadStorePair(SDNode *N); 241 242 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 243 244 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 245 /// looking for aliasing nodes and adding them to the Aliases vector. 246 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 247 SmallVector<SDValue, 8> &Aliases); 248 249 /// isAlias - Return true if there is any possibility that the two addresses 250 /// overlap. 251 bool isAlias(SDValue Ptr1, int64_t Size1, 252 const Value *SrcValue1, int SrcValueOffset1, 253 unsigned SrcValueAlign1, 254 const MDNode *TBAAInfo1, 255 SDValue Ptr2, int64_t Size2, 256 const Value *SrcValue2, int SrcValueOffset2, 257 unsigned SrcValueAlign2, 258 const MDNode *TBAAInfo2) const; 259 260 /// FindAliasInfo - Extracts the relevant alias information from the memory 261 /// node. Returns true if the operand was a load. 262 bool FindAliasInfo(SDNode *N, 263 SDValue &Ptr, int64_t &Size, 264 const Value *&SrcValue, int &SrcValueOffset, 265 unsigned &SrcValueAlignment, 266 const MDNode *&TBAAInfo) const; 267 268 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 269 /// looking for a better chain (aliasing node.) 270 SDValue FindBetterChain(SDNode *N, SDValue Chain); 271 272 public: 273 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 274 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 275 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 276 277 /// Run - runs the dag combiner on all nodes in the work list 278 void Run(CombineLevel AtLevel); 279 280 SelectionDAG &getDAG() const { return DAG; } 281 282 /// getShiftAmountTy - Returns a type large enough to hold any valid 283 /// shift amount - before type legalization these can be huge. 284 EVT getShiftAmountTy(EVT LHSTy) { 285 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 286 } 287 288 /// isTypeLegal - This method returns true if we are running before type 289 /// legalization or if the specified VT is legal. 290 bool isTypeLegal(const EVT &VT) { 291 if (!LegalTypes) return true; 292 return TLI.isTypeLegal(VT); 293 } 294 }; 295} 296 297 298namespace { 299/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 300/// nodes from the worklist. 301class WorkListRemover : public SelectionDAG::DAGUpdateListener { 302 DAGCombiner &DC; 303public: 304 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 305 306 virtual void NodeDeleted(SDNode *N, SDNode *E) { 307 DC.removeFromWorkList(N); 308 } 309 310 virtual void NodeUpdated(SDNode *N) { 311 // Ignore updates. 312 } 313}; 314} 315 316//===----------------------------------------------------------------------===// 317// TargetLowering::DAGCombinerInfo implementation 318//===----------------------------------------------------------------------===// 319 320void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 321 ((DAGCombiner*)DC)->AddToWorkList(N); 322} 323 324void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 325 ((DAGCombiner*)DC)->removeFromWorkList(N); 326} 327 328SDValue TargetLowering::DAGCombinerInfo:: 329CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 330 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 331} 332 333SDValue TargetLowering::DAGCombinerInfo:: 334CombineTo(SDNode *N, SDValue Res, bool AddTo) { 335 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 336} 337 338 339SDValue TargetLowering::DAGCombinerInfo:: 340CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 341 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 342} 343 344void TargetLowering::DAGCombinerInfo:: 345CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 346 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 347} 348 349//===----------------------------------------------------------------------===// 350// Helper Functions 351//===----------------------------------------------------------------------===// 352 353/// isNegatibleForFree - Return 1 if we can compute the negated form of the 354/// specified expression for the same cost as the expression itself, or 2 if we 355/// can compute the negated form more cheaply than the expression itself. 356static char isNegatibleForFree(SDValue Op, bool LegalOperations, 357 unsigned Depth = 0) { 358 // No compile time optimizations on this type. 359 if (Op.getValueType() == MVT::ppcf128) 360 return 0; 361 362 // fneg is removable even if it has multiple uses. 363 if (Op.getOpcode() == ISD::FNEG) return 2; 364 365 // Don't allow anything with multiple uses. 366 if (!Op.hasOneUse()) return 0; 367 368 // Don't recurse exponentially. 369 if (Depth > 6) return 0; 370 371 switch (Op.getOpcode()) { 372 default: return false; 373 case ISD::ConstantFP: 374 // Don't invert constant FP values after legalize. The negated constant 375 // isn't necessarily legal. 376 return LegalOperations ? 0 : 1; 377 case ISD::FADD: 378 // FIXME: determine better conditions for this xform. 379 if (!UnsafeFPMath) return 0; 380 381 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 382 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 383 return V; 384 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 385 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 386 case ISD::FSUB: 387 // We can't turn -(A-B) into B-A when we honor signed zeros. 388 if (!UnsafeFPMath) return 0; 389 390 // fold (fneg (fsub A, B)) -> (fsub B, A) 391 return 1; 392 393 case ISD::FMUL: 394 case ISD::FDIV: 395 if (HonorSignDependentRoundingFPMath()) return 0; 396 397 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 398 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 399 return V; 400 401 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 402 403 case ISD::FP_EXTEND: 404 case ISD::FP_ROUND: 405 case ISD::FSIN: 406 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 407 } 408} 409 410/// GetNegatedExpression - If isNegatibleForFree returns true, this function 411/// returns the newly negated expression. 412static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 413 bool LegalOperations, unsigned Depth = 0) { 414 // fneg is removable even if it has multiple uses. 415 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 416 417 // Don't allow anything with multiple uses. 418 assert(Op.hasOneUse() && "Unknown reuse!"); 419 420 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 421 switch (Op.getOpcode()) { 422 default: llvm_unreachable("Unknown code"); 423 case ISD::ConstantFP: { 424 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 425 V.changeSign(); 426 return DAG.getConstantFP(V, Op.getValueType()); 427 } 428 case ISD::FADD: 429 // FIXME: determine better conditions for this xform. 430 assert(UnsafeFPMath); 431 432 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 433 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 434 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 435 GetNegatedExpression(Op.getOperand(0), DAG, 436 LegalOperations, Depth+1), 437 Op.getOperand(1)); 438 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 439 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 440 GetNegatedExpression(Op.getOperand(1), DAG, 441 LegalOperations, Depth+1), 442 Op.getOperand(0)); 443 case ISD::FSUB: 444 // We can't turn -(A-B) into B-A when we honor signed zeros. 445 assert(UnsafeFPMath); 446 447 // fold (fneg (fsub 0, B)) -> B 448 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 449 if (N0CFP->getValueAPF().isZero()) 450 return Op.getOperand(1); 451 452 // fold (fneg (fsub A, B)) -> (fsub B, A) 453 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 454 Op.getOperand(1), Op.getOperand(0)); 455 456 case ISD::FMUL: 457 case ISD::FDIV: 458 assert(!HonorSignDependentRoundingFPMath()); 459 460 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 461 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 462 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 463 GetNegatedExpression(Op.getOperand(0), DAG, 464 LegalOperations, Depth+1), 465 Op.getOperand(1)); 466 467 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 468 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 469 Op.getOperand(0), 470 GetNegatedExpression(Op.getOperand(1), DAG, 471 LegalOperations, Depth+1)); 472 473 case ISD::FP_EXTEND: 474 case ISD::FSIN: 475 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 476 GetNegatedExpression(Op.getOperand(0), DAG, 477 LegalOperations, Depth+1)); 478 case ISD::FP_ROUND: 479 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 480 GetNegatedExpression(Op.getOperand(0), DAG, 481 LegalOperations, Depth+1), 482 Op.getOperand(1)); 483 } 484} 485 486 487// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 488// that selects between the values 1 and 0, making it equivalent to a setcc. 489// Also, set the incoming LHS, RHS, and CC references to the appropriate 490// nodes based on the type of node we are checking. This simplifies life a 491// bit for the callers. 492static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 493 SDValue &CC) { 494 if (N.getOpcode() == ISD::SETCC) { 495 LHS = N.getOperand(0); 496 RHS = N.getOperand(1); 497 CC = N.getOperand(2); 498 return true; 499 } 500 if (N.getOpcode() == ISD::SELECT_CC && 501 N.getOperand(2).getOpcode() == ISD::Constant && 502 N.getOperand(3).getOpcode() == ISD::Constant && 503 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 504 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 505 LHS = N.getOperand(0); 506 RHS = N.getOperand(1); 507 CC = N.getOperand(4); 508 return true; 509 } 510 return false; 511} 512 513// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 514// one use. If this is true, it allows the users to invert the operation for 515// free when it is profitable to do so. 516static bool isOneUseSetCC(SDValue N) { 517 SDValue N0, N1, N2; 518 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 519 return true; 520 return false; 521} 522 523SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 524 SDValue N0, SDValue N1) { 525 EVT VT = N0.getValueType(); 526 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 527 if (isa<ConstantSDNode>(N1)) { 528 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 529 SDValue OpNode = 530 DAG.FoldConstantArithmetic(Opc, VT, 531 cast<ConstantSDNode>(N0.getOperand(1)), 532 cast<ConstantSDNode>(N1)); 533 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 534 } 535 if (N0.hasOneUse()) { 536 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 537 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 538 N0.getOperand(0), N1); 539 AddToWorkList(OpNode.getNode()); 540 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 541 } 542 } 543 544 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 545 if (isa<ConstantSDNode>(N0)) { 546 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 547 SDValue OpNode = 548 DAG.FoldConstantArithmetic(Opc, VT, 549 cast<ConstantSDNode>(N1.getOperand(1)), 550 cast<ConstantSDNode>(N0)); 551 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 552 } 553 if (N1.hasOneUse()) { 554 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 555 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 556 N1.getOperand(0), N0); 557 AddToWorkList(OpNode.getNode()); 558 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 559 } 560 } 561 562 return SDValue(); 563} 564 565SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 566 bool AddTo) { 567 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 568 ++NodesCombined; 569 DEBUG(dbgs() << "\nReplacing.1 "; 570 N->dump(&DAG); 571 dbgs() << "\nWith: "; 572 To[0].getNode()->dump(&DAG); 573 dbgs() << " and " << NumTo-1 << " other values\n"; 574 for (unsigned i = 0, e = NumTo; i != e; ++i) 575 assert((!To[i].getNode() || 576 N->getValueType(i) == To[i].getValueType()) && 577 "Cannot combine value to value of different type!")); 578 WorkListRemover DeadNodes(*this); 579 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 580 581 if (AddTo) { 582 // Push the new nodes and any users onto the worklist 583 for (unsigned i = 0, e = NumTo; i != e; ++i) { 584 if (To[i].getNode()) { 585 AddToWorkList(To[i].getNode()); 586 AddUsersToWorkList(To[i].getNode()); 587 } 588 } 589 } 590 591 // Finally, if the node is now dead, remove it from the graph. The node 592 // may not be dead if the replacement process recursively simplified to 593 // something else needing this node. 594 if (N->use_empty()) { 595 // Nodes can be reintroduced into the worklist. Make sure we do not 596 // process a node that has been replaced. 597 removeFromWorkList(N); 598 599 // Finally, since the node is now dead, remove it from the graph. 600 DAG.DeleteNode(N); 601 } 602 return SDValue(N, 0); 603} 604 605void DAGCombiner:: 606CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 607 // Replace all uses. If any nodes become isomorphic to other nodes and 608 // are deleted, make sure to remove them from our worklist. 609 WorkListRemover DeadNodes(*this); 610 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 611 612 // Push the new node and any (possibly new) users onto the worklist. 613 AddToWorkList(TLO.New.getNode()); 614 AddUsersToWorkList(TLO.New.getNode()); 615 616 // Finally, if the node is now dead, remove it from the graph. The node 617 // may not be dead if the replacement process recursively simplified to 618 // something else needing this node. 619 if (TLO.Old.getNode()->use_empty()) { 620 removeFromWorkList(TLO.Old.getNode()); 621 622 // If the operands of this node are only used by the node, they will now 623 // be dead. Make sure to visit them first to delete dead nodes early. 624 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 625 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 626 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 627 628 DAG.DeleteNode(TLO.Old.getNode()); 629 } 630} 631 632/// SimplifyDemandedBits - Check the specified integer node value to see if 633/// it can be simplified or if things it uses can be simplified by bit 634/// propagation. If so, return true. 635bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 636 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 637 APInt KnownZero, KnownOne; 638 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 639 return false; 640 641 // Revisit the node. 642 AddToWorkList(Op.getNode()); 643 644 // Replace the old value with the new one. 645 ++NodesCombined; 646 DEBUG(dbgs() << "\nReplacing.2 "; 647 TLO.Old.getNode()->dump(&DAG); 648 dbgs() << "\nWith: "; 649 TLO.New.getNode()->dump(&DAG); 650 dbgs() << '\n'); 651 652 CommitTargetLoweringOpt(TLO); 653 return true; 654} 655 656void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 657 DebugLoc dl = Load->getDebugLoc(); 658 EVT VT = Load->getValueType(0); 659 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 660 661 DEBUG(dbgs() << "\nReplacing.9 "; 662 Load->dump(&DAG); 663 dbgs() << "\nWith: "; 664 Trunc.getNode()->dump(&DAG); 665 dbgs() << '\n'); 666 WorkListRemover DeadNodes(*this); 667 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 668 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 669 &DeadNodes); 670 removeFromWorkList(Load); 671 DAG.DeleteNode(Load); 672 AddToWorkList(Trunc.getNode()); 673} 674 675SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 676 Replace = false; 677 DebugLoc dl = Op.getDebugLoc(); 678 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 679 EVT MemVT = LD->getMemoryVT(); 680 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 681 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 682 : ISD::EXTLOAD) 683 : LD->getExtensionType(); 684 Replace = true; 685 return DAG.getExtLoad(ExtType, dl, PVT, 686 LD->getChain(), LD->getBasePtr(), 687 LD->getPointerInfo(), 688 MemVT, LD->isVolatile(), 689 LD->isNonTemporal(), LD->getAlignment()); 690 } 691 692 unsigned Opc = Op.getOpcode(); 693 switch (Opc) { 694 default: break; 695 case ISD::AssertSext: 696 return DAG.getNode(ISD::AssertSext, dl, PVT, 697 SExtPromoteOperand(Op.getOperand(0), PVT), 698 Op.getOperand(1)); 699 case ISD::AssertZext: 700 return DAG.getNode(ISD::AssertZext, dl, PVT, 701 ZExtPromoteOperand(Op.getOperand(0), PVT), 702 Op.getOperand(1)); 703 case ISD::Constant: { 704 unsigned ExtOpc = 705 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 706 return DAG.getNode(ExtOpc, dl, PVT, Op); 707 } 708 } 709 710 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 711 return SDValue(); 712 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 713} 714 715SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 716 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 717 return SDValue(); 718 EVT OldVT = Op.getValueType(); 719 DebugLoc dl = Op.getDebugLoc(); 720 bool Replace = false; 721 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 722 if (NewOp.getNode() == 0) 723 return SDValue(); 724 AddToWorkList(NewOp.getNode()); 725 726 if (Replace) 727 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 728 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 729 DAG.getValueType(OldVT)); 730} 731 732SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 733 EVT OldVT = Op.getValueType(); 734 DebugLoc dl = Op.getDebugLoc(); 735 bool Replace = false; 736 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 737 if (NewOp.getNode() == 0) 738 return SDValue(); 739 AddToWorkList(NewOp.getNode()); 740 741 if (Replace) 742 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 743 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 744} 745 746/// PromoteIntBinOp - Promote the specified integer binary operation if the 747/// target indicates it is beneficial. e.g. On x86, it's usually better to 748/// promote i16 operations to i32 since i16 instructions are longer. 749SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 750 if (!LegalOperations) 751 return SDValue(); 752 753 EVT VT = Op.getValueType(); 754 if (VT.isVector() || !VT.isInteger()) 755 return SDValue(); 756 757 // If operation type is 'undesirable', e.g. i16 on x86, consider 758 // promoting it. 759 unsigned Opc = Op.getOpcode(); 760 if (TLI.isTypeDesirableForOp(Opc, VT)) 761 return SDValue(); 762 763 EVT PVT = VT; 764 // Consult target whether it is a good idea to promote this operation and 765 // what's the right type to promote it to. 766 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 767 assert(PVT != VT && "Don't know what type to promote to!"); 768 769 bool Replace0 = false; 770 SDValue N0 = Op.getOperand(0); 771 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 772 if (NN0.getNode() == 0) 773 return SDValue(); 774 775 bool Replace1 = false; 776 SDValue N1 = Op.getOperand(1); 777 SDValue NN1; 778 if (N0 == N1) 779 NN1 = NN0; 780 else { 781 NN1 = PromoteOperand(N1, PVT, Replace1); 782 if (NN1.getNode() == 0) 783 return SDValue(); 784 } 785 786 AddToWorkList(NN0.getNode()); 787 if (NN1.getNode()) 788 AddToWorkList(NN1.getNode()); 789 790 if (Replace0) 791 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 792 if (Replace1) 793 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 794 795 DEBUG(dbgs() << "\nPromoting "; 796 Op.getNode()->dump(&DAG)); 797 DebugLoc dl = Op.getDebugLoc(); 798 return DAG.getNode(ISD::TRUNCATE, dl, VT, 799 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 800 } 801 return SDValue(); 802} 803 804/// PromoteIntShiftOp - Promote the specified integer shift operation if the 805/// target indicates it is beneficial. e.g. On x86, it's usually better to 806/// promote i16 operations to i32 since i16 instructions are longer. 807SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 808 if (!LegalOperations) 809 return SDValue(); 810 811 EVT VT = Op.getValueType(); 812 if (VT.isVector() || !VT.isInteger()) 813 return SDValue(); 814 815 // If operation type is 'undesirable', e.g. i16 on x86, consider 816 // promoting it. 817 unsigned Opc = Op.getOpcode(); 818 if (TLI.isTypeDesirableForOp(Opc, VT)) 819 return SDValue(); 820 821 EVT PVT = VT; 822 // Consult target whether it is a good idea to promote this operation and 823 // what's the right type to promote it to. 824 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 825 assert(PVT != VT && "Don't know what type to promote to!"); 826 827 bool Replace = false; 828 SDValue N0 = Op.getOperand(0); 829 if (Opc == ISD::SRA) 830 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 831 else if (Opc == ISD::SRL) 832 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 833 else 834 N0 = PromoteOperand(N0, PVT, Replace); 835 if (N0.getNode() == 0) 836 return SDValue(); 837 838 AddToWorkList(N0.getNode()); 839 if (Replace) 840 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 841 842 DEBUG(dbgs() << "\nPromoting "; 843 Op.getNode()->dump(&DAG)); 844 DebugLoc dl = Op.getDebugLoc(); 845 return DAG.getNode(ISD::TRUNCATE, dl, VT, 846 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 847 } 848 return SDValue(); 849} 850 851SDValue DAGCombiner::PromoteExtend(SDValue Op) { 852 if (!LegalOperations) 853 return SDValue(); 854 855 EVT VT = Op.getValueType(); 856 if (VT.isVector() || !VT.isInteger()) 857 return SDValue(); 858 859 // If operation type is 'undesirable', e.g. i16 on x86, consider 860 // promoting it. 861 unsigned Opc = Op.getOpcode(); 862 if (TLI.isTypeDesirableForOp(Opc, VT)) 863 return SDValue(); 864 865 EVT PVT = VT; 866 // Consult target whether it is a good idea to promote this operation and 867 // what's the right type to promote it to. 868 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 869 assert(PVT != VT && "Don't know what type to promote to!"); 870 // fold (aext (aext x)) -> (aext x) 871 // fold (aext (zext x)) -> (zext x) 872 // fold (aext (sext x)) -> (sext x) 873 DEBUG(dbgs() << "\nPromoting "; 874 Op.getNode()->dump(&DAG)); 875 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 876 } 877 return SDValue(); 878} 879 880bool DAGCombiner::PromoteLoad(SDValue Op) { 881 if (!LegalOperations) 882 return false; 883 884 EVT VT = Op.getValueType(); 885 if (VT.isVector() || !VT.isInteger()) 886 return false; 887 888 // If operation type is 'undesirable', e.g. i16 on x86, consider 889 // promoting it. 890 unsigned Opc = Op.getOpcode(); 891 if (TLI.isTypeDesirableForOp(Opc, VT)) 892 return false; 893 894 EVT PVT = VT; 895 // Consult target whether it is a good idea to promote this operation and 896 // what's the right type to promote it to. 897 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 898 assert(PVT != VT && "Don't know what type to promote to!"); 899 900 DebugLoc dl = Op.getDebugLoc(); 901 SDNode *N = Op.getNode(); 902 LoadSDNode *LD = cast<LoadSDNode>(N); 903 EVT MemVT = LD->getMemoryVT(); 904 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 905 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 906 : ISD::EXTLOAD) 907 : LD->getExtensionType(); 908 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 909 LD->getChain(), LD->getBasePtr(), 910 LD->getPointerInfo(), 911 MemVT, LD->isVolatile(), 912 LD->isNonTemporal(), LD->getAlignment()); 913 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 914 915 DEBUG(dbgs() << "\nPromoting "; 916 N->dump(&DAG); 917 dbgs() << "\nTo: "; 918 Result.getNode()->dump(&DAG); 919 dbgs() << '\n'); 920 WorkListRemover DeadNodes(*this); 921 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 922 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 923 removeFromWorkList(N); 924 DAG.DeleteNode(N); 925 AddToWorkList(Result.getNode()); 926 return true; 927 } 928 return false; 929} 930 931 932//===----------------------------------------------------------------------===// 933// Main DAG Combiner implementation 934//===----------------------------------------------------------------------===// 935 936void DAGCombiner::Run(CombineLevel AtLevel) { 937 // set the instance variables, so that the various visit routines may use it. 938 Level = AtLevel; 939 LegalOperations = Level >= NoIllegalOperations; 940 LegalTypes = Level >= NoIllegalTypes; 941 942 // Add all the dag nodes to the worklist. 943 WorkList.reserve(DAG.allnodes_size()); 944 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 945 E = DAG.allnodes_end(); I != E; ++I) 946 WorkList.push_back(I); 947 948 // Create a dummy node (which is not added to allnodes), that adds a reference 949 // to the root node, preventing it from being deleted, and tracking any 950 // changes of the root. 951 HandleSDNode Dummy(DAG.getRoot()); 952 953 // The root of the dag may dangle to deleted nodes until the dag combiner is 954 // done. Set it to null to avoid confusion. 955 DAG.setRoot(SDValue()); 956 957 // while the worklist isn't empty, inspect the node on the end of it and 958 // try and combine it. 959 while (!WorkList.empty()) { 960 SDNode *N = WorkList.back(); 961 WorkList.pop_back(); 962 963 // If N has no uses, it is dead. Make sure to revisit all N's operands once 964 // N is deleted from the DAG, since they too may now be dead or may have a 965 // reduced number of uses, allowing other xforms. 966 if (N->use_empty() && N != &Dummy) { 967 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 968 AddToWorkList(N->getOperand(i).getNode()); 969 970 DAG.DeleteNode(N); 971 continue; 972 } 973 974 SDValue RV = combine(N); 975 976 if (RV.getNode() == 0) 977 continue; 978 979 ++NodesCombined; 980 981 // If we get back the same node we passed in, rather than a new node or 982 // zero, we know that the node must have defined multiple values and 983 // CombineTo was used. Since CombineTo takes care of the worklist 984 // mechanics for us, we have no work to do in this case. 985 if (RV.getNode() == N) 986 continue; 987 988 assert(N->getOpcode() != ISD::DELETED_NODE && 989 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 990 "Node was deleted but visit returned new node!"); 991 992 DEBUG(dbgs() << "\nReplacing.3 "; 993 N->dump(&DAG); 994 dbgs() << "\nWith: "; 995 RV.getNode()->dump(&DAG); 996 dbgs() << '\n'); 997 998 // Transfer debug value. 999 DAG.TransferDbgValues(SDValue(N, 0), RV); 1000 WorkListRemover DeadNodes(*this); 1001 if (N->getNumValues() == RV.getNode()->getNumValues()) 1002 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 1003 else { 1004 assert(N->getValueType(0) == RV.getValueType() && 1005 N->getNumValues() == 1 && "Type mismatch"); 1006 SDValue OpV = RV; 1007 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 1008 } 1009 1010 // Push the new node and any users onto the worklist 1011 AddToWorkList(RV.getNode()); 1012 AddUsersToWorkList(RV.getNode()); 1013 1014 // Add any uses of the old node to the worklist in case this node is the 1015 // last one that uses them. They may become dead after this node is 1016 // deleted. 1017 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1018 AddToWorkList(N->getOperand(i).getNode()); 1019 1020 // Finally, if the node is now dead, remove it from the graph. The node 1021 // may not be dead if the replacement process recursively simplified to 1022 // something else needing this node. 1023 if (N->use_empty()) { 1024 // Nodes can be reintroduced into the worklist. Make sure we do not 1025 // process a node that has been replaced. 1026 removeFromWorkList(N); 1027 1028 // Finally, since the node is now dead, remove it from the graph. 1029 DAG.DeleteNode(N); 1030 } 1031 } 1032 1033 // If the root changed (e.g. it was a dead load, update the root). 1034 DAG.setRoot(Dummy.getValue()); 1035} 1036 1037SDValue DAGCombiner::visit(SDNode *N) { 1038 switch (N->getOpcode()) { 1039 default: break; 1040 case ISD::TokenFactor: return visitTokenFactor(N); 1041 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1042 case ISD::ADD: return visitADD(N); 1043 case ISD::SUB: return visitSUB(N); 1044 case ISD::ADDC: return visitADDC(N); 1045 case ISD::ADDE: return visitADDE(N); 1046 case ISD::MUL: return visitMUL(N); 1047 case ISD::SDIV: return visitSDIV(N); 1048 case ISD::UDIV: return visitUDIV(N); 1049 case ISD::SREM: return visitSREM(N); 1050 case ISD::UREM: return visitUREM(N); 1051 case ISD::MULHU: return visitMULHU(N); 1052 case ISD::MULHS: return visitMULHS(N); 1053 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1054 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1055 case ISD::SMULO: return visitSMULO(N); 1056 case ISD::UMULO: return visitUMULO(N); 1057 case ISD::SDIVREM: return visitSDIVREM(N); 1058 case ISD::UDIVREM: return visitUDIVREM(N); 1059 case ISD::AND: return visitAND(N); 1060 case ISD::OR: return visitOR(N); 1061 case ISD::XOR: return visitXOR(N); 1062 case ISD::SHL: return visitSHL(N); 1063 case ISD::SRA: return visitSRA(N); 1064 case ISD::SRL: return visitSRL(N); 1065 case ISD::CTLZ: return visitCTLZ(N); 1066 case ISD::CTTZ: return visitCTTZ(N); 1067 case ISD::CTPOP: return visitCTPOP(N); 1068 case ISD::SELECT: return visitSELECT(N); 1069 case ISD::SELECT_CC: return visitSELECT_CC(N); 1070 case ISD::SETCC: return visitSETCC(N); 1071 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1072 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1073 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1074 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1075 case ISD::TRUNCATE: return visitTRUNCATE(N); 1076 case ISD::BITCAST: return visitBITCAST(N); 1077 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1078 case ISD::FADD: return visitFADD(N); 1079 case ISD::FSUB: return visitFSUB(N); 1080 case ISD::FMUL: return visitFMUL(N); 1081 case ISD::FDIV: return visitFDIV(N); 1082 case ISD::FREM: return visitFREM(N); 1083 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1084 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1085 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1086 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1087 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1088 case ISD::FP_ROUND: return visitFP_ROUND(N); 1089 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1090 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1091 case ISD::FNEG: return visitFNEG(N); 1092 case ISD::FABS: return visitFABS(N); 1093 case ISD::BRCOND: return visitBRCOND(N); 1094 case ISD::BR_CC: return visitBR_CC(N); 1095 case ISD::LOAD: return visitLOAD(N); 1096 case ISD::STORE: return visitSTORE(N); 1097 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1098 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1099 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1100 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1101 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1102 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1103 } 1104 return SDValue(); 1105} 1106 1107SDValue DAGCombiner::combine(SDNode *N) { 1108 SDValue RV = visit(N); 1109 1110 // If nothing happened, try a target-specific DAG combine. 1111 if (RV.getNode() == 0) { 1112 assert(N->getOpcode() != ISD::DELETED_NODE && 1113 "Node was deleted but visit returned NULL!"); 1114 1115 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1116 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1117 1118 // Expose the DAG combiner to the target combiner impls. 1119 TargetLowering::DAGCombinerInfo 1120 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1121 1122 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1123 } 1124 } 1125 1126 // If nothing happened still, try promoting the operation. 1127 if (RV.getNode() == 0) { 1128 switch (N->getOpcode()) { 1129 default: break; 1130 case ISD::ADD: 1131 case ISD::SUB: 1132 case ISD::MUL: 1133 case ISD::AND: 1134 case ISD::OR: 1135 case ISD::XOR: 1136 RV = PromoteIntBinOp(SDValue(N, 0)); 1137 break; 1138 case ISD::SHL: 1139 case ISD::SRA: 1140 case ISD::SRL: 1141 RV = PromoteIntShiftOp(SDValue(N, 0)); 1142 break; 1143 case ISD::SIGN_EXTEND: 1144 case ISD::ZERO_EXTEND: 1145 case ISD::ANY_EXTEND: 1146 RV = PromoteExtend(SDValue(N, 0)); 1147 break; 1148 case ISD::LOAD: 1149 if (PromoteLoad(SDValue(N, 0))) 1150 RV = SDValue(N, 0); 1151 break; 1152 } 1153 } 1154 1155 // If N is a commutative binary node, try commuting it to enable more 1156 // sdisel CSE. 1157 if (RV.getNode() == 0 && 1158 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1159 N->getNumValues() == 1) { 1160 SDValue N0 = N->getOperand(0); 1161 SDValue N1 = N->getOperand(1); 1162 1163 // Constant operands are canonicalized to RHS. 1164 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1165 SDValue Ops[] = { N1, N0 }; 1166 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1167 Ops, 2); 1168 if (CSENode) 1169 return SDValue(CSENode, 0); 1170 } 1171 } 1172 1173 return RV; 1174} 1175 1176/// getInputChainForNode - Given a node, return its input chain if it has one, 1177/// otherwise return a null sd operand. 1178static SDValue getInputChainForNode(SDNode *N) { 1179 if (unsigned NumOps = N->getNumOperands()) { 1180 if (N->getOperand(0).getValueType() == MVT::Other) 1181 return N->getOperand(0); 1182 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1183 return N->getOperand(NumOps-1); 1184 for (unsigned i = 1; i < NumOps-1; ++i) 1185 if (N->getOperand(i).getValueType() == MVT::Other) 1186 return N->getOperand(i); 1187 } 1188 return SDValue(); 1189} 1190 1191SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1192 // If N has two operands, where one has an input chain equal to the other, 1193 // the 'other' chain is redundant. 1194 if (N->getNumOperands() == 2) { 1195 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1196 return N->getOperand(0); 1197 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1198 return N->getOperand(1); 1199 } 1200 1201 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1202 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1203 SmallPtrSet<SDNode*, 16> SeenOps; 1204 bool Changed = false; // If we should replace this token factor. 1205 1206 // Start out with this token factor. 1207 TFs.push_back(N); 1208 1209 // Iterate through token factors. The TFs grows when new token factors are 1210 // encountered. 1211 for (unsigned i = 0; i < TFs.size(); ++i) { 1212 SDNode *TF = TFs[i]; 1213 1214 // Check each of the operands. 1215 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1216 SDValue Op = TF->getOperand(i); 1217 1218 switch (Op.getOpcode()) { 1219 case ISD::EntryToken: 1220 // Entry tokens don't need to be added to the list. They are 1221 // rededundant. 1222 Changed = true; 1223 break; 1224 1225 case ISD::TokenFactor: 1226 if (Op.hasOneUse() && 1227 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1228 // Queue up for processing. 1229 TFs.push_back(Op.getNode()); 1230 // Clean up in case the token factor is removed. 1231 AddToWorkList(Op.getNode()); 1232 Changed = true; 1233 break; 1234 } 1235 // Fall thru 1236 1237 default: 1238 // Only add if it isn't already in the list. 1239 if (SeenOps.insert(Op.getNode())) 1240 Ops.push_back(Op); 1241 else 1242 Changed = true; 1243 break; 1244 } 1245 } 1246 } 1247 1248 SDValue Result; 1249 1250 // If we've change things around then replace token factor. 1251 if (Changed) { 1252 if (Ops.empty()) { 1253 // The entry token is the only possible outcome. 1254 Result = DAG.getEntryNode(); 1255 } else { 1256 // New and improved token factor. 1257 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1258 MVT::Other, &Ops[0], Ops.size()); 1259 } 1260 1261 // Don't add users to work list. 1262 return CombineTo(N, Result, false); 1263 } 1264 1265 return Result; 1266} 1267 1268/// MERGE_VALUES can always be eliminated. 1269SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1270 WorkListRemover DeadNodes(*this); 1271 // Replacing results may cause a different MERGE_VALUES to suddenly 1272 // be CSE'd with N, and carry its uses with it. Iterate until no 1273 // uses remain, to ensure that the node can be safely deleted. 1274 do { 1275 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1276 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1277 &DeadNodes); 1278 } while (!N->use_empty()); 1279 removeFromWorkList(N); 1280 DAG.DeleteNode(N); 1281 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1282} 1283 1284static 1285SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1286 SelectionDAG &DAG) { 1287 EVT VT = N0.getValueType(); 1288 SDValue N00 = N0.getOperand(0); 1289 SDValue N01 = N0.getOperand(1); 1290 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1291 1292 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1293 isa<ConstantSDNode>(N00.getOperand(1))) { 1294 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1295 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1296 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1297 N00.getOperand(0), N01), 1298 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1299 N00.getOperand(1), N01)); 1300 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1301 } 1302 1303 return SDValue(); 1304} 1305 1306/// isCarryMaterialization - Returns true if V is an ADDE node that is known to 1307/// return 0 or 1 depending on the carry flag. 1308static bool isCarryMaterialization(SDValue V) { 1309 if (V.getOpcode() != ISD::ADDE) 1310 return false; 1311 1312 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(0)); 1313 return C && C->isNullValue() && V.getOperand(0) == V.getOperand(1); 1314} 1315 1316SDValue DAGCombiner::visitADD(SDNode *N) { 1317 SDValue N0 = N->getOperand(0); 1318 SDValue N1 = N->getOperand(1); 1319 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1320 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1321 EVT VT = N0.getValueType(); 1322 1323 // fold vector ops 1324 if (VT.isVector()) { 1325 SDValue FoldedVOp = SimplifyVBinOp(N); 1326 if (FoldedVOp.getNode()) return FoldedVOp; 1327 } 1328 1329 // fold (add x, undef) -> undef 1330 if (N0.getOpcode() == ISD::UNDEF) 1331 return N0; 1332 if (N1.getOpcode() == ISD::UNDEF) 1333 return N1; 1334 // fold (add c1, c2) -> c1+c2 1335 if (N0C && N1C) 1336 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1337 // canonicalize constant to RHS 1338 if (N0C && !N1C) 1339 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1340 // fold (add x, 0) -> x 1341 if (N1C && N1C->isNullValue()) 1342 return N0; 1343 // fold (add Sym, c) -> Sym+c 1344 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1345 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1346 GA->getOpcode() == ISD::GlobalAddress) 1347 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1348 GA->getOffset() + 1349 (uint64_t)N1C->getSExtValue()); 1350 // fold ((c1-A)+c2) -> (c1+c2)-A 1351 if (N1C && N0.getOpcode() == ISD::SUB) 1352 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1353 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1354 DAG.getConstant(N1C->getAPIntValue()+ 1355 N0C->getAPIntValue(), VT), 1356 N0.getOperand(1)); 1357 // reassociate add 1358 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1359 if (RADD.getNode() != 0) 1360 return RADD; 1361 // fold ((0-A) + B) -> B-A 1362 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1363 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1364 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1365 // fold (A + (0-B)) -> A-B 1366 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1367 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1368 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1369 // fold (A+(B-A)) -> B 1370 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1371 return N1.getOperand(0); 1372 // fold ((B-A)+A) -> B 1373 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1374 return N0.getOperand(0); 1375 // fold (A+(B-(A+C))) to (B-C) 1376 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1377 N0 == N1.getOperand(1).getOperand(0)) 1378 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1379 N1.getOperand(1).getOperand(1)); 1380 // fold (A+(B-(C+A))) to (B-C) 1381 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1382 N0 == N1.getOperand(1).getOperand(1)) 1383 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1384 N1.getOperand(1).getOperand(0)); 1385 // fold (A+((B-A)+or-C)) to (B+or-C) 1386 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1387 N1.getOperand(0).getOpcode() == ISD::SUB && 1388 N0 == N1.getOperand(0).getOperand(1)) 1389 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1390 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1391 1392 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1393 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1394 SDValue N00 = N0.getOperand(0); 1395 SDValue N01 = N0.getOperand(1); 1396 SDValue N10 = N1.getOperand(0); 1397 SDValue N11 = N1.getOperand(1); 1398 1399 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1400 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1401 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1402 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1403 } 1404 1405 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1406 return SDValue(N, 0); 1407 1408 // fold (a+b) -> (a|b) iff a and b share no bits. 1409 if (VT.isInteger() && !VT.isVector()) { 1410 APInt LHSZero, LHSOne; 1411 APInt RHSZero, RHSOne; 1412 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1413 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1414 1415 if (LHSZero.getBoolValue()) { 1416 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1417 1418 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1419 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1420 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1421 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1422 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1423 } 1424 } 1425 1426 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1427 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1428 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1429 if (Result.getNode()) return Result; 1430 } 1431 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1432 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1433 if (Result.getNode()) return Result; 1434 } 1435 1436 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1437 if (N1.getOpcode() == ISD::SHL && 1438 N1.getOperand(0).getOpcode() == ISD::SUB) 1439 if (ConstantSDNode *C = 1440 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1441 if (C->getAPIntValue() == 0) 1442 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1443 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1444 N1.getOperand(0).getOperand(1), 1445 N1.getOperand(1))); 1446 if (N0.getOpcode() == ISD::SHL && 1447 N0.getOperand(0).getOpcode() == ISD::SUB) 1448 if (ConstantSDNode *C = 1449 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1450 if (C->getAPIntValue() == 0) 1451 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1452 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1453 N0.getOperand(0).getOperand(1), 1454 N0.getOperand(1))); 1455 1456 if (N1.getOpcode() == ISD::AND) { 1457 SDValue AndOp0 = N1.getOperand(0); 1458 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1459 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1460 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1461 1462 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1463 // and similar xforms where the inner op is either ~0 or 0. 1464 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1465 DebugLoc DL = N->getDebugLoc(); 1466 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1467 } 1468 } 1469 1470 // add (sext i1), X -> sub X, (zext i1) 1471 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1472 N0.getOperand(0).getValueType() == MVT::i1 && 1473 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1474 DebugLoc DL = N->getDebugLoc(); 1475 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1476 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1477 } 1478 1479 // add (adde 0, 0, glue), X -> adde X, 0, glue 1480 if (N0->hasOneUse() && isCarryMaterialization(N0)) 1481 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), 1482 DAG.getVTList(VT, MVT::Glue), N1, N0.getOperand(0), 1483 N0.getOperand(2)); 1484 1485 // add X, (adde 0, 0, glue) -> adde X, 0, glue 1486 if (N1->hasOneUse() && isCarryMaterialization(N1)) 1487 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), 1488 DAG.getVTList(VT, MVT::Glue), N0, N1.getOperand(0), 1489 N1.getOperand(2)); 1490 1491 return SDValue(); 1492} 1493 1494SDValue DAGCombiner::visitADDC(SDNode *N) { 1495 SDValue N0 = N->getOperand(0); 1496 SDValue N1 = N->getOperand(1); 1497 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1498 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1499 EVT VT = N0.getValueType(); 1500 1501 // If the flag result is dead, turn this into an ADD. 1502 if (N->hasNUsesOfValue(0, 1)) 1503 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1504 DAG.getNode(ISD::CARRY_FALSE, 1505 N->getDebugLoc(), MVT::Glue)); 1506 1507 // canonicalize constant to RHS. 1508 if (N0C && !N1C) 1509 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1510 1511 // fold (addc x, 0) -> x + no carry out 1512 if (N1C && N1C->isNullValue()) 1513 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1514 N->getDebugLoc(), MVT::Glue)); 1515 1516 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1517 APInt LHSZero, LHSOne; 1518 APInt RHSZero, RHSOne; 1519 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1520 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1521 1522 if (LHSZero.getBoolValue()) { 1523 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1524 1525 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1526 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1527 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1528 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1529 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1530 DAG.getNode(ISD::CARRY_FALSE, 1531 N->getDebugLoc(), MVT::Glue)); 1532 } 1533 1534 // addc (adde 0, 0, glue), X -> adde X, 0, glue 1535 if (N0->hasOneUse() && isCarryMaterialization(N0)) 1536 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N1, 1537 DAG.getConstant(0, VT), N0.getOperand(2)); 1538 1539 // addc X, (adde 0, 0, glue) -> adde X, 0, glue 1540 if (N1->hasOneUse() && isCarryMaterialization(N1)) 1541 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N0, 1542 DAG.getConstant(0, VT), N1.getOperand(2)); 1543 1544 return SDValue(); 1545} 1546 1547SDValue DAGCombiner::visitADDE(SDNode *N) { 1548 SDValue N0 = N->getOperand(0); 1549 SDValue N1 = N->getOperand(1); 1550 SDValue CarryIn = N->getOperand(2); 1551 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1552 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1553 1554 // If both operands are null we know that carry out will always be false. 1555 if (N0C && N0C->isNullValue() && N0 == N1) 1556 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), DAG.getNode(ISD::CARRY_FALSE, 1557 N->getDebugLoc(), 1558 MVT::Glue)); 1559 1560 // canonicalize constant to RHS 1561 if (N0C && !N1C) 1562 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1563 N1, N0, CarryIn); 1564 1565 // fold (adde x, y, false) -> (addc x, y) 1566 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1567 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1568 1569 return SDValue(); 1570} 1571 1572// Since it may not be valid to emit a fold to zero for vector initializers 1573// check if we can before folding. 1574static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1575 SelectionDAG &DAG, bool LegalOperations) { 1576 if (!VT.isVector()) { 1577 return DAG.getConstant(0, VT); 1578 } 1579 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1580 // Produce a vector of zeros. 1581 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1582 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1583 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1584 &Ops[0], Ops.size()); 1585 } 1586 return SDValue(); 1587} 1588 1589SDValue DAGCombiner::visitSUB(SDNode *N) { 1590 SDValue N0 = N->getOperand(0); 1591 SDValue N1 = N->getOperand(1); 1592 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1593 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1594 EVT VT = N0.getValueType(); 1595 1596 // fold vector ops 1597 if (VT.isVector()) { 1598 SDValue FoldedVOp = SimplifyVBinOp(N); 1599 if (FoldedVOp.getNode()) return FoldedVOp; 1600 } 1601 1602 // fold (sub x, x) -> 0 1603 // FIXME: Refactor this and xor and other similar operations together. 1604 if (N0 == N1) 1605 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1606 // fold (sub c1, c2) -> c1-c2 1607 if (N0C && N1C) 1608 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1609 // fold (sub x, c) -> (add x, -c) 1610 if (N1C) 1611 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1612 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1613 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1614 if (N0C && N0C->isAllOnesValue()) 1615 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1616 // fold A-(A-B) -> B 1617 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1618 return N1.getOperand(1); 1619 // fold (A+B)-A -> B 1620 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1621 return N0.getOperand(1); 1622 // fold (A+B)-B -> A 1623 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1624 return N0.getOperand(0); 1625 // fold ((A+(B+or-C))-B) -> A+or-C 1626 if (N0.getOpcode() == ISD::ADD && 1627 (N0.getOperand(1).getOpcode() == ISD::SUB || 1628 N0.getOperand(1).getOpcode() == ISD::ADD) && 1629 N0.getOperand(1).getOperand(0) == N1) 1630 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1631 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1632 // fold ((A+(C+B))-B) -> A+C 1633 if (N0.getOpcode() == ISD::ADD && 1634 N0.getOperand(1).getOpcode() == ISD::ADD && 1635 N0.getOperand(1).getOperand(1) == N1) 1636 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1637 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1638 // fold ((A-(B-C))-C) -> A-B 1639 if (N0.getOpcode() == ISD::SUB && 1640 N0.getOperand(1).getOpcode() == ISD::SUB && 1641 N0.getOperand(1).getOperand(1) == N1) 1642 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1643 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1644 1645 // If either operand of a sub is undef, the result is undef 1646 if (N0.getOpcode() == ISD::UNDEF) 1647 return N0; 1648 if (N1.getOpcode() == ISD::UNDEF) 1649 return N1; 1650 1651 // If the relocation model supports it, consider symbol offsets. 1652 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1653 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1654 // fold (sub Sym, c) -> Sym-c 1655 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1656 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1657 GA->getOffset() - 1658 (uint64_t)N1C->getSExtValue()); 1659 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1660 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1661 if (GA->getGlobal() == GB->getGlobal()) 1662 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1663 VT); 1664 } 1665 1666 return SDValue(); 1667} 1668 1669SDValue DAGCombiner::visitMUL(SDNode *N) { 1670 SDValue N0 = N->getOperand(0); 1671 SDValue N1 = N->getOperand(1); 1672 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1673 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1674 EVT VT = N0.getValueType(); 1675 1676 // fold vector ops 1677 if (VT.isVector()) { 1678 SDValue FoldedVOp = SimplifyVBinOp(N); 1679 if (FoldedVOp.getNode()) return FoldedVOp; 1680 } 1681 1682 // fold (mul x, undef) -> 0 1683 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1684 return DAG.getConstant(0, VT); 1685 // fold (mul c1, c2) -> c1*c2 1686 if (N0C && N1C) 1687 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1688 // canonicalize constant to RHS 1689 if (N0C && !N1C) 1690 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1691 // fold (mul x, 0) -> 0 1692 if (N1C && N1C->isNullValue()) 1693 return N1; 1694 // fold (mul x, -1) -> 0-x 1695 if (N1C && N1C->isAllOnesValue()) 1696 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1697 DAG.getConstant(0, VT), N0); 1698 // fold (mul x, (1 << c)) -> x << c 1699 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1700 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1701 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1702 getShiftAmountTy(N0.getValueType()))); 1703 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1704 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1705 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1706 // FIXME: If the input is something that is easily negated (e.g. a 1707 // single-use add), we should put the negate there. 1708 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1709 DAG.getConstant(0, VT), 1710 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1711 DAG.getConstant(Log2Val, 1712 getShiftAmountTy(N0.getValueType())))); 1713 } 1714 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1715 if (N1C && N0.getOpcode() == ISD::SHL && 1716 isa<ConstantSDNode>(N0.getOperand(1))) { 1717 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1718 N1, N0.getOperand(1)); 1719 AddToWorkList(C3.getNode()); 1720 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1721 N0.getOperand(0), C3); 1722 } 1723 1724 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1725 // use. 1726 { 1727 SDValue Sh(0,0), Y(0,0); 1728 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1729 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1730 N0.getNode()->hasOneUse()) { 1731 Sh = N0; Y = N1; 1732 } else if (N1.getOpcode() == ISD::SHL && 1733 isa<ConstantSDNode>(N1.getOperand(1)) && 1734 N1.getNode()->hasOneUse()) { 1735 Sh = N1; Y = N0; 1736 } 1737 1738 if (Sh.getNode()) { 1739 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1740 Sh.getOperand(0), Y); 1741 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1742 Mul, Sh.getOperand(1)); 1743 } 1744 } 1745 1746 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1747 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1748 isa<ConstantSDNode>(N0.getOperand(1))) 1749 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1750 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1751 N0.getOperand(0), N1), 1752 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1753 N0.getOperand(1), N1)); 1754 1755 // reassociate mul 1756 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1757 if (RMUL.getNode() != 0) 1758 return RMUL; 1759 1760 return SDValue(); 1761} 1762 1763SDValue DAGCombiner::visitSDIV(SDNode *N) { 1764 SDValue N0 = N->getOperand(0); 1765 SDValue N1 = N->getOperand(1); 1766 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1767 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1768 EVT VT = N->getValueType(0); 1769 1770 // fold vector ops 1771 if (VT.isVector()) { 1772 SDValue FoldedVOp = SimplifyVBinOp(N); 1773 if (FoldedVOp.getNode()) return FoldedVOp; 1774 } 1775 1776 // fold (sdiv c1, c2) -> c1/c2 1777 if (N0C && N1C && !N1C->isNullValue()) 1778 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1779 // fold (sdiv X, 1) -> X 1780 if (N1C && N1C->getSExtValue() == 1LL) 1781 return N0; 1782 // fold (sdiv X, -1) -> 0-X 1783 if (N1C && N1C->isAllOnesValue()) 1784 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1785 DAG.getConstant(0, VT), N0); 1786 // If we know the sign bits of both operands are zero, strength reduce to a 1787 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1788 if (!VT.isVector()) { 1789 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1790 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1791 N0, N1); 1792 } 1793 // fold (sdiv X, pow2) -> simple ops after legalize 1794 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1795 (isPowerOf2_64(N1C->getSExtValue()) || 1796 isPowerOf2_64(-N1C->getSExtValue()))) { 1797 // If dividing by powers of two is cheap, then don't perform the following 1798 // fold. 1799 if (TLI.isPow2DivCheap()) 1800 return SDValue(); 1801 1802 int64_t pow2 = N1C->getSExtValue(); 1803 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1804 unsigned lg2 = Log2_64(abs2); 1805 1806 // Splat the sign bit into the register 1807 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1808 DAG.getConstant(VT.getSizeInBits()-1, 1809 getShiftAmountTy(N0.getValueType()))); 1810 AddToWorkList(SGN.getNode()); 1811 1812 // Add (N0 < 0) ? abs2 - 1 : 0; 1813 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1814 DAG.getConstant(VT.getSizeInBits() - lg2, 1815 getShiftAmountTy(SGN.getValueType()))); 1816 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1817 AddToWorkList(SRL.getNode()); 1818 AddToWorkList(ADD.getNode()); // Divide by pow2 1819 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1820 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1821 1822 // If we're dividing by a positive value, we're done. Otherwise, we must 1823 // negate the result. 1824 if (pow2 > 0) 1825 return SRA; 1826 1827 AddToWorkList(SRA.getNode()); 1828 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1829 DAG.getConstant(0, VT), SRA); 1830 } 1831 1832 // if integer divide is expensive and we satisfy the requirements, emit an 1833 // alternate sequence. 1834 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1835 !TLI.isIntDivCheap()) { 1836 SDValue Op = BuildSDIV(N); 1837 if (Op.getNode()) return Op; 1838 } 1839 1840 // undef / X -> 0 1841 if (N0.getOpcode() == ISD::UNDEF) 1842 return DAG.getConstant(0, VT); 1843 // X / undef -> undef 1844 if (N1.getOpcode() == ISD::UNDEF) 1845 return N1; 1846 1847 return SDValue(); 1848} 1849 1850SDValue DAGCombiner::visitUDIV(SDNode *N) { 1851 SDValue N0 = N->getOperand(0); 1852 SDValue N1 = N->getOperand(1); 1853 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1854 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1855 EVT VT = N->getValueType(0); 1856 1857 // fold vector ops 1858 if (VT.isVector()) { 1859 SDValue FoldedVOp = SimplifyVBinOp(N); 1860 if (FoldedVOp.getNode()) return FoldedVOp; 1861 } 1862 1863 // fold (udiv c1, c2) -> c1/c2 1864 if (N0C && N1C && !N1C->isNullValue()) 1865 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1866 // fold (udiv x, (1 << c)) -> x >>u c 1867 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1868 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1869 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1870 getShiftAmountTy(N0.getValueType()))); 1871 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1872 if (N1.getOpcode() == ISD::SHL) { 1873 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1874 if (SHC->getAPIntValue().isPowerOf2()) { 1875 EVT ADDVT = N1.getOperand(1).getValueType(); 1876 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1877 N1.getOperand(1), 1878 DAG.getConstant(SHC->getAPIntValue() 1879 .logBase2(), 1880 ADDVT)); 1881 AddToWorkList(Add.getNode()); 1882 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1883 } 1884 } 1885 } 1886 // fold (udiv x, c) -> alternate 1887 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1888 SDValue Op = BuildUDIV(N); 1889 if (Op.getNode()) return Op; 1890 } 1891 1892 // undef / X -> 0 1893 if (N0.getOpcode() == ISD::UNDEF) 1894 return DAG.getConstant(0, VT); 1895 // X / undef -> undef 1896 if (N1.getOpcode() == ISD::UNDEF) 1897 return N1; 1898 1899 return SDValue(); 1900} 1901 1902SDValue DAGCombiner::visitSREM(SDNode *N) { 1903 SDValue N0 = N->getOperand(0); 1904 SDValue N1 = N->getOperand(1); 1905 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1906 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1907 EVT VT = N->getValueType(0); 1908 1909 // fold (srem c1, c2) -> c1%c2 1910 if (N0C && N1C && !N1C->isNullValue()) 1911 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1912 // If we know the sign bits of both operands are zero, strength reduce to a 1913 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1914 if (!VT.isVector()) { 1915 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1916 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1917 } 1918 1919 // If X/C can be simplified by the division-by-constant logic, lower 1920 // X%C to the equivalent of X-X/C*C. 1921 if (N1C && !N1C->isNullValue()) { 1922 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1923 AddToWorkList(Div.getNode()); 1924 SDValue OptimizedDiv = combine(Div.getNode()); 1925 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1926 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1927 OptimizedDiv, N1); 1928 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1929 AddToWorkList(Mul.getNode()); 1930 return Sub; 1931 } 1932 } 1933 1934 // undef % X -> 0 1935 if (N0.getOpcode() == ISD::UNDEF) 1936 return DAG.getConstant(0, VT); 1937 // X % undef -> undef 1938 if (N1.getOpcode() == ISD::UNDEF) 1939 return N1; 1940 1941 return SDValue(); 1942} 1943 1944SDValue DAGCombiner::visitUREM(SDNode *N) { 1945 SDValue N0 = N->getOperand(0); 1946 SDValue N1 = N->getOperand(1); 1947 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1948 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1949 EVT VT = N->getValueType(0); 1950 1951 // fold (urem c1, c2) -> c1%c2 1952 if (N0C && N1C && !N1C->isNullValue()) 1953 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1954 // fold (urem x, pow2) -> (and x, pow2-1) 1955 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1956 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1957 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1958 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1959 if (N1.getOpcode() == ISD::SHL) { 1960 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1961 if (SHC->getAPIntValue().isPowerOf2()) { 1962 SDValue Add = 1963 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1964 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1965 VT)); 1966 AddToWorkList(Add.getNode()); 1967 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1968 } 1969 } 1970 } 1971 1972 // If X/C can be simplified by the division-by-constant logic, lower 1973 // X%C to the equivalent of X-X/C*C. 1974 if (N1C && !N1C->isNullValue()) { 1975 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1976 AddToWorkList(Div.getNode()); 1977 SDValue OptimizedDiv = combine(Div.getNode()); 1978 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1979 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1980 OptimizedDiv, N1); 1981 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1982 AddToWorkList(Mul.getNode()); 1983 return Sub; 1984 } 1985 } 1986 1987 // undef % X -> 0 1988 if (N0.getOpcode() == ISD::UNDEF) 1989 return DAG.getConstant(0, VT); 1990 // X % undef -> undef 1991 if (N1.getOpcode() == ISD::UNDEF) 1992 return N1; 1993 1994 return SDValue(); 1995} 1996 1997SDValue DAGCombiner::visitMULHS(SDNode *N) { 1998 SDValue N0 = N->getOperand(0); 1999 SDValue N1 = N->getOperand(1); 2000 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2001 EVT VT = N->getValueType(0); 2002 DebugLoc DL = N->getDebugLoc(); 2003 2004 // fold (mulhs x, 0) -> 0 2005 if (N1C && N1C->isNullValue()) 2006 return N1; 2007 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2008 if (N1C && N1C->getAPIntValue() == 1) 2009 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2010 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2011 getShiftAmountTy(N0.getValueType()))); 2012 // fold (mulhs x, undef) -> 0 2013 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2014 return DAG.getConstant(0, VT); 2015 2016 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2017 // plus a shift. 2018 if (VT.isSimple() && !VT.isVector()) { 2019 MVT Simple = VT.getSimpleVT(); 2020 unsigned SimpleSize = Simple.getSizeInBits(); 2021 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2022 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2023 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2024 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2025 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2026 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2027 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2028 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2029 } 2030 } 2031 2032 return SDValue(); 2033} 2034 2035SDValue DAGCombiner::visitMULHU(SDNode *N) { 2036 SDValue N0 = N->getOperand(0); 2037 SDValue N1 = N->getOperand(1); 2038 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2039 EVT VT = N->getValueType(0); 2040 DebugLoc DL = N->getDebugLoc(); 2041 2042 // fold (mulhu x, 0) -> 0 2043 if (N1C && N1C->isNullValue()) 2044 return N1; 2045 // fold (mulhu x, 1) -> 0 2046 if (N1C && N1C->getAPIntValue() == 1) 2047 return DAG.getConstant(0, N0.getValueType()); 2048 // fold (mulhu x, undef) -> 0 2049 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2050 return DAG.getConstant(0, VT); 2051 2052 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2053 // plus a shift. 2054 if (VT.isSimple() && !VT.isVector()) { 2055 MVT Simple = VT.getSimpleVT(); 2056 unsigned SimpleSize = Simple.getSizeInBits(); 2057 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2058 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2059 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2060 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2061 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2062 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2063 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2064 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2065 } 2066 } 2067 2068 return SDValue(); 2069} 2070 2071/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2072/// compute two values. LoOp and HiOp give the opcodes for the two computations 2073/// that are being performed. Return true if a simplification was made. 2074/// 2075SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2076 unsigned HiOp) { 2077 // If the high half is not needed, just compute the low half. 2078 bool HiExists = N->hasAnyUseOfValue(1); 2079 if (!HiExists && 2080 (!LegalOperations || 2081 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2082 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2083 N->op_begin(), N->getNumOperands()); 2084 return CombineTo(N, Res, Res); 2085 } 2086 2087 // If the low half is not needed, just compute the high half. 2088 bool LoExists = N->hasAnyUseOfValue(0); 2089 if (!LoExists && 2090 (!LegalOperations || 2091 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2092 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2093 N->op_begin(), N->getNumOperands()); 2094 return CombineTo(N, Res, Res); 2095 } 2096 2097 // If both halves are used, return as it is. 2098 if (LoExists && HiExists) 2099 return SDValue(); 2100 2101 // If the two computed results can be simplified separately, separate them. 2102 if (LoExists) { 2103 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2104 N->op_begin(), N->getNumOperands()); 2105 AddToWorkList(Lo.getNode()); 2106 SDValue LoOpt = combine(Lo.getNode()); 2107 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2108 (!LegalOperations || 2109 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2110 return CombineTo(N, LoOpt, LoOpt); 2111 } 2112 2113 if (HiExists) { 2114 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2115 N->op_begin(), N->getNumOperands()); 2116 AddToWorkList(Hi.getNode()); 2117 SDValue HiOpt = combine(Hi.getNode()); 2118 if (HiOpt.getNode() && HiOpt != Hi && 2119 (!LegalOperations || 2120 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2121 return CombineTo(N, HiOpt, HiOpt); 2122 } 2123 2124 return SDValue(); 2125} 2126 2127SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2128 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2129 if (Res.getNode()) return Res; 2130 2131 EVT VT = N->getValueType(0); 2132 DebugLoc DL = N->getDebugLoc(); 2133 2134 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2135 // plus a shift. 2136 if (VT.isSimple() && !VT.isVector()) { 2137 MVT Simple = VT.getSimpleVT(); 2138 unsigned SimpleSize = Simple.getSizeInBits(); 2139 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2140 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2141 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2142 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2143 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2144 // Compute the high part as N1. 2145 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2146 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2147 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2148 // Compute the low part as N0. 2149 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2150 return CombineTo(N, Lo, Hi); 2151 } 2152 } 2153 2154 return SDValue(); 2155} 2156 2157SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2158 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2159 if (Res.getNode()) return Res; 2160 2161 EVT VT = N->getValueType(0); 2162 DebugLoc DL = N->getDebugLoc(); 2163 2164 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2165 // plus a shift. 2166 if (VT.isSimple() && !VT.isVector()) { 2167 MVT Simple = VT.getSimpleVT(); 2168 unsigned SimpleSize = Simple.getSizeInBits(); 2169 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2170 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2171 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2172 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2173 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2174 // Compute the high part as N1. 2175 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2176 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2177 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2178 // Compute the low part as N0. 2179 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2180 return CombineTo(N, Lo, Hi); 2181 } 2182 } 2183 2184 return SDValue(); 2185} 2186 2187SDValue DAGCombiner::visitSMULO(SDNode *N) { 2188 // (smulo x, 2) -> (saddo x, x) 2189 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2190 if (C2->getAPIntValue() == 2) 2191 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2192 N->getOperand(0), N->getOperand(0)); 2193 2194 return SDValue(); 2195} 2196 2197SDValue DAGCombiner::visitUMULO(SDNode *N) { 2198 // (umulo x, 2) -> (uaddo x, x) 2199 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2200 if (C2->getAPIntValue() == 2) 2201 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2202 N->getOperand(0), N->getOperand(0)); 2203 2204 return SDValue(); 2205} 2206 2207SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2208 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2209 if (Res.getNode()) return Res; 2210 2211 return SDValue(); 2212} 2213 2214SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2215 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2216 if (Res.getNode()) return Res; 2217 2218 return SDValue(); 2219} 2220 2221/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2222/// two operands of the same opcode, try to simplify it. 2223SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2224 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2225 EVT VT = N0.getValueType(); 2226 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2227 2228 // Bail early if none of these transforms apply. 2229 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2230 2231 // For each of OP in AND/OR/XOR: 2232 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2233 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2234 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2235 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2236 // 2237 // do not sink logical op inside of a vector extend, since it may combine 2238 // into a vsetcc. 2239 EVT Op0VT = N0.getOperand(0).getValueType(); 2240 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2241 N0.getOpcode() == ISD::SIGN_EXTEND || 2242 // Avoid infinite looping with PromoteIntBinOp. 2243 (N0.getOpcode() == ISD::ANY_EXTEND && 2244 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2245 (N0.getOpcode() == ISD::TRUNCATE && 2246 (!TLI.isZExtFree(VT, Op0VT) || 2247 !TLI.isTruncateFree(Op0VT, VT)) && 2248 TLI.isTypeLegal(Op0VT))) && 2249 !VT.isVector() && 2250 Op0VT == N1.getOperand(0).getValueType() && 2251 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2252 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2253 N0.getOperand(0).getValueType(), 2254 N0.getOperand(0), N1.getOperand(0)); 2255 AddToWorkList(ORNode.getNode()); 2256 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2257 } 2258 2259 // For each of OP in SHL/SRL/SRA/AND... 2260 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2261 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2262 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2263 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2264 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2265 N0.getOperand(1) == N1.getOperand(1)) { 2266 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2267 N0.getOperand(0).getValueType(), 2268 N0.getOperand(0), N1.getOperand(0)); 2269 AddToWorkList(ORNode.getNode()); 2270 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2271 ORNode, N0.getOperand(1)); 2272 } 2273 2274 return SDValue(); 2275} 2276 2277SDValue DAGCombiner::visitAND(SDNode *N) { 2278 SDValue N0 = N->getOperand(0); 2279 SDValue N1 = N->getOperand(1); 2280 SDValue LL, LR, RL, RR, CC0, CC1; 2281 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2282 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2283 EVT VT = N1.getValueType(); 2284 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2285 2286 // fold vector ops 2287 if (VT.isVector()) { 2288 SDValue FoldedVOp = SimplifyVBinOp(N); 2289 if (FoldedVOp.getNode()) return FoldedVOp; 2290 } 2291 2292 // fold (and x, undef) -> 0 2293 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2294 return DAG.getConstant(0, VT); 2295 // fold (and c1, c2) -> c1&c2 2296 if (N0C && N1C) 2297 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2298 // canonicalize constant to RHS 2299 if (N0C && !N1C) 2300 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2301 // fold (and x, -1) -> x 2302 if (N1C && N1C->isAllOnesValue()) 2303 return N0; 2304 // if (and x, c) is known to be zero, return 0 2305 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2306 APInt::getAllOnesValue(BitWidth))) 2307 return DAG.getConstant(0, VT); 2308 // reassociate and 2309 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2310 if (RAND.getNode() != 0) 2311 return RAND; 2312 // fold (and (or x, C), D) -> D if (C & D) == D 2313 if (N1C && N0.getOpcode() == ISD::OR) 2314 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2315 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2316 return N1; 2317 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2318 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2319 SDValue N0Op0 = N0.getOperand(0); 2320 APInt Mask = ~N1C->getAPIntValue(); 2321 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2322 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2323 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2324 N0.getValueType(), N0Op0); 2325 2326 // Replace uses of the AND with uses of the Zero extend node. 2327 CombineTo(N, Zext); 2328 2329 // We actually want to replace all uses of the any_extend with the 2330 // zero_extend, to avoid duplicating things. This will later cause this 2331 // AND to be folded. 2332 CombineTo(N0.getNode(), Zext); 2333 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2334 } 2335 } 2336 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2337 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2338 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2339 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2340 2341 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2342 LL.getValueType().isInteger()) { 2343 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2344 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2345 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2346 LR.getValueType(), LL, RL); 2347 AddToWorkList(ORNode.getNode()); 2348 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2349 } 2350 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2351 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2352 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2353 LR.getValueType(), LL, RL); 2354 AddToWorkList(ANDNode.getNode()); 2355 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2356 } 2357 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2358 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2359 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2360 LR.getValueType(), LL, RL); 2361 AddToWorkList(ORNode.getNode()); 2362 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2363 } 2364 } 2365 // canonicalize equivalent to ll == rl 2366 if (LL == RR && LR == RL) { 2367 Op1 = ISD::getSetCCSwappedOperands(Op1); 2368 std::swap(RL, RR); 2369 } 2370 if (LL == RL && LR == RR) { 2371 bool isInteger = LL.getValueType().isInteger(); 2372 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2373 if (Result != ISD::SETCC_INVALID && 2374 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2375 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2376 LL, LR, Result); 2377 } 2378 } 2379 2380 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2381 if (N0.getOpcode() == N1.getOpcode()) { 2382 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2383 if (Tmp.getNode()) return Tmp; 2384 } 2385 2386 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2387 // fold (and (sra)) -> (and (srl)) when possible. 2388 if (!VT.isVector() && 2389 SimplifyDemandedBits(SDValue(N, 0))) 2390 return SDValue(N, 0); 2391 2392 // fold (zext_inreg (extload x)) -> (zextload x) 2393 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2394 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2395 EVT MemVT = LN0->getMemoryVT(); 2396 // If we zero all the possible extended bits, then we can turn this into 2397 // a zextload if we are running before legalize or the operation is legal. 2398 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2399 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2400 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2401 ((!LegalOperations && !LN0->isVolatile()) || 2402 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2403 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2404 LN0->getChain(), LN0->getBasePtr(), 2405 LN0->getPointerInfo(), MemVT, 2406 LN0->isVolatile(), LN0->isNonTemporal(), 2407 LN0->getAlignment()); 2408 AddToWorkList(N); 2409 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2410 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2411 } 2412 } 2413 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2414 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2415 N0.hasOneUse()) { 2416 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2417 EVT MemVT = LN0->getMemoryVT(); 2418 // If we zero all the possible extended bits, then we can turn this into 2419 // a zextload if we are running before legalize or the operation is legal. 2420 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2421 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2422 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2423 ((!LegalOperations && !LN0->isVolatile()) || 2424 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2425 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2426 LN0->getChain(), 2427 LN0->getBasePtr(), LN0->getPointerInfo(), 2428 MemVT, 2429 LN0->isVolatile(), LN0->isNonTemporal(), 2430 LN0->getAlignment()); 2431 AddToWorkList(N); 2432 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2433 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2434 } 2435 } 2436 2437 // fold (and (load x), 255) -> (zextload x, i8) 2438 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2439 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2440 if (N1C && (N0.getOpcode() == ISD::LOAD || 2441 (N0.getOpcode() == ISD::ANY_EXTEND && 2442 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2443 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2444 LoadSDNode *LN0 = HasAnyExt 2445 ? cast<LoadSDNode>(N0.getOperand(0)) 2446 : cast<LoadSDNode>(N0); 2447 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2448 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2449 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2450 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2451 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2452 EVT LoadedVT = LN0->getMemoryVT(); 2453 2454 if (ExtVT == LoadedVT && 2455 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2456 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2457 2458 SDValue NewLoad = 2459 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2460 LN0->getChain(), LN0->getBasePtr(), 2461 LN0->getPointerInfo(), 2462 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2463 LN0->getAlignment()); 2464 AddToWorkList(N); 2465 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2466 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2467 } 2468 2469 // Do not change the width of a volatile load. 2470 // Do not generate loads of non-round integer types since these can 2471 // be expensive (and would be wrong if the type is not byte sized). 2472 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2473 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2474 EVT PtrType = LN0->getOperand(1).getValueType(); 2475 2476 unsigned Alignment = LN0->getAlignment(); 2477 SDValue NewPtr = LN0->getBasePtr(); 2478 2479 // For big endian targets, we need to add an offset to the pointer 2480 // to load the correct bytes. For little endian systems, we merely 2481 // need to read fewer bytes from the same pointer. 2482 if (TLI.isBigEndian()) { 2483 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2484 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2485 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2486 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2487 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2488 Alignment = MinAlign(Alignment, PtrOff); 2489 } 2490 2491 AddToWorkList(NewPtr.getNode()); 2492 2493 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2494 SDValue Load = 2495 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2496 LN0->getChain(), NewPtr, 2497 LN0->getPointerInfo(), 2498 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2499 Alignment); 2500 AddToWorkList(N); 2501 CombineTo(LN0, Load, Load.getValue(1)); 2502 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2503 } 2504 } 2505 } 2506 } 2507 2508 return SDValue(); 2509} 2510 2511SDValue DAGCombiner::visitOR(SDNode *N) { 2512 SDValue N0 = N->getOperand(0); 2513 SDValue N1 = N->getOperand(1); 2514 SDValue LL, LR, RL, RR, CC0, CC1; 2515 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2516 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2517 EVT VT = N1.getValueType(); 2518 2519 // fold vector ops 2520 if (VT.isVector()) { 2521 SDValue FoldedVOp = SimplifyVBinOp(N); 2522 if (FoldedVOp.getNode()) return FoldedVOp; 2523 } 2524 2525 // fold (or x, undef) -> -1 2526 if (!LegalOperations && 2527 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2528 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2529 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2530 } 2531 // fold (or c1, c2) -> c1|c2 2532 if (N0C && N1C) 2533 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2534 // canonicalize constant to RHS 2535 if (N0C && !N1C) 2536 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2537 // fold (or x, 0) -> x 2538 if (N1C && N1C->isNullValue()) 2539 return N0; 2540 // fold (or x, -1) -> -1 2541 if (N1C && N1C->isAllOnesValue()) 2542 return N1; 2543 // fold (or x, c) -> c iff (x & ~c) == 0 2544 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2545 return N1; 2546 // reassociate or 2547 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2548 if (ROR.getNode() != 0) 2549 return ROR; 2550 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2551 // iff (c1 & c2) == 0. 2552 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2553 isa<ConstantSDNode>(N0.getOperand(1))) { 2554 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2555 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2556 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2557 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2558 N0.getOperand(0), N1), 2559 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2560 } 2561 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2562 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2563 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2564 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2565 2566 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2567 LL.getValueType().isInteger()) { 2568 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2569 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2570 if (cast<ConstantSDNode>(LR)->isNullValue() && 2571 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2572 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2573 LR.getValueType(), LL, RL); 2574 AddToWorkList(ORNode.getNode()); 2575 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2576 } 2577 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2578 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2579 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2580 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2581 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2582 LR.getValueType(), LL, RL); 2583 AddToWorkList(ANDNode.getNode()); 2584 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2585 } 2586 } 2587 // canonicalize equivalent to ll == rl 2588 if (LL == RR && LR == RL) { 2589 Op1 = ISD::getSetCCSwappedOperands(Op1); 2590 std::swap(RL, RR); 2591 } 2592 if (LL == RL && LR == RR) { 2593 bool isInteger = LL.getValueType().isInteger(); 2594 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2595 if (Result != ISD::SETCC_INVALID && 2596 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2597 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2598 LL, LR, Result); 2599 } 2600 } 2601 2602 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2603 if (N0.getOpcode() == N1.getOpcode()) { 2604 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2605 if (Tmp.getNode()) return Tmp; 2606 } 2607 2608 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2609 if (N0.getOpcode() == ISD::AND && 2610 N1.getOpcode() == ISD::AND && 2611 N0.getOperand(1).getOpcode() == ISD::Constant && 2612 N1.getOperand(1).getOpcode() == ISD::Constant && 2613 // Don't increase # computations. 2614 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2615 // We can only do this xform if we know that bits from X that are set in C2 2616 // but not in C1 are already zero. Likewise for Y. 2617 const APInt &LHSMask = 2618 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2619 const APInt &RHSMask = 2620 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2621 2622 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2623 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2624 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2625 N0.getOperand(0), N1.getOperand(0)); 2626 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2627 DAG.getConstant(LHSMask | RHSMask, VT)); 2628 } 2629 } 2630 2631 // See if this is some rotate idiom. 2632 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2633 return SDValue(Rot, 0); 2634 2635 // Simplify the operands using demanded-bits information. 2636 if (!VT.isVector() && 2637 SimplifyDemandedBits(SDValue(N, 0))) 2638 return SDValue(N, 0); 2639 2640 return SDValue(); 2641} 2642 2643/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2644static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2645 if (Op.getOpcode() == ISD::AND) { 2646 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2647 Mask = Op.getOperand(1); 2648 Op = Op.getOperand(0); 2649 } else { 2650 return false; 2651 } 2652 } 2653 2654 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2655 Shift = Op; 2656 return true; 2657 } 2658 2659 return false; 2660} 2661 2662// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2663// idioms for rotate, and if the target supports rotation instructions, generate 2664// a rot[lr]. 2665SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2666 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2667 EVT VT = LHS.getValueType(); 2668 if (!TLI.isTypeLegal(VT)) return 0; 2669 2670 // The target must have at least one rotate flavor. 2671 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2672 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2673 if (!HasROTL && !HasROTR) return 0; 2674 2675 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2676 SDValue LHSShift; // The shift. 2677 SDValue LHSMask; // AND value if any. 2678 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2679 return 0; // Not part of a rotate. 2680 2681 SDValue RHSShift; // The shift. 2682 SDValue RHSMask; // AND value if any. 2683 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2684 return 0; // Not part of a rotate. 2685 2686 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2687 return 0; // Not shifting the same value. 2688 2689 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2690 return 0; // Shifts must disagree. 2691 2692 // Canonicalize shl to left side in a shl/srl pair. 2693 if (RHSShift.getOpcode() == ISD::SHL) { 2694 std::swap(LHS, RHS); 2695 std::swap(LHSShift, RHSShift); 2696 std::swap(LHSMask , RHSMask ); 2697 } 2698 2699 unsigned OpSizeInBits = VT.getSizeInBits(); 2700 SDValue LHSShiftArg = LHSShift.getOperand(0); 2701 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2702 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2703 2704 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2705 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2706 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2707 RHSShiftAmt.getOpcode() == ISD::Constant) { 2708 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2709 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2710 if ((LShVal + RShVal) != OpSizeInBits) 2711 return 0; 2712 2713 SDValue Rot; 2714 if (HasROTL) 2715 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2716 else 2717 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2718 2719 // If there is an AND of either shifted operand, apply it to the result. 2720 if (LHSMask.getNode() || RHSMask.getNode()) { 2721 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2722 2723 if (LHSMask.getNode()) { 2724 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2725 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2726 } 2727 if (RHSMask.getNode()) { 2728 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2729 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2730 } 2731 2732 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2733 } 2734 2735 return Rot.getNode(); 2736 } 2737 2738 // If there is a mask here, and we have a variable shift, we can't be sure 2739 // that we're masking out the right stuff. 2740 if (LHSMask.getNode() || RHSMask.getNode()) 2741 return 0; 2742 2743 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2744 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2745 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2746 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2747 if (ConstantSDNode *SUBC = 2748 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2749 if (SUBC->getAPIntValue() == OpSizeInBits) { 2750 if (HasROTL) 2751 return DAG.getNode(ISD::ROTL, DL, VT, 2752 LHSShiftArg, LHSShiftAmt).getNode(); 2753 else 2754 return DAG.getNode(ISD::ROTR, DL, VT, 2755 LHSShiftArg, RHSShiftAmt).getNode(); 2756 } 2757 } 2758 } 2759 2760 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2761 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2762 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2763 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2764 if (ConstantSDNode *SUBC = 2765 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2766 if (SUBC->getAPIntValue() == OpSizeInBits) { 2767 if (HasROTR) 2768 return DAG.getNode(ISD::ROTR, DL, VT, 2769 LHSShiftArg, RHSShiftAmt).getNode(); 2770 else 2771 return DAG.getNode(ISD::ROTL, DL, VT, 2772 LHSShiftArg, LHSShiftAmt).getNode(); 2773 } 2774 } 2775 } 2776 2777 // Look for sign/zext/any-extended or truncate cases: 2778 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2779 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2780 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2781 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2782 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2783 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2784 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2785 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2786 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2787 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2788 if (RExtOp0.getOpcode() == ISD::SUB && 2789 RExtOp0.getOperand(1) == LExtOp0) { 2790 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2791 // (rotl x, y) 2792 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2793 // (rotr x, (sub 32, y)) 2794 if (ConstantSDNode *SUBC = 2795 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2796 if (SUBC->getAPIntValue() == OpSizeInBits) { 2797 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2798 LHSShiftArg, 2799 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2800 } 2801 } 2802 } else if (LExtOp0.getOpcode() == ISD::SUB && 2803 RExtOp0 == LExtOp0.getOperand(1)) { 2804 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2805 // (rotr x, y) 2806 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2807 // (rotl x, (sub 32, y)) 2808 if (ConstantSDNode *SUBC = 2809 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2810 if (SUBC->getAPIntValue() == OpSizeInBits) { 2811 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2812 LHSShiftArg, 2813 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2814 } 2815 } 2816 } 2817 } 2818 2819 return 0; 2820} 2821 2822SDValue DAGCombiner::visitXOR(SDNode *N) { 2823 SDValue N0 = N->getOperand(0); 2824 SDValue N1 = N->getOperand(1); 2825 SDValue LHS, RHS, CC; 2826 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2827 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2828 EVT VT = N0.getValueType(); 2829 2830 // fold vector ops 2831 if (VT.isVector()) { 2832 SDValue FoldedVOp = SimplifyVBinOp(N); 2833 if (FoldedVOp.getNode()) return FoldedVOp; 2834 } 2835 2836 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2837 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2838 return DAG.getConstant(0, VT); 2839 // fold (xor x, undef) -> undef 2840 if (N0.getOpcode() == ISD::UNDEF) 2841 return N0; 2842 if (N1.getOpcode() == ISD::UNDEF) 2843 return N1; 2844 // fold (xor c1, c2) -> c1^c2 2845 if (N0C && N1C) 2846 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2847 // canonicalize constant to RHS 2848 if (N0C && !N1C) 2849 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2850 // fold (xor x, 0) -> x 2851 if (N1C && N1C->isNullValue()) 2852 return N0; 2853 // reassociate xor 2854 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2855 if (RXOR.getNode() != 0) 2856 return RXOR; 2857 2858 // fold !(x cc y) -> (x !cc y) 2859 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2860 bool isInt = LHS.getValueType().isInteger(); 2861 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2862 isInt); 2863 2864 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2865 switch (N0.getOpcode()) { 2866 default: 2867 llvm_unreachable("Unhandled SetCC Equivalent!"); 2868 case ISD::SETCC: 2869 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2870 case ISD::SELECT_CC: 2871 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2872 N0.getOperand(3), NotCC); 2873 } 2874 } 2875 } 2876 2877 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2878 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2879 N0.getNode()->hasOneUse() && 2880 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2881 SDValue V = N0.getOperand(0); 2882 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2883 DAG.getConstant(1, V.getValueType())); 2884 AddToWorkList(V.getNode()); 2885 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2886 } 2887 2888 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2889 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2890 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2891 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2892 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2893 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2894 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2895 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2896 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2897 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2898 } 2899 } 2900 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2901 if (N1C && N1C->isAllOnesValue() && 2902 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2903 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2904 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2905 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2906 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2907 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2908 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2909 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2910 } 2911 } 2912 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2913 if (N1C && N0.getOpcode() == ISD::XOR) { 2914 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2915 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2916 if (N00C) 2917 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2918 DAG.getConstant(N1C->getAPIntValue() ^ 2919 N00C->getAPIntValue(), VT)); 2920 if (N01C) 2921 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2922 DAG.getConstant(N1C->getAPIntValue() ^ 2923 N01C->getAPIntValue(), VT)); 2924 } 2925 // fold (xor x, x) -> 0 2926 if (N0 == N1) 2927 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 2928 2929 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2930 if (N0.getOpcode() == N1.getOpcode()) { 2931 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2932 if (Tmp.getNode()) return Tmp; 2933 } 2934 2935 // Simplify the expression using non-local knowledge. 2936 if (!VT.isVector() && 2937 SimplifyDemandedBits(SDValue(N, 0))) 2938 return SDValue(N, 0); 2939 2940 return SDValue(); 2941} 2942 2943/// visitShiftByConstant - Handle transforms common to the three shifts, when 2944/// the shift amount is a constant. 2945SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2946 SDNode *LHS = N->getOperand(0).getNode(); 2947 if (!LHS->hasOneUse()) return SDValue(); 2948 2949 // We want to pull some binops through shifts, so that we have (and (shift)) 2950 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2951 // thing happens with address calculations, so it's important to canonicalize 2952 // it. 2953 bool HighBitSet = false; // Can we transform this if the high bit is set? 2954 2955 switch (LHS->getOpcode()) { 2956 default: return SDValue(); 2957 case ISD::OR: 2958 case ISD::XOR: 2959 HighBitSet = false; // We can only transform sra if the high bit is clear. 2960 break; 2961 case ISD::AND: 2962 HighBitSet = true; // We can only transform sra if the high bit is set. 2963 break; 2964 case ISD::ADD: 2965 if (N->getOpcode() != ISD::SHL) 2966 return SDValue(); // only shl(add) not sr[al](add). 2967 HighBitSet = false; // We can only transform sra if the high bit is clear. 2968 break; 2969 } 2970 2971 // We require the RHS of the binop to be a constant as well. 2972 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2973 if (!BinOpCst) return SDValue(); 2974 2975 // FIXME: disable this unless the input to the binop is a shift by a constant. 2976 // If it is not a shift, it pessimizes some common cases like: 2977 // 2978 // void foo(int *X, int i) { X[i & 1235] = 1; } 2979 // int bar(int *X, int i) { return X[i & 255]; } 2980 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2981 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2982 BinOpLHSVal->getOpcode() != ISD::SRA && 2983 BinOpLHSVal->getOpcode() != ISD::SRL) || 2984 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2985 return SDValue(); 2986 2987 EVT VT = N->getValueType(0); 2988 2989 // If this is a signed shift right, and the high bit is modified by the 2990 // logical operation, do not perform the transformation. The highBitSet 2991 // boolean indicates the value of the high bit of the constant which would 2992 // cause it to be modified for this operation. 2993 if (N->getOpcode() == ISD::SRA) { 2994 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2995 if (BinOpRHSSignSet != HighBitSet) 2996 return SDValue(); 2997 } 2998 2999 // Fold the constants, shifting the binop RHS by the shift amount. 3000 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3001 N->getValueType(0), 3002 LHS->getOperand(1), N->getOperand(1)); 3003 3004 // Create the new shift. 3005 SDValue NewShift = DAG.getNode(N->getOpcode(), 3006 LHS->getOperand(0).getDebugLoc(), 3007 VT, LHS->getOperand(0), N->getOperand(1)); 3008 3009 // Create the new binop. 3010 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3011} 3012 3013SDValue DAGCombiner::visitSHL(SDNode *N) { 3014 SDValue N0 = N->getOperand(0); 3015 SDValue N1 = N->getOperand(1); 3016 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3017 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3018 EVT VT = N0.getValueType(); 3019 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3020 3021 // fold (shl c1, c2) -> c1<<c2 3022 if (N0C && N1C) 3023 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3024 // fold (shl 0, x) -> 0 3025 if (N0C && N0C->isNullValue()) 3026 return N0; 3027 // fold (shl x, c >= size(x)) -> undef 3028 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3029 return DAG.getUNDEF(VT); 3030 // fold (shl x, 0) -> x 3031 if (N1C && N1C->isNullValue()) 3032 return N0; 3033 // if (shl x, c) is known to be zero, return 0 3034 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3035 APInt::getAllOnesValue(OpSizeInBits))) 3036 return DAG.getConstant(0, VT); 3037 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3038 if (N1.getOpcode() == ISD::TRUNCATE && 3039 N1.getOperand(0).getOpcode() == ISD::AND && 3040 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3041 SDValue N101 = N1.getOperand(0).getOperand(1); 3042 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3043 EVT TruncVT = N1.getValueType(); 3044 SDValue N100 = N1.getOperand(0).getOperand(0); 3045 APInt TruncC = N101C->getAPIntValue(); 3046 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3047 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3048 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3049 DAG.getNode(ISD::TRUNCATE, 3050 N->getDebugLoc(), 3051 TruncVT, N100), 3052 DAG.getConstant(TruncC, TruncVT))); 3053 } 3054 } 3055 3056 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3057 return SDValue(N, 0); 3058 3059 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3060 if (N1C && N0.getOpcode() == ISD::SHL && 3061 N0.getOperand(1).getOpcode() == ISD::Constant) { 3062 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3063 uint64_t c2 = N1C->getZExtValue(); 3064 if (c1 + c2 >= OpSizeInBits) 3065 return DAG.getConstant(0, VT); 3066 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3067 DAG.getConstant(c1 + c2, N1.getValueType())); 3068 } 3069 3070 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3071 // For this to be valid, the second form must not preserve any of the bits 3072 // that are shifted out by the inner shift in the first form. This means 3073 // the outer shift size must be >= the number of bits added by the ext. 3074 // As a corollary, we don't care what kind of ext it is. 3075 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3076 N0.getOpcode() == ISD::ANY_EXTEND || 3077 N0.getOpcode() == ISD::SIGN_EXTEND) && 3078 N0.getOperand(0).getOpcode() == ISD::SHL && 3079 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3080 uint64_t c1 = 3081 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3082 uint64_t c2 = N1C->getZExtValue(); 3083 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3084 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3085 if (c2 >= OpSizeInBits - InnerShiftSize) { 3086 if (c1 + c2 >= OpSizeInBits) 3087 return DAG.getConstant(0, VT); 3088 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3089 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3090 N0.getOperand(0)->getOperand(0)), 3091 DAG.getConstant(c1 + c2, N1.getValueType())); 3092 } 3093 } 3094 3095 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3096 // (and (srl x, (sub c1, c2), MASK) 3097 if (N1C && N0.getOpcode() == ISD::SRL && 3098 N0.getOperand(1).getOpcode() == ISD::Constant) { 3099 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3100 if (c1 < VT.getSizeInBits()) { 3101 uint64_t c2 = N1C->getZExtValue(); 3102 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3103 VT.getSizeInBits() - c1); 3104 SDValue Shift; 3105 if (c2 > c1) { 3106 Mask = Mask.shl(c2-c1); 3107 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3108 DAG.getConstant(c2-c1, N1.getValueType())); 3109 } else { 3110 Mask = Mask.lshr(c1-c2); 3111 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3112 DAG.getConstant(c1-c2, N1.getValueType())); 3113 } 3114 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3115 DAG.getConstant(Mask, VT)); 3116 } 3117 } 3118 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3119 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3120 SDValue HiBitsMask = 3121 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3122 VT.getSizeInBits() - 3123 N1C->getZExtValue()), 3124 VT); 3125 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3126 HiBitsMask); 3127 } 3128 3129 if (N1C) { 3130 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3131 if (NewSHL.getNode()) 3132 return NewSHL; 3133 } 3134 3135 return SDValue(); 3136} 3137 3138SDValue DAGCombiner::visitSRA(SDNode *N) { 3139 SDValue N0 = N->getOperand(0); 3140 SDValue N1 = N->getOperand(1); 3141 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3142 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3143 EVT VT = N0.getValueType(); 3144 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3145 3146 // fold (sra c1, c2) -> (sra c1, c2) 3147 if (N0C && N1C) 3148 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3149 // fold (sra 0, x) -> 0 3150 if (N0C && N0C->isNullValue()) 3151 return N0; 3152 // fold (sra -1, x) -> -1 3153 if (N0C && N0C->isAllOnesValue()) 3154 return N0; 3155 // fold (sra x, (setge c, size(x))) -> undef 3156 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3157 return DAG.getUNDEF(VT); 3158 // fold (sra x, 0) -> x 3159 if (N1C && N1C->isNullValue()) 3160 return N0; 3161 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3162 // sext_inreg. 3163 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3164 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3165 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3166 if (VT.isVector()) 3167 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3168 ExtVT, VT.getVectorNumElements()); 3169 if ((!LegalOperations || 3170 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3171 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3172 N0.getOperand(0), DAG.getValueType(ExtVT)); 3173 } 3174 3175 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3176 if (N1C && N0.getOpcode() == ISD::SRA) { 3177 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3178 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3179 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3180 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3181 DAG.getConstant(Sum, N1C->getValueType(0))); 3182 } 3183 } 3184 3185 // fold (sra (shl X, m), (sub result_size, n)) 3186 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3187 // result_size - n != m. 3188 // If truncate is free for the target sext(shl) is likely to result in better 3189 // code. 3190 if (N0.getOpcode() == ISD::SHL) { 3191 // Get the two constanst of the shifts, CN0 = m, CN = n. 3192 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3193 if (N01C && N1C) { 3194 // Determine what the truncate's result bitsize and type would be. 3195 EVT TruncVT = 3196 EVT::getIntegerVT(*DAG.getContext(), 3197 OpSizeInBits - N1C->getZExtValue()); 3198 // Determine the residual right-shift amount. 3199 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3200 3201 // If the shift is not a no-op (in which case this should be just a sign 3202 // extend already), the truncated to type is legal, sign_extend is legal 3203 // on that type, and the truncate to that type is both legal and free, 3204 // perform the transform. 3205 if ((ShiftAmt > 0) && 3206 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3207 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3208 TLI.isTruncateFree(VT, TruncVT)) { 3209 3210 SDValue Amt = DAG.getConstant(ShiftAmt, 3211 getShiftAmountTy(N0.getOperand(0).getValueType())); 3212 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3213 N0.getOperand(0), Amt); 3214 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3215 Shift); 3216 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3217 N->getValueType(0), Trunc); 3218 } 3219 } 3220 } 3221 3222 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3223 if (N1.getOpcode() == ISD::TRUNCATE && 3224 N1.getOperand(0).getOpcode() == ISD::AND && 3225 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3226 SDValue N101 = N1.getOperand(0).getOperand(1); 3227 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3228 EVT TruncVT = N1.getValueType(); 3229 SDValue N100 = N1.getOperand(0).getOperand(0); 3230 APInt TruncC = N101C->getAPIntValue(); 3231 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3232 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3233 DAG.getNode(ISD::AND, N->getDebugLoc(), 3234 TruncVT, 3235 DAG.getNode(ISD::TRUNCATE, 3236 N->getDebugLoc(), 3237 TruncVT, N100), 3238 DAG.getConstant(TruncC, TruncVT))); 3239 } 3240 } 3241 3242 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3243 // if c1 is equal to the number of bits the trunc removes 3244 if (N0.getOpcode() == ISD::TRUNCATE && 3245 (N0.getOperand(0).getOpcode() == ISD::SRL || 3246 N0.getOperand(0).getOpcode() == ISD::SRA) && 3247 N0.getOperand(0).hasOneUse() && 3248 N0.getOperand(0).getOperand(1).hasOneUse() && 3249 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3250 EVT LargeVT = N0.getOperand(0).getValueType(); 3251 ConstantSDNode *LargeShiftAmt = 3252 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3253 3254 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3255 LargeShiftAmt->getZExtValue()) { 3256 SDValue Amt = 3257 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3258 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3259 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3260 N0.getOperand(0).getOperand(0), Amt); 3261 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3262 } 3263 } 3264 3265 // Simplify, based on bits shifted out of the LHS. 3266 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3267 return SDValue(N, 0); 3268 3269 3270 // If the sign bit is known to be zero, switch this to a SRL. 3271 if (DAG.SignBitIsZero(N0)) 3272 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3273 3274 if (N1C) { 3275 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3276 if (NewSRA.getNode()) 3277 return NewSRA; 3278 } 3279 3280 return SDValue(); 3281} 3282 3283SDValue DAGCombiner::visitSRL(SDNode *N) { 3284 SDValue N0 = N->getOperand(0); 3285 SDValue N1 = N->getOperand(1); 3286 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3287 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3288 EVT VT = N0.getValueType(); 3289 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3290 3291 // fold (srl c1, c2) -> c1 >>u c2 3292 if (N0C && N1C) 3293 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3294 // fold (srl 0, x) -> 0 3295 if (N0C && N0C->isNullValue()) 3296 return N0; 3297 // fold (srl x, c >= size(x)) -> undef 3298 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3299 return DAG.getUNDEF(VT); 3300 // fold (srl x, 0) -> x 3301 if (N1C && N1C->isNullValue()) 3302 return N0; 3303 // if (srl x, c) is known to be zero, return 0 3304 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3305 APInt::getAllOnesValue(OpSizeInBits))) 3306 return DAG.getConstant(0, VT); 3307 3308 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3309 if (N1C && N0.getOpcode() == ISD::SRL && 3310 N0.getOperand(1).getOpcode() == ISD::Constant) { 3311 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3312 uint64_t c2 = N1C->getZExtValue(); 3313 if (c1 + c2 >= OpSizeInBits) 3314 return DAG.getConstant(0, VT); 3315 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3316 DAG.getConstant(c1 + c2, N1.getValueType())); 3317 } 3318 3319 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3320 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3321 N0.getOperand(0).getOpcode() == ISD::SRL && 3322 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3323 uint64_t c1 = 3324 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3325 uint64_t c2 = N1C->getZExtValue(); 3326 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3327 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3328 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3329 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3330 if (c1 + OpSizeInBits == InnerShiftSize) { 3331 if (c1 + c2 >= InnerShiftSize) 3332 return DAG.getConstant(0, VT); 3333 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3334 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3335 N0.getOperand(0)->getOperand(0), 3336 DAG.getConstant(c1 + c2, ShiftCountVT))); 3337 } 3338 } 3339 3340 // fold (srl (shl x, c), c) -> (and x, cst2) 3341 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3342 N0.getValueSizeInBits() <= 64) { 3343 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3344 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3345 DAG.getConstant(~0ULL >> ShAmt, VT)); 3346 } 3347 3348 3349 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3350 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3351 // Shifting in all undef bits? 3352 EVT SmallVT = N0.getOperand(0).getValueType(); 3353 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3354 return DAG.getUNDEF(VT); 3355 3356 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3357 uint64_t ShiftAmt = N1C->getZExtValue(); 3358 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3359 N0.getOperand(0), 3360 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3361 AddToWorkList(SmallShift.getNode()); 3362 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3363 } 3364 } 3365 3366 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3367 // bit, which is unmodified by sra. 3368 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3369 if (N0.getOpcode() == ISD::SRA) 3370 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3371 } 3372 3373 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3374 if (N1C && N0.getOpcode() == ISD::CTLZ && 3375 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3376 APInt KnownZero, KnownOne; 3377 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3378 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3379 3380 // If any of the input bits are KnownOne, then the input couldn't be all 3381 // zeros, thus the result of the srl will always be zero. 3382 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3383 3384 // If all of the bits input the to ctlz node are known to be zero, then 3385 // the result of the ctlz is "32" and the result of the shift is one. 3386 APInt UnknownBits = ~KnownZero & Mask; 3387 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3388 3389 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3390 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3391 // Okay, we know that only that the single bit specified by UnknownBits 3392 // could be set on input to the CTLZ node. If this bit is set, the SRL 3393 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3394 // to an SRL/XOR pair, which is likely to simplify more. 3395 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3396 SDValue Op = N0.getOperand(0); 3397 3398 if (ShAmt) { 3399 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3400 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3401 AddToWorkList(Op.getNode()); 3402 } 3403 3404 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3405 Op, DAG.getConstant(1, VT)); 3406 } 3407 } 3408 3409 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3410 if (N1.getOpcode() == ISD::TRUNCATE && 3411 N1.getOperand(0).getOpcode() == ISD::AND && 3412 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3413 SDValue N101 = N1.getOperand(0).getOperand(1); 3414 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3415 EVT TruncVT = N1.getValueType(); 3416 SDValue N100 = N1.getOperand(0).getOperand(0); 3417 APInt TruncC = N101C->getAPIntValue(); 3418 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3419 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3420 DAG.getNode(ISD::AND, N->getDebugLoc(), 3421 TruncVT, 3422 DAG.getNode(ISD::TRUNCATE, 3423 N->getDebugLoc(), 3424 TruncVT, N100), 3425 DAG.getConstant(TruncC, TruncVT))); 3426 } 3427 } 3428 3429 // fold operands of srl based on knowledge that the low bits are not 3430 // demanded. 3431 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3432 return SDValue(N, 0); 3433 3434 if (N1C) { 3435 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3436 if (NewSRL.getNode()) 3437 return NewSRL; 3438 } 3439 3440 // Attempt to convert a srl of a load into a narrower zero-extending load. 3441 SDValue NarrowLoad = ReduceLoadWidth(N); 3442 if (NarrowLoad.getNode()) 3443 return NarrowLoad; 3444 3445 // Here is a common situation. We want to optimize: 3446 // 3447 // %a = ... 3448 // %b = and i32 %a, 2 3449 // %c = srl i32 %b, 1 3450 // brcond i32 %c ... 3451 // 3452 // into 3453 // 3454 // %a = ... 3455 // %b = and %a, 2 3456 // %c = setcc eq %b, 0 3457 // brcond %c ... 3458 // 3459 // However when after the source operand of SRL is optimized into AND, the SRL 3460 // itself may not be optimized further. Look for it and add the BRCOND into 3461 // the worklist. 3462 if (N->hasOneUse()) { 3463 SDNode *Use = *N->use_begin(); 3464 if (Use->getOpcode() == ISD::BRCOND) 3465 AddToWorkList(Use); 3466 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3467 // Also look pass the truncate. 3468 Use = *Use->use_begin(); 3469 if (Use->getOpcode() == ISD::BRCOND) 3470 AddToWorkList(Use); 3471 } 3472 } 3473 3474 return SDValue(); 3475} 3476 3477SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3478 SDValue N0 = N->getOperand(0); 3479 EVT VT = N->getValueType(0); 3480 3481 // fold (ctlz c1) -> c2 3482 if (isa<ConstantSDNode>(N0)) 3483 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3484 return SDValue(); 3485} 3486 3487SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3488 SDValue N0 = N->getOperand(0); 3489 EVT VT = N->getValueType(0); 3490 3491 // fold (cttz c1) -> c2 3492 if (isa<ConstantSDNode>(N0)) 3493 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3494 return SDValue(); 3495} 3496 3497SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3498 SDValue N0 = N->getOperand(0); 3499 EVT VT = N->getValueType(0); 3500 3501 // fold (ctpop c1) -> c2 3502 if (isa<ConstantSDNode>(N0)) 3503 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3504 return SDValue(); 3505} 3506 3507SDValue DAGCombiner::visitSELECT(SDNode *N) { 3508 SDValue N0 = N->getOperand(0); 3509 SDValue N1 = N->getOperand(1); 3510 SDValue N2 = N->getOperand(2); 3511 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3512 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3513 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3514 EVT VT = N->getValueType(0); 3515 EVT VT0 = N0.getValueType(); 3516 3517 // fold (select C, X, X) -> X 3518 if (N1 == N2) 3519 return N1; 3520 // fold (select true, X, Y) -> X 3521 if (N0C && !N0C->isNullValue()) 3522 return N1; 3523 // fold (select false, X, Y) -> Y 3524 if (N0C && N0C->isNullValue()) 3525 return N2; 3526 // fold (select C, 1, X) -> (or C, X) 3527 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3528 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3529 // fold (select C, 0, 1) -> (xor C, 1) 3530 if (VT.isInteger() && 3531 (VT0 == MVT::i1 || 3532 (VT0.isInteger() && 3533 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 3534 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3535 SDValue XORNode; 3536 if (VT == VT0) 3537 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3538 N0, DAG.getConstant(1, VT0)); 3539 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3540 N0, DAG.getConstant(1, VT0)); 3541 AddToWorkList(XORNode.getNode()); 3542 if (VT.bitsGT(VT0)) 3543 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3544 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3545 } 3546 // fold (select C, 0, X) -> (and (not C), X) 3547 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3548 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3549 AddToWorkList(NOTNode.getNode()); 3550 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3551 } 3552 // fold (select C, X, 1) -> (or (not C), X) 3553 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3554 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3555 AddToWorkList(NOTNode.getNode()); 3556 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3557 } 3558 // fold (select C, X, 0) -> (and C, X) 3559 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3560 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3561 // fold (select X, X, Y) -> (or X, Y) 3562 // fold (select X, 1, Y) -> (or X, Y) 3563 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3564 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3565 // fold (select X, Y, X) -> (and X, Y) 3566 // fold (select X, Y, 0) -> (and X, Y) 3567 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3568 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3569 3570 // If we can fold this based on the true/false value, do so. 3571 if (SimplifySelectOps(N, N1, N2)) 3572 return SDValue(N, 0); // Don't revisit N. 3573 3574 // fold selects based on a setcc into other things, such as min/max/abs 3575 if (N0.getOpcode() == ISD::SETCC) { 3576 // FIXME: 3577 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3578 // having to say they don't support SELECT_CC on every type the DAG knows 3579 // about, since there is no way to mark an opcode illegal at all value types 3580 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3581 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3582 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3583 N0.getOperand(0), N0.getOperand(1), 3584 N1, N2, N0.getOperand(2)); 3585 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3586 } 3587 3588 return SDValue(); 3589} 3590 3591SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3592 SDValue N0 = N->getOperand(0); 3593 SDValue N1 = N->getOperand(1); 3594 SDValue N2 = N->getOperand(2); 3595 SDValue N3 = N->getOperand(3); 3596 SDValue N4 = N->getOperand(4); 3597 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3598 3599 // fold select_cc lhs, rhs, x, x, cc -> x 3600 if (N2 == N3) 3601 return N2; 3602 3603 // Determine if the condition we're dealing with is constant 3604 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3605 N0, N1, CC, N->getDebugLoc(), false); 3606 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3607 3608 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3609 if (!SCCC->isNullValue()) 3610 return N2; // cond always true -> true val 3611 else 3612 return N3; // cond always false -> false val 3613 } 3614 3615 // Fold to a simpler select_cc 3616 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3617 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3618 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3619 SCC.getOperand(2)); 3620 3621 // If we can fold this based on the true/false value, do so. 3622 if (SimplifySelectOps(N, N2, N3)) 3623 return SDValue(N, 0); // Don't revisit N. 3624 3625 // fold select_cc into other things, such as min/max/abs 3626 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3627} 3628 3629SDValue DAGCombiner::visitSETCC(SDNode *N) { 3630 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3631 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3632 N->getDebugLoc()); 3633} 3634 3635// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3636// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3637// transformation. Returns true if extension are possible and the above 3638// mentioned transformation is profitable. 3639static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3640 unsigned ExtOpc, 3641 SmallVector<SDNode*, 4> &ExtendNodes, 3642 const TargetLowering &TLI) { 3643 bool HasCopyToRegUses = false; 3644 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3645 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3646 UE = N0.getNode()->use_end(); 3647 UI != UE; ++UI) { 3648 SDNode *User = *UI; 3649 if (User == N) 3650 continue; 3651 if (UI.getUse().getResNo() != N0.getResNo()) 3652 continue; 3653 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3654 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3655 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3656 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3657 // Sign bits will be lost after a zext. 3658 return false; 3659 bool Add = false; 3660 for (unsigned i = 0; i != 2; ++i) { 3661 SDValue UseOp = User->getOperand(i); 3662 if (UseOp == N0) 3663 continue; 3664 if (!isa<ConstantSDNode>(UseOp)) 3665 return false; 3666 Add = true; 3667 } 3668 if (Add) 3669 ExtendNodes.push_back(User); 3670 continue; 3671 } 3672 // If truncates aren't free and there are users we can't 3673 // extend, it isn't worthwhile. 3674 if (!isTruncFree) 3675 return false; 3676 // Remember if this value is live-out. 3677 if (User->getOpcode() == ISD::CopyToReg) 3678 HasCopyToRegUses = true; 3679 } 3680 3681 if (HasCopyToRegUses) { 3682 bool BothLiveOut = false; 3683 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3684 UI != UE; ++UI) { 3685 SDUse &Use = UI.getUse(); 3686 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3687 BothLiveOut = true; 3688 break; 3689 } 3690 } 3691 if (BothLiveOut) 3692 // Both unextended and extended values are live out. There had better be 3693 // a good reason for the transformation. 3694 return ExtendNodes.size(); 3695 } 3696 return true; 3697} 3698 3699SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3700 SDValue N0 = N->getOperand(0); 3701 EVT VT = N->getValueType(0); 3702 3703 // fold (sext c1) -> c1 3704 if (isa<ConstantSDNode>(N0)) 3705 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3706 3707 // fold (sext (sext x)) -> (sext x) 3708 // fold (sext (aext x)) -> (sext x) 3709 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3710 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3711 N0.getOperand(0)); 3712 3713 if (N0.getOpcode() == ISD::TRUNCATE) { 3714 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3715 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3716 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3717 if (NarrowLoad.getNode()) { 3718 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3719 if (NarrowLoad.getNode() != N0.getNode()) { 3720 CombineTo(N0.getNode(), NarrowLoad); 3721 // CombineTo deleted the truncate, if needed, but not what's under it. 3722 AddToWorkList(oye); 3723 } 3724 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3725 } 3726 3727 // See if the value being truncated is already sign extended. If so, just 3728 // eliminate the trunc/sext pair. 3729 SDValue Op = N0.getOperand(0); 3730 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3731 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3732 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3733 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3734 3735 if (OpBits == DestBits) { 3736 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3737 // bits, it is already ready. 3738 if (NumSignBits > DestBits-MidBits) 3739 return Op; 3740 } else if (OpBits < DestBits) { 3741 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3742 // bits, just sext from i32. 3743 if (NumSignBits > OpBits-MidBits) 3744 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3745 } else { 3746 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3747 // bits, just truncate to i32. 3748 if (NumSignBits > OpBits-MidBits) 3749 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3750 } 3751 3752 // fold (sext (truncate x)) -> (sextinreg x). 3753 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3754 N0.getValueType())) { 3755 if (OpBits < DestBits) 3756 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3757 else if (OpBits > DestBits) 3758 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3759 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3760 DAG.getValueType(N0.getValueType())); 3761 } 3762 } 3763 3764 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3765 // None of the supported targets knows how to perform load and sign extend 3766 // on vectors in one instruction. We only perform this transformation on 3767 // scalars. 3768 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 3769 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3770 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3771 bool DoXform = true; 3772 SmallVector<SDNode*, 4> SetCCs; 3773 if (!N0.hasOneUse()) 3774 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3775 if (DoXform) { 3776 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3777 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3778 LN0->getChain(), 3779 LN0->getBasePtr(), LN0->getPointerInfo(), 3780 N0.getValueType(), 3781 LN0->isVolatile(), LN0->isNonTemporal(), 3782 LN0->getAlignment()); 3783 CombineTo(N, ExtLoad); 3784 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3785 N0.getValueType(), ExtLoad); 3786 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3787 3788 // Extend SetCC uses if necessary. 3789 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3790 SDNode *SetCC = SetCCs[i]; 3791 SmallVector<SDValue, 4> Ops; 3792 3793 for (unsigned j = 0; j != 2; ++j) { 3794 SDValue SOp = SetCC->getOperand(j); 3795 if (SOp == Trunc) 3796 Ops.push_back(ExtLoad); 3797 else 3798 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3799 N->getDebugLoc(), VT, SOp)); 3800 } 3801 3802 Ops.push_back(SetCC->getOperand(2)); 3803 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3804 SetCC->getValueType(0), 3805 &Ops[0], Ops.size())); 3806 } 3807 3808 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3809 } 3810 } 3811 3812 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3813 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3814 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3815 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3816 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3817 EVT MemVT = LN0->getMemoryVT(); 3818 if ((!LegalOperations && !LN0->isVolatile()) || 3819 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3820 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3821 LN0->getChain(), 3822 LN0->getBasePtr(), LN0->getPointerInfo(), 3823 MemVT, 3824 LN0->isVolatile(), LN0->isNonTemporal(), 3825 LN0->getAlignment()); 3826 CombineTo(N, ExtLoad); 3827 CombineTo(N0.getNode(), 3828 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3829 N0.getValueType(), ExtLoad), 3830 ExtLoad.getValue(1)); 3831 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3832 } 3833 } 3834 3835 if (N0.getOpcode() == ISD::SETCC) { 3836 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3837 // Only do this before legalize for now. 3838 if (VT.isVector() && !LegalOperations) { 3839 EVT N0VT = N0.getOperand(0).getValueType(); 3840 // We know that the # elements of the results is the same as the 3841 // # elements of the compare (and the # elements of the compare result 3842 // for that matter). Check to see that they are the same size. If so, 3843 // we know that the element size of the sext'd result matches the 3844 // element size of the compare operands. 3845 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3846 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3847 N0.getOperand(1), 3848 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3849 // If the desired elements are smaller or larger than the source 3850 // elements we can use a matching integer vector type and then 3851 // truncate/sign extend 3852 else { 3853 EVT MatchingElementType = 3854 EVT::getIntegerVT(*DAG.getContext(), 3855 N0VT.getScalarType().getSizeInBits()); 3856 EVT MatchingVectorType = 3857 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3858 N0VT.getVectorNumElements()); 3859 SDValue VsetCC = 3860 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3861 N0.getOperand(1), 3862 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3863 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3864 } 3865 } 3866 3867 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3868 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 3869 SDValue NegOne = 3870 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 3871 SDValue SCC = 3872 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3873 NegOne, DAG.getConstant(0, VT), 3874 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3875 if (SCC.getNode()) return SCC; 3876 if (!LegalOperations || 3877 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3878 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3879 DAG.getSetCC(N->getDebugLoc(), 3880 TLI.getSetCCResultType(VT), 3881 N0.getOperand(0), N0.getOperand(1), 3882 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3883 NegOne, DAG.getConstant(0, VT)); 3884 } 3885 3886 // fold (sext x) -> (zext x) if the sign bit is known zero. 3887 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3888 DAG.SignBitIsZero(N0)) 3889 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3890 3891 return SDValue(); 3892} 3893 3894SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3895 SDValue N0 = N->getOperand(0); 3896 EVT VT = N->getValueType(0); 3897 3898 // fold (zext c1) -> c1 3899 if (isa<ConstantSDNode>(N0)) 3900 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3901 // fold (zext (zext x)) -> (zext x) 3902 // fold (zext (aext x)) -> (zext x) 3903 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3904 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3905 N0.getOperand(0)); 3906 3907 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3908 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3909 if (N0.getOpcode() == ISD::TRUNCATE) { 3910 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3911 if (NarrowLoad.getNode()) { 3912 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3913 if (NarrowLoad.getNode() != N0.getNode()) { 3914 CombineTo(N0.getNode(), NarrowLoad); 3915 // CombineTo deleted the truncate, if needed, but not what's under it. 3916 AddToWorkList(oye); 3917 } 3918 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3919 } 3920 } 3921 3922 // fold (zext (truncate x)) -> (and x, mask) 3923 if (N0.getOpcode() == ISD::TRUNCATE && 3924 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3925 3926 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3927 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 3928 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3929 if (NarrowLoad.getNode()) { 3930 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3931 if (NarrowLoad.getNode() != N0.getNode()) { 3932 CombineTo(N0.getNode(), NarrowLoad); 3933 // CombineTo deleted the truncate, if needed, but not what's under it. 3934 AddToWorkList(oye); 3935 } 3936 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3937 } 3938 3939 SDValue Op = N0.getOperand(0); 3940 if (Op.getValueType().bitsLT(VT)) { 3941 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3942 } else if (Op.getValueType().bitsGT(VT)) { 3943 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3944 } 3945 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3946 N0.getValueType().getScalarType()); 3947 } 3948 3949 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3950 // if either of the casts is not free. 3951 if (N0.getOpcode() == ISD::AND && 3952 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3953 N0.getOperand(1).getOpcode() == ISD::Constant && 3954 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3955 N0.getValueType()) || 3956 !TLI.isZExtFree(N0.getValueType(), VT))) { 3957 SDValue X = N0.getOperand(0).getOperand(0); 3958 if (X.getValueType().bitsLT(VT)) { 3959 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3960 } else if (X.getValueType().bitsGT(VT)) { 3961 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3962 } 3963 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3964 Mask = Mask.zext(VT.getSizeInBits()); 3965 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3966 X, DAG.getConstant(Mask, VT)); 3967 } 3968 3969 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3970 // None of the supported targets knows how to perform load and vector_zext 3971 // on vectors in one instruction. We only perform this transformation on 3972 // scalars. 3973 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 3974 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3975 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3976 bool DoXform = true; 3977 SmallVector<SDNode*, 4> SetCCs; 3978 if (!N0.hasOneUse()) 3979 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3980 if (DoXform) { 3981 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3982 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3983 LN0->getChain(), 3984 LN0->getBasePtr(), LN0->getPointerInfo(), 3985 N0.getValueType(), 3986 LN0->isVolatile(), LN0->isNonTemporal(), 3987 LN0->getAlignment()); 3988 CombineTo(N, ExtLoad); 3989 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3990 N0.getValueType(), ExtLoad); 3991 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3992 3993 // Extend SetCC uses if necessary. 3994 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3995 SDNode *SetCC = SetCCs[i]; 3996 SmallVector<SDValue, 4> Ops; 3997 3998 for (unsigned j = 0; j != 2; ++j) { 3999 SDValue SOp = SetCC->getOperand(j); 4000 if (SOp == Trunc) 4001 Ops.push_back(ExtLoad); 4002 else 4003 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 4004 N->getDebugLoc(), VT, SOp)); 4005 } 4006 4007 Ops.push_back(SetCC->getOperand(2)); 4008 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 4009 SetCC->getValueType(0), 4010 &Ops[0], Ops.size())); 4011 } 4012 4013 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4014 } 4015 } 4016 4017 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4018 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4019 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4020 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4021 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4022 EVT MemVT = LN0->getMemoryVT(); 4023 if ((!LegalOperations && !LN0->isVolatile()) || 4024 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4025 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4026 LN0->getChain(), 4027 LN0->getBasePtr(), LN0->getPointerInfo(), 4028 MemVT, 4029 LN0->isVolatile(), LN0->isNonTemporal(), 4030 LN0->getAlignment()); 4031 CombineTo(N, ExtLoad); 4032 CombineTo(N0.getNode(), 4033 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4034 ExtLoad), 4035 ExtLoad.getValue(1)); 4036 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4037 } 4038 } 4039 4040 if (N0.getOpcode() == ISD::SETCC) { 4041 if (!LegalOperations && VT.isVector()) { 4042 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4043 // Only do this before legalize for now. 4044 EVT N0VT = N0.getOperand(0).getValueType(); 4045 EVT EltVT = VT.getVectorElementType(); 4046 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4047 DAG.getConstant(1, EltVT)); 4048 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4049 // We know that the # elements of the results is the same as the 4050 // # elements of the compare (and the # elements of the compare result 4051 // for that matter). Check to see that they are the same size. If so, 4052 // we know that the element size of the sext'd result matches the 4053 // element size of the compare operands. 4054 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4055 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4056 N0.getOperand(1), 4057 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4058 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4059 &OneOps[0], OneOps.size())); 4060 4061 // If the desired elements are smaller or larger than the source 4062 // elements we can use a matching integer vector type and then 4063 // truncate/sign extend 4064 EVT MatchingElementType = 4065 EVT::getIntegerVT(*DAG.getContext(), 4066 N0VT.getScalarType().getSizeInBits()); 4067 EVT MatchingVectorType = 4068 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4069 N0VT.getVectorNumElements()); 4070 SDValue VsetCC = 4071 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4072 N0.getOperand(1), 4073 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4074 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4075 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4076 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4077 &OneOps[0], OneOps.size())); 4078 } 4079 4080 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4081 SDValue SCC = 4082 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4083 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4084 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4085 if (SCC.getNode()) return SCC; 4086 } 4087 4088 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4089 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4090 isa<ConstantSDNode>(N0.getOperand(1)) && 4091 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4092 N0.hasOneUse()) { 4093 SDValue ShAmt = N0.getOperand(1); 4094 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4095 if (N0.getOpcode() == ISD::SHL) { 4096 SDValue InnerZExt = N0.getOperand(0); 4097 // If the original shl may be shifting out bits, do not perform this 4098 // transformation. 4099 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4100 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4101 if (ShAmtVal > KnownZeroBits) 4102 return SDValue(); 4103 } 4104 4105 DebugLoc DL = N->getDebugLoc(); 4106 4107 // Ensure that the shift amount is wide enough for the shifted value. 4108 if (VT.getSizeInBits() >= 256) 4109 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4110 4111 return DAG.getNode(N0.getOpcode(), DL, VT, 4112 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4113 ShAmt); 4114 } 4115 4116 return SDValue(); 4117} 4118 4119SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4120 SDValue N0 = N->getOperand(0); 4121 EVT VT = N->getValueType(0); 4122 4123 // fold (aext c1) -> c1 4124 if (isa<ConstantSDNode>(N0)) 4125 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4126 // fold (aext (aext x)) -> (aext x) 4127 // fold (aext (zext x)) -> (zext x) 4128 // fold (aext (sext x)) -> (sext x) 4129 if (N0.getOpcode() == ISD::ANY_EXTEND || 4130 N0.getOpcode() == ISD::ZERO_EXTEND || 4131 N0.getOpcode() == ISD::SIGN_EXTEND) 4132 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4133 4134 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4135 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4136 if (N0.getOpcode() == ISD::TRUNCATE) { 4137 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4138 if (NarrowLoad.getNode()) { 4139 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4140 if (NarrowLoad.getNode() != N0.getNode()) { 4141 CombineTo(N0.getNode(), NarrowLoad); 4142 // CombineTo deleted the truncate, if needed, but not what's under it. 4143 AddToWorkList(oye); 4144 } 4145 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4146 } 4147 } 4148 4149 // fold (aext (truncate x)) 4150 if (N0.getOpcode() == ISD::TRUNCATE) { 4151 SDValue TruncOp = N0.getOperand(0); 4152 if (TruncOp.getValueType() == VT) 4153 return TruncOp; // x iff x size == zext size. 4154 if (TruncOp.getValueType().bitsGT(VT)) 4155 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4156 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4157 } 4158 4159 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4160 // if the trunc is not free. 4161 if (N0.getOpcode() == ISD::AND && 4162 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4163 N0.getOperand(1).getOpcode() == ISD::Constant && 4164 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4165 N0.getValueType())) { 4166 SDValue X = N0.getOperand(0).getOperand(0); 4167 if (X.getValueType().bitsLT(VT)) { 4168 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4169 } else if (X.getValueType().bitsGT(VT)) { 4170 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4171 } 4172 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4173 Mask = Mask.zext(VT.getSizeInBits()); 4174 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4175 X, DAG.getConstant(Mask, VT)); 4176 } 4177 4178 // fold (aext (load x)) -> (aext (truncate (extload x))) 4179 // None of the supported targets knows how to perform load and any_ext 4180 // on vectors in one instruction. We only perform this transformation on 4181 // scalars. 4182 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4183 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4184 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4185 bool DoXform = true; 4186 SmallVector<SDNode*, 4> SetCCs; 4187 if (!N0.hasOneUse()) 4188 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4189 if (DoXform) { 4190 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4191 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4192 LN0->getChain(), 4193 LN0->getBasePtr(), LN0->getPointerInfo(), 4194 N0.getValueType(), 4195 LN0->isVolatile(), LN0->isNonTemporal(), 4196 LN0->getAlignment()); 4197 CombineTo(N, ExtLoad); 4198 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4199 N0.getValueType(), ExtLoad); 4200 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4201 4202 // Extend SetCC uses if necessary. 4203 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4204 SDNode *SetCC = SetCCs[i]; 4205 SmallVector<SDValue, 4> Ops; 4206 4207 for (unsigned j = 0; j != 2; ++j) { 4208 SDValue SOp = SetCC->getOperand(j); 4209 if (SOp == Trunc) 4210 Ops.push_back(ExtLoad); 4211 else 4212 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 4213 N->getDebugLoc(), VT, SOp)); 4214 } 4215 4216 Ops.push_back(SetCC->getOperand(2)); 4217 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 4218 SetCC->getValueType(0), 4219 &Ops[0], Ops.size())); 4220 } 4221 4222 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4223 } 4224 } 4225 4226 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4227 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4228 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4229 if (N0.getOpcode() == ISD::LOAD && 4230 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4231 N0.hasOneUse()) { 4232 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4233 EVT MemVT = LN0->getMemoryVT(); 4234 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4235 VT, LN0->getChain(), LN0->getBasePtr(), 4236 LN0->getPointerInfo(), MemVT, 4237 LN0->isVolatile(), LN0->isNonTemporal(), 4238 LN0->getAlignment()); 4239 CombineTo(N, ExtLoad); 4240 CombineTo(N0.getNode(), 4241 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4242 N0.getValueType(), ExtLoad), 4243 ExtLoad.getValue(1)); 4244 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4245 } 4246 4247 if (N0.getOpcode() == ISD::SETCC) { 4248 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4249 // Only do this before legalize for now. 4250 if (VT.isVector() && !LegalOperations) { 4251 EVT N0VT = N0.getOperand(0).getValueType(); 4252 // We know that the # elements of the results is the same as the 4253 // # elements of the compare (and the # elements of the compare result 4254 // for that matter). Check to see that they are the same size. If so, 4255 // we know that the element size of the sext'd result matches the 4256 // element size of the compare operands. 4257 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4258 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4259 N0.getOperand(1), 4260 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4261 // If the desired elements are smaller or larger than the source 4262 // elements we can use a matching integer vector type and then 4263 // truncate/sign extend 4264 else { 4265 EVT MatchingElementType = 4266 EVT::getIntegerVT(*DAG.getContext(), 4267 N0VT.getScalarType().getSizeInBits()); 4268 EVT MatchingVectorType = 4269 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4270 N0VT.getVectorNumElements()); 4271 SDValue VsetCC = 4272 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4273 N0.getOperand(1), 4274 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4275 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4276 } 4277 } 4278 4279 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4280 SDValue SCC = 4281 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4282 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4283 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4284 if (SCC.getNode()) 4285 return SCC; 4286 } 4287 4288 return SDValue(); 4289} 4290 4291/// GetDemandedBits - See if the specified operand can be simplified with the 4292/// knowledge that only the bits specified by Mask are used. If so, return the 4293/// simpler operand, otherwise return a null SDValue. 4294SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4295 switch (V.getOpcode()) { 4296 default: break; 4297 case ISD::OR: 4298 case ISD::XOR: 4299 // If the LHS or RHS don't contribute bits to the or, drop them. 4300 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4301 return V.getOperand(1); 4302 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4303 return V.getOperand(0); 4304 break; 4305 case ISD::SRL: 4306 // Only look at single-use SRLs. 4307 if (!V.getNode()->hasOneUse()) 4308 break; 4309 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4310 // See if we can recursively simplify the LHS. 4311 unsigned Amt = RHSC->getZExtValue(); 4312 4313 // Watch out for shift count overflow though. 4314 if (Amt >= Mask.getBitWidth()) break; 4315 APInt NewMask = Mask << Amt; 4316 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4317 if (SimplifyLHS.getNode()) 4318 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4319 SimplifyLHS, V.getOperand(1)); 4320 } 4321 } 4322 return SDValue(); 4323} 4324 4325/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4326/// bits and then truncated to a narrower type and where N is a multiple 4327/// of number of bits of the narrower type, transform it to a narrower load 4328/// from address + N / num of bits of new type. If the result is to be 4329/// extended, also fold the extension to form a extending load. 4330SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4331 unsigned Opc = N->getOpcode(); 4332 4333 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4334 SDValue N0 = N->getOperand(0); 4335 EVT VT = N->getValueType(0); 4336 EVT ExtVT = VT; 4337 4338 // This transformation isn't valid for vector loads. 4339 if (VT.isVector()) 4340 return SDValue(); 4341 4342 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4343 // extended to VT. 4344 if (Opc == ISD::SIGN_EXTEND_INREG) { 4345 ExtType = ISD::SEXTLOAD; 4346 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4347 } else if (Opc == ISD::SRL) { 4348 // Another special-case: SRL is basically zero-extending a narrower value. 4349 ExtType = ISD::ZEXTLOAD; 4350 N0 = SDValue(N, 0); 4351 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4352 if (!N01) return SDValue(); 4353 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4354 VT.getSizeInBits() - N01->getZExtValue()); 4355 } 4356 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4357 return SDValue(); 4358 4359 unsigned EVTBits = ExtVT.getSizeInBits(); 4360 4361 // Do not generate loads of non-round integer types since these can 4362 // be expensive (and would be wrong if the type is not byte sized). 4363 if (!ExtVT.isRound()) 4364 return SDValue(); 4365 4366 unsigned ShAmt = 0; 4367 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4368 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4369 ShAmt = N01->getZExtValue(); 4370 // Is the shift amount a multiple of size of VT? 4371 if ((ShAmt & (EVTBits-1)) == 0) { 4372 N0 = N0.getOperand(0); 4373 // Is the load width a multiple of size of VT? 4374 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4375 return SDValue(); 4376 } 4377 4378 // At this point, we must have a load or else we can't do the transform. 4379 if (!isa<LoadSDNode>(N0)) return SDValue(); 4380 4381 // If the shift amount is larger than the input type then we're not 4382 // accessing any of the loaded bytes. If the load was a zextload/extload 4383 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4384 // If the load was a sextload then the result is a splat of the sign bit 4385 // of the extended byte. This is not worth optimizing for. 4386 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4387 return SDValue(); 4388 } 4389 } 4390 4391 // If the load is shifted left (and the result isn't shifted back right), 4392 // we can fold the truncate through the shift. 4393 unsigned ShLeftAmt = 0; 4394 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4395 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4396 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4397 ShLeftAmt = N01->getZExtValue(); 4398 N0 = N0.getOperand(0); 4399 } 4400 } 4401 4402 // If we haven't found a load, we can't narrow it. Don't transform one with 4403 // multiple uses, this would require adding a new load. 4404 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 4405 // Don't change the width of a volatile load. 4406 cast<LoadSDNode>(N0)->isVolatile()) 4407 return SDValue(); 4408 4409 // Verify that we are actually reducing a load width here. 4410 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 4411 return SDValue(); 4412 4413 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4414 EVT PtrType = N0.getOperand(1).getValueType(); 4415 4416 // For big endian targets, we need to adjust the offset to the pointer to 4417 // load the correct bytes. 4418 if (TLI.isBigEndian()) { 4419 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4420 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4421 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4422 } 4423 4424 uint64_t PtrOff = ShAmt / 8; 4425 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4426 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4427 PtrType, LN0->getBasePtr(), 4428 DAG.getConstant(PtrOff, PtrType)); 4429 AddToWorkList(NewPtr.getNode()); 4430 4431 SDValue Load; 4432 if (ExtType == ISD::NON_EXTLOAD) 4433 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4434 LN0->getPointerInfo().getWithOffset(PtrOff), 4435 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign); 4436 else 4437 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 4438 LN0->getPointerInfo().getWithOffset(PtrOff), 4439 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4440 NewAlign); 4441 4442 // Replace the old load's chain with the new load's chain. 4443 WorkListRemover DeadNodes(*this); 4444 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4445 &DeadNodes); 4446 4447 // Shift the result left, if we've swallowed a left shift. 4448 SDValue Result = Load; 4449 if (ShLeftAmt != 0) { 4450 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 4451 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 4452 ShImmTy = VT; 4453 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 4454 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 4455 } 4456 4457 // Return the new loaded value. 4458 return Result; 4459} 4460 4461SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4462 SDValue N0 = N->getOperand(0); 4463 SDValue N1 = N->getOperand(1); 4464 EVT VT = N->getValueType(0); 4465 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4466 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4467 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4468 4469 // fold (sext_in_reg c1) -> c1 4470 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4471 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4472 4473 // If the input is already sign extended, just drop the extension. 4474 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4475 return N0; 4476 4477 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4478 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4479 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4480 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4481 N0.getOperand(0), N1); 4482 } 4483 4484 // fold (sext_in_reg (sext x)) -> (sext x) 4485 // fold (sext_in_reg (aext x)) -> (sext x) 4486 // if x is small enough. 4487 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4488 SDValue N00 = N0.getOperand(0); 4489 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4490 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4491 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4492 } 4493 4494 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4495 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4496 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4497 4498 // fold operands of sext_in_reg based on knowledge that the top bits are not 4499 // demanded. 4500 if (SimplifyDemandedBits(SDValue(N, 0))) 4501 return SDValue(N, 0); 4502 4503 // fold (sext_in_reg (load x)) -> (smaller sextload x) 4504 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4505 SDValue NarrowLoad = ReduceLoadWidth(N); 4506 if (NarrowLoad.getNode()) 4507 return NarrowLoad; 4508 4509 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4510 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4511 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4512 if (N0.getOpcode() == ISD::SRL) { 4513 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4514 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4515 // We can turn this into an SRA iff the input to the SRL is already sign 4516 // extended enough. 4517 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4518 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4519 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4520 N0.getOperand(0), N0.getOperand(1)); 4521 } 4522 } 4523 4524 // fold (sext_inreg (extload x)) -> (sextload x) 4525 if (ISD::isEXTLoad(N0.getNode()) && 4526 ISD::isUNINDEXEDLoad(N0.getNode()) && 4527 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4528 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4529 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4530 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4531 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4532 LN0->getChain(), 4533 LN0->getBasePtr(), LN0->getPointerInfo(), 4534 EVT, 4535 LN0->isVolatile(), LN0->isNonTemporal(), 4536 LN0->getAlignment()); 4537 CombineTo(N, ExtLoad); 4538 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4539 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4540 } 4541 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4542 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4543 N0.hasOneUse() && 4544 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4545 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4546 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4547 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4548 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4549 LN0->getChain(), 4550 LN0->getBasePtr(), LN0->getPointerInfo(), 4551 EVT, 4552 LN0->isVolatile(), LN0->isNonTemporal(), 4553 LN0->getAlignment()); 4554 CombineTo(N, ExtLoad); 4555 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4556 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4557 } 4558 return SDValue(); 4559} 4560 4561SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4562 SDValue N0 = N->getOperand(0); 4563 EVT VT = N->getValueType(0); 4564 4565 // noop truncate 4566 if (N0.getValueType() == N->getValueType(0)) 4567 return N0; 4568 // fold (truncate c1) -> c1 4569 if (isa<ConstantSDNode>(N0)) 4570 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4571 // fold (truncate (truncate x)) -> (truncate x) 4572 if (N0.getOpcode() == ISD::TRUNCATE) 4573 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4574 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4575 if (N0.getOpcode() == ISD::ZERO_EXTEND || 4576 N0.getOpcode() == ISD::SIGN_EXTEND || 4577 N0.getOpcode() == ISD::ANY_EXTEND) { 4578 if (N0.getOperand(0).getValueType().bitsLT(VT)) 4579 // if the source is smaller than the dest, we still need an extend 4580 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4581 N0.getOperand(0)); 4582 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4583 // if the source is larger than the dest, than we just need the truncate 4584 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4585 else 4586 // if the source and dest are the same type, we can drop both the extend 4587 // and the truncate. 4588 return N0.getOperand(0); 4589 } 4590 4591 // See if we can simplify the input to this truncate through knowledge that 4592 // only the low bits are being used. 4593 // For example "trunc (or (shl x, 8), y)" // -> trunc y 4594 // Currently we only perform this optimization on scalars because vectors 4595 // may have different active low bits. 4596 if (!VT.isVector()) { 4597 SDValue Shorter = 4598 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4599 VT.getSizeInBits())); 4600 if (Shorter.getNode()) 4601 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4602 } 4603 // fold (truncate (load x)) -> (smaller load x) 4604 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4605 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 4606 SDValue Reduced = ReduceLoadWidth(N); 4607 if (Reduced.getNode()) 4608 return Reduced; 4609 } 4610 4611 // Simplify the operands using demanded-bits information. 4612 if (!VT.isVector() && 4613 SimplifyDemandedBits(SDValue(N, 0))) 4614 return SDValue(N, 0); 4615 4616 return SDValue(); 4617} 4618 4619static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4620 SDValue Elt = N->getOperand(i); 4621 if (Elt.getOpcode() != ISD::MERGE_VALUES) 4622 return Elt.getNode(); 4623 return Elt.getOperand(Elt.getResNo()).getNode(); 4624} 4625 4626/// CombineConsecutiveLoads - build_pair (load, load) -> load 4627/// if load locations are consecutive. 4628SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 4629 assert(N->getOpcode() == ISD::BUILD_PAIR); 4630 4631 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 4632 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 4633 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 4634 LD1->getPointerInfo().getAddrSpace() != 4635 LD2->getPointerInfo().getAddrSpace()) 4636 return SDValue(); 4637 EVT LD1VT = LD1->getValueType(0); 4638 4639 if (ISD::isNON_EXTLoad(LD2) && 4640 LD2->hasOneUse() && 4641 // If both are volatile this would reduce the number of volatile loads. 4642 // If one is volatile it might be ok, but play conservative and bail out. 4643 !LD1->isVolatile() && 4644 !LD2->isVolatile() && 4645 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 4646 unsigned Align = LD1->getAlignment(); 4647 unsigned NewAlign = TLI.getTargetData()-> 4648 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4649 4650 if (NewAlign <= Align && 4651 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 4652 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 4653 LD1->getBasePtr(), LD1->getPointerInfo(), 4654 false, false, Align); 4655 } 4656 4657 return SDValue(); 4658} 4659 4660SDValue DAGCombiner::visitBITCAST(SDNode *N) { 4661 SDValue N0 = N->getOperand(0); 4662 EVT VT = N->getValueType(0); 4663 4664 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 4665 // Only do this before legalize, since afterward the target may be depending 4666 // on the bitconvert. 4667 // First check to see if this is all constant. 4668 if (!LegalTypes && 4669 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 4670 VT.isVector()) { 4671 bool isSimple = true; 4672 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 4673 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 4674 N0.getOperand(i).getOpcode() != ISD::Constant && 4675 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 4676 isSimple = false; 4677 break; 4678 } 4679 4680 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 4681 assert(!DestEltVT.isVector() && 4682 "Element type of vector ValueType must not be vector!"); 4683 if (isSimple) 4684 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 4685 } 4686 4687 // If the input is a constant, let getNode fold it. 4688 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 4689 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 4690 if (Res.getNode() != N) { 4691 if (!LegalOperations || 4692 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 4693 return Res; 4694 4695 // Folding it resulted in an illegal node, and it's too late to 4696 // do that. Clean up the old node and forego the transformation. 4697 // Ideally this won't happen very often, because instcombine 4698 // and the earlier dagcombine runs (where illegal nodes are 4699 // permitted) should have folded most of them already. 4700 DAG.DeleteNode(Res.getNode()); 4701 } 4702 } 4703 4704 // (conv (conv x, t1), t2) -> (conv x, t2) 4705 if (N0.getOpcode() == ISD::BITCAST) 4706 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 4707 N0.getOperand(0)); 4708 4709 // fold (conv (load x)) -> (load (conv*)x) 4710 // If the resultant load doesn't need a higher alignment than the original! 4711 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 4712 // Do not change the width of a volatile load. 4713 !cast<LoadSDNode>(N0)->isVolatile() && 4714 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 4715 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4716 unsigned Align = TLI.getTargetData()-> 4717 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4718 unsigned OrigAlign = LN0->getAlignment(); 4719 4720 if (Align <= OrigAlign) { 4721 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 4722 LN0->getBasePtr(), LN0->getPointerInfo(), 4723 LN0->isVolatile(), LN0->isNonTemporal(), 4724 OrigAlign); 4725 AddToWorkList(N); 4726 CombineTo(N0.getNode(), 4727 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4728 N0.getValueType(), Load), 4729 Load.getValue(1)); 4730 return Load; 4731 } 4732 } 4733 4734 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 4735 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 4736 // This often reduces constant pool loads. 4737 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 4738 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 4739 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 4740 N0.getOperand(0)); 4741 AddToWorkList(NewConv.getNode()); 4742 4743 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4744 if (N0.getOpcode() == ISD::FNEG) 4745 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 4746 NewConv, DAG.getConstant(SignBit, VT)); 4747 assert(N0.getOpcode() == ISD::FABS); 4748 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4749 NewConv, DAG.getConstant(~SignBit, VT)); 4750 } 4751 4752 // fold (bitconvert (fcopysign cst, x)) -> 4753 // (or (and (bitconvert x), sign), (and cst, (not sign))) 4754 // Note that we don't handle (copysign x, cst) because this can always be 4755 // folded to an fneg or fabs. 4756 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 4757 isa<ConstantFPSDNode>(N0.getOperand(0)) && 4758 VT.isInteger() && !VT.isVector()) { 4759 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 4760 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 4761 if (isTypeLegal(IntXVT)) { 4762 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4763 IntXVT, N0.getOperand(1)); 4764 AddToWorkList(X.getNode()); 4765 4766 // If X has a different width than the result/lhs, sext it or truncate it. 4767 unsigned VTWidth = VT.getSizeInBits(); 4768 if (OrigXWidth < VTWidth) { 4769 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 4770 AddToWorkList(X.getNode()); 4771 } else if (OrigXWidth > VTWidth) { 4772 // To get the sign bit in the right place, we have to shift it right 4773 // before truncating. 4774 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 4775 X.getValueType(), X, 4776 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 4777 AddToWorkList(X.getNode()); 4778 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4779 AddToWorkList(X.getNode()); 4780 } 4781 4782 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4783 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 4784 X, DAG.getConstant(SignBit, VT)); 4785 AddToWorkList(X.getNode()); 4786 4787 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4788 VT, N0.getOperand(0)); 4789 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 4790 Cst, DAG.getConstant(~SignBit, VT)); 4791 AddToWorkList(Cst.getNode()); 4792 4793 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 4794 } 4795 } 4796 4797 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 4798 if (N0.getOpcode() == ISD::BUILD_PAIR) { 4799 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 4800 if (CombineLD.getNode()) 4801 return CombineLD; 4802 } 4803 4804 return SDValue(); 4805} 4806 4807SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4808 EVT VT = N->getValueType(0); 4809 return CombineConsecutiveLoads(N, VT); 4810} 4811 4812/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 4813/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4814/// destination element value type. 4815SDValue DAGCombiner:: 4816ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4817 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4818 4819 // If this is already the right type, we're done. 4820 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4821 4822 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4823 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4824 4825 // If this is a conversion of N elements of one type to N elements of another 4826 // type, convert each element. This handles FP<->INT cases. 4827 if (SrcBitSize == DstBitSize) { 4828 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4829 BV->getValueType(0).getVectorNumElements()); 4830 4831 // Due to the FP element handling below calling this routine recursively, 4832 // we can end up with a scalar-to-vector node here. 4833 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 4834 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4835 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4836 DstEltVT, BV->getOperand(0))); 4837 4838 SmallVector<SDValue, 8> Ops; 4839 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4840 SDValue Op = BV->getOperand(i); 4841 // If the vector element type is not legal, the BUILD_VECTOR operands 4842 // are promoted and implicitly truncated. Make that explicit here. 4843 if (Op.getValueType() != SrcEltVT) 4844 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4845 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4846 DstEltVT, Op)); 4847 AddToWorkList(Ops.back().getNode()); 4848 } 4849 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4850 &Ops[0], Ops.size()); 4851 } 4852 4853 // Otherwise, we're growing or shrinking the elements. To avoid having to 4854 // handle annoying details of growing/shrinking FP values, we convert them to 4855 // int first. 4856 if (SrcEltVT.isFloatingPoint()) { 4857 // Convert the input float vector to a int vector where the elements are the 4858 // same sizes. 4859 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4860 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4861 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 4862 SrcEltVT = IntVT; 4863 } 4864 4865 // Now we know the input is an integer vector. If the output is a FP type, 4866 // convert to integer first, then to FP of the right size. 4867 if (DstEltVT.isFloatingPoint()) { 4868 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4869 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4870 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 4871 4872 // Next, convert to FP elements of the same size. 4873 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 4874 } 4875 4876 // Okay, we know the src/dst types are both integers of differing types. 4877 // Handling growing first. 4878 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4879 if (SrcBitSize < DstBitSize) { 4880 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4881 4882 SmallVector<SDValue, 8> Ops; 4883 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4884 i += NumInputsPerOutput) { 4885 bool isLE = TLI.isLittleEndian(); 4886 APInt NewBits = APInt(DstBitSize, 0); 4887 bool EltIsUndef = true; 4888 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4889 // Shift the previously computed bits over. 4890 NewBits <<= SrcBitSize; 4891 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4892 if (Op.getOpcode() == ISD::UNDEF) continue; 4893 EltIsUndef = false; 4894 4895 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 4896 zextOrTrunc(SrcBitSize).zext(DstBitSize); 4897 } 4898 4899 if (EltIsUndef) 4900 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4901 else 4902 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4903 } 4904 4905 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4906 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4907 &Ops[0], Ops.size()); 4908 } 4909 4910 // Finally, this must be the case where we are shrinking elements: each input 4911 // turns into multiple outputs. 4912 bool isS2V = ISD::isScalarToVector(BV); 4913 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4914 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4915 NumOutputsPerInput*BV->getNumOperands()); 4916 SmallVector<SDValue, 8> Ops; 4917 4918 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4919 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4920 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4921 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4922 continue; 4923 } 4924 4925 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 4926 getAPIntValue().zextOrTrunc(SrcBitSize); 4927 4928 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4929 APInt ThisVal = OpVal.trunc(DstBitSize); 4930 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4931 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 4932 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4933 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4934 Ops[0]); 4935 OpVal = OpVal.lshr(DstBitSize); 4936 } 4937 4938 // For big endian targets, swap the order of the pieces of each element. 4939 if (TLI.isBigEndian()) 4940 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4941 } 4942 4943 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4944 &Ops[0], Ops.size()); 4945} 4946 4947SDValue DAGCombiner::visitFADD(SDNode *N) { 4948 SDValue N0 = N->getOperand(0); 4949 SDValue N1 = N->getOperand(1); 4950 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4951 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4952 EVT VT = N->getValueType(0); 4953 4954 // fold vector ops 4955 if (VT.isVector()) { 4956 SDValue FoldedVOp = SimplifyVBinOp(N); 4957 if (FoldedVOp.getNode()) return FoldedVOp; 4958 } 4959 4960 // fold (fadd c1, c2) -> (fadd c1, c2) 4961 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4962 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4963 // canonicalize constant to RHS 4964 if (N0CFP && !N1CFP) 4965 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4966 // fold (fadd A, 0) -> A 4967 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4968 return N0; 4969 // fold (fadd A, (fneg B)) -> (fsub A, B) 4970 if (isNegatibleForFree(N1, LegalOperations) == 2) 4971 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4972 GetNegatedExpression(N1, DAG, LegalOperations)); 4973 // fold (fadd (fneg A), B) -> (fsub B, A) 4974 if (isNegatibleForFree(N0, LegalOperations) == 2) 4975 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4976 GetNegatedExpression(N0, DAG, LegalOperations)); 4977 4978 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4979 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4980 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4981 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4982 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4983 N0.getOperand(1), N1)); 4984 4985 return SDValue(); 4986} 4987 4988SDValue DAGCombiner::visitFSUB(SDNode *N) { 4989 SDValue N0 = N->getOperand(0); 4990 SDValue N1 = N->getOperand(1); 4991 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4992 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4993 EVT VT = N->getValueType(0); 4994 4995 // fold vector ops 4996 if (VT.isVector()) { 4997 SDValue FoldedVOp = SimplifyVBinOp(N); 4998 if (FoldedVOp.getNode()) return FoldedVOp; 4999 } 5000 5001 // fold (fsub c1, c2) -> c1-c2 5002 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5003 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5004 // fold (fsub A, 0) -> A 5005 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 5006 return N0; 5007 // fold (fsub 0, B) -> -B 5008 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 5009 if (isNegatibleForFree(N1, LegalOperations)) 5010 return GetNegatedExpression(N1, DAG, LegalOperations); 5011 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5012 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 5013 } 5014 // fold (fsub A, (fneg B)) -> (fadd A, B) 5015 if (isNegatibleForFree(N1, LegalOperations)) 5016 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 5017 GetNegatedExpression(N1, DAG, LegalOperations)); 5018 5019 return SDValue(); 5020} 5021 5022SDValue DAGCombiner::visitFMUL(SDNode *N) { 5023 SDValue N0 = N->getOperand(0); 5024 SDValue N1 = N->getOperand(1); 5025 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5026 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5027 EVT VT = N->getValueType(0); 5028 5029 // fold vector ops 5030 if (VT.isVector()) { 5031 SDValue FoldedVOp = SimplifyVBinOp(N); 5032 if (FoldedVOp.getNode()) return FoldedVOp; 5033 } 5034 5035 // fold (fmul c1, c2) -> c1*c2 5036 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5037 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5038 // canonicalize constant to RHS 5039 if (N0CFP && !N1CFP) 5040 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5041 // fold (fmul A, 0) -> 0 5042 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 5043 return N1; 5044 // fold (fmul A, 0) -> 0, vector edition. 5045 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 5046 return N1; 5047 // fold (fmul X, 2.0) -> (fadd X, X) 5048 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5049 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5050 // fold (fmul X, -1.0) -> (fneg X) 5051 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5052 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5053 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5054 5055 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5056 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 5057 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 5058 // Both can be negated for free, check to see if at least one is cheaper 5059 // negated. 5060 if (LHSNeg == 2 || RHSNeg == 2) 5061 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5062 GetNegatedExpression(N0, DAG, LegalOperations), 5063 GetNegatedExpression(N1, DAG, LegalOperations)); 5064 } 5065 } 5066 5067 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5068 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 5069 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5070 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5071 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5072 N0.getOperand(1), N1)); 5073 5074 return SDValue(); 5075} 5076 5077SDValue DAGCombiner::visitFDIV(SDNode *N) { 5078 SDValue N0 = N->getOperand(0); 5079 SDValue N1 = N->getOperand(1); 5080 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5081 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5082 EVT VT = N->getValueType(0); 5083 5084 // fold vector ops 5085 if (VT.isVector()) { 5086 SDValue FoldedVOp = SimplifyVBinOp(N); 5087 if (FoldedVOp.getNode()) return FoldedVOp; 5088 } 5089 5090 // fold (fdiv c1, c2) -> c1/c2 5091 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5092 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5093 5094 5095 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5096 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 5097 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 5098 // Both can be negated for free, check to see if at least one is cheaper 5099 // negated. 5100 if (LHSNeg == 2 || RHSNeg == 2) 5101 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5102 GetNegatedExpression(N0, DAG, LegalOperations), 5103 GetNegatedExpression(N1, DAG, LegalOperations)); 5104 } 5105 } 5106 5107 return SDValue(); 5108} 5109 5110SDValue DAGCombiner::visitFREM(SDNode *N) { 5111 SDValue N0 = N->getOperand(0); 5112 SDValue N1 = N->getOperand(1); 5113 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5114 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5115 EVT VT = N->getValueType(0); 5116 5117 // fold (frem c1, c2) -> fmod(c1,c2) 5118 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5119 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5120 5121 return SDValue(); 5122} 5123 5124SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5125 SDValue N0 = N->getOperand(0); 5126 SDValue N1 = N->getOperand(1); 5127 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5128 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5129 EVT VT = N->getValueType(0); 5130 5131 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5132 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5133 5134 if (N1CFP) { 5135 const APFloat& V = N1CFP->getValueAPF(); 5136 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5137 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5138 if (!V.isNegative()) { 5139 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5140 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5141 } else { 5142 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5143 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5144 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5145 } 5146 } 5147 5148 // copysign(fabs(x), y) -> copysign(x, y) 5149 // copysign(fneg(x), y) -> copysign(x, y) 5150 // copysign(copysign(x,z), y) -> copysign(x, y) 5151 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5152 N0.getOpcode() == ISD::FCOPYSIGN) 5153 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5154 N0.getOperand(0), N1); 5155 5156 // copysign(x, abs(y)) -> abs(x) 5157 if (N1.getOpcode() == ISD::FABS) 5158 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5159 5160 // copysign(x, copysign(y,z)) -> copysign(x, z) 5161 if (N1.getOpcode() == ISD::FCOPYSIGN) 5162 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5163 N0, N1.getOperand(1)); 5164 5165 // copysign(x, fp_extend(y)) -> copysign(x, y) 5166 // copysign(x, fp_round(y)) -> copysign(x, y) 5167 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5168 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5169 N0, N1.getOperand(0)); 5170 5171 return SDValue(); 5172} 5173 5174SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5175 SDValue N0 = N->getOperand(0); 5176 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5177 EVT VT = N->getValueType(0); 5178 EVT OpVT = N0.getValueType(); 5179 5180 // fold (sint_to_fp c1) -> c1fp 5181 if (N0C && OpVT != MVT::ppcf128 && 5182 // ...but only if the target supports immediate floating-point values 5183 (Level == llvm::Unrestricted || TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5184 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5185 5186 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5187 // but UINT_TO_FP is legal on this target, try to convert. 5188 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5189 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5190 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5191 if (DAG.SignBitIsZero(N0)) 5192 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5193 } 5194 5195 return SDValue(); 5196} 5197 5198SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5199 SDValue N0 = N->getOperand(0); 5200 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5201 EVT VT = N->getValueType(0); 5202 EVT OpVT = N0.getValueType(); 5203 5204 // fold (uint_to_fp c1) -> c1fp 5205 if (N0C && OpVT != MVT::ppcf128 && 5206 // ...but only if the target supports immediate floating-point values 5207 (Level == llvm::Unrestricted || TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5208 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5209 5210 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5211 // but SINT_TO_FP is legal on this target, try to convert. 5212 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5213 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5214 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5215 if (DAG.SignBitIsZero(N0)) 5216 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5217 } 5218 5219 return SDValue(); 5220} 5221 5222SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5223 SDValue N0 = N->getOperand(0); 5224 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5225 EVT VT = N->getValueType(0); 5226 5227 // fold (fp_to_sint c1fp) -> c1 5228 if (N0CFP) 5229 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5230 5231 return SDValue(); 5232} 5233 5234SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5235 SDValue N0 = N->getOperand(0); 5236 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5237 EVT VT = N->getValueType(0); 5238 5239 // fold (fp_to_uint c1fp) -> c1 5240 if (N0CFP && VT != MVT::ppcf128) 5241 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5242 5243 return SDValue(); 5244} 5245 5246SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5247 SDValue N0 = N->getOperand(0); 5248 SDValue N1 = N->getOperand(1); 5249 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5250 EVT VT = N->getValueType(0); 5251 5252 // fold (fp_round c1fp) -> c1fp 5253 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5254 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5255 5256 // fold (fp_round (fp_extend x)) -> x 5257 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5258 return N0.getOperand(0); 5259 5260 // fold (fp_round (fp_round x)) -> (fp_round x) 5261 if (N0.getOpcode() == ISD::FP_ROUND) { 5262 // This is a value preserving truncation if both round's are. 5263 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5264 N0.getNode()->getConstantOperandVal(1) == 1; 5265 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5266 DAG.getIntPtrConstant(IsTrunc)); 5267 } 5268 5269 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5270 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5271 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5272 N0.getOperand(0), N1); 5273 AddToWorkList(Tmp.getNode()); 5274 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5275 Tmp, N0.getOperand(1)); 5276 } 5277 5278 return SDValue(); 5279} 5280 5281SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5282 SDValue N0 = N->getOperand(0); 5283 EVT VT = N->getValueType(0); 5284 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5285 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5286 5287 // fold (fp_round_inreg c1fp) -> c1fp 5288 if (N0CFP && isTypeLegal(EVT)) { 5289 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5290 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5291 } 5292 5293 return SDValue(); 5294} 5295 5296SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5297 SDValue N0 = N->getOperand(0); 5298 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5299 EVT VT = N->getValueType(0); 5300 5301 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5302 if (N->hasOneUse() && 5303 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5304 return SDValue(); 5305 5306 // fold (fp_extend c1fp) -> c1fp 5307 if (N0CFP && VT != MVT::ppcf128) 5308 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5309 5310 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5311 // value of X. 5312 if (N0.getOpcode() == ISD::FP_ROUND 5313 && N0.getNode()->getConstantOperandVal(1) == 1) { 5314 SDValue In = N0.getOperand(0); 5315 if (In.getValueType() == VT) return In; 5316 if (VT.bitsLT(In.getValueType())) 5317 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5318 In, N0.getOperand(1)); 5319 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5320 } 5321 5322 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5323 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5324 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5325 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5326 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5327 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 5328 LN0->getChain(), 5329 LN0->getBasePtr(), LN0->getPointerInfo(), 5330 N0.getValueType(), 5331 LN0->isVolatile(), LN0->isNonTemporal(), 5332 LN0->getAlignment()); 5333 CombineTo(N, ExtLoad); 5334 CombineTo(N0.getNode(), 5335 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5336 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5337 ExtLoad.getValue(1)); 5338 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5339 } 5340 5341 return SDValue(); 5342} 5343 5344SDValue DAGCombiner::visitFNEG(SDNode *N) { 5345 SDValue N0 = N->getOperand(0); 5346 EVT VT = N->getValueType(0); 5347 5348 if (isNegatibleForFree(N0, LegalOperations)) 5349 return GetNegatedExpression(N0, DAG, LegalOperations); 5350 5351 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5352 // constant pool values. 5353 if (N0.getOpcode() == ISD::BITCAST && 5354 !VT.isVector() && 5355 N0.getNode()->hasOneUse() && 5356 N0.getOperand(0).getValueType().isInteger()) { 5357 SDValue Int = N0.getOperand(0); 5358 EVT IntVT = Int.getValueType(); 5359 if (IntVT.isInteger() && !IntVT.isVector()) { 5360 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5361 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5362 AddToWorkList(Int.getNode()); 5363 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5364 VT, Int); 5365 } 5366 } 5367 5368 return SDValue(); 5369} 5370 5371SDValue DAGCombiner::visitFABS(SDNode *N) { 5372 SDValue N0 = N->getOperand(0); 5373 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5374 EVT VT = N->getValueType(0); 5375 5376 // fold (fabs c1) -> fabs(c1) 5377 if (N0CFP && VT != MVT::ppcf128) 5378 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5379 // fold (fabs (fabs x)) -> (fabs x) 5380 if (N0.getOpcode() == ISD::FABS) 5381 return N->getOperand(0); 5382 // fold (fabs (fneg x)) -> (fabs x) 5383 // fold (fabs (fcopysign x, y)) -> (fabs x) 5384 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5385 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5386 5387 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5388 // constant pool values. 5389 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 5390 N0.getOperand(0).getValueType().isInteger() && 5391 !N0.getOperand(0).getValueType().isVector()) { 5392 SDValue Int = N0.getOperand(0); 5393 EVT IntVT = Int.getValueType(); 5394 if (IntVT.isInteger() && !IntVT.isVector()) { 5395 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5396 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5397 AddToWorkList(Int.getNode()); 5398 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5399 N->getValueType(0), Int); 5400 } 5401 } 5402 5403 return SDValue(); 5404} 5405 5406SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5407 SDValue Chain = N->getOperand(0); 5408 SDValue N1 = N->getOperand(1); 5409 SDValue N2 = N->getOperand(2); 5410 5411 // If N is a constant we could fold this into a fallthrough or unconditional 5412 // branch. However that doesn't happen very often in normal code, because 5413 // Instcombine/SimplifyCFG should have handled the available opportunities. 5414 // If we did this folding here, it would be necessary to update the 5415 // MachineBasicBlock CFG, which is awkward. 5416 5417 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5418 // on the target. 5419 if (N1.getOpcode() == ISD::SETCC && 5420 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5421 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5422 Chain, N1.getOperand(2), 5423 N1.getOperand(0), N1.getOperand(1), N2); 5424 } 5425 5426 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 5427 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 5428 (N1.getOperand(0).hasOneUse() && 5429 N1.getOperand(0).getOpcode() == ISD::SRL))) { 5430 SDNode *Trunc = 0; 5431 if (N1.getOpcode() == ISD::TRUNCATE) { 5432 // Look pass the truncate. 5433 Trunc = N1.getNode(); 5434 N1 = N1.getOperand(0); 5435 } 5436 5437 // Match this pattern so that we can generate simpler code: 5438 // 5439 // %a = ... 5440 // %b = and i32 %a, 2 5441 // %c = srl i32 %b, 1 5442 // brcond i32 %c ... 5443 // 5444 // into 5445 // 5446 // %a = ... 5447 // %b = and i32 %a, 2 5448 // %c = setcc eq %b, 0 5449 // brcond %c ... 5450 // 5451 // This applies only when the AND constant value has one bit set and the 5452 // SRL constant is equal to the log2 of the AND constant. The back-end is 5453 // smart enough to convert the result into a TEST/JMP sequence. 5454 SDValue Op0 = N1.getOperand(0); 5455 SDValue Op1 = N1.getOperand(1); 5456 5457 if (Op0.getOpcode() == ISD::AND && 5458 Op1.getOpcode() == ISD::Constant) { 5459 SDValue AndOp1 = Op0.getOperand(1); 5460 5461 if (AndOp1.getOpcode() == ISD::Constant) { 5462 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5463 5464 if (AndConst.isPowerOf2() && 5465 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5466 SDValue SetCC = 5467 DAG.getSetCC(N->getDebugLoc(), 5468 TLI.getSetCCResultType(Op0.getValueType()), 5469 Op0, DAG.getConstant(0, Op0.getValueType()), 5470 ISD::SETNE); 5471 5472 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5473 MVT::Other, Chain, SetCC, N2); 5474 // Don't add the new BRCond into the worklist or else SimplifySelectCC 5475 // will convert it back to (X & C1) >> C2. 5476 CombineTo(N, NewBRCond, false); 5477 // Truncate is dead. 5478 if (Trunc) { 5479 removeFromWorkList(Trunc); 5480 DAG.DeleteNode(Trunc); 5481 } 5482 // Replace the uses of SRL with SETCC 5483 WorkListRemover DeadNodes(*this); 5484 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5485 removeFromWorkList(N1.getNode()); 5486 DAG.DeleteNode(N1.getNode()); 5487 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5488 } 5489 } 5490 } 5491 5492 if (Trunc) 5493 // Restore N1 if the above transformation doesn't match. 5494 N1 = N->getOperand(1); 5495 } 5496 5497 // Transform br(xor(x, y)) -> br(x != y) 5498 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5499 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5500 SDNode *TheXor = N1.getNode(); 5501 SDValue Op0 = TheXor->getOperand(0); 5502 SDValue Op1 = TheXor->getOperand(1); 5503 if (Op0.getOpcode() == Op1.getOpcode()) { 5504 // Avoid missing important xor optimizations. 5505 SDValue Tmp = visitXOR(TheXor); 5506 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5507 DEBUG(dbgs() << "\nReplacing.8 "; 5508 TheXor->dump(&DAG); 5509 dbgs() << "\nWith: "; 5510 Tmp.getNode()->dump(&DAG); 5511 dbgs() << '\n'); 5512 WorkListRemover DeadNodes(*this); 5513 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5514 removeFromWorkList(TheXor); 5515 DAG.DeleteNode(TheXor); 5516 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5517 MVT::Other, Chain, Tmp, N2); 5518 } 5519 } 5520 5521 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5522 bool Equal = false; 5523 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5524 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5525 Op0.getOpcode() == ISD::XOR) { 5526 TheXor = Op0.getNode(); 5527 Equal = true; 5528 } 5529 5530 EVT SetCCVT = N1.getValueType(); 5531 if (LegalTypes) 5532 SetCCVT = TLI.getSetCCResultType(SetCCVT); 5533 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5534 SetCCVT, 5535 Op0, Op1, 5536 Equal ? ISD::SETEQ : ISD::SETNE); 5537 // Replace the uses of XOR with SETCC 5538 WorkListRemover DeadNodes(*this); 5539 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5540 removeFromWorkList(N1.getNode()); 5541 DAG.DeleteNode(N1.getNode()); 5542 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5543 MVT::Other, Chain, SetCC, N2); 5544 } 5545 } 5546 5547 return SDValue(); 5548} 5549 5550// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5551// 5552SDValue DAGCombiner::visitBR_CC(SDNode *N) { 5553 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5554 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5555 5556 // If N is a constant we could fold this into a fallthrough or unconditional 5557 // branch. However that doesn't happen very often in normal code, because 5558 // Instcombine/SimplifyCFG should have handled the available opportunities. 5559 // If we did this folding here, it would be necessary to update the 5560 // MachineBasicBlock CFG, which is awkward. 5561 5562 // Use SimplifySetCC to simplify SETCC's. 5563 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5564 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5565 false); 5566 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5567 5568 // fold to a simpler setcc 5569 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5570 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5571 N->getOperand(0), Simp.getOperand(2), 5572 Simp.getOperand(0), Simp.getOperand(1), 5573 N->getOperand(4)); 5574 5575 return SDValue(); 5576} 5577 5578/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5579/// pre-indexed load / store when the base pointer is an add or subtract 5580/// and it has other uses besides the load / store. After the 5581/// transformation, the new indexed load / store has effectively folded 5582/// the add / subtract in and all of its other uses are redirected to the 5583/// new load / store. 5584bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5585 if (!LegalOperations) 5586 return false; 5587 5588 bool isLoad = true; 5589 SDValue Ptr; 5590 EVT VT; 5591 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5592 if (LD->isIndexed()) 5593 return false; 5594 VT = LD->getMemoryVT(); 5595 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5596 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5597 return false; 5598 Ptr = LD->getBasePtr(); 5599 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5600 if (ST->isIndexed()) 5601 return false; 5602 VT = ST->getMemoryVT(); 5603 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5604 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5605 return false; 5606 Ptr = ST->getBasePtr(); 5607 isLoad = false; 5608 } else { 5609 return false; 5610 } 5611 5612 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5613 // out. There is no reason to make this a preinc/predec. 5614 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 5615 Ptr.getNode()->hasOneUse()) 5616 return false; 5617 5618 // Ask the target to do addressing mode selection. 5619 SDValue BasePtr; 5620 SDValue Offset; 5621 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5622 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 5623 return false; 5624 // Don't create a indexed load / store with zero offset. 5625 if (isa<ConstantSDNode>(Offset) && 5626 cast<ConstantSDNode>(Offset)->isNullValue()) 5627 return false; 5628 5629 // Try turning it into a pre-indexed load / store except when: 5630 // 1) The new base ptr is a frame index. 5631 // 2) If N is a store and the new base ptr is either the same as or is a 5632 // predecessor of the value being stored. 5633 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 5634 // that would create a cycle. 5635 // 4) All uses are load / store ops that use it as old base ptr. 5636 5637 // Check #1. Preinc'ing a frame index would require copying the stack pointer 5638 // (plus the implicit offset) to a register to preinc anyway. 5639 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5640 return false; 5641 5642 // Check #2. 5643 if (!isLoad) { 5644 SDValue Val = cast<StoreSDNode>(N)->getValue(); 5645 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 5646 return false; 5647 } 5648 5649 // Now check for #3 and #4. 5650 bool RealUse = false; 5651 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5652 E = Ptr.getNode()->use_end(); I != E; ++I) { 5653 SDNode *Use = *I; 5654 if (Use == N) 5655 continue; 5656 if (Use->isPredecessorOf(N)) 5657 return false; 5658 5659 if (!((Use->getOpcode() == ISD::LOAD && 5660 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 5661 (Use->getOpcode() == ISD::STORE && 5662 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 5663 RealUse = true; 5664 } 5665 5666 if (!RealUse) 5667 return false; 5668 5669 SDValue Result; 5670 if (isLoad) 5671 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5672 BasePtr, Offset, AM); 5673 else 5674 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5675 BasePtr, Offset, AM); 5676 ++PreIndexedNodes; 5677 ++NodesCombined; 5678 DEBUG(dbgs() << "\nReplacing.4 "; 5679 N->dump(&DAG); 5680 dbgs() << "\nWith: "; 5681 Result.getNode()->dump(&DAG); 5682 dbgs() << '\n'); 5683 WorkListRemover DeadNodes(*this); 5684 if (isLoad) { 5685 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5686 &DeadNodes); 5687 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5688 &DeadNodes); 5689 } else { 5690 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5691 &DeadNodes); 5692 } 5693 5694 // Finally, since the node is now dead, remove it from the graph. 5695 DAG.DeleteNode(N); 5696 5697 // Replace the uses of Ptr with uses of the updated base value. 5698 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 5699 &DeadNodes); 5700 removeFromWorkList(Ptr.getNode()); 5701 DAG.DeleteNode(Ptr.getNode()); 5702 5703 return true; 5704} 5705 5706/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 5707/// add / sub of the base pointer node into a post-indexed load / store. 5708/// The transformation folded the add / subtract into the new indexed 5709/// load / store effectively and all of its uses are redirected to the 5710/// new load / store. 5711bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 5712 if (!LegalOperations) 5713 return false; 5714 5715 bool isLoad = true; 5716 SDValue Ptr; 5717 EVT VT; 5718 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5719 if (LD->isIndexed()) 5720 return false; 5721 VT = LD->getMemoryVT(); 5722 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 5723 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 5724 return false; 5725 Ptr = LD->getBasePtr(); 5726 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5727 if (ST->isIndexed()) 5728 return false; 5729 VT = ST->getMemoryVT(); 5730 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 5731 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 5732 return false; 5733 Ptr = ST->getBasePtr(); 5734 isLoad = false; 5735 } else { 5736 return false; 5737 } 5738 5739 if (Ptr.getNode()->hasOneUse()) 5740 return false; 5741 5742 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5743 E = Ptr.getNode()->use_end(); I != E; ++I) { 5744 SDNode *Op = *I; 5745 if (Op == N || 5746 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 5747 continue; 5748 5749 SDValue BasePtr; 5750 SDValue Offset; 5751 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5752 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 5753 // Don't create a indexed load / store with zero offset. 5754 if (isa<ConstantSDNode>(Offset) && 5755 cast<ConstantSDNode>(Offset)->isNullValue()) 5756 continue; 5757 5758 // Try turning it into a post-indexed load / store except when 5759 // 1) All uses are load / store ops that use it as base ptr. 5760 // 2) Op must be independent of N, i.e. Op is neither a predecessor 5761 // nor a successor of N. Otherwise, if Op is folded that would 5762 // create a cycle. 5763 5764 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5765 continue; 5766 5767 // Check for #1. 5768 bool TryNext = false; 5769 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 5770 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 5771 SDNode *Use = *II; 5772 if (Use == Ptr.getNode()) 5773 continue; 5774 5775 // If all the uses are load / store addresses, then don't do the 5776 // transformation. 5777 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 5778 bool RealUse = false; 5779 for (SDNode::use_iterator III = Use->use_begin(), 5780 EEE = Use->use_end(); III != EEE; ++III) { 5781 SDNode *UseUse = *III; 5782 if (!((UseUse->getOpcode() == ISD::LOAD && 5783 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 5784 (UseUse->getOpcode() == ISD::STORE && 5785 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 5786 RealUse = true; 5787 } 5788 5789 if (!RealUse) { 5790 TryNext = true; 5791 break; 5792 } 5793 } 5794 } 5795 5796 if (TryNext) 5797 continue; 5798 5799 // Check for #2 5800 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 5801 SDValue Result = isLoad 5802 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5803 BasePtr, Offset, AM) 5804 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5805 BasePtr, Offset, AM); 5806 ++PostIndexedNodes; 5807 ++NodesCombined; 5808 DEBUG(dbgs() << "\nReplacing.5 "; 5809 N->dump(&DAG); 5810 dbgs() << "\nWith: "; 5811 Result.getNode()->dump(&DAG); 5812 dbgs() << '\n'); 5813 WorkListRemover DeadNodes(*this); 5814 if (isLoad) { 5815 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5816 &DeadNodes); 5817 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5818 &DeadNodes); 5819 } else { 5820 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5821 &DeadNodes); 5822 } 5823 5824 // Finally, since the node is now dead, remove it from the graph. 5825 DAG.DeleteNode(N); 5826 5827 // Replace the uses of Use with uses of the updated base value. 5828 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5829 Result.getValue(isLoad ? 1 : 0), 5830 &DeadNodes); 5831 removeFromWorkList(Op); 5832 DAG.DeleteNode(Op); 5833 return true; 5834 } 5835 } 5836 } 5837 5838 return false; 5839} 5840 5841SDValue DAGCombiner::visitLOAD(SDNode *N) { 5842 LoadSDNode *LD = cast<LoadSDNode>(N); 5843 SDValue Chain = LD->getChain(); 5844 SDValue Ptr = LD->getBasePtr(); 5845 5846 // If load is not volatile and there are no uses of the loaded value (and 5847 // the updated indexed value in case of indexed loads), change uses of the 5848 // chain value into uses of the chain input (i.e. delete the dead load). 5849 if (!LD->isVolatile()) { 5850 if (N->getValueType(1) == MVT::Other) { 5851 // Unindexed loads. 5852 if (N->hasNUsesOfValue(0, 0)) { 5853 // It's not safe to use the two value CombineTo variant here. e.g. 5854 // v1, chain2 = load chain1, loc 5855 // v2, chain3 = load chain2, loc 5856 // v3 = add v2, c 5857 // Now we replace use of chain2 with chain1. This makes the second load 5858 // isomorphic to the one we are deleting, and thus makes this load live. 5859 DEBUG(dbgs() << "\nReplacing.6 "; 5860 N->dump(&DAG); 5861 dbgs() << "\nWith chain: "; 5862 Chain.getNode()->dump(&DAG); 5863 dbgs() << "\n"); 5864 WorkListRemover DeadNodes(*this); 5865 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5866 5867 if (N->use_empty()) { 5868 removeFromWorkList(N); 5869 DAG.DeleteNode(N); 5870 } 5871 5872 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5873 } 5874 } else { 5875 // Indexed loads. 5876 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5877 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5878 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5879 DEBUG(dbgs() << "\nReplacing.7 "; 5880 N->dump(&DAG); 5881 dbgs() << "\nWith: "; 5882 Undef.getNode()->dump(&DAG); 5883 dbgs() << " and 2 other values\n"); 5884 WorkListRemover DeadNodes(*this); 5885 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5886 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5887 DAG.getUNDEF(N->getValueType(1)), 5888 &DeadNodes); 5889 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5890 removeFromWorkList(N); 5891 DAG.DeleteNode(N); 5892 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5893 } 5894 } 5895 } 5896 5897 // If this load is directly stored, replace the load value with the stored 5898 // value. 5899 // TODO: Handle store large -> read small portion. 5900 // TODO: Handle TRUNCSTORE/LOADEXT 5901 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 5902 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5903 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5904 if (PrevST->getBasePtr() == Ptr && 5905 PrevST->getValue().getValueType() == N->getValueType(0)) 5906 return CombineTo(N, Chain.getOperand(1), Chain); 5907 } 5908 } 5909 5910 // Try to infer better alignment information than the load already has. 5911 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5912 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5913 if (Align > LD->getAlignment()) 5914 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 5915 LD->getValueType(0), 5916 Chain, Ptr, LD->getPointerInfo(), 5917 LD->getMemoryVT(), 5918 LD->isVolatile(), LD->isNonTemporal(), Align); 5919 } 5920 } 5921 5922 if (CombinerAA) { 5923 // Walk up chain skipping non-aliasing memory nodes. 5924 SDValue BetterChain = FindBetterChain(N, Chain); 5925 5926 // If there is a better chain. 5927 if (Chain != BetterChain) { 5928 SDValue ReplLoad; 5929 5930 // Replace the chain to void dependency. 5931 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5932 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5933 BetterChain, Ptr, LD->getPointerInfo(), 5934 LD->isVolatile(), LD->isNonTemporal(), 5935 LD->getAlignment()); 5936 } else { 5937 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5938 LD->getValueType(0), 5939 BetterChain, Ptr, LD->getPointerInfo(), 5940 LD->getMemoryVT(), 5941 LD->isVolatile(), 5942 LD->isNonTemporal(), 5943 LD->getAlignment()); 5944 } 5945 5946 // Create token factor to keep old chain connected. 5947 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5948 MVT::Other, Chain, ReplLoad.getValue(1)); 5949 5950 // Make sure the new and old chains are cleaned up. 5951 AddToWorkList(Token.getNode()); 5952 5953 // Replace uses with load result and token factor. Don't add users 5954 // to work list. 5955 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5956 } 5957 } 5958 5959 // Try transforming N to an indexed load. 5960 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5961 return SDValue(N, 0); 5962 5963 return SDValue(); 5964} 5965 5966/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 5967/// load is having specific bytes cleared out. If so, return the byte size 5968/// being masked out and the shift amount. 5969static std::pair<unsigned, unsigned> 5970CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 5971 std::pair<unsigned, unsigned> Result(0, 0); 5972 5973 // Check for the structure we're looking for. 5974 if (V->getOpcode() != ISD::AND || 5975 !isa<ConstantSDNode>(V->getOperand(1)) || 5976 !ISD::isNormalLoad(V->getOperand(0).getNode())) 5977 return Result; 5978 5979 // Check the chain and pointer. 5980 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 5981 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 5982 5983 // The store should be chained directly to the load or be an operand of a 5984 // tokenfactor. 5985 if (LD == Chain.getNode()) 5986 ; // ok. 5987 else if (Chain->getOpcode() != ISD::TokenFactor) 5988 return Result; // Fail. 5989 else { 5990 bool isOk = false; 5991 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 5992 if (Chain->getOperand(i).getNode() == LD) { 5993 isOk = true; 5994 break; 5995 } 5996 if (!isOk) return Result; 5997 } 5998 5999 // This only handles simple types. 6000 if (V.getValueType() != MVT::i16 && 6001 V.getValueType() != MVT::i32 && 6002 V.getValueType() != MVT::i64) 6003 return Result; 6004 6005 // Check the constant mask. Invert it so that the bits being masked out are 6006 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 6007 // follow the sign bit for uniformity. 6008 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 6009 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 6010 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 6011 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 6012 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 6013 if (NotMaskLZ == 64) return Result; // All zero mask. 6014 6015 // See if we have a continuous run of bits. If so, we have 0*1+0* 6016 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 6017 return Result; 6018 6019 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 6020 if (V.getValueType() != MVT::i64 && NotMaskLZ) 6021 NotMaskLZ -= 64-V.getValueSizeInBits(); 6022 6023 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 6024 switch (MaskedBytes) { 6025 case 1: 6026 case 2: 6027 case 4: break; 6028 default: return Result; // All one mask, or 5-byte mask. 6029 } 6030 6031 // Verify that the first bit starts at a multiple of mask so that the access 6032 // is aligned the same as the access width. 6033 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 6034 6035 Result.first = MaskedBytes; 6036 Result.second = NotMaskTZ/8; 6037 return Result; 6038} 6039 6040 6041/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 6042/// provides a value as specified by MaskInfo. If so, replace the specified 6043/// store with a narrower store of truncated IVal. 6044static SDNode * 6045ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 6046 SDValue IVal, StoreSDNode *St, 6047 DAGCombiner *DC) { 6048 unsigned NumBytes = MaskInfo.first; 6049 unsigned ByteShift = MaskInfo.second; 6050 SelectionDAG &DAG = DC->getDAG(); 6051 6052 // Check to see if IVal is all zeros in the part being masked in by the 'or' 6053 // that uses this. If not, this is not a replacement. 6054 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 6055 ByteShift*8, (ByteShift+NumBytes)*8); 6056 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 6057 6058 // Check that it is legal on the target to do this. It is legal if the new 6059 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 6060 // legalization. 6061 MVT VT = MVT::getIntegerVT(NumBytes*8); 6062 if (!DC->isTypeLegal(VT)) 6063 return 0; 6064 6065 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 6066 // shifted by ByteShift and truncated down to NumBytes. 6067 if (ByteShift) 6068 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 6069 DAG.getConstant(ByteShift*8, 6070 DC->getShiftAmountTy(IVal.getValueType()))); 6071 6072 // Figure out the offset for the store and the alignment of the access. 6073 unsigned StOffset; 6074 unsigned NewAlign = St->getAlignment(); 6075 6076 if (DAG.getTargetLoweringInfo().isLittleEndian()) 6077 StOffset = ByteShift; 6078 else 6079 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6080 6081 SDValue Ptr = St->getBasePtr(); 6082 if (StOffset) { 6083 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6084 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6085 NewAlign = MinAlign(NewAlign, StOffset); 6086 } 6087 6088 // Truncate down to the new size. 6089 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6090 6091 ++OpsNarrowed; 6092 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6093 St->getPointerInfo().getWithOffset(StOffset), 6094 false, false, NewAlign).getNode(); 6095} 6096 6097 6098/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6099/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6100/// of the loaded bits, try narrowing the load and store if it would end up 6101/// being a win for performance or code size. 6102SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6103 StoreSDNode *ST = cast<StoreSDNode>(N); 6104 if (ST->isVolatile()) 6105 return SDValue(); 6106 6107 SDValue Chain = ST->getChain(); 6108 SDValue Value = ST->getValue(); 6109 SDValue Ptr = ST->getBasePtr(); 6110 EVT VT = Value.getValueType(); 6111 6112 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6113 return SDValue(); 6114 6115 unsigned Opc = Value.getOpcode(); 6116 6117 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6118 // is a byte mask indicating a consecutive number of bytes, check to see if 6119 // Y is known to provide just those bytes. If so, we try to replace the 6120 // load + replace + store sequence with a single (narrower) store, which makes 6121 // the load dead. 6122 if (Opc == ISD::OR) { 6123 std::pair<unsigned, unsigned> MaskedLoad; 6124 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6125 if (MaskedLoad.first) 6126 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6127 Value.getOperand(1), ST,this)) 6128 return SDValue(NewST, 0); 6129 6130 // Or is commutative, so try swapping X and Y. 6131 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6132 if (MaskedLoad.first) 6133 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6134 Value.getOperand(0), ST,this)) 6135 return SDValue(NewST, 0); 6136 } 6137 6138 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6139 Value.getOperand(1).getOpcode() != ISD::Constant) 6140 return SDValue(); 6141 6142 SDValue N0 = Value.getOperand(0); 6143 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6144 Chain == SDValue(N0.getNode(), 1)) { 6145 LoadSDNode *LD = cast<LoadSDNode>(N0); 6146 if (LD->getBasePtr() != Ptr || 6147 LD->getPointerInfo().getAddrSpace() != 6148 ST->getPointerInfo().getAddrSpace()) 6149 return SDValue(); 6150 6151 // Find the type to narrow it the load / op / store to. 6152 SDValue N1 = Value.getOperand(1); 6153 unsigned BitWidth = N1.getValueSizeInBits(); 6154 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6155 if (Opc == ISD::AND) 6156 Imm ^= APInt::getAllOnesValue(BitWidth); 6157 if (Imm == 0 || Imm.isAllOnesValue()) 6158 return SDValue(); 6159 unsigned ShAmt = Imm.countTrailingZeros(); 6160 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6161 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6162 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6163 while (NewBW < BitWidth && 6164 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6165 TLI.isNarrowingProfitable(VT, NewVT))) { 6166 NewBW = NextPowerOf2(NewBW); 6167 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6168 } 6169 if (NewBW >= BitWidth) 6170 return SDValue(); 6171 6172 // If the lsb changed does not start at the type bitwidth boundary, 6173 // start at the previous one. 6174 if (ShAmt % NewBW) 6175 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6176 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6177 if ((Imm & Mask) == Imm) { 6178 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6179 if (Opc == ISD::AND) 6180 NewImm ^= APInt::getAllOnesValue(NewBW); 6181 uint64_t PtrOff = ShAmt / 8; 6182 // For big endian targets, we need to adjust the offset to the pointer to 6183 // load the correct bytes. 6184 if (TLI.isBigEndian()) 6185 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6186 6187 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6188 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6189 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6190 return SDValue(); 6191 6192 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6193 Ptr.getValueType(), Ptr, 6194 DAG.getConstant(PtrOff, Ptr.getValueType())); 6195 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6196 LD->getChain(), NewPtr, 6197 LD->getPointerInfo().getWithOffset(PtrOff), 6198 LD->isVolatile(), LD->isNonTemporal(), 6199 NewAlign); 6200 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6201 DAG.getConstant(NewImm, NewVT)); 6202 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6203 NewVal, NewPtr, 6204 ST->getPointerInfo().getWithOffset(PtrOff), 6205 false, false, NewAlign); 6206 6207 AddToWorkList(NewPtr.getNode()); 6208 AddToWorkList(NewLD.getNode()); 6209 AddToWorkList(NewVal.getNode()); 6210 WorkListRemover DeadNodes(*this); 6211 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6212 &DeadNodes); 6213 ++OpsNarrowed; 6214 return NewST; 6215 } 6216 } 6217 6218 return SDValue(); 6219} 6220 6221/// TransformFPLoadStorePair - For a given floating point load / store pair, 6222/// if the load value isn't used by any other operations, then consider 6223/// transforming the pair to integer load / store operations if the target 6224/// deems the transformation profitable. 6225SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 6226 StoreSDNode *ST = cast<StoreSDNode>(N); 6227 SDValue Chain = ST->getChain(); 6228 SDValue Value = ST->getValue(); 6229 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 6230 Value.hasOneUse() && 6231 Chain == SDValue(Value.getNode(), 1)) { 6232 LoadSDNode *LD = cast<LoadSDNode>(Value); 6233 EVT VT = LD->getMemoryVT(); 6234 if (!VT.isFloatingPoint() || 6235 VT != ST->getMemoryVT() || 6236 LD->isNonTemporal() || 6237 ST->isNonTemporal() || 6238 LD->getPointerInfo().getAddrSpace() != 0 || 6239 ST->getPointerInfo().getAddrSpace() != 0) 6240 return SDValue(); 6241 6242 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 6243 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 6244 !TLI.isOperationLegal(ISD::STORE, IntVT) || 6245 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 6246 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 6247 return SDValue(); 6248 6249 unsigned LDAlign = LD->getAlignment(); 6250 unsigned STAlign = ST->getAlignment(); 6251 const Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 6252 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 6253 if (LDAlign < ABIAlign || STAlign < ABIAlign) 6254 return SDValue(); 6255 6256 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 6257 LD->getChain(), LD->getBasePtr(), 6258 LD->getPointerInfo(), 6259 false, false, LDAlign); 6260 6261 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 6262 NewLD, ST->getBasePtr(), 6263 ST->getPointerInfo(), 6264 false, false, STAlign); 6265 6266 AddToWorkList(NewLD.getNode()); 6267 AddToWorkList(NewST.getNode()); 6268 WorkListRemover DeadNodes(*this); 6269 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1), 6270 &DeadNodes); 6271 ++LdStFP2Int; 6272 return NewST; 6273 } 6274 6275 return SDValue(); 6276} 6277 6278SDValue DAGCombiner::visitSTORE(SDNode *N) { 6279 StoreSDNode *ST = cast<StoreSDNode>(N); 6280 SDValue Chain = ST->getChain(); 6281 SDValue Value = ST->getValue(); 6282 SDValue Ptr = ST->getBasePtr(); 6283 6284 // If this is a store of a bit convert, store the input value if the 6285 // resultant store does not need a higher alignment than the original. 6286 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 6287 ST->isUnindexed()) { 6288 unsigned OrigAlign = ST->getAlignment(); 6289 EVT SVT = Value.getOperand(0).getValueType(); 6290 unsigned Align = TLI.getTargetData()-> 6291 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 6292 if (Align <= OrigAlign && 6293 ((!LegalOperations && !ST->isVolatile()) || 6294 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 6295 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6296 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6297 ST->isNonTemporal(), OrigAlign); 6298 } 6299 6300 // Turn 'store undef, Ptr' -> nothing. 6301 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 6302 return Chain; 6303 6304 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 6305 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 6306 // NOTE: If the original store is volatile, this transform must not increase 6307 // the number of stores. For example, on x86-32 an f64 can be stored in one 6308 // processor operation but an i64 (which is not legal) requires two. So the 6309 // transform should not be done in this case. 6310 if (Value.getOpcode() != ISD::TargetConstantFP) { 6311 SDValue Tmp; 6312 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 6313 default: llvm_unreachable("Unknown FP type"); 6314 case MVT::f80: // We don't do this for these yet. 6315 case MVT::f128: 6316 case MVT::ppcf128: 6317 break; 6318 case MVT::f32: 6319 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 6320 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6321 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 6322 bitcastToAPInt().getZExtValue(), MVT::i32); 6323 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6324 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6325 ST->isNonTemporal(), ST->getAlignment()); 6326 } 6327 break; 6328 case MVT::f64: 6329 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 6330 !ST->isVolatile()) || 6331 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 6332 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 6333 getZExtValue(), MVT::i64); 6334 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6335 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6336 ST->isNonTemporal(), ST->getAlignment()); 6337 } 6338 6339 if (!ST->isVolatile() && 6340 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6341 // Many FP stores are not made apparent until after legalize, e.g. for 6342 // argument passing. Since this is so common, custom legalize the 6343 // 64-bit integer store into two 32-bit stores. 6344 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 6345 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 6346 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 6347 if (TLI.isBigEndian()) std::swap(Lo, Hi); 6348 6349 unsigned Alignment = ST->getAlignment(); 6350 bool isVolatile = ST->isVolatile(); 6351 bool isNonTemporal = ST->isNonTemporal(); 6352 6353 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 6354 Ptr, ST->getPointerInfo(), 6355 isVolatile, isNonTemporal, 6356 ST->getAlignment()); 6357 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 6358 DAG.getConstant(4, Ptr.getValueType())); 6359 Alignment = MinAlign(Alignment, 4U); 6360 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 6361 Ptr, ST->getPointerInfo().getWithOffset(4), 6362 isVolatile, isNonTemporal, 6363 Alignment); 6364 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6365 St0, St1); 6366 } 6367 6368 break; 6369 } 6370 } 6371 } 6372 6373 // Try to infer better alignment information than the store already has. 6374 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 6375 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6376 if (Align > ST->getAlignment()) 6377 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 6378 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6379 ST->isVolatile(), ST->isNonTemporal(), Align); 6380 } 6381 } 6382 6383 // Try transforming a pair floating point load / store ops to integer 6384 // load / store ops. 6385 SDValue NewST = TransformFPLoadStorePair(N); 6386 if (NewST.getNode()) 6387 return NewST; 6388 6389 if (CombinerAA) { 6390 // Walk up chain skipping non-aliasing memory nodes. 6391 SDValue BetterChain = FindBetterChain(N, Chain); 6392 6393 // If there is a better chain. 6394 if (Chain != BetterChain) { 6395 SDValue ReplStore; 6396 6397 // Replace the chain to avoid dependency. 6398 if (ST->isTruncatingStore()) { 6399 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6400 ST->getPointerInfo(), 6401 ST->getMemoryVT(), ST->isVolatile(), 6402 ST->isNonTemporal(), ST->getAlignment()); 6403 } else { 6404 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6405 ST->getPointerInfo(), 6406 ST->isVolatile(), ST->isNonTemporal(), 6407 ST->getAlignment()); 6408 } 6409 6410 // Create token to keep both nodes around. 6411 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6412 MVT::Other, Chain, ReplStore); 6413 6414 // Make sure the new and old chains are cleaned up. 6415 AddToWorkList(Token.getNode()); 6416 6417 // Don't add users to work list. 6418 return CombineTo(N, Token, false); 6419 } 6420 } 6421 6422 // Try transforming N to an indexed store. 6423 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6424 return SDValue(N, 0); 6425 6426 // FIXME: is there such a thing as a truncating indexed store? 6427 if (ST->isTruncatingStore() && ST->isUnindexed() && 6428 Value.getValueType().isInteger()) { 6429 // See if we can simplify the input to this truncstore with knowledge that 6430 // only the low bits are being used. For example: 6431 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 6432 SDValue Shorter = 6433 GetDemandedBits(Value, 6434 APInt::getLowBitsSet(Value.getValueSizeInBits(), 6435 ST->getMemoryVT().getSizeInBits())); 6436 AddToWorkList(Value.getNode()); 6437 if (Shorter.getNode()) 6438 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 6439 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6440 ST->isVolatile(), ST->isNonTemporal(), 6441 ST->getAlignment()); 6442 6443 // Otherwise, see if we can simplify the operation with 6444 // SimplifyDemandedBits, which only works if the value has a single use. 6445 if (SimplifyDemandedBits(Value, 6446 APInt::getLowBitsSet( 6447 Value.getValueType().getScalarType().getSizeInBits(), 6448 ST->getMemoryVT().getScalarType().getSizeInBits()))) 6449 return SDValue(N, 0); 6450 } 6451 6452 // If this is a load followed by a store to the same location, then the store 6453 // is dead/noop. 6454 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 6455 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 6456 ST->isUnindexed() && !ST->isVolatile() && 6457 // There can't be any side effects between the load and store, such as 6458 // a call or store. 6459 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6460 // The store is dead, remove it. 6461 return Chain; 6462 } 6463 } 6464 6465 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6466 // truncating store. We can do this even if this is already a truncstore. 6467 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6468 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6469 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6470 ST->getMemoryVT())) { 6471 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6472 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6473 ST->isVolatile(), ST->isNonTemporal(), 6474 ST->getAlignment()); 6475 } 6476 6477 return ReduceLoadOpStoreWidth(N); 6478} 6479 6480SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6481 SDValue InVec = N->getOperand(0); 6482 SDValue InVal = N->getOperand(1); 6483 SDValue EltNo = N->getOperand(2); 6484 6485 // If the inserted element is an UNDEF, just use the input vector. 6486 if (InVal.getOpcode() == ISD::UNDEF) 6487 return InVec; 6488 6489 EVT VT = InVec.getValueType(); 6490 6491 // If we can't generate a legal BUILD_VECTOR, exit 6492 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 6493 return SDValue(); 6494 6495 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 6496 // vector with the inserted element. 6497 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 6498 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6499 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 6500 InVec.getNode()->op_end()); 6501 if (Elt < Ops.size()) 6502 Ops[Elt] = InVal; 6503 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6504 VT, &Ops[0], Ops.size()); 6505 } 6506 // If the invec is an UNDEF and if EltNo is a constant, create a new 6507 // BUILD_VECTOR with undef elements and the inserted element. 6508 if (InVec.getOpcode() == ISD::UNDEF && 6509 isa<ConstantSDNode>(EltNo)) { 6510 EVT EltVT = VT.getVectorElementType(); 6511 unsigned NElts = VT.getVectorNumElements(); 6512 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 6513 6514 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6515 if (Elt < Ops.size()) 6516 Ops[Elt] = InVal; 6517 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6518 VT, &Ops[0], Ops.size()); 6519 } 6520 return SDValue(); 6521} 6522 6523SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6524 // (vextract (scalar_to_vector val, 0) -> val 6525 SDValue InVec = N->getOperand(0); 6526 6527 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6528 // Check if the result type doesn't match the inserted element type. A 6529 // SCALAR_TO_VECTOR may truncate the inserted element and the 6530 // EXTRACT_VECTOR_ELT may widen the extracted vector. 6531 SDValue InOp = InVec.getOperand(0); 6532 EVT NVT = N->getValueType(0); 6533 if (InOp.getValueType() != NVT) { 6534 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6535 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6536 } 6537 return InOp; 6538 } 6539 6540 // Perform only after legalization to ensure build_vector / vector_shuffle 6541 // optimizations have already been done. 6542 if (!LegalOperations) return SDValue(); 6543 6544 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6545 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6546 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6547 SDValue EltNo = N->getOperand(1); 6548 6549 if (isa<ConstantSDNode>(EltNo)) { 6550 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6551 bool NewLoad = false; 6552 bool BCNumEltsChanged = false; 6553 EVT VT = InVec.getValueType(); 6554 EVT ExtVT = VT.getVectorElementType(); 6555 EVT LVT = ExtVT; 6556 6557 if (InVec.getOpcode() == ISD::BITCAST) { 6558 EVT BCVT = InVec.getOperand(0).getValueType(); 6559 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6560 return SDValue(); 6561 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6562 BCNumEltsChanged = true; 6563 InVec = InVec.getOperand(0); 6564 ExtVT = BCVT.getVectorElementType(); 6565 NewLoad = true; 6566 } 6567 6568 LoadSDNode *LN0 = NULL; 6569 const ShuffleVectorSDNode *SVN = NULL; 6570 if (ISD::isNormalLoad(InVec.getNode())) { 6571 LN0 = cast<LoadSDNode>(InVec); 6572 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6573 InVec.getOperand(0).getValueType() == ExtVT && 6574 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6575 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6576 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6577 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6578 // => 6579 // (load $addr+1*size) 6580 6581 // If the bit convert changed the number of elements, it is unsafe 6582 // to examine the mask. 6583 if (BCNumEltsChanged) 6584 return SDValue(); 6585 6586 // Select the input vector, guarding against out of range extract vector. 6587 unsigned NumElems = VT.getVectorNumElements(); 6588 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 6589 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 6590 6591 if (InVec.getOpcode() == ISD::BITCAST) 6592 InVec = InVec.getOperand(0); 6593 if (ISD::isNormalLoad(InVec.getNode())) { 6594 LN0 = cast<LoadSDNode>(InVec); 6595 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 6596 } 6597 } 6598 6599 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 6600 return SDValue(); 6601 6602 // If Idx was -1 above, Elt is going to be -1, so just return undef. 6603 if (Elt == -1) 6604 return DAG.getUNDEF(LN0->getBasePtr().getValueType()); 6605 6606 unsigned Align = LN0->getAlignment(); 6607 if (NewLoad) { 6608 // Check the resultant load doesn't need a higher alignment than the 6609 // original load. 6610 unsigned NewAlign = 6611 TLI.getTargetData() 6612 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 6613 6614 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 6615 return SDValue(); 6616 6617 Align = NewAlign; 6618 } 6619 6620 SDValue NewPtr = LN0->getBasePtr(); 6621 unsigned PtrOff = 0; 6622 6623 if (Elt) { 6624 PtrOff = LVT.getSizeInBits() * Elt / 8; 6625 EVT PtrType = NewPtr.getValueType(); 6626 if (TLI.isBigEndian()) 6627 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 6628 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 6629 DAG.getConstant(PtrOff, PtrType)); 6630 } 6631 6632 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 6633 LN0->getPointerInfo().getWithOffset(PtrOff), 6634 LN0->isVolatile(), LN0->isNonTemporal(), Align); 6635 } 6636 6637 return SDValue(); 6638} 6639 6640SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 6641 unsigned NumInScalars = N->getNumOperands(); 6642 EVT VT = N->getValueType(0); 6643 6644 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 6645 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 6646 // at most two distinct vectors, turn this into a shuffle node. 6647 SDValue VecIn1, VecIn2; 6648 for (unsigned i = 0; i != NumInScalars; ++i) { 6649 // Ignore undef inputs. 6650 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 6651 6652 // If this input is something other than a EXTRACT_VECTOR_ELT with a 6653 // constant index, bail out. 6654 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6655 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 6656 VecIn1 = VecIn2 = SDValue(0, 0); 6657 break; 6658 } 6659 6660 // If the input vector type disagrees with the result of the build_vector, 6661 // we can't make a shuffle. 6662 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 6663 if (ExtractedFromVec.getValueType() != VT) { 6664 VecIn1 = VecIn2 = SDValue(0, 0); 6665 break; 6666 } 6667 6668 // Otherwise, remember this. We allow up to two distinct input vectors. 6669 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 6670 continue; 6671 6672 if (VecIn1.getNode() == 0) { 6673 VecIn1 = ExtractedFromVec; 6674 } else if (VecIn2.getNode() == 0) { 6675 VecIn2 = ExtractedFromVec; 6676 } else { 6677 // Too many inputs. 6678 VecIn1 = VecIn2 = SDValue(0, 0); 6679 break; 6680 } 6681 } 6682 6683 // If everything is good, we can make a shuffle operation. 6684 if (VecIn1.getNode()) { 6685 SmallVector<int, 8> Mask; 6686 for (unsigned i = 0; i != NumInScalars; ++i) { 6687 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 6688 Mask.push_back(-1); 6689 continue; 6690 } 6691 6692 // If extracting from the first vector, just use the index directly. 6693 SDValue Extract = N->getOperand(i); 6694 SDValue ExtVal = Extract.getOperand(1); 6695 if (Extract.getOperand(0) == VecIn1) { 6696 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6697 if (ExtIndex > VT.getVectorNumElements()) 6698 return SDValue(); 6699 6700 Mask.push_back(ExtIndex); 6701 continue; 6702 } 6703 6704 // Otherwise, use InIdx + VecSize 6705 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6706 Mask.push_back(Idx+NumInScalars); 6707 } 6708 6709 // Add count and size info. 6710 if (!isTypeLegal(VT)) 6711 return SDValue(); 6712 6713 // Return the new VECTOR_SHUFFLE node. 6714 SDValue Ops[2]; 6715 Ops[0] = VecIn1; 6716 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 6717 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 6718 } 6719 6720 return SDValue(); 6721} 6722 6723SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 6724 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 6725 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 6726 // inputs come from at most two distinct vectors, turn this into a shuffle 6727 // node. 6728 6729 // If we only have one input vector, we don't need to do any concatenation. 6730 if (N->getNumOperands() == 1) 6731 return N->getOperand(0); 6732 6733 return SDValue(); 6734} 6735 6736SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 6737 EVT VT = N->getValueType(0); 6738 unsigned NumElts = VT.getVectorNumElements(); 6739 6740 SDValue N0 = N->getOperand(0); 6741 6742 assert(N0.getValueType().getVectorNumElements() == NumElts && 6743 "Vector shuffle must be normalized in DAG"); 6744 6745 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 6746 6747 // If it is a splat, check if the argument vector is another splat or a 6748 // build_vector with all scalar elements the same. 6749 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 6750 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 6751 SDNode *V = N0.getNode(); 6752 6753 // If this is a bit convert that changes the element type of the vector but 6754 // not the number of vector elements, look through it. Be careful not to 6755 // look though conversions that change things like v4f32 to v2f64. 6756 if (V->getOpcode() == ISD::BITCAST) { 6757 SDValue ConvInput = V->getOperand(0); 6758 if (ConvInput.getValueType().isVector() && 6759 ConvInput.getValueType().getVectorNumElements() == NumElts) 6760 V = ConvInput.getNode(); 6761 } 6762 6763 if (V->getOpcode() == ISD::BUILD_VECTOR) { 6764 assert(V->getNumOperands() == NumElts && 6765 "BUILD_VECTOR has wrong number of operands"); 6766 SDValue Base; 6767 bool AllSame = true; 6768 for (unsigned i = 0; i != NumElts; ++i) { 6769 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 6770 Base = V->getOperand(i); 6771 break; 6772 } 6773 } 6774 // Splat of <u, u, u, u>, return <u, u, u, u> 6775 if (!Base.getNode()) 6776 return N0; 6777 for (unsigned i = 0; i != NumElts; ++i) { 6778 if (V->getOperand(i) != Base) { 6779 AllSame = false; 6780 break; 6781 } 6782 } 6783 // Splat of <x, x, x, x>, return <x, x, x, x> 6784 if (AllSame) 6785 return N0; 6786 } 6787 } 6788 return SDValue(); 6789} 6790 6791SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 6792 if (!TLI.getShouldFoldAtomicFences()) 6793 return SDValue(); 6794 6795 SDValue atomic = N->getOperand(0); 6796 switch (atomic.getOpcode()) { 6797 case ISD::ATOMIC_CMP_SWAP: 6798 case ISD::ATOMIC_SWAP: 6799 case ISD::ATOMIC_LOAD_ADD: 6800 case ISD::ATOMIC_LOAD_SUB: 6801 case ISD::ATOMIC_LOAD_AND: 6802 case ISD::ATOMIC_LOAD_OR: 6803 case ISD::ATOMIC_LOAD_XOR: 6804 case ISD::ATOMIC_LOAD_NAND: 6805 case ISD::ATOMIC_LOAD_MIN: 6806 case ISD::ATOMIC_LOAD_MAX: 6807 case ISD::ATOMIC_LOAD_UMIN: 6808 case ISD::ATOMIC_LOAD_UMAX: 6809 break; 6810 default: 6811 return SDValue(); 6812 } 6813 6814 SDValue fence = atomic.getOperand(0); 6815 if (fence.getOpcode() != ISD::MEMBARRIER) 6816 return SDValue(); 6817 6818 switch (atomic.getOpcode()) { 6819 case ISD::ATOMIC_CMP_SWAP: 6820 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6821 fence.getOperand(0), 6822 atomic.getOperand(1), atomic.getOperand(2), 6823 atomic.getOperand(3)), atomic.getResNo()); 6824 case ISD::ATOMIC_SWAP: 6825 case ISD::ATOMIC_LOAD_ADD: 6826 case ISD::ATOMIC_LOAD_SUB: 6827 case ISD::ATOMIC_LOAD_AND: 6828 case ISD::ATOMIC_LOAD_OR: 6829 case ISD::ATOMIC_LOAD_XOR: 6830 case ISD::ATOMIC_LOAD_NAND: 6831 case ISD::ATOMIC_LOAD_MIN: 6832 case ISD::ATOMIC_LOAD_MAX: 6833 case ISD::ATOMIC_LOAD_UMIN: 6834 case ISD::ATOMIC_LOAD_UMAX: 6835 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6836 fence.getOperand(0), 6837 atomic.getOperand(1), atomic.getOperand(2)), 6838 atomic.getResNo()); 6839 default: 6840 return SDValue(); 6841 } 6842} 6843 6844/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 6845/// an AND to a vector_shuffle with the destination vector and a zero vector. 6846/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 6847/// vector_shuffle V, Zero, <0, 4, 2, 4> 6848SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 6849 EVT VT = N->getValueType(0); 6850 DebugLoc dl = N->getDebugLoc(); 6851 SDValue LHS = N->getOperand(0); 6852 SDValue RHS = N->getOperand(1); 6853 if (N->getOpcode() == ISD::AND) { 6854 if (RHS.getOpcode() == ISD::BITCAST) 6855 RHS = RHS.getOperand(0); 6856 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 6857 SmallVector<int, 8> Indices; 6858 unsigned NumElts = RHS.getNumOperands(); 6859 for (unsigned i = 0; i != NumElts; ++i) { 6860 SDValue Elt = RHS.getOperand(i); 6861 if (!isa<ConstantSDNode>(Elt)) 6862 return SDValue(); 6863 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 6864 Indices.push_back(i); 6865 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 6866 Indices.push_back(NumElts); 6867 else 6868 return SDValue(); 6869 } 6870 6871 // Let's see if the target supports this vector_shuffle. 6872 EVT RVT = RHS.getValueType(); 6873 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 6874 return SDValue(); 6875 6876 // Return the new VECTOR_SHUFFLE node. 6877 EVT EltVT = RVT.getVectorElementType(); 6878 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 6879 DAG.getConstant(0, EltVT)); 6880 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6881 RVT, &ZeroOps[0], ZeroOps.size()); 6882 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 6883 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 6884 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 6885 } 6886 } 6887 6888 return SDValue(); 6889} 6890 6891/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 6892SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 6893 // After legalize, the target may be depending on adds and other 6894 // binary ops to provide legal ways to construct constants or other 6895 // things. Simplifying them may result in a loss of legality. 6896 if (LegalOperations) return SDValue(); 6897 6898 assert(N->getValueType(0).isVector() && 6899 "SimplifyVBinOp only works on vectors!"); 6900 6901 SDValue LHS = N->getOperand(0); 6902 SDValue RHS = N->getOperand(1); 6903 SDValue Shuffle = XformToShuffleWithZero(N); 6904 if (Shuffle.getNode()) return Shuffle; 6905 6906 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 6907 // this operation. 6908 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 6909 RHS.getOpcode() == ISD::BUILD_VECTOR) { 6910 SmallVector<SDValue, 8> Ops; 6911 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 6912 SDValue LHSOp = LHS.getOperand(i); 6913 SDValue RHSOp = RHS.getOperand(i); 6914 // If these two elements can't be folded, bail out. 6915 if ((LHSOp.getOpcode() != ISD::UNDEF && 6916 LHSOp.getOpcode() != ISD::Constant && 6917 LHSOp.getOpcode() != ISD::ConstantFP) || 6918 (RHSOp.getOpcode() != ISD::UNDEF && 6919 RHSOp.getOpcode() != ISD::Constant && 6920 RHSOp.getOpcode() != ISD::ConstantFP)) 6921 break; 6922 6923 // Can't fold divide by zero. 6924 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 6925 N->getOpcode() == ISD::FDIV) { 6926 if ((RHSOp.getOpcode() == ISD::Constant && 6927 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 6928 (RHSOp.getOpcode() == ISD::ConstantFP && 6929 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 6930 break; 6931 } 6932 6933 EVT VT = LHSOp.getValueType(); 6934 assert(RHSOp.getValueType() == VT && 6935 "SimplifyVBinOp with different BUILD_VECTOR element types"); 6936 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 6937 LHSOp, RHSOp); 6938 if (FoldOp.getOpcode() != ISD::UNDEF && 6939 FoldOp.getOpcode() != ISD::Constant && 6940 FoldOp.getOpcode() != ISD::ConstantFP) 6941 break; 6942 Ops.push_back(FoldOp); 6943 AddToWorkList(FoldOp.getNode()); 6944 } 6945 6946 if (Ops.size() == LHS.getNumOperands()) 6947 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6948 LHS.getValueType(), &Ops[0], Ops.size()); 6949 } 6950 6951 return SDValue(); 6952} 6953 6954SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 6955 SDValue N1, SDValue N2){ 6956 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 6957 6958 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 6959 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 6960 6961 // If we got a simplified select_cc node back from SimplifySelectCC, then 6962 // break it down into a new SETCC node, and a new SELECT node, and then return 6963 // the SELECT node, since we were called with a SELECT node. 6964 if (SCC.getNode()) { 6965 // Check to see if we got a select_cc back (to turn into setcc/select). 6966 // Otherwise, just return whatever node we got back, like fabs. 6967 if (SCC.getOpcode() == ISD::SELECT_CC) { 6968 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 6969 N0.getValueType(), 6970 SCC.getOperand(0), SCC.getOperand(1), 6971 SCC.getOperand(4)); 6972 AddToWorkList(SETCC.getNode()); 6973 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 6974 SCC.getOperand(2), SCC.getOperand(3), SETCC); 6975 } 6976 6977 return SCC; 6978 } 6979 return SDValue(); 6980} 6981 6982/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 6983/// are the two values being selected between, see if we can simplify the 6984/// select. Callers of this should assume that TheSelect is deleted if this 6985/// returns true. As such, they should return the appropriate thing (e.g. the 6986/// node) back to the top-level of the DAG combiner loop to avoid it being 6987/// looked at. 6988bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 6989 SDValue RHS) { 6990 6991 // Cannot simplify select with vector condition 6992 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 6993 6994 // If this is a select from two identical things, try to pull the operation 6995 // through the select. 6996 if (LHS.getOpcode() != RHS.getOpcode() || 6997 !LHS.hasOneUse() || !RHS.hasOneUse()) 6998 return false; 6999 7000 // If this is a load and the token chain is identical, replace the select 7001 // of two loads with a load through a select of the address to load from. 7002 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 7003 // constants have been dropped into the constant pool. 7004 if (LHS.getOpcode() == ISD::LOAD) { 7005 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 7006 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 7007 7008 // Token chains must be identical. 7009 if (LHS.getOperand(0) != RHS.getOperand(0) || 7010 // Do not let this transformation reduce the number of volatile loads. 7011 LLD->isVolatile() || RLD->isVolatile() || 7012 // If this is an EXTLOAD, the VT's must match. 7013 LLD->getMemoryVT() != RLD->getMemoryVT() || 7014 // If this is an EXTLOAD, the kind of extension must match. 7015 (LLD->getExtensionType() != RLD->getExtensionType() && 7016 // The only exception is if one of the extensions is anyext. 7017 LLD->getExtensionType() != ISD::EXTLOAD && 7018 RLD->getExtensionType() != ISD::EXTLOAD) || 7019 // FIXME: this discards src value information. This is 7020 // over-conservative. It would be beneficial to be able to remember 7021 // both potential memory locations. Since we are discarding 7022 // src value info, don't do the transformation if the memory 7023 // locations are not in the default address space. 7024 LLD->getPointerInfo().getAddrSpace() != 0 || 7025 RLD->getPointerInfo().getAddrSpace() != 0) 7026 return false; 7027 7028 // Check that the select condition doesn't reach either load. If so, 7029 // folding this will induce a cycle into the DAG. If not, this is safe to 7030 // xform, so create a select of the addresses. 7031 SDValue Addr; 7032 if (TheSelect->getOpcode() == ISD::SELECT) { 7033 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 7034 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 7035 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 7036 return false; 7037 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 7038 LLD->getBasePtr().getValueType(), 7039 TheSelect->getOperand(0), LLD->getBasePtr(), 7040 RLD->getBasePtr()); 7041 } else { // Otherwise SELECT_CC 7042 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 7043 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 7044 7045 if ((LLD->hasAnyUseOfValue(1) && 7046 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 7047 (LLD->hasAnyUseOfValue(1) && 7048 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS)))) 7049 return false; 7050 7051 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 7052 LLD->getBasePtr().getValueType(), 7053 TheSelect->getOperand(0), 7054 TheSelect->getOperand(1), 7055 LLD->getBasePtr(), RLD->getBasePtr(), 7056 TheSelect->getOperand(4)); 7057 } 7058 7059 SDValue Load; 7060 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 7061 Load = DAG.getLoad(TheSelect->getValueType(0), 7062 TheSelect->getDebugLoc(), 7063 // FIXME: Discards pointer info. 7064 LLD->getChain(), Addr, MachinePointerInfo(), 7065 LLD->isVolatile(), LLD->isNonTemporal(), 7066 LLD->getAlignment()); 7067 } else { 7068 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 7069 RLD->getExtensionType() : LLD->getExtensionType(), 7070 TheSelect->getDebugLoc(), 7071 TheSelect->getValueType(0), 7072 // FIXME: Discards pointer info. 7073 LLD->getChain(), Addr, MachinePointerInfo(), 7074 LLD->getMemoryVT(), LLD->isVolatile(), 7075 LLD->isNonTemporal(), LLD->getAlignment()); 7076 } 7077 7078 // Users of the select now use the result of the load. 7079 CombineTo(TheSelect, Load); 7080 7081 // Users of the old loads now use the new load's chain. We know the 7082 // old-load value is dead now. 7083 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 7084 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 7085 return true; 7086 } 7087 7088 return false; 7089} 7090 7091/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 7092/// where 'cond' is the comparison specified by CC. 7093SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 7094 SDValue N2, SDValue N3, 7095 ISD::CondCode CC, bool NotExtCompare) { 7096 // (x ? y : y) -> y. 7097 if (N2 == N3) return N2; 7098 7099 EVT VT = N2.getValueType(); 7100 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 7101 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 7102 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 7103 7104 // Determine if the condition we're dealing with is constant 7105 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 7106 N0, N1, CC, DL, false); 7107 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 7108 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 7109 7110 // fold select_cc true, x, y -> x 7111 if (SCCC && !SCCC->isNullValue()) 7112 return N2; 7113 // fold select_cc false, x, y -> y 7114 if (SCCC && SCCC->isNullValue()) 7115 return N3; 7116 7117 // Check to see if we can simplify the select into an fabs node 7118 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 7119 // Allow either -0.0 or 0.0 7120 if (CFP->getValueAPF().isZero()) { 7121 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 7122 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 7123 N0 == N2 && N3.getOpcode() == ISD::FNEG && 7124 N2 == N3.getOperand(0)) 7125 return DAG.getNode(ISD::FABS, DL, VT, N0); 7126 7127 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 7128 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 7129 N0 == N3 && N2.getOpcode() == ISD::FNEG && 7130 N2.getOperand(0) == N3) 7131 return DAG.getNode(ISD::FABS, DL, VT, N3); 7132 } 7133 } 7134 7135 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 7136 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 7137 // in it. This is a win when the constant is not otherwise available because 7138 // it replaces two constant pool loads with one. We only do this if the FP 7139 // type is known to be legal, because if it isn't, then we are before legalize 7140 // types an we want the other legalization to happen first (e.g. to avoid 7141 // messing with soft float) and if the ConstantFP is not legal, because if 7142 // it is legal, we may not need to store the FP constant in a constant pool. 7143 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 7144 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 7145 if (TLI.isTypeLegal(N2.getValueType()) && 7146 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 7147 TargetLowering::Legal) && 7148 // If both constants have multiple uses, then we won't need to do an 7149 // extra load, they are likely around in registers for other users. 7150 (TV->hasOneUse() || FV->hasOneUse())) { 7151 Constant *Elts[] = { 7152 const_cast<ConstantFP*>(FV->getConstantFPValue()), 7153 const_cast<ConstantFP*>(TV->getConstantFPValue()) 7154 }; 7155 const Type *FPTy = Elts[0]->getType(); 7156 const TargetData &TD = *TLI.getTargetData(); 7157 7158 // Create a ConstantArray of the two constants. 7159 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 7160 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 7161 TD.getPrefTypeAlignment(FPTy)); 7162 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 7163 7164 // Get the offsets to the 0 and 1 element of the array so that we can 7165 // select between them. 7166 SDValue Zero = DAG.getIntPtrConstant(0); 7167 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 7168 SDValue One = DAG.getIntPtrConstant(EltSize); 7169 7170 SDValue Cond = DAG.getSetCC(DL, 7171 TLI.getSetCCResultType(N0.getValueType()), 7172 N0, N1, CC); 7173 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 7174 Cond, One, Zero); 7175 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 7176 CstOffset); 7177 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 7178 MachinePointerInfo::getConstantPool(), false, 7179 false, Alignment); 7180 7181 } 7182 } 7183 7184 // Check to see if we can perform the "gzip trick", transforming 7185 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 7186 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 7187 N0.getValueType().isInteger() && 7188 N2.getValueType().isInteger() && 7189 (N1C->isNullValue() || // (a < 0) ? b : 0 7190 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 7191 EVT XType = N0.getValueType(); 7192 EVT AType = N2.getValueType(); 7193 if (XType.bitsGE(AType)) { 7194 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 7195 // single-bit constant. 7196 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 7197 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 7198 ShCtV = XType.getSizeInBits()-ShCtV-1; 7199 SDValue ShCt = DAG.getConstant(ShCtV, 7200 getShiftAmountTy(N0.getValueType())); 7201 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 7202 XType, N0, ShCt); 7203 AddToWorkList(Shift.getNode()); 7204 7205 if (XType.bitsGT(AType)) { 7206 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7207 AddToWorkList(Shift.getNode()); 7208 } 7209 7210 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7211 } 7212 7213 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 7214 XType, N0, 7215 DAG.getConstant(XType.getSizeInBits()-1, 7216 getShiftAmountTy(N0.getValueType()))); 7217 AddToWorkList(Shift.getNode()); 7218 7219 if (XType.bitsGT(AType)) { 7220 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7221 AddToWorkList(Shift.getNode()); 7222 } 7223 7224 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7225 } 7226 } 7227 7228 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 7229 // where y is has a single bit set. 7230 // A plaintext description would be, we can turn the SELECT_CC into an AND 7231 // when the condition can be materialized as an all-ones register. Any 7232 // single bit-test can be materialized as an all-ones register with 7233 // shift-left and shift-right-arith. 7234 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 7235 N0->getValueType(0) == VT && 7236 N1C && N1C->isNullValue() && 7237 N2C && N2C->isNullValue()) { 7238 SDValue AndLHS = N0->getOperand(0); 7239 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 7240 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 7241 // Shift the tested bit over the sign bit. 7242 APInt AndMask = ConstAndRHS->getAPIntValue(); 7243 SDValue ShlAmt = 7244 DAG.getConstant(AndMask.countLeadingZeros(), 7245 getShiftAmountTy(AndLHS.getValueType())); 7246 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 7247 7248 // Now arithmetic right shift it all the way over, so the result is either 7249 // all-ones, or zero. 7250 SDValue ShrAmt = 7251 DAG.getConstant(AndMask.getBitWidth()-1, 7252 getShiftAmountTy(Shl.getValueType())); 7253 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 7254 7255 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 7256 } 7257 } 7258 7259 // fold select C, 16, 0 -> shl C, 4 7260 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 7261 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 7262 7263 // If the caller doesn't want us to simplify this into a zext of a compare, 7264 // don't do it. 7265 if (NotExtCompare && N2C->getAPIntValue() == 1) 7266 return SDValue(); 7267 7268 // Get a SetCC of the condition 7269 // FIXME: Should probably make sure that setcc is legal if we ever have a 7270 // target where it isn't. 7271 SDValue Temp, SCC; 7272 // cast from setcc result type to select result type 7273 if (LegalTypes) { 7274 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 7275 N0, N1, CC); 7276 if (N2.getValueType().bitsLT(SCC.getValueType())) 7277 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 7278 else 7279 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7280 N2.getValueType(), SCC); 7281 } else { 7282 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 7283 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7284 N2.getValueType(), SCC); 7285 } 7286 7287 AddToWorkList(SCC.getNode()); 7288 AddToWorkList(Temp.getNode()); 7289 7290 if (N2C->getAPIntValue() == 1) 7291 return Temp; 7292 7293 // shl setcc result by log2 n2c 7294 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 7295 DAG.getConstant(N2C->getAPIntValue().logBase2(), 7296 getShiftAmountTy(Temp.getValueType()))); 7297 } 7298 7299 // Check to see if this is the equivalent of setcc 7300 // FIXME: Turn all of these into setcc if setcc if setcc is legal 7301 // otherwise, go ahead with the folds. 7302 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 7303 EVT XType = N0.getValueType(); 7304 if (!LegalOperations || 7305 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 7306 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 7307 if (Res.getValueType() != VT) 7308 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 7309 return Res; 7310 } 7311 7312 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 7313 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 7314 (!LegalOperations || 7315 TLI.isOperationLegal(ISD::CTLZ, XType))) { 7316 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 7317 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 7318 DAG.getConstant(Log2_32(XType.getSizeInBits()), 7319 getShiftAmountTy(Ctlz.getValueType()))); 7320 } 7321 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 7322 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 7323 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 7324 XType, DAG.getConstant(0, XType), N0); 7325 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 7326 return DAG.getNode(ISD::SRL, DL, XType, 7327 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 7328 DAG.getConstant(XType.getSizeInBits()-1, 7329 getShiftAmountTy(XType))); 7330 } 7331 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 7332 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 7333 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 7334 DAG.getConstant(XType.getSizeInBits()-1, 7335 getShiftAmountTy(N0.getValueType()))); 7336 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 7337 } 7338 } 7339 7340 // Check to see if this is an integer abs. 7341 // select_cc setg[te] X, 0, X, -X -> 7342 // select_cc setgt X, -1, X, -X -> 7343 // select_cc setl[te] X, 0, -X, X -> 7344 // select_cc setlt X, 1, -X, X -> 7345 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 7346 if (N1C) { 7347 ConstantSDNode *SubC = NULL; 7348 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 7349 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 7350 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 7351 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 7352 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 7353 (N1C->isOne() && CC == ISD::SETLT)) && 7354 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 7355 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 7356 7357 EVT XType = N0.getValueType(); 7358 if (SubC && SubC->isNullValue() && XType.isInteger()) { 7359 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 7360 N0, 7361 DAG.getConstant(XType.getSizeInBits()-1, 7362 getShiftAmountTy(N0.getValueType()))); 7363 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 7364 XType, N0, Shift); 7365 AddToWorkList(Shift.getNode()); 7366 AddToWorkList(Add.getNode()); 7367 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 7368 } 7369 } 7370 7371 return SDValue(); 7372} 7373 7374/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 7375SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 7376 SDValue N1, ISD::CondCode Cond, 7377 DebugLoc DL, bool foldBooleans) { 7378 TargetLowering::DAGCombinerInfo 7379 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 7380 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 7381} 7382 7383/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 7384/// return a DAG expression to select that will generate the same value by 7385/// multiplying by a magic number. See: 7386/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7387SDValue DAGCombiner::BuildSDIV(SDNode *N) { 7388 std::vector<SDNode*> Built; 7389 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 7390 7391 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7392 ii != ee; ++ii) 7393 AddToWorkList(*ii); 7394 return S; 7395} 7396 7397/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 7398/// return a DAG expression to select that will generate the same value by 7399/// multiplying by a magic number. See: 7400/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7401SDValue DAGCombiner::BuildUDIV(SDNode *N) { 7402 std::vector<SDNode*> Built; 7403 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 7404 7405 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7406 ii != ee; ++ii) 7407 AddToWorkList(*ii); 7408 return S; 7409} 7410 7411/// FindBaseOffset - Return true if base is a frame index, which is known not 7412// to alias with anything but itself. Provides base object and offset as 7413// results. 7414static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 7415 const GlobalValue *&GV, void *&CV) { 7416 // Assume it is a primitive operation. 7417 Base = Ptr; Offset = 0; GV = 0; CV = 0; 7418 7419 // If it's an adding a simple constant then integrate the offset. 7420 if (Base.getOpcode() == ISD::ADD) { 7421 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 7422 Base = Base.getOperand(0); 7423 Offset += C->getZExtValue(); 7424 } 7425 } 7426 7427 // Return the underlying GlobalValue, and update the Offset. Return false 7428 // for GlobalAddressSDNode since the same GlobalAddress may be represented 7429 // by multiple nodes with different offsets. 7430 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 7431 GV = G->getGlobal(); 7432 Offset += G->getOffset(); 7433 return false; 7434 } 7435 7436 // Return the underlying Constant value, and update the Offset. Return false 7437 // for ConstantSDNodes since the same constant pool entry may be represented 7438 // by multiple nodes with different offsets. 7439 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 7440 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 7441 : (void *)C->getConstVal(); 7442 Offset += C->getOffset(); 7443 return false; 7444 } 7445 // If it's any of the following then it can't alias with anything but itself. 7446 return isa<FrameIndexSDNode>(Base); 7447} 7448 7449/// isAlias - Return true if there is any possibility that the two addresses 7450/// overlap. 7451bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 7452 const Value *SrcValue1, int SrcValueOffset1, 7453 unsigned SrcValueAlign1, 7454 const MDNode *TBAAInfo1, 7455 SDValue Ptr2, int64_t Size2, 7456 const Value *SrcValue2, int SrcValueOffset2, 7457 unsigned SrcValueAlign2, 7458 const MDNode *TBAAInfo2) const { 7459 // If they are the same then they must be aliases. 7460 if (Ptr1 == Ptr2) return true; 7461 7462 // Gather base node and offset information. 7463 SDValue Base1, Base2; 7464 int64_t Offset1, Offset2; 7465 const GlobalValue *GV1, *GV2; 7466 void *CV1, *CV2; 7467 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 7468 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 7469 7470 // If they have a same base address then check to see if they overlap. 7471 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 7472 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7473 7474 // It is possible for different frame indices to alias each other, mostly 7475 // when tail call optimization reuses return address slots for arguments. 7476 // To catch this case, look up the actual index of frame indices to compute 7477 // the real alias relationship. 7478 if (isFrameIndex1 && isFrameIndex2) { 7479 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7480 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 7481 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 7482 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7483 } 7484 7485 // Otherwise, if we know what the bases are, and they aren't identical, then 7486 // we know they cannot alias. 7487 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 7488 return false; 7489 7490 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 7491 // compared to the size and offset of the access, we may be able to prove they 7492 // do not alias. This check is conservative for now to catch cases created by 7493 // splitting vector types. 7494 if ((SrcValueAlign1 == SrcValueAlign2) && 7495 (SrcValueOffset1 != SrcValueOffset2) && 7496 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 7497 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 7498 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 7499 7500 // There is no overlap between these relatively aligned accesses of similar 7501 // size, return no alias. 7502 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 7503 return false; 7504 } 7505 7506 if (CombinerGlobalAA) { 7507 // Use alias analysis information. 7508 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 7509 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 7510 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 7511 AliasAnalysis::AliasResult AAResult = 7512 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 7513 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 7514 if (AAResult == AliasAnalysis::NoAlias) 7515 return false; 7516 } 7517 7518 // Otherwise we have to assume they alias. 7519 return true; 7520} 7521 7522/// FindAliasInfo - Extracts the relevant alias information from the memory 7523/// node. Returns true if the operand was a load. 7524bool DAGCombiner::FindAliasInfo(SDNode *N, 7525 SDValue &Ptr, int64_t &Size, 7526 const Value *&SrcValue, 7527 int &SrcValueOffset, 7528 unsigned &SrcValueAlign, 7529 const MDNode *&TBAAInfo) const { 7530 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7531 Ptr = LD->getBasePtr(); 7532 Size = LD->getMemoryVT().getSizeInBits() >> 3; 7533 SrcValue = LD->getSrcValue(); 7534 SrcValueOffset = LD->getSrcValueOffset(); 7535 SrcValueAlign = LD->getOriginalAlignment(); 7536 TBAAInfo = LD->getTBAAInfo(); 7537 return true; 7538 } 7539 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7540 Ptr = ST->getBasePtr(); 7541 Size = ST->getMemoryVT().getSizeInBits() >> 3; 7542 SrcValue = ST->getSrcValue(); 7543 SrcValueOffset = ST->getSrcValueOffset(); 7544 SrcValueAlign = ST->getOriginalAlignment(); 7545 TBAAInfo = ST->getTBAAInfo(); 7546 return false; 7547 } 7548 llvm_unreachable("FindAliasInfo expected a memory operand"); 7549} 7550 7551/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 7552/// looking for aliasing nodes and adding them to the Aliases vector. 7553void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 7554 SmallVector<SDValue, 8> &Aliases) { 7555 SmallVector<SDValue, 8> Chains; // List of chains to visit. 7556 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 7557 7558 // Get alias information for node. 7559 SDValue Ptr; 7560 int64_t Size; 7561 const Value *SrcValue; 7562 int SrcValueOffset; 7563 unsigned SrcValueAlign; 7564 const MDNode *SrcTBAAInfo; 7565 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 7566 SrcValueAlign, SrcTBAAInfo); 7567 7568 // Starting off. 7569 Chains.push_back(OriginalChain); 7570 unsigned Depth = 0; 7571 7572 // Look at each chain and determine if it is an alias. If so, add it to the 7573 // aliases list. If not, then continue up the chain looking for the next 7574 // candidate. 7575 while (!Chains.empty()) { 7576 SDValue Chain = Chains.back(); 7577 Chains.pop_back(); 7578 7579 // For TokenFactor nodes, look at each operand and only continue up the 7580 // chain until we find two aliases. If we've seen two aliases, assume we'll 7581 // find more and revert to original chain since the xform is unlikely to be 7582 // profitable. 7583 // 7584 // FIXME: The depth check could be made to return the last non-aliasing 7585 // chain we found before we hit a tokenfactor rather than the original 7586 // chain. 7587 if (Depth > 6 || Aliases.size() == 2) { 7588 Aliases.clear(); 7589 Aliases.push_back(OriginalChain); 7590 break; 7591 } 7592 7593 // Don't bother if we've been before. 7594 if (!Visited.insert(Chain.getNode())) 7595 continue; 7596 7597 switch (Chain.getOpcode()) { 7598 case ISD::EntryToken: 7599 // Entry token is ideal chain operand, but handled in FindBetterChain. 7600 break; 7601 7602 case ISD::LOAD: 7603 case ISD::STORE: { 7604 // Get alias information for Chain. 7605 SDValue OpPtr; 7606 int64_t OpSize; 7607 const Value *OpSrcValue; 7608 int OpSrcValueOffset; 7609 unsigned OpSrcValueAlign; 7610 const MDNode *OpSrcTBAAInfo; 7611 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 7612 OpSrcValue, OpSrcValueOffset, 7613 OpSrcValueAlign, 7614 OpSrcTBAAInfo); 7615 7616 // If chain is alias then stop here. 7617 if (!(IsLoad && IsOpLoad) && 7618 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 7619 SrcTBAAInfo, 7620 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 7621 OpSrcValueAlign, OpSrcTBAAInfo)) { 7622 Aliases.push_back(Chain); 7623 } else { 7624 // Look further up the chain. 7625 Chains.push_back(Chain.getOperand(0)); 7626 ++Depth; 7627 } 7628 break; 7629 } 7630 7631 case ISD::TokenFactor: 7632 // We have to check each of the operands of the token factor for "small" 7633 // token factors, so we queue them up. Adding the operands to the queue 7634 // (stack) in reverse order maintains the original order and increases the 7635 // likelihood that getNode will find a matching token factor (CSE.) 7636 if (Chain.getNumOperands() > 16) { 7637 Aliases.push_back(Chain); 7638 break; 7639 } 7640 for (unsigned n = Chain.getNumOperands(); n;) 7641 Chains.push_back(Chain.getOperand(--n)); 7642 ++Depth; 7643 break; 7644 7645 default: 7646 // For all other instructions we will just have to take what we can get. 7647 Aliases.push_back(Chain); 7648 break; 7649 } 7650 } 7651} 7652 7653/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 7654/// for a better chain (aliasing node.) 7655SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 7656 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 7657 7658 // Accumulate all the aliases to this node. 7659 GatherAllAliases(N, OldChain, Aliases); 7660 7661 // If no operands then chain to entry token. 7662 if (Aliases.size() == 0) 7663 return DAG.getEntryNode(); 7664 7665 // If a single operand then chain to it. We don't need to revisit it. 7666 if (Aliases.size() == 1) 7667 return Aliases[0]; 7668 7669 // Construct a custom tailored token factor. 7670 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7671 &Aliases[0], Aliases.size()); 7672} 7673 7674// SelectionDAG::Combine - This is the entry point for the file. 7675// 7676void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 7677 CodeGenOpt::Level OptLevel) { 7678 /// run - This is the main entry point to this class. 7679 /// 7680 DAGCombiner(*this, AA, OptLevel).Run(Level); 7681} 7682