DAGCombiner.cpp revision 202878
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 133 /// combine - call the node-specific routine that knows how to fold each 134 /// particular type of node. If that doesn't do anything, try the 135 /// target-specific DAG combines. 136 SDValue combine(SDNode *N); 137 138 // Visitation implementation - Implement dag node combining for different 139 // node types. The semantics are as follows: 140 // Return Value: 141 // SDValue.getNode() == 0 - No change was made 142 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 143 // otherwise - N should be replaced by the returned Operand. 144 // 145 SDValue visitTokenFactor(SDNode *N); 146 SDValue visitMERGE_VALUES(SDNode *N); 147 SDValue visitADD(SDNode *N); 148 SDValue visitSUB(SDNode *N); 149 SDValue visitADDC(SDNode *N); 150 SDValue visitADDE(SDNode *N); 151 SDValue visitMUL(SDNode *N); 152 SDValue visitSDIV(SDNode *N); 153 SDValue visitUDIV(SDNode *N); 154 SDValue visitSREM(SDNode *N); 155 SDValue visitUREM(SDNode *N); 156 SDValue visitMULHU(SDNode *N); 157 SDValue visitMULHS(SDNode *N); 158 SDValue visitSMUL_LOHI(SDNode *N); 159 SDValue visitUMUL_LOHI(SDNode *N); 160 SDValue visitSDIVREM(SDNode *N); 161 SDValue visitUDIVREM(SDNode *N); 162 SDValue visitAND(SDNode *N); 163 SDValue visitOR(SDNode *N); 164 SDValue visitXOR(SDNode *N); 165 SDValue SimplifyVBinOp(SDNode *N); 166 SDValue visitSHL(SDNode *N); 167 SDValue visitSRA(SDNode *N); 168 SDValue visitSRL(SDNode *N); 169 SDValue visitCTLZ(SDNode *N); 170 SDValue visitCTTZ(SDNode *N); 171 SDValue visitCTPOP(SDNode *N); 172 SDValue visitSELECT(SDNode *N); 173 SDValue visitSELECT_CC(SDNode *N); 174 SDValue visitSETCC(SDNode *N); 175 SDValue visitSIGN_EXTEND(SDNode *N); 176 SDValue visitZERO_EXTEND(SDNode *N); 177 SDValue visitANY_EXTEND(SDNode *N); 178 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 179 SDValue visitTRUNCATE(SDNode *N); 180 SDValue visitBIT_CONVERT(SDNode *N); 181 SDValue visitBUILD_PAIR(SDNode *N); 182 SDValue visitFADD(SDNode *N); 183 SDValue visitFSUB(SDNode *N); 184 SDValue visitFMUL(SDNode *N); 185 SDValue visitFDIV(SDNode *N); 186 SDValue visitFREM(SDNode *N); 187 SDValue visitFCOPYSIGN(SDNode *N); 188 SDValue visitSINT_TO_FP(SDNode *N); 189 SDValue visitUINT_TO_FP(SDNode *N); 190 SDValue visitFP_TO_SINT(SDNode *N); 191 SDValue visitFP_TO_UINT(SDNode *N); 192 SDValue visitFP_ROUND(SDNode *N); 193 SDValue visitFP_ROUND_INREG(SDNode *N); 194 SDValue visitFP_EXTEND(SDNode *N); 195 SDValue visitFNEG(SDNode *N); 196 SDValue visitFABS(SDNode *N); 197 SDValue visitBRCOND(SDNode *N); 198 SDValue visitBR_CC(SDNode *N); 199 SDValue visitLOAD(SDNode *N); 200 SDValue visitSTORE(SDNode *N); 201 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 203 SDValue visitBUILD_VECTOR(SDNode *N); 204 SDValue visitCONCAT_VECTORS(SDNode *N); 205 SDValue visitVECTOR_SHUFFLE(SDNode *N); 206 207 SDValue XformToShuffleWithZero(SDNode *N); 208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 209 210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 216 SDValue N3, ISD::CondCode CC, 217 bool NotExtCompare = false); 218 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 219 DebugLoc DL, bool foldBooleans = true); 220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 221 unsigned HiOp); 222 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); 224 SDValue BuildSDIV(SDNode *N); 225 SDValue BuildUDIV(SDNode *N); 226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 227 SDValue ReduceLoadWidth(SDNode *N); 228 SDValue ReduceLoadOpStoreWidth(SDNode *N); 229 230 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 231 232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 233 /// looking for aliasing nodes and adding them to the Aliases vector. 234 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 235 SmallVector<SDValue, 8> &Aliases); 236 237 /// isAlias - Return true if there is any possibility that the two addresses 238 /// overlap. 239 bool isAlias(SDValue Ptr1, int64_t Size1, 240 const Value *SrcValue1, int SrcValueOffset1, 241 unsigned SrcValueAlign1, 242 SDValue Ptr2, int64_t Size2, 243 const Value *SrcValue2, int SrcValueOffset2, 244 unsigned SrcValueAlign2) const; 245 246 /// FindAliasInfo - Extracts the relevant alias information from the memory 247 /// node. Returns true if the operand was a load. 248 bool FindAliasInfo(SDNode *N, 249 SDValue &Ptr, int64_t &Size, 250 const Value *&SrcValue, int &SrcValueOffset, 251 unsigned &SrcValueAlignment) const; 252 253 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 254 /// looking for a better chain (aliasing node.) 255 SDValue FindBetterChain(SDNode *N, SDValue Chain); 256 257 /// getShiftAmountTy - Returns a type large enough to hold any valid 258 /// shift amount - before type legalization these can be huge. 259 EVT getShiftAmountTy() { 260 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 261 } 262 263public: 264 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 265 : DAG(D), 266 TLI(D.getTargetLoweringInfo()), 267 Level(Unrestricted), 268 OptLevel(OL), 269 LegalOperations(false), 270 LegalTypes(false), 271 AA(A) {} 272 273 /// Run - runs the dag combiner on all nodes in the work list 274 void Run(CombineLevel AtLevel); 275 }; 276} 277 278 279namespace { 280/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 281/// nodes from the worklist. 282class WorkListRemover : public SelectionDAG::DAGUpdateListener { 283 DAGCombiner &DC; 284public: 285 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 286 287 virtual void NodeDeleted(SDNode *N, SDNode *E) { 288 DC.removeFromWorkList(N); 289 } 290 291 virtual void NodeUpdated(SDNode *N) { 292 // Ignore updates. 293 } 294}; 295} 296 297//===----------------------------------------------------------------------===// 298// TargetLowering::DAGCombinerInfo implementation 299//===----------------------------------------------------------------------===// 300 301void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 302 ((DAGCombiner*)DC)->AddToWorkList(N); 303} 304 305SDValue TargetLowering::DAGCombinerInfo:: 306CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 307 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 308} 309 310SDValue TargetLowering::DAGCombinerInfo:: 311CombineTo(SDNode *N, SDValue Res, bool AddTo) { 312 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 313} 314 315 316SDValue TargetLowering::DAGCombinerInfo:: 317CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 318 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 319} 320 321void TargetLowering::DAGCombinerInfo:: 322CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 323 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 324} 325 326//===----------------------------------------------------------------------===// 327// Helper Functions 328//===----------------------------------------------------------------------===// 329 330/// isNegatibleForFree - Return 1 if we can compute the negated form of the 331/// specified expression for the same cost as the expression itself, or 2 if we 332/// can compute the negated form more cheaply than the expression itself. 333static char isNegatibleForFree(SDValue Op, bool LegalOperations, 334 unsigned Depth = 0) { 335 // No compile time optimizations on this type. 336 if (Op.getValueType() == MVT::ppcf128) 337 return 0; 338 339 // fneg is removable even if it has multiple uses. 340 if (Op.getOpcode() == ISD::FNEG) return 2; 341 342 // Don't allow anything with multiple uses. 343 if (!Op.hasOneUse()) return 0; 344 345 // Don't recurse exponentially. 346 if (Depth > 6) return 0; 347 348 switch (Op.getOpcode()) { 349 default: return false; 350 case ISD::ConstantFP: 351 // Don't invert constant FP values after legalize. The negated constant 352 // isn't necessarily legal. 353 return LegalOperations ? 0 : 1; 354 case ISD::FADD: 355 // FIXME: determine better conditions for this xform. 356 if (!UnsafeFPMath) return 0; 357 358 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 359 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 360 return V; 361 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 362 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 363 case ISD::FSUB: 364 // We can't turn -(A-B) into B-A when we honor signed zeros. 365 if (!UnsafeFPMath) return 0; 366 367 // fold (fneg (fsub A, B)) -> (fsub B, A) 368 return 1; 369 370 case ISD::FMUL: 371 case ISD::FDIV: 372 if (HonorSignDependentRoundingFPMath()) return 0; 373 374 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 375 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 376 return V; 377 378 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 379 380 case ISD::FP_EXTEND: 381 case ISD::FP_ROUND: 382 case ISD::FSIN: 383 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 384 } 385} 386 387/// GetNegatedExpression - If isNegatibleForFree returns true, this function 388/// returns the newly negated expression. 389static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 390 bool LegalOperations, unsigned Depth = 0) { 391 // fneg is removable even if it has multiple uses. 392 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 393 394 // Don't allow anything with multiple uses. 395 assert(Op.hasOneUse() && "Unknown reuse!"); 396 397 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 398 switch (Op.getOpcode()) { 399 default: llvm_unreachable("Unknown code"); 400 case ISD::ConstantFP: { 401 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 402 V.changeSign(); 403 return DAG.getConstantFP(V, Op.getValueType()); 404 } 405 case ISD::FADD: 406 // FIXME: determine better conditions for this xform. 407 assert(UnsafeFPMath); 408 409 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 410 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 411 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 412 GetNegatedExpression(Op.getOperand(0), DAG, 413 LegalOperations, Depth+1), 414 Op.getOperand(1)); 415 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 416 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 417 GetNegatedExpression(Op.getOperand(1), DAG, 418 LegalOperations, Depth+1), 419 Op.getOperand(0)); 420 case ISD::FSUB: 421 // We can't turn -(A-B) into B-A when we honor signed zeros. 422 assert(UnsafeFPMath); 423 424 // fold (fneg (fsub 0, B)) -> B 425 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 426 if (N0CFP->getValueAPF().isZero()) 427 return Op.getOperand(1); 428 429 // fold (fneg (fsub A, B)) -> (fsub B, A) 430 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 431 Op.getOperand(1), Op.getOperand(0)); 432 433 case ISD::FMUL: 434 case ISD::FDIV: 435 assert(!HonorSignDependentRoundingFPMath()); 436 437 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 438 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 439 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 440 GetNegatedExpression(Op.getOperand(0), DAG, 441 LegalOperations, Depth+1), 442 Op.getOperand(1)); 443 444 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 445 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 446 Op.getOperand(0), 447 GetNegatedExpression(Op.getOperand(1), DAG, 448 LegalOperations, Depth+1)); 449 450 case ISD::FP_EXTEND: 451 case ISD::FSIN: 452 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 453 GetNegatedExpression(Op.getOperand(0), DAG, 454 LegalOperations, Depth+1)); 455 case ISD::FP_ROUND: 456 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 457 GetNegatedExpression(Op.getOperand(0), DAG, 458 LegalOperations, Depth+1), 459 Op.getOperand(1)); 460 } 461} 462 463 464// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 465// that selects between the values 1 and 0, making it equivalent to a setcc. 466// Also, set the incoming LHS, RHS, and CC references to the appropriate 467// nodes based on the type of node we are checking. This simplifies life a 468// bit for the callers. 469static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 470 SDValue &CC) { 471 if (N.getOpcode() == ISD::SETCC) { 472 LHS = N.getOperand(0); 473 RHS = N.getOperand(1); 474 CC = N.getOperand(2); 475 return true; 476 } 477 if (N.getOpcode() == ISD::SELECT_CC && 478 N.getOperand(2).getOpcode() == ISD::Constant && 479 N.getOperand(3).getOpcode() == ISD::Constant && 480 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 481 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 482 LHS = N.getOperand(0); 483 RHS = N.getOperand(1); 484 CC = N.getOperand(4); 485 return true; 486 } 487 return false; 488} 489 490// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 491// one use. If this is true, it allows the users to invert the operation for 492// free when it is profitable to do so. 493static bool isOneUseSetCC(SDValue N) { 494 SDValue N0, N1, N2; 495 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 496 return true; 497 return false; 498} 499 500SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 501 SDValue N0, SDValue N1) { 502 EVT VT = N0.getValueType(); 503 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 504 if (isa<ConstantSDNode>(N1)) { 505 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 506 SDValue OpNode = 507 DAG.FoldConstantArithmetic(Opc, VT, 508 cast<ConstantSDNode>(N0.getOperand(1)), 509 cast<ConstantSDNode>(N1)); 510 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 511 } else if (N0.hasOneUse()) { 512 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 513 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 514 N0.getOperand(0), N1); 515 AddToWorkList(OpNode.getNode()); 516 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 517 } 518 } 519 520 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 521 if (isa<ConstantSDNode>(N0)) { 522 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 523 SDValue OpNode = 524 DAG.FoldConstantArithmetic(Opc, VT, 525 cast<ConstantSDNode>(N1.getOperand(1)), 526 cast<ConstantSDNode>(N0)); 527 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 528 } else if (N1.hasOneUse()) { 529 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 530 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 531 N1.getOperand(0), N0); 532 AddToWorkList(OpNode.getNode()); 533 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 534 } 535 } 536 537 return SDValue(); 538} 539 540SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 541 bool AddTo) { 542 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 543 ++NodesCombined; 544 DEBUG(dbgs() << "\nReplacing.1 "; 545 N->dump(&DAG); 546 dbgs() << "\nWith: "; 547 To[0].getNode()->dump(&DAG); 548 dbgs() << " and " << NumTo-1 << " other values\n"; 549 for (unsigned i = 0, e = NumTo; i != e; ++i) 550 assert((!To[i].getNode() || 551 N->getValueType(i) == To[i].getValueType()) && 552 "Cannot combine value to value of different type!")); 553 WorkListRemover DeadNodes(*this); 554 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 555 556 if (AddTo) { 557 // Push the new nodes and any users onto the worklist 558 for (unsigned i = 0, e = NumTo; i != e; ++i) { 559 if (To[i].getNode()) { 560 AddToWorkList(To[i].getNode()); 561 AddUsersToWorkList(To[i].getNode()); 562 } 563 } 564 } 565 566 // Finally, if the node is now dead, remove it from the graph. The node 567 // may not be dead if the replacement process recursively simplified to 568 // something else needing this node. 569 if (N->use_empty()) { 570 // Nodes can be reintroduced into the worklist. Make sure we do not 571 // process a node that has been replaced. 572 removeFromWorkList(N); 573 574 // Finally, since the node is now dead, remove it from the graph. 575 DAG.DeleteNode(N); 576 } 577 return SDValue(N, 0); 578} 579 580void 581DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 582 TLO) { 583 // Replace all uses. If any nodes become isomorphic to other nodes and 584 // are deleted, make sure to remove them from our worklist. 585 WorkListRemover DeadNodes(*this); 586 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 587 588 // Push the new node and any (possibly new) users onto the worklist. 589 AddToWorkList(TLO.New.getNode()); 590 AddUsersToWorkList(TLO.New.getNode()); 591 592 // Finally, if the node is now dead, remove it from the graph. The node 593 // may not be dead if the replacement process recursively simplified to 594 // something else needing this node. 595 if (TLO.Old.getNode()->use_empty()) { 596 removeFromWorkList(TLO.Old.getNode()); 597 598 // If the operands of this node are only used by the node, they will now 599 // be dead. Make sure to visit them first to delete dead nodes early. 600 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 601 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 602 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 603 604 DAG.DeleteNode(TLO.Old.getNode()); 605 } 606} 607 608/// SimplifyDemandedBits - Check the specified integer node value to see if 609/// it can be simplified or if things it uses can be simplified by bit 610/// propagation. If so, return true. 611bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 612 TargetLowering::TargetLoweringOpt TLO(DAG); 613 APInt KnownZero, KnownOne; 614 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 615 return false; 616 617 // Revisit the node. 618 AddToWorkList(Op.getNode()); 619 620 // Replace the old value with the new one. 621 ++NodesCombined; 622 DEBUG(dbgs() << "\nReplacing.2 "; 623 TLO.Old.getNode()->dump(&DAG); 624 dbgs() << "\nWith: "; 625 TLO.New.getNode()->dump(&DAG); 626 dbgs() << '\n'); 627 628 CommitTargetLoweringOpt(TLO); 629 return true; 630} 631 632//===----------------------------------------------------------------------===// 633// Main DAG Combiner implementation 634//===----------------------------------------------------------------------===// 635 636void DAGCombiner::Run(CombineLevel AtLevel) { 637 // set the instance variables, so that the various visit routines may use it. 638 Level = AtLevel; 639 LegalOperations = Level >= NoIllegalOperations; 640 LegalTypes = Level >= NoIllegalTypes; 641 642 // Add all the dag nodes to the worklist. 643 WorkList.reserve(DAG.allnodes_size()); 644 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 645 E = DAG.allnodes_end(); I != E; ++I) 646 WorkList.push_back(I); 647 648 // Create a dummy node (which is not added to allnodes), that adds a reference 649 // to the root node, preventing it from being deleted, and tracking any 650 // changes of the root. 651 HandleSDNode Dummy(DAG.getRoot()); 652 653 // The root of the dag may dangle to deleted nodes until the dag combiner is 654 // done. Set it to null to avoid confusion. 655 DAG.setRoot(SDValue()); 656 657 // while the worklist isn't empty, inspect the node on the end of it and 658 // try and combine it. 659 while (!WorkList.empty()) { 660 SDNode *N = WorkList.back(); 661 WorkList.pop_back(); 662 663 // If N has no uses, it is dead. Make sure to revisit all N's operands once 664 // N is deleted from the DAG, since they too may now be dead or may have a 665 // reduced number of uses, allowing other xforms. 666 if (N->use_empty() && N != &Dummy) { 667 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 668 AddToWorkList(N->getOperand(i).getNode()); 669 670 DAG.DeleteNode(N); 671 continue; 672 } 673 674 SDValue RV = combine(N); 675 676 if (RV.getNode() == 0) 677 continue; 678 679 ++NodesCombined; 680 681 // If we get back the same node we passed in, rather than a new node or 682 // zero, we know that the node must have defined multiple values and 683 // CombineTo was used. Since CombineTo takes care of the worklist 684 // mechanics for us, we have no work to do in this case. 685 if (RV.getNode() == N) 686 continue; 687 688 assert(N->getOpcode() != ISD::DELETED_NODE && 689 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 690 "Node was deleted but visit returned new node!"); 691 692 DEBUG(dbgs() << "\nReplacing.3 "; 693 N->dump(&DAG); 694 dbgs() << "\nWith: "; 695 RV.getNode()->dump(&DAG); 696 dbgs() << '\n'); 697 WorkListRemover DeadNodes(*this); 698 if (N->getNumValues() == RV.getNode()->getNumValues()) 699 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 700 else { 701 assert(N->getValueType(0) == RV.getValueType() && 702 N->getNumValues() == 1 && "Type mismatch"); 703 SDValue OpV = RV; 704 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 705 } 706 707 // Push the new node and any users onto the worklist 708 AddToWorkList(RV.getNode()); 709 AddUsersToWorkList(RV.getNode()); 710 711 // Add any uses of the old node to the worklist in case this node is the 712 // last one that uses them. They may become dead after this node is 713 // deleted. 714 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 715 AddToWorkList(N->getOperand(i).getNode()); 716 717 // Finally, if the node is now dead, remove it from the graph. The node 718 // may not be dead if the replacement process recursively simplified to 719 // something else needing this node. 720 if (N->use_empty()) { 721 // Nodes can be reintroduced into the worklist. Make sure we do not 722 // process a node that has been replaced. 723 removeFromWorkList(N); 724 725 // Finally, since the node is now dead, remove it from the graph. 726 DAG.DeleteNode(N); 727 } 728 } 729 730 // If the root changed (e.g. it was a dead load, update the root). 731 DAG.setRoot(Dummy.getValue()); 732} 733 734SDValue DAGCombiner::visit(SDNode *N) { 735 switch(N->getOpcode()) { 736 default: break; 737 case ISD::TokenFactor: return visitTokenFactor(N); 738 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 739 case ISD::ADD: return visitADD(N); 740 case ISD::SUB: return visitSUB(N); 741 case ISD::ADDC: return visitADDC(N); 742 case ISD::ADDE: return visitADDE(N); 743 case ISD::MUL: return visitMUL(N); 744 case ISD::SDIV: return visitSDIV(N); 745 case ISD::UDIV: return visitUDIV(N); 746 case ISD::SREM: return visitSREM(N); 747 case ISD::UREM: return visitUREM(N); 748 case ISD::MULHU: return visitMULHU(N); 749 case ISD::MULHS: return visitMULHS(N); 750 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 751 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 752 case ISD::SDIVREM: return visitSDIVREM(N); 753 case ISD::UDIVREM: return visitUDIVREM(N); 754 case ISD::AND: return visitAND(N); 755 case ISD::OR: return visitOR(N); 756 case ISD::XOR: return visitXOR(N); 757 case ISD::SHL: return visitSHL(N); 758 case ISD::SRA: return visitSRA(N); 759 case ISD::SRL: return visitSRL(N); 760 case ISD::CTLZ: return visitCTLZ(N); 761 case ISD::CTTZ: return visitCTTZ(N); 762 case ISD::CTPOP: return visitCTPOP(N); 763 case ISD::SELECT: return visitSELECT(N); 764 case ISD::SELECT_CC: return visitSELECT_CC(N); 765 case ISD::SETCC: return visitSETCC(N); 766 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 767 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 768 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 769 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 770 case ISD::TRUNCATE: return visitTRUNCATE(N); 771 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 772 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 773 case ISD::FADD: return visitFADD(N); 774 case ISD::FSUB: return visitFSUB(N); 775 case ISD::FMUL: return visitFMUL(N); 776 case ISD::FDIV: return visitFDIV(N); 777 case ISD::FREM: return visitFREM(N); 778 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 779 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 780 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 781 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 782 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 783 case ISD::FP_ROUND: return visitFP_ROUND(N); 784 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 785 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 786 case ISD::FNEG: return visitFNEG(N); 787 case ISD::FABS: return visitFABS(N); 788 case ISD::BRCOND: return visitBRCOND(N); 789 case ISD::BR_CC: return visitBR_CC(N); 790 case ISD::LOAD: return visitLOAD(N); 791 case ISD::STORE: return visitSTORE(N); 792 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 793 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 794 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 795 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 796 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 797 } 798 return SDValue(); 799} 800 801SDValue DAGCombiner::combine(SDNode *N) { 802 SDValue RV = visit(N); 803 804 // If nothing happened, try a target-specific DAG combine. 805 if (RV.getNode() == 0) { 806 assert(N->getOpcode() != ISD::DELETED_NODE && 807 "Node was deleted but visit returned NULL!"); 808 809 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 810 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 811 812 // Expose the DAG combiner to the target combiner impls. 813 TargetLowering::DAGCombinerInfo 814 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 815 816 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 817 } 818 } 819 820 // If N is a commutative binary node, try commuting it to enable more 821 // sdisel CSE. 822 if (RV.getNode() == 0 && 823 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 824 N->getNumValues() == 1) { 825 SDValue N0 = N->getOperand(0); 826 SDValue N1 = N->getOperand(1); 827 828 // Constant operands are canonicalized to RHS. 829 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 830 SDValue Ops[] = { N1, N0 }; 831 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 832 Ops, 2); 833 if (CSENode) 834 return SDValue(CSENode, 0); 835 } 836 } 837 838 return RV; 839} 840 841/// getInputChainForNode - Given a node, return its input chain if it has one, 842/// otherwise return a null sd operand. 843static SDValue getInputChainForNode(SDNode *N) { 844 if (unsigned NumOps = N->getNumOperands()) { 845 if (N->getOperand(0).getValueType() == MVT::Other) 846 return N->getOperand(0); 847 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 848 return N->getOperand(NumOps-1); 849 for (unsigned i = 1; i < NumOps-1; ++i) 850 if (N->getOperand(i).getValueType() == MVT::Other) 851 return N->getOperand(i); 852 } 853 return SDValue(); 854} 855 856SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 857 // If N has two operands, where one has an input chain equal to the other, 858 // the 'other' chain is redundant. 859 if (N->getNumOperands() == 2) { 860 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 861 return N->getOperand(0); 862 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 863 return N->getOperand(1); 864 } 865 866 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 867 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 868 SmallPtrSet<SDNode*, 16> SeenOps; 869 bool Changed = false; // If we should replace this token factor. 870 871 // Start out with this token factor. 872 TFs.push_back(N); 873 874 // Iterate through token factors. The TFs grows when new token factors are 875 // encountered. 876 for (unsigned i = 0; i < TFs.size(); ++i) { 877 SDNode *TF = TFs[i]; 878 879 // Check each of the operands. 880 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 881 SDValue Op = TF->getOperand(i); 882 883 switch (Op.getOpcode()) { 884 case ISD::EntryToken: 885 // Entry tokens don't need to be added to the list. They are 886 // rededundant. 887 Changed = true; 888 break; 889 890 case ISD::TokenFactor: 891 if (Op.hasOneUse() && 892 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 893 // Queue up for processing. 894 TFs.push_back(Op.getNode()); 895 // Clean up in case the token factor is removed. 896 AddToWorkList(Op.getNode()); 897 Changed = true; 898 break; 899 } 900 // Fall thru 901 902 default: 903 // Only add if it isn't already in the list. 904 if (SeenOps.insert(Op.getNode())) 905 Ops.push_back(Op); 906 else 907 Changed = true; 908 break; 909 } 910 } 911 } 912 913 SDValue Result; 914 915 // If we've change things around then replace token factor. 916 if (Changed) { 917 if (Ops.empty()) { 918 // The entry token is the only possible outcome. 919 Result = DAG.getEntryNode(); 920 } else { 921 // New and improved token factor. 922 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 923 MVT::Other, &Ops[0], Ops.size()); 924 } 925 926 // Don't add users to work list. 927 return CombineTo(N, Result, false); 928 } 929 930 return Result; 931} 932 933/// MERGE_VALUES can always be eliminated. 934SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 935 WorkListRemover DeadNodes(*this); 936 // Replacing results may cause a different MERGE_VALUES to suddenly 937 // be CSE'd with N, and carry its uses with it. Iterate until no 938 // uses remain, to ensure that the node can be safely deleted. 939 do { 940 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 941 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 942 &DeadNodes); 943 } while (!N->use_empty()); 944 removeFromWorkList(N); 945 DAG.DeleteNode(N); 946 return SDValue(N, 0); // Return N so it doesn't get rechecked! 947} 948 949static 950SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 951 SelectionDAG &DAG) { 952 EVT VT = N0.getValueType(); 953 SDValue N00 = N0.getOperand(0); 954 SDValue N01 = N0.getOperand(1); 955 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 956 957 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 958 isa<ConstantSDNode>(N00.getOperand(1))) { 959 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 960 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 961 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 962 N00.getOperand(0), N01), 963 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 964 N00.getOperand(1), N01)); 965 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 966 } 967 968 return SDValue(); 969} 970 971SDValue DAGCombiner::visitADD(SDNode *N) { 972 SDValue N0 = N->getOperand(0); 973 SDValue N1 = N->getOperand(1); 974 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 975 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 976 EVT VT = N0.getValueType(); 977 978 // fold vector ops 979 if (VT.isVector()) { 980 SDValue FoldedVOp = SimplifyVBinOp(N); 981 if (FoldedVOp.getNode()) return FoldedVOp; 982 } 983 984 // fold (add x, undef) -> undef 985 if (N0.getOpcode() == ISD::UNDEF) 986 return N0; 987 if (N1.getOpcode() == ISD::UNDEF) 988 return N1; 989 // fold (add c1, c2) -> c1+c2 990 if (N0C && N1C) 991 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 992 // canonicalize constant to RHS 993 if (N0C && !N1C) 994 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 995 // fold (add x, 0) -> x 996 if (N1C && N1C->isNullValue()) 997 return N0; 998 // fold (add Sym, c) -> Sym+c 999 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1000 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1001 GA->getOpcode() == ISD::GlobalAddress) 1002 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1003 GA->getOffset() + 1004 (uint64_t)N1C->getSExtValue()); 1005 // fold ((c1-A)+c2) -> (c1+c2)-A 1006 if (N1C && N0.getOpcode() == ISD::SUB) 1007 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1008 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1009 DAG.getConstant(N1C->getAPIntValue()+ 1010 N0C->getAPIntValue(), VT), 1011 N0.getOperand(1)); 1012 // reassociate add 1013 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1014 if (RADD.getNode() != 0) 1015 return RADD; 1016 // fold ((0-A) + B) -> B-A 1017 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1018 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1019 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1020 // fold (A + (0-B)) -> A-B 1021 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1022 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1023 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1024 // fold (A+(B-A)) -> B 1025 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1026 return N1.getOperand(0); 1027 // fold ((B-A)+A) -> B 1028 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1029 return N0.getOperand(0); 1030 // fold (A+(B-(A+C))) to (B-C) 1031 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1032 N0 == N1.getOperand(1).getOperand(0)) 1033 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1034 N1.getOperand(1).getOperand(1)); 1035 // fold (A+(B-(C+A))) to (B-C) 1036 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1037 N0 == N1.getOperand(1).getOperand(1)) 1038 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1039 N1.getOperand(1).getOperand(0)); 1040 // fold (A+((B-A)+or-C)) to (B+or-C) 1041 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1042 N1.getOperand(0).getOpcode() == ISD::SUB && 1043 N0 == N1.getOperand(0).getOperand(1)) 1044 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1045 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1046 1047 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1048 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1049 SDValue N00 = N0.getOperand(0); 1050 SDValue N01 = N0.getOperand(1); 1051 SDValue N10 = N1.getOperand(0); 1052 SDValue N11 = N1.getOperand(1); 1053 1054 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1055 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1056 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1057 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1058 } 1059 1060 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1061 return SDValue(N, 0); 1062 1063 // fold (a+b) -> (a|b) iff a and b share no bits. 1064 if (VT.isInteger() && !VT.isVector()) { 1065 APInt LHSZero, LHSOne; 1066 APInt RHSZero, RHSOne; 1067 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1068 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1069 1070 if (LHSZero.getBoolValue()) { 1071 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1072 1073 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1074 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1075 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1076 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1077 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1078 } 1079 } 1080 1081 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1082 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1083 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1084 if (Result.getNode()) return Result; 1085 } 1086 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1087 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1088 if (Result.getNode()) return Result; 1089 } 1090 1091 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1092 if (N1.getOpcode() == ISD::SHL && 1093 N1.getOperand(0).getOpcode() == ISD::SUB) 1094 if (ConstantSDNode *C = 1095 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1096 if (C->getAPIntValue() == 0) 1097 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1098 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1099 N1.getOperand(0).getOperand(1), 1100 N1.getOperand(1))); 1101 if (N0.getOpcode() == ISD::SHL && 1102 N0.getOperand(0).getOpcode() == ISD::SUB) 1103 if (ConstantSDNode *C = 1104 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1105 if (C->getAPIntValue() == 0) 1106 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1107 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1108 N0.getOperand(0).getOperand(1), 1109 N0.getOperand(1))); 1110 1111 return SDValue(); 1112} 1113 1114SDValue DAGCombiner::visitADDC(SDNode *N) { 1115 SDValue N0 = N->getOperand(0); 1116 SDValue N1 = N->getOperand(1); 1117 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1118 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1119 EVT VT = N0.getValueType(); 1120 1121 // If the flag result is dead, turn this into an ADD. 1122 if (N->hasNUsesOfValue(0, 1)) 1123 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1124 DAG.getNode(ISD::CARRY_FALSE, 1125 N->getDebugLoc(), MVT::Flag)); 1126 1127 // canonicalize constant to RHS. 1128 if (N0C && !N1C) 1129 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1130 1131 // fold (addc x, 0) -> x + no carry out 1132 if (N1C && N1C->isNullValue()) 1133 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1134 N->getDebugLoc(), MVT::Flag)); 1135 1136 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1137 APInt LHSZero, LHSOne; 1138 APInt RHSZero, RHSOne; 1139 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1140 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1141 1142 if (LHSZero.getBoolValue()) { 1143 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1144 1145 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1146 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1147 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1148 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1149 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1150 DAG.getNode(ISD::CARRY_FALSE, 1151 N->getDebugLoc(), MVT::Flag)); 1152 } 1153 1154 return SDValue(); 1155} 1156 1157SDValue DAGCombiner::visitADDE(SDNode *N) { 1158 SDValue N0 = N->getOperand(0); 1159 SDValue N1 = N->getOperand(1); 1160 SDValue CarryIn = N->getOperand(2); 1161 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1162 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1163 1164 // canonicalize constant to RHS 1165 if (N0C && !N1C) 1166 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1167 N1, N0, CarryIn); 1168 1169 // fold (adde x, y, false) -> (addc x, y) 1170 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1171 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1172 1173 return SDValue(); 1174} 1175 1176SDValue DAGCombiner::visitSUB(SDNode *N) { 1177 SDValue N0 = N->getOperand(0); 1178 SDValue N1 = N->getOperand(1); 1179 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1180 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1181 EVT VT = N0.getValueType(); 1182 1183 // fold vector ops 1184 if (VT.isVector()) { 1185 SDValue FoldedVOp = SimplifyVBinOp(N); 1186 if (FoldedVOp.getNode()) return FoldedVOp; 1187 } 1188 1189 // fold (sub x, x) -> 0 1190 if (N0 == N1) 1191 return DAG.getConstant(0, N->getValueType(0)); 1192 // fold (sub c1, c2) -> c1-c2 1193 if (N0C && N1C) 1194 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1195 // fold (sub x, c) -> (add x, -c) 1196 if (N1C) 1197 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1198 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1199 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1200 if (N0C && N0C->isAllOnesValue()) 1201 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1202 // fold (A+B)-A -> B 1203 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1204 return N0.getOperand(1); 1205 // fold (A+B)-B -> A 1206 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1207 return N0.getOperand(0); 1208 // fold ((A+(B+or-C))-B) -> A+or-C 1209 if (N0.getOpcode() == ISD::ADD && 1210 (N0.getOperand(1).getOpcode() == ISD::SUB || 1211 N0.getOperand(1).getOpcode() == ISD::ADD) && 1212 N0.getOperand(1).getOperand(0) == N1) 1213 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1214 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1215 // fold ((A+(C+B))-B) -> A+C 1216 if (N0.getOpcode() == ISD::ADD && 1217 N0.getOperand(1).getOpcode() == ISD::ADD && 1218 N0.getOperand(1).getOperand(1) == N1) 1219 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1220 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1221 // fold ((A-(B-C))-C) -> A-B 1222 if (N0.getOpcode() == ISD::SUB && 1223 N0.getOperand(1).getOpcode() == ISD::SUB && 1224 N0.getOperand(1).getOperand(1) == N1) 1225 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1226 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1227 1228 // If either operand of a sub is undef, the result is undef 1229 if (N0.getOpcode() == ISD::UNDEF) 1230 return N0; 1231 if (N1.getOpcode() == ISD::UNDEF) 1232 return N1; 1233 1234 // If the relocation model supports it, consider symbol offsets. 1235 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1236 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1237 // fold (sub Sym, c) -> Sym-c 1238 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1239 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1240 GA->getOffset() - 1241 (uint64_t)N1C->getSExtValue()); 1242 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1243 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1244 if (GA->getGlobal() == GB->getGlobal()) 1245 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1246 VT); 1247 } 1248 1249 return SDValue(); 1250} 1251 1252SDValue DAGCombiner::visitMUL(SDNode *N) { 1253 SDValue N0 = N->getOperand(0); 1254 SDValue N1 = N->getOperand(1); 1255 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1256 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1257 EVT VT = N0.getValueType(); 1258 1259 // fold vector ops 1260 if (VT.isVector()) { 1261 SDValue FoldedVOp = SimplifyVBinOp(N); 1262 if (FoldedVOp.getNode()) return FoldedVOp; 1263 } 1264 1265 // fold (mul x, undef) -> 0 1266 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1267 return DAG.getConstant(0, VT); 1268 // fold (mul c1, c2) -> c1*c2 1269 if (N0C && N1C) 1270 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1271 // canonicalize constant to RHS 1272 if (N0C && !N1C) 1273 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1274 // fold (mul x, 0) -> 0 1275 if (N1C && N1C->isNullValue()) 1276 return N1; 1277 // fold (mul x, -1) -> 0-x 1278 if (N1C && N1C->isAllOnesValue()) 1279 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1280 DAG.getConstant(0, VT), N0); 1281 // fold (mul x, (1 << c)) -> x << c 1282 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1283 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1284 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1285 getShiftAmountTy())); 1286 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1287 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1288 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1289 // FIXME: If the input is something that is easily negated (e.g. a 1290 // single-use add), we should put the negate there. 1291 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1292 DAG.getConstant(0, VT), 1293 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1294 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1295 } 1296 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1297 if (N1C && N0.getOpcode() == ISD::SHL && 1298 isa<ConstantSDNode>(N0.getOperand(1))) { 1299 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1300 N1, N0.getOperand(1)); 1301 AddToWorkList(C3.getNode()); 1302 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1303 N0.getOperand(0), C3); 1304 } 1305 1306 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1307 // use. 1308 { 1309 SDValue Sh(0,0), Y(0,0); 1310 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1311 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1312 N0.getNode()->hasOneUse()) { 1313 Sh = N0; Y = N1; 1314 } else if (N1.getOpcode() == ISD::SHL && 1315 isa<ConstantSDNode>(N1.getOperand(1)) && 1316 N1.getNode()->hasOneUse()) { 1317 Sh = N1; Y = N0; 1318 } 1319 1320 if (Sh.getNode()) { 1321 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1322 Sh.getOperand(0), Y); 1323 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1324 Mul, Sh.getOperand(1)); 1325 } 1326 } 1327 1328 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1329 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1330 isa<ConstantSDNode>(N0.getOperand(1))) 1331 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1332 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1333 N0.getOperand(0), N1), 1334 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1335 N0.getOperand(1), N1)); 1336 1337 // reassociate mul 1338 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1339 if (RMUL.getNode() != 0) 1340 return RMUL; 1341 1342 return SDValue(); 1343} 1344 1345SDValue DAGCombiner::visitSDIV(SDNode *N) { 1346 SDValue N0 = N->getOperand(0); 1347 SDValue N1 = N->getOperand(1); 1348 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1349 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1350 EVT VT = N->getValueType(0); 1351 1352 // fold vector ops 1353 if (VT.isVector()) { 1354 SDValue FoldedVOp = SimplifyVBinOp(N); 1355 if (FoldedVOp.getNode()) return FoldedVOp; 1356 } 1357 1358 // fold (sdiv c1, c2) -> c1/c2 1359 if (N0C && N1C && !N1C->isNullValue()) 1360 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1361 // fold (sdiv X, 1) -> X 1362 if (N1C && N1C->getSExtValue() == 1LL) 1363 return N0; 1364 // fold (sdiv X, -1) -> 0-X 1365 if (N1C && N1C->isAllOnesValue()) 1366 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1367 DAG.getConstant(0, VT), N0); 1368 // If we know the sign bits of both operands are zero, strength reduce to a 1369 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1370 if (!VT.isVector()) { 1371 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1372 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1373 N0, N1); 1374 } 1375 // fold (sdiv X, pow2) -> simple ops after legalize 1376 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1377 (isPowerOf2_64(N1C->getSExtValue()) || 1378 isPowerOf2_64(-N1C->getSExtValue()))) { 1379 // If dividing by powers of two is cheap, then don't perform the following 1380 // fold. 1381 if (TLI.isPow2DivCheap()) 1382 return SDValue(); 1383 1384 int64_t pow2 = N1C->getSExtValue(); 1385 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1386 unsigned lg2 = Log2_64(abs2); 1387 1388 // Splat the sign bit into the register 1389 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1390 DAG.getConstant(VT.getSizeInBits()-1, 1391 getShiftAmountTy())); 1392 AddToWorkList(SGN.getNode()); 1393 1394 // Add (N0 < 0) ? abs2 - 1 : 0; 1395 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1396 DAG.getConstant(VT.getSizeInBits() - lg2, 1397 getShiftAmountTy())); 1398 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1399 AddToWorkList(SRL.getNode()); 1400 AddToWorkList(ADD.getNode()); // Divide by pow2 1401 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1402 DAG.getConstant(lg2, getShiftAmountTy())); 1403 1404 // If we're dividing by a positive value, we're done. Otherwise, we must 1405 // negate the result. 1406 if (pow2 > 0) 1407 return SRA; 1408 1409 AddToWorkList(SRA.getNode()); 1410 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1411 DAG.getConstant(0, VT), SRA); 1412 } 1413 1414 // if integer divide is expensive and we satisfy the requirements, emit an 1415 // alternate sequence. 1416 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1417 !TLI.isIntDivCheap()) { 1418 SDValue Op = BuildSDIV(N); 1419 if (Op.getNode()) return Op; 1420 } 1421 1422 // undef / X -> 0 1423 if (N0.getOpcode() == ISD::UNDEF) 1424 return DAG.getConstant(0, VT); 1425 // X / undef -> undef 1426 if (N1.getOpcode() == ISD::UNDEF) 1427 return N1; 1428 1429 return SDValue(); 1430} 1431 1432SDValue DAGCombiner::visitUDIV(SDNode *N) { 1433 SDValue N0 = N->getOperand(0); 1434 SDValue N1 = N->getOperand(1); 1435 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1436 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1437 EVT VT = N->getValueType(0); 1438 1439 // fold vector ops 1440 if (VT.isVector()) { 1441 SDValue FoldedVOp = SimplifyVBinOp(N); 1442 if (FoldedVOp.getNode()) return FoldedVOp; 1443 } 1444 1445 // fold (udiv c1, c2) -> c1/c2 1446 if (N0C && N1C && !N1C->isNullValue()) 1447 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1448 // fold (udiv x, (1 << c)) -> x >>u c 1449 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1450 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1451 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1452 getShiftAmountTy())); 1453 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1454 if (N1.getOpcode() == ISD::SHL) { 1455 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1456 if (SHC->getAPIntValue().isPowerOf2()) { 1457 EVT ADDVT = N1.getOperand(1).getValueType(); 1458 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1459 N1.getOperand(1), 1460 DAG.getConstant(SHC->getAPIntValue() 1461 .logBase2(), 1462 ADDVT)); 1463 AddToWorkList(Add.getNode()); 1464 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1465 } 1466 } 1467 } 1468 // fold (udiv x, c) -> alternate 1469 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1470 SDValue Op = BuildUDIV(N); 1471 if (Op.getNode()) return Op; 1472 } 1473 1474 // undef / X -> 0 1475 if (N0.getOpcode() == ISD::UNDEF) 1476 return DAG.getConstant(0, VT); 1477 // X / undef -> undef 1478 if (N1.getOpcode() == ISD::UNDEF) 1479 return N1; 1480 1481 return SDValue(); 1482} 1483 1484SDValue DAGCombiner::visitSREM(SDNode *N) { 1485 SDValue N0 = N->getOperand(0); 1486 SDValue N1 = N->getOperand(1); 1487 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1488 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1489 EVT VT = N->getValueType(0); 1490 1491 // fold (srem c1, c2) -> c1%c2 1492 if (N0C && N1C && !N1C->isNullValue()) 1493 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1494 // If we know the sign bits of both operands are zero, strength reduce to a 1495 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1496 if (!VT.isVector()) { 1497 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1498 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1499 } 1500 1501 // If X/C can be simplified by the division-by-constant logic, lower 1502 // X%C to the equivalent of X-X/C*C. 1503 if (N1C && !N1C->isNullValue()) { 1504 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1505 AddToWorkList(Div.getNode()); 1506 SDValue OptimizedDiv = combine(Div.getNode()); 1507 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1508 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1509 OptimizedDiv, N1); 1510 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1511 AddToWorkList(Mul.getNode()); 1512 return Sub; 1513 } 1514 } 1515 1516 // undef % X -> 0 1517 if (N0.getOpcode() == ISD::UNDEF) 1518 return DAG.getConstant(0, VT); 1519 // X % undef -> undef 1520 if (N1.getOpcode() == ISD::UNDEF) 1521 return N1; 1522 1523 return SDValue(); 1524} 1525 1526SDValue DAGCombiner::visitUREM(SDNode *N) { 1527 SDValue N0 = N->getOperand(0); 1528 SDValue N1 = N->getOperand(1); 1529 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1530 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1531 EVT VT = N->getValueType(0); 1532 1533 // fold (urem c1, c2) -> c1%c2 1534 if (N0C && N1C && !N1C->isNullValue()) 1535 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1536 // fold (urem x, pow2) -> (and x, pow2-1) 1537 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1538 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1539 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1540 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1541 if (N1.getOpcode() == ISD::SHL) { 1542 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1543 if (SHC->getAPIntValue().isPowerOf2()) { 1544 SDValue Add = 1545 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1546 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1547 VT)); 1548 AddToWorkList(Add.getNode()); 1549 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1550 } 1551 } 1552 } 1553 1554 // If X/C can be simplified by the division-by-constant logic, lower 1555 // X%C to the equivalent of X-X/C*C. 1556 if (N1C && !N1C->isNullValue()) { 1557 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1558 AddToWorkList(Div.getNode()); 1559 SDValue OptimizedDiv = combine(Div.getNode()); 1560 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1561 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1562 OptimizedDiv, N1); 1563 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1564 AddToWorkList(Mul.getNode()); 1565 return Sub; 1566 } 1567 } 1568 1569 // undef % X -> 0 1570 if (N0.getOpcode() == ISD::UNDEF) 1571 return DAG.getConstant(0, VT); 1572 // X % undef -> undef 1573 if (N1.getOpcode() == ISD::UNDEF) 1574 return N1; 1575 1576 return SDValue(); 1577} 1578 1579SDValue DAGCombiner::visitMULHS(SDNode *N) { 1580 SDValue N0 = N->getOperand(0); 1581 SDValue N1 = N->getOperand(1); 1582 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1583 EVT VT = N->getValueType(0); 1584 1585 // fold (mulhs x, 0) -> 0 1586 if (N1C && N1C->isNullValue()) 1587 return N1; 1588 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1589 if (N1C && N1C->getAPIntValue() == 1) 1590 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1591 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1592 getShiftAmountTy())); 1593 // fold (mulhs x, undef) -> 0 1594 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1595 return DAG.getConstant(0, VT); 1596 1597 return SDValue(); 1598} 1599 1600SDValue DAGCombiner::visitMULHU(SDNode *N) { 1601 SDValue N0 = N->getOperand(0); 1602 SDValue N1 = N->getOperand(1); 1603 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1604 EVT VT = N->getValueType(0); 1605 1606 // fold (mulhu x, 0) -> 0 1607 if (N1C && N1C->isNullValue()) 1608 return N1; 1609 // fold (mulhu x, 1) -> 0 1610 if (N1C && N1C->getAPIntValue() == 1) 1611 return DAG.getConstant(0, N0.getValueType()); 1612 // fold (mulhu x, undef) -> 0 1613 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1614 return DAG.getConstant(0, VT); 1615 1616 return SDValue(); 1617} 1618 1619/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1620/// compute two values. LoOp and HiOp give the opcodes for the two computations 1621/// that are being performed. Return true if a simplification was made. 1622/// 1623SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1624 unsigned HiOp) { 1625 // If the high half is not needed, just compute the low half. 1626 bool HiExists = N->hasAnyUseOfValue(1); 1627 if (!HiExists && 1628 (!LegalOperations || 1629 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1630 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1631 N->op_begin(), N->getNumOperands()); 1632 return CombineTo(N, Res, Res); 1633 } 1634 1635 // If the low half is not needed, just compute the high half. 1636 bool LoExists = N->hasAnyUseOfValue(0); 1637 if (!LoExists && 1638 (!LegalOperations || 1639 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1640 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1641 N->op_begin(), N->getNumOperands()); 1642 return CombineTo(N, Res, Res); 1643 } 1644 1645 // If both halves are used, return as it is. 1646 if (LoExists && HiExists) 1647 return SDValue(); 1648 1649 // If the two computed results can be simplified separately, separate them. 1650 if (LoExists) { 1651 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1652 N->op_begin(), N->getNumOperands()); 1653 AddToWorkList(Lo.getNode()); 1654 SDValue LoOpt = combine(Lo.getNode()); 1655 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1656 (!LegalOperations || 1657 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1658 return CombineTo(N, LoOpt, LoOpt); 1659 } 1660 1661 if (HiExists) { 1662 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1663 N->op_begin(), N->getNumOperands()); 1664 AddToWorkList(Hi.getNode()); 1665 SDValue HiOpt = combine(Hi.getNode()); 1666 if (HiOpt.getNode() && HiOpt != Hi && 1667 (!LegalOperations || 1668 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1669 return CombineTo(N, HiOpt, HiOpt); 1670 } 1671 1672 return SDValue(); 1673} 1674 1675SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1676 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1677 if (Res.getNode()) return Res; 1678 1679 return SDValue(); 1680} 1681 1682SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1683 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1684 if (Res.getNode()) return Res; 1685 1686 return SDValue(); 1687} 1688 1689SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1690 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1691 if (Res.getNode()) return Res; 1692 1693 return SDValue(); 1694} 1695 1696SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1697 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1698 if (Res.getNode()) return Res; 1699 1700 return SDValue(); 1701} 1702 1703/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1704/// two operands of the same opcode, try to simplify it. 1705SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1706 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1707 EVT VT = N0.getValueType(); 1708 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1709 1710 // Bail early if none of these transforms apply. 1711 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 1712 1713 // For each of OP in AND/OR/XOR: 1714 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1715 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1716 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1717 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1718 // 1719 // do not sink logical op inside of a vector extend, since it may combine 1720 // into a vsetcc. 1721 EVT Op0VT = N0.getOperand(0).getValueType(); 1722 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 1723 N0.getOpcode() == ISD::ANY_EXTEND || 1724 N0.getOpcode() == ISD::SIGN_EXTEND || 1725 (N0.getOpcode() == ISD::TRUNCATE && TLI.isTypeLegal(Op0VT))) && 1726 !VT.isVector() && 1727 Op0VT == N1.getOperand(0).getValueType() && 1728 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 1729 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1730 N0.getOperand(0).getValueType(), 1731 N0.getOperand(0), N1.getOperand(0)); 1732 AddToWorkList(ORNode.getNode()); 1733 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1734 } 1735 1736 // For each of OP in SHL/SRL/SRA/AND... 1737 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1738 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1739 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1740 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1741 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1742 N0.getOperand(1) == N1.getOperand(1)) { 1743 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1744 N0.getOperand(0).getValueType(), 1745 N0.getOperand(0), N1.getOperand(0)); 1746 AddToWorkList(ORNode.getNode()); 1747 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1748 ORNode, N0.getOperand(1)); 1749 } 1750 1751 return SDValue(); 1752} 1753 1754SDValue DAGCombiner::visitAND(SDNode *N) { 1755 SDValue N0 = N->getOperand(0); 1756 SDValue N1 = N->getOperand(1); 1757 SDValue LL, LR, RL, RR, CC0, CC1; 1758 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1759 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1760 EVT VT = N1.getValueType(); 1761 unsigned BitWidth = VT.getSizeInBits(); 1762 1763 // fold vector ops 1764 if (VT.isVector()) { 1765 SDValue FoldedVOp = SimplifyVBinOp(N); 1766 if (FoldedVOp.getNode()) return FoldedVOp; 1767 } 1768 1769 // fold (and x, undef) -> 0 1770 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1771 return DAG.getConstant(0, VT); 1772 // fold (and c1, c2) -> c1&c2 1773 if (N0C && N1C) 1774 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1775 // canonicalize constant to RHS 1776 if (N0C && !N1C) 1777 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1778 // fold (and x, -1) -> x 1779 if (N1C && N1C->isAllOnesValue()) 1780 return N0; 1781 // if (and x, c) is known to be zero, return 0 1782 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1783 APInt::getAllOnesValue(BitWidth))) 1784 return DAG.getConstant(0, VT); 1785 // reassociate and 1786 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1787 if (RAND.getNode() != 0) 1788 return RAND; 1789 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1790 if (N1C && N0.getOpcode() == ISD::OR) 1791 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1792 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1793 return N1; 1794 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1795 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1796 SDValue N0Op0 = N0.getOperand(0); 1797 APInt Mask = ~N1C->getAPIntValue(); 1798 Mask.trunc(N0Op0.getValueSizeInBits()); 1799 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1800 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1801 N0.getValueType(), N0Op0); 1802 1803 // Replace uses of the AND with uses of the Zero extend node. 1804 CombineTo(N, Zext); 1805 1806 // We actually want to replace all uses of the any_extend with the 1807 // zero_extend, to avoid duplicating things. This will later cause this 1808 // AND to be folded. 1809 CombineTo(N0.getNode(), Zext); 1810 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1811 } 1812 } 1813 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1814 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1815 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1816 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1817 1818 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1819 LL.getValueType().isInteger()) { 1820 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1821 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1822 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1823 LR.getValueType(), LL, RL); 1824 AddToWorkList(ORNode.getNode()); 1825 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1826 } 1827 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1828 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1829 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1830 LR.getValueType(), LL, RL); 1831 AddToWorkList(ANDNode.getNode()); 1832 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1833 } 1834 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1835 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1836 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1837 LR.getValueType(), LL, RL); 1838 AddToWorkList(ORNode.getNode()); 1839 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1840 } 1841 } 1842 // canonicalize equivalent to ll == rl 1843 if (LL == RR && LR == RL) { 1844 Op1 = ISD::getSetCCSwappedOperands(Op1); 1845 std::swap(RL, RR); 1846 } 1847 if (LL == RL && LR == RR) { 1848 bool isInteger = LL.getValueType().isInteger(); 1849 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1850 if (Result != ISD::SETCC_INVALID && 1851 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1852 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1853 LL, LR, Result); 1854 } 1855 } 1856 1857 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1858 if (N0.getOpcode() == N1.getOpcode()) { 1859 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1860 if (Tmp.getNode()) return Tmp; 1861 } 1862 1863 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1864 // fold (and (sra)) -> (and (srl)) when possible. 1865 if (!VT.isVector() && 1866 SimplifyDemandedBits(SDValue(N, 0))) 1867 return SDValue(N, 0); 1868 1869 // fold (zext_inreg (extload x)) -> (zextload x) 1870 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1871 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1872 EVT MemVT = LN0->getMemoryVT(); 1873 // If we zero all the possible extended bits, then we can turn this into 1874 // a zextload if we are running before legalize or the operation is legal. 1875 unsigned BitWidth = N1.getValueSizeInBits(); 1876 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1877 BitWidth - MemVT.getSizeInBits())) && 1878 ((!LegalOperations && !LN0->isVolatile()) || 1879 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1880 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1881 LN0->getChain(), LN0->getBasePtr(), 1882 LN0->getSrcValue(), 1883 LN0->getSrcValueOffset(), MemVT, 1884 LN0->isVolatile(), LN0->getAlignment()); 1885 AddToWorkList(N); 1886 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1887 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1888 } 1889 } 1890 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1891 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1892 N0.hasOneUse()) { 1893 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1894 EVT MemVT = LN0->getMemoryVT(); 1895 // If we zero all the possible extended bits, then we can turn this into 1896 // a zextload if we are running before legalize or the operation is legal. 1897 unsigned BitWidth = N1.getValueSizeInBits(); 1898 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1899 BitWidth - MemVT.getSizeInBits())) && 1900 ((!LegalOperations && !LN0->isVolatile()) || 1901 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1902 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1903 LN0->getChain(), 1904 LN0->getBasePtr(), LN0->getSrcValue(), 1905 LN0->getSrcValueOffset(), MemVT, 1906 LN0->isVolatile(), LN0->getAlignment()); 1907 AddToWorkList(N); 1908 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1909 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1910 } 1911 } 1912 1913 // fold (and (load x), 255) -> (zextload x, i8) 1914 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1915 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 1916 if (N1C && (N0.getOpcode() == ISD::LOAD || 1917 (N0.getOpcode() == ISD::ANY_EXTEND && 1918 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 1919 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 1920 LoadSDNode *LN0 = HasAnyExt 1921 ? cast<LoadSDNode>(N0.getOperand(0)) 1922 : cast<LoadSDNode>(N0); 1923 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1924 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 1925 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1926 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 1927 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 1928 EVT LoadedVT = LN0->getMemoryVT(); 1929 1930 if (ExtVT == LoadedVT && 1931 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1932 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 1933 1934 SDValue NewLoad = 1935 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 1936 LN0->getChain(), LN0->getBasePtr(), 1937 LN0->getSrcValue(), LN0->getSrcValueOffset(), 1938 ExtVT, LN0->isVolatile(), LN0->getAlignment()); 1939 AddToWorkList(N); 1940 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 1941 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1942 } 1943 1944 // Do not change the width of a volatile load. 1945 // Do not generate loads of non-round integer types since these can 1946 // be expensive (and would be wrong if the type is not byte sized). 1947 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 1948 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1949 EVT PtrType = LN0->getOperand(1).getValueType(); 1950 1951 unsigned Alignment = LN0->getAlignment(); 1952 SDValue NewPtr = LN0->getBasePtr(); 1953 1954 // For big endian targets, we need to add an offset to the pointer 1955 // to load the correct bytes. For little endian systems, we merely 1956 // need to read fewer bytes from the same pointer. 1957 if (TLI.isBigEndian()) { 1958 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 1959 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 1960 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1961 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1962 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1963 Alignment = MinAlign(Alignment, PtrOff); 1964 } 1965 1966 AddToWorkList(NewPtr.getNode()); 1967 1968 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 1969 SDValue Load = 1970 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 1971 LN0->getChain(), NewPtr, 1972 LN0->getSrcValue(), LN0->getSrcValueOffset(), 1973 ExtVT, LN0->isVolatile(), Alignment); 1974 AddToWorkList(N); 1975 CombineTo(LN0, Load, Load.getValue(1)); 1976 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1977 } 1978 } 1979 } 1980 } 1981 1982 return SDValue(); 1983} 1984 1985SDValue DAGCombiner::visitOR(SDNode *N) { 1986 SDValue N0 = N->getOperand(0); 1987 SDValue N1 = N->getOperand(1); 1988 SDValue LL, LR, RL, RR, CC0, CC1; 1989 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1990 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1991 EVT VT = N1.getValueType(); 1992 1993 // fold vector ops 1994 if (VT.isVector()) { 1995 SDValue FoldedVOp = SimplifyVBinOp(N); 1996 if (FoldedVOp.getNode()) return FoldedVOp; 1997 } 1998 1999 // fold (or x, undef) -> -1 2000 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) { 2001 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2002 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2003 } 2004 // fold (or c1, c2) -> c1|c2 2005 if (N0C && N1C) 2006 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2007 // canonicalize constant to RHS 2008 if (N0C && !N1C) 2009 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2010 // fold (or x, 0) -> x 2011 if (N1C && N1C->isNullValue()) 2012 return N0; 2013 // fold (or x, -1) -> -1 2014 if (N1C && N1C->isAllOnesValue()) 2015 return N1; 2016 // fold (or x, c) -> c iff (x & ~c) == 0 2017 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2018 return N1; 2019 // reassociate or 2020 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2021 if (ROR.getNode() != 0) 2022 return ROR; 2023 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2024 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2025 isa<ConstantSDNode>(N0.getOperand(1))) { 2026 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2027 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2028 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2029 N0.getOperand(0), N1), 2030 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2031 } 2032 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2033 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2034 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2035 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2036 2037 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2038 LL.getValueType().isInteger()) { 2039 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2040 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2041 if (cast<ConstantSDNode>(LR)->isNullValue() && 2042 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2043 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2044 LR.getValueType(), LL, RL); 2045 AddToWorkList(ORNode.getNode()); 2046 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2047 } 2048 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2049 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2050 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2051 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2052 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2053 LR.getValueType(), LL, RL); 2054 AddToWorkList(ANDNode.getNode()); 2055 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2056 } 2057 } 2058 // canonicalize equivalent to ll == rl 2059 if (LL == RR && LR == RL) { 2060 Op1 = ISD::getSetCCSwappedOperands(Op1); 2061 std::swap(RL, RR); 2062 } 2063 if (LL == RL && LR == RR) { 2064 bool isInteger = LL.getValueType().isInteger(); 2065 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2066 if (Result != ISD::SETCC_INVALID && 2067 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2068 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2069 LL, LR, Result); 2070 } 2071 } 2072 2073 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2074 if (N0.getOpcode() == N1.getOpcode()) { 2075 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2076 if (Tmp.getNode()) return Tmp; 2077 } 2078 2079 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2080 if (N0.getOpcode() == ISD::AND && 2081 N1.getOpcode() == ISD::AND && 2082 N0.getOperand(1).getOpcode() == ISD::Constant && 2083 N1.getOperand(1).getOpcode() == ISD::Constant && 2084 // Don't increase # computations. 2085 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2086 // We can only do this xform if we know that bits from X that are set in C2 2087 // but not in C1 are already zero. Likewise for Y. 2088 const APInt &LHSMask = 2089 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2090 const APInt &RHSMask = 2091 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2092 2093 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2094 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2095 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2096 N0.getOperand(0), N1.getOperand(0)); 2097 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2098 DAG.getConstant(LHSMask | RHSMask, VT)); 2099 } 2100 } 2101 2102 // See if this is some rotate idiom. 2103 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2104 return SDValue(Rot, 0); 2105 2106 return SDValue(); 2107} 2108 2109/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2110static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2111 if (Op.getOpcode() == ISD::AND) { 2112 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2113 Mask = Op.getOperand(1); 2114 Op = Op.getOperand(0); 2115 } else { 2116 return false; 2117 } 2118 } 2119 2120 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2121 Shift = Op; 2122 return true; 2123 } 2124 2125 return false; 2126} 2127 2128// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2129// idioms for rotate, and if the target supports rotation instructions, generate 2130// a rot[lr]. 2131SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2132 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2133 EVT VT = LHS.getValueType(); 2134 if (!TLI.isTypeLegal(VT)) return 0; 2135 2136 // The target must have at least one rotate flavor. 2137 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2138 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2139 if (!HasROTL && !HasROTR) return 0; 2140 2141 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2142 SDValue LHSShift; // The shift. 2143 SDValue LHSMask; // AND value if any. 2144 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2145 return 0; // Not part of a rotate. 2146 2147 SDValue RHSShift; // The shift. 2148 SDValue RHSMask; // AND value if any. 2149 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2150 return 0; // Not part of a rotate. 2151 2152 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2153 return 0; // Not shifting the same value. 2154 2155 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2156 return 0; // Shifts must disagree. 2157 2158 // Canonicalize shl to left side in a shl/srl pair. 2159 if (RHSShift.getOpcode() == ISD::SHL) { 2160 std::swap(LHS, RHS); 2161 std::swap(LHSShift, RHSShift); 2162 std::swap(LHSMask , RHSMask ); 2163 } 2164 2165 unsigned OpSizeInBits = VT.getSizeInBits(); 2166 SDValue LHSShiftArg = LHSShift.getOperand(0); 2167 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2168 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2169 2170 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2171 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2172 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2173 RHSShiftAmt.getOpcode() == ISD::Constant) { 2174 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2175 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2176 if ((LShVal + RShVal) != OpSizeInBits) 2177 return 0; 2178 2179 SDValue Rot; 2180 if (HasROTL) 2181 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2182 else 2183 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2184 2185 // If there is an AND of either shifted operand, apply it to the result. 2186 if (LHSMask.getNode() || RHSMask.getNode()) { 2187 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2188 2189 if (LHSMask.getNode()) { 2190 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2191 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2192 } 2193 if (RHSMask.getNode()) { 2194 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2195 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2196 } 2197 2198 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2199 } 2200 2201 return Rot.getNode(); 2202 } 2203 2204 // If there is a mask here, and we have a variable shift, we can't be sure 2205 // that we're masking out the right stuff. 2206 if (LHSMask.getNode() || RHSMask.getNode()) 2207 return 0; 2208 2209 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2210 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2211 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2212 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2213 if (ConstantSDNode *SUBC = 2214 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2215 if (SUBC->getAPIntValue() == OpSizeInBits) { 2216 if (HasROTL) 2217 return DAG.getNode(ISD::ROTL, DL, VT, 2218 LHSShiftArg, LHSShiftAmt).getNode(); 2219 else 2220 return DAG.getNode(ISD::ROTR, DL, VT, 2221 LHSShiftArg, RHSShiftAmt).getNode(); 2222 } 2223 } 2224 } 2225 2226 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2227 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2228 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2229 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2230 if (ConstantSDNode *SUBC = 2231 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2232 if (SUBC->getAPIntValue() == OpSizeInBits) { 2233 if (HasROTR) 2234 return DAG.getNode(ISD::ROTR, DL, VT, 2235 LHSShiftArg, RHSShiftAmt).getNode(); 2236 else 2237 return DAG.getNode(ISD::ROTL, DL, VT, 2238 LHSShiftArg, LHSShiftAmt).getNode(); 2239 } 2240 } 2241 } 2242 2243 // Look for sign/zext/any-extended or truncate cases: 2244 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2245 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2246 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2247 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2248 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2249 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2250 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2251 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2252 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2253 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2254 if (RExtOp0.getOpcode() == ISD::SUB && 2255 RExtOp0.getOperand(1) == LExtOp0) { 2256 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2257 // (rotl x, y) 2258 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2259 // (rotr x, (sub 32, y)) 2260 if (ConstantSDNode *SUBC = 2261 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2262 if (SUBC->getAPIntValue() == OpSizeInBits) { 2263 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2264 LHSShiftArg, 2265 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2266 } 2267 } 2268 } else if (LExtOp0.getOpcode() == ISD::SUB && 2269 RExtOp0 == LExtOp0.getOperand(1)) { 2270 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2271 // (rotr x, y) 2272 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2273 // (rotl x, (sub 32, y)) 2274 if (ConstantSDNode *SUBC = 2275 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2276 if (SUBC->getAPIntValue() == OpSizeInBits) { 2277 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2278 LHSShiftArg, 2279 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2280 } 2281 } 2282 } 2283 } 2284 2285 return 0; 2286} 2287 2288SDValue DAGCombiner::visitXOR(SDNode *N) { 2289 SDValue N0 = N->getOperand(0); 2290 SDValue N1 = N->getOperand(1); 2291 SDValue LHS, RHS, CC; 2292 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2293 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2294 EVT VT = N0.getValueType(); 2295 2296 // fold vector ops 2297 if (VT.isVector()) { 2298 SDValue FoldedVOp = SimplifyVBinOp(N); 2299 if (FoldedVOp.getNode()) return FoldedVOp; 2300 } 2301 2302 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2303 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2304 return DAG.getConstant(0, VT); 2305 // fold (xor x, undef) -> undef 2306 if (N0.getOpcode() == ISD::UNDEF) 2307 return N0; 2308 if (N1.getOpcode() == ISD::UNDEF) 2309 return N1; 2310 // fold (xor c1, c2) -> c1^c2 2311 if (N0C && N1C) 2312 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2313 // canonicalize constant to RHS 2314 if (N0C && !N1C) 2315 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2316 // fold (xor x, 0) -> x 2317 if (N1C && N1C->isNullValue()) 2318 return N0; 2319 // reassociate xor 2320 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2321 if (RXOR.getNode() != 0) 2322 return RXOR; 2323 2324 // fold !(x cc y) -> (x !cc y) 2325 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2326 bool isInt = LHS.getValueType().isInteger(); 2327 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2328 isInt); 2329 2330 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2331 switch (N0.getOpcode()) { 2332 default: 2333 llvm_unreachable("Unhandled SetCC Equivalent!"); 2334 case ISD::SETCC: 2335 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2336 case ISD::SELECT_CC: 2337 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2338 N0.getOperand(3), NotCC); 2339 } 2340 } 2341 } 2342 2343 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2344 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2345 N0.getNode()->hasOneUse() && 2346 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2347 SDValue V = N0.getOperand(0); 2348 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2349 DAG.getConstant(1, V.getValueType())); 2350 AddToWorkList(V.getNode()); 2351 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2352 } 2353 2354 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2355 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2356 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2357 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2358 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2359 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2360 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2361 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2362 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2363 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2364 } 2365 } 2366 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2367 if (N1C && N1C->isAllOnesValue() && 2368 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2369 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2370 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2371 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2372 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2373 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2374 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2375 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2376 } 2377 } 2378 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2379 if (N1C && N0.getOpcode() == ISD::XOR) { 2380 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2381 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2382 if (N00C) 2383 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2384 DAG.getConstant(N1C->getAPIntValue() ^ 2385 N00C->getAPIntValue(), VT)); 2386 if (N01C) 2387 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2388 DAG.getConstant(N1C->getAPIntValue() ^ 2389 N01C->getAPIntValue(), VT)); 2390 } 2391 // fold (xor x, x) -> 0 2392 if (N0 == N1) { 2393 if (!VT.isVector()) { 2394 return DAG.getConstant(0, VT); 2395 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2396 // Produce a vector of zeros. 2397 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2398 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2399 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2400 &Ops[0], Ops.size()); 2401 } 2402 } 2403 2404 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2405 if (N0.getOpcode() == N1.getOpcode()) { 2406 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2407 if (Tmp.getNode()) return Tmp; 2408 } 2409 2410 // Simplify the expression using non-local knowledge. 2411 if (!VT.isVector() && 2412 SimplifyDemandedBits(SDValue(N, 0))) 2413 return SDValue(N, 0); 2414 2415 return SDValue(); 2416} 2417 2418/// visitShiftByConstant - Handle transforms common to the three shifts, when 2419/// the shift amount is a constant. 2420SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2421 SDNode *LHS = N->getOperand(0).getNode(); 2422 if (!LHS->hasOneUse()) return SDValue(); 2423 2424 // We want to pull some binops through shifts, so that we have (and (shift)) 2425 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2426 // thing happens with address calculations, so it's important to canonicalize 2427 // it. 2428 bool HighBitSet = false; // Can we transform this if the high bit is set? 2429 2430 switch (LHS->getOpcode()) { 2431 default: return SDValue(); 2432 case ISD::OR: 2433 case ISD::XOR: 2434 HighBitSet = false; // We can only transform sra if the high bit is clear. 2435 break; 2436 case ISD::AND: 2437 HighBitSet = true; // We can only transform sra if the high bit is set. 2438 break; 2439 case ISD::ADD: 2440 if (N->getOpcode() != ISD::SHL) 2441 return SDValue(); // only shl(add) not sr[al](add). 2442 HighBitSet = false; // We can only transform sra if the high bit is clear. 2443 break; 2444 } 2445 2446 // We require the RHS of the binop to be a constant as well. 2447 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2448 if (!BinOpCst) return SDValue(); 2449 2450 // FIXME: disable this unless the input to the binop is a shift by a constant. 2451 // If it is not a shift, it pessimizes some common cases like: 2452 // 2453 // void foo(int *X, int i) { X[i & 1235] = 1; } 2454 // int bar(int *X, int i) { return X[i & 255]; } 2455 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2456 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2457 BinOpLHSVal->getOpcode() != ISD::SRA && 2458 BinOpLHSVal->getOpcode() != ISD::SRL) || 2459 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2460 return SDValue(); 2461 2462 EVT VT = N->getValueType(0); 2463 2464 // If this is a signed shift right, and the high bit is modified by the 2465 // logical operation, do not perform the transformation. The highBitSet 2466 // boolean indicates the value of the high bit of the constant which would 2467 // cause it to be modified for this operation. 2468 if (N->getOpcode() == ISD::SRA) { 2469 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2470 if (BinOpRHSSignSet != HighBitSet) 2471 return SDValue(); 2472 } 2473 2474 // Fold the constants, shifting the binop RHS by the shift amount. 2475 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2476 N->getValueType(0), 2477 LHS->getOperand(1), N->getOperand(1)); 2478 2479 // Create the new shift. 2480 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2481 VT, LHS->getOperand(0), N->getOperand(1)); 2482 2483 // Create the new binop. 2484 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2485} 2486 2487SDValue DAGCombiner::visitSHL(SDNode *N) { 2488 SDValue N0 = N->getOperand(0); 2489 SDValue N1 = N->getOperand(1); 2490 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2491 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2492 EVT VT = N0.getValueType(); 2493 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2494 2495 // fold (shl c1, c2) -> c1<<c2 2496 if (N0C && N1C) 2497 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2498 // fold (shl 0, x) -> 0 2499 if (N0C && N0C->isNullValue()) 2500 return N0; 2501 // fold (shl x, c >= size(x)) -> undef 2502 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2503 return DAG.getUNDEF(VT); 2504 // fold (shl x, 0) -> x 2505 if (N1C && N1C->isNullValue()) 2506 return N0; 2507 // if (shl x, c) is known to be zero, return 0 2508 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2509 APInt::getAllOnesValue(OpSizeInBits))) 2510 return DAG.getConstant(0, VT); 2511 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2512 if (N1.getOpcode() == ISD::TRUNCATE && 2513 N1.getOperand(0).getOpcode() == ISD::AND && 2514 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2515 SDValue N101 = N1.getOperand(0).getOperand(1); 2516 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2517 EVT TruncVT = N1.getValueType(); 2518 SDValue N100 = N1.getOperand(0).getOperand(0); 2519 APInt TruncC = N101C->getAPIntValue(); 2520 TruncC.trunc(TruncVT.getSizeInBits()); 2521 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2522 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2523 DAG.getNode(ISD::TRUNCATE, 2524 N->getDebugLoc(), 2525 TruncVT, N100), 2526 DAG.getConstant(TruncC, TruncVT))); 2527 } 2528 } 2529 2530 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2531 return SDValue(N, 0); 2532 2533 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2534 if (N1C && N0.getOpcode() == ISD::SHL && 2535 N0.getOperand(1).getOpcode() == ISD::Constant) { 2536 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2537 uint64_t c2 = N1C->getZExtValue(); 2538 if (c1 + c2 > OpSizeInBits) 2539 return DAG.getConstant(0, VT); 2540 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2541 DAG.getConstant(c1 + c2, N1.getValueType())); 2542 } 2543 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2544 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2545 if (N1C && N0.getOpcode() == ISD::SRL && 2546 N0.getOperand(1).getOpcode() == ISD::Constant) { 2547 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2548 if (c1 < VT.getSizeInBits()) { 2549 uint64_t c2 = N1C->getZExtValue(); 2550 SDValue HiBitsMask = 2551 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2552 VT.getSizeInBits() - c1), 2553 VT); 2554 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2555 N0.getOperand(0), 2556 HiBitsMask); 2557 if (c2 > c1) 2558 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2559 DAG.getConstant(c2-c1, N1.getValueType())); 2560 else 2561 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2562 DAG.getConstant(c1-c2, N1.getValueType())); 2563 } 2564 } 2565 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2566 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2567 SDValue HiBitsMask = 2568 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2569 VT.getSizeInBits() - 2570 N1C->getZExtValue()), 2571 VT); 2572 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2573 HiBitsMask); 2574 } 2575 2576 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2577} 2578 2579SDValue DAGCombiner::visitSRA(SDNode *N) { 2580 SDValue N0 = N->getOperand(0); 2581 SDValue N1 = N->getOperand(1); 2582 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2583 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2584 EVT VT = N0.getValueType(); 2585 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2586 2587 // fold (sra c1, c2) -> (sra c1, c2) 2588 if (N0C && N1C) 2589 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2590 // fold (sra 0, x) -> 0 2591 if (N0C && N0C->isNullValue()) 2592 return N0; 2593 // fold (sra -1, x) -> -1 2594 if (N0C && N0C->isAllOnesValue()) 2595 return N0; 2596 // fold (sra x, (setge c, size(x))) -> undef 2597 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2598 return DAG.getUNDEF(VT); 2599 // fold (sra x, 0) -> x 2600 if (N1C && N1C->isNullValue()) 2601 return N0; 2602 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2603 // sext_inreg. 2604 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2605 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 2606 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2607 if (VT.isVector()) 2608 ExtVT = EVT::getVectorVT(*DAG.getContext(), 2609 ExtVT, VT.getVectorNumElements()); 2610 if ((!LegalOperations || 2611 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 2612 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2613 N0.getOperand(0), DAG.getValueType(ExtVT)); 2614 } 2615 2616 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2617 if (N1C && N0.getOpcode() == ISD::SRA) { 2618 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2619 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2620 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 2621 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2622 DAG.getConstant(Sum, N1C->getValueType(0))); 2623 } 2624 } 2625 2626 // fold (sra (shl X, m), (sub result_size, n)) 2627 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2628 // result_size - n != m. 2629 // If truncate is free for the target sext(shl) is likely to result in better 2630 // code. 2631 if (N0.getOpcode() == ISD::SHL) { 2632 // Get the two constanst of the shifts, CN0 = m, CN = n. 2633 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2634 if (N01C && N1C) { 2635 // Determine what the truncate's result bitsize and type would be. 2636 EVT TruncVT = 2637 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue()); 2638 // Determine the residual right-shift amount. 2639 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2640 2641 // If the shift is not a no-op (in which case this should be just a sign 2642 // extend already), the truncated to type is legal, sign_extend is legal 2643 // on that type, and the the truncate to that type is both legal and free, 2644 // perform the transform. 2645 if ((ShiftAmt > 0) && 2646 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2647 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2648 TLI.isTruncateFree(VT, TruncVT)) { 2649 2650 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2651 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2652 N0.getOperand(0), Amt); 2653 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2654 Shift); 2655 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2656 N->getValueType(0), Trunc); 2657 } 2658 } 2659 } 2660 2661 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2662 if (N1.getOpcode() == ISD::TRUNCATE && 2663 N1.getOperand(0).getOpcode() == ISD::AND && 2664 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2665 SDValue N101 = N1.getOperand(0).getOperand(1); 2666 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2667 EVT TruncVT = N1.getValueType(); 2668 SDValue N100 = N1.getOperand(0).getOperand(0); 2669 APInt TruncC = N101C->getAPIntValue(); 2670 TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 2671 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2672 DAG.getNode(ISD::AND, N->getDebugLoc(), 2673 TruncVT, 2674 DAG.getNode(ISD::TRUNCATE, 2675 N->getDebugLoc(), 2676 TruncVT, N100), 2677 DAG.getConstant(TruncC, TruncVT))); 2678 } 2679 } 2680 2681 // Simplify, based on bits shifted out of the LHS. 2682 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2683 return SDValue(N, 0); 2684 2685 2686 // If the sign bit is known to be zero, switch this to a SRL. 2687 if (DAG.SignBitIsZero(N0)) 2688 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2689 2690 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2691} 2692 2693SDValue DAGCombiner::visitSRL(SDNode *N) { 2694 SDValue N0 = N->getOperand(0); 2695 SDValue N1 = N->getOperand(1); 2696 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2697 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2698 EVT VT = N0.getValueType(); 2699 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2700 2701 // fold (srl c1, c2) -> c1 >>u c2 2702 if (N0C && N1C) 2703 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2704 // fold (srl 0, x) -> 0 2705 if (N0C && N0C->isNullValue()) 2706 return N0; 2707 // fold (srl x, c >= size(x)) -> undef 2708 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2709 return DAG.getUNDEF(VT); 2710 // fold (srl x, 0) -> x 2711 if (N1C && N1C->isNullValue()) 2712 return N0; 2713 // if (srl x, c) is known to be zero, return 0 2714 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2715 APInt::getAllOnesValue(OpSizeInBits))) 2716 return DAG.getConstant(0, VT); 2717 2718 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2719 if (N1C && N0.getOpcode() == ISD::SRL && 2720 N0.getOperand(1).getOpcode() == ISD::Constant) { 2721 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2722 uint64_t c2 = N1C->getZExtValue(); 2723 if (c1 + c2 > OpSizeInBits) 2724 return DAG.getConstant(0, VT); 2725 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2726 DAG.getConstant(c1 + c2, N1.getValueType())); 2727 } 2728 2729 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2730 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2731 // Shifting in all undef bits? 2732 EVT SmallVT = N0.getOperand(0).getValueType(); 2733 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2734 return DAG.getUNDEF(VT); 2735 2736 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2737 N0.getOperand(0), N1); 2738 AddToWorkList(SmallShift.getNode()); 2739 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2740 } 2741 2742 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2743 // bit, which is unmodified by sra. 2744 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2745 if (N0.getOpcode() == ISD::SRA) 2746 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2747 } 2748 2749 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2750 if (N1C && N0.getOpcode() == ISD::CTLZ && 2751 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2752 APInt KnownZero, KnownOne; 2753 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2754 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2755 2756 // If any of the input bits are KnownOne, then the input couldn't be all 2757 // zeros, thus the result of the srl will always be zero. 2758 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2759 2760 // If all of the bits input the to ctlz node are known to be zero, then 2761 // the result of the ctlz is "32" and the result of the shift is one. 2762 APInt UnknownBits = ~KnownZero & Mask; 2763 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2764 2765 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2766 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2767 // Okay, we know that only that the single bit specified by UnknownBits 2768 // could be set on input to the CTLZ node. If this bit is set, the SRL 2769 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2770 // to an SRL/XOR pair, which is likely to simplify more. 2771 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2772 SDValue Op = N0.getOperand(0); 2773 2774 if (ShAmt) { 2775 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2776 DAG.getConstant(ShAmt, getShiftAmountTy())); 2777 AddToWorkList(Op.getNode()); 2778 } 2779 2780 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2781 Op, DAG.getConstant(1, VT)); 2782 } 2783 } 2784 2785 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2786 if (N1.getOpcode() == ISD::TRUNCATE && 2787 N1.getOperand(0).getOpcode() == ISD::AND && 2788 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2789 SDValue N101 = N1.getOperand(0).getOperand(1); 2790 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2791 EVT TruncVT = N1.getValueType(); 2792 SDValue N100 = N1.getOperand(0).getOperand(0); 2793 APInt TruncC = N101C->getAPIntValue(); 2794 TruncC.trunc(TruncVT.getSizeInBits()); 2795 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2796 DAG.getNode(ISD::AND, N->getDebugLoc(), 2797 TruncVT, 2798 DAG.getNode(ISD::TRUNCATE, 2799 N->getDebugLoc(), 2800 TruncVT, N100), 2801 DAG.getConstant(TruncC, TruncVT))); 2802 } 2803 } 2804 2805 // fold operands of srl based on knowledge that the low bits are not 2806 // demanded. 2807 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2808 return SDValue(N, 0); 2809 2810 if (N1C) { 2811 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 2812 if (NewSRL.getNode()) 2813 return NewSRL; 2814 } 2815 2816 // Here is a common situation. We want to optimize: 2817 // 2818 // %a = ... 2819 // %b = and i32 %a, 2 2820 // %c = srl i32 %b, 1 2821 // brcond i32 %c ... 2822 // 2823 // into 2824 // 2825 // %a = ... 2826 // %b = and %a, 2 2827 // %c = setcc eq %b, 0 2828 // brcond %c ... 2829 // 2830 // However when after the source operand of SRL is optimized into AND, the SRL 2831 // itself may not be optimized further. Look for it and add the BRCOND into 2832 // the worklist. 2833 if (N->hasOneUse()) { 2834 SDNode *Use = *N->use_begin(); 2835 if (Use->getOpcode() == ISD::BRCOND) 2836 AddToWorkList(Use); 2837 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 2838 // Also look pass the truncate. 2839 Use = *Use->use_begin(); 2840 if (Use->getOpcode() == ISD::BRCOND) 2841 AddToWorkList(Use); 2842 } 2843 } 2844 2845 return SDValue(); 2846} 2847 2848SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2849 SDValue N0 = N->getOperand(0); 2850 EVT VT = N->getValueType(0); 2851 2852 // fold (ctlz c1) -> c2 2853 if (isa<ConstantSDNode>(N0)) 2854 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2855 return SDValue(); 2856} 2857 2858SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2859 SDValue N0 = N->getOperand(0); 2860 EVT VT = N->getValueType(0); 2861 2862 // fold (cttz c1) -> c2 2863 if (isa<ConstantSDNode>(N0)) 2864 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2865 return SDValue(); 2866} 2867 2868SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2869 SDValue N0 = N->getOperand(0); 2870 EVT VT = N->getValueType(0); 2871 2872 // fold (ctpop c1) -> c2 2873 if (isa<ConstantSDNode>(N0)) 2874 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2875 return SDValue(); 2876} 2877 2878SDValue DAGCombiner::visitSELECT(SDNode *N) { 2879 SDValue N0 = N->getOperand(0); 2880 SDValue N1 = N->getOperand(1); 2881 SDValue N2 = N->getOperand(2); 2882 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2883 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2884 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2885 EVT VT = N->getValueType(0); 2886 EVT VT0 = N0.getValueType(); 2887 2888 // fold (select C, X, X) -> X 2889 if (N1 == N2) 2890 return N1; 2891 // fold (select true, X, Y) -> X 2892 if (N0C && !N0C->isNullValue()) 2893 return N1; 2894 // fold (select false, X, Y) -> Y 2895 if (N0C && N0C->isNullValue()) 2896 return N2; 2897 // fold (select C, 1, X) -> (or C, X) 2898 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2899 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2900 // fold (select C, 0, 1) -> (xor C, 1) 2901 if (VT.isInteger() && 2902 (VT0 == MVT::i1 || 2903 (VT0.isInteger() && 2904 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2905 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2906 SDValue XORNode; 2907 if (VT == VT0) 2908 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2909 N0, DAG.getConstant(1, VT0)); 2910 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2911 N0, DAG.getConstant(1, VT0)); 2912 AddToWorkList(XORNode.getNode()); 2913 if (VT.bitsGT(VT0)) 2914 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2915 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2916 } 2917 // fold (select C, 0, X) -> (and (not C), X) 2918 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2919 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2920 AddToWorkList(NOTNode.getNode()); 2921 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2922 } 2923 // fold (select C, X, 1) -> (or (not C), X) 2924 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2925 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2926 AddToWorkList(NOTNode.getNode()); 2927 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2928 } 2929 // fold (select C, X, 0) -> (and C, X) 2930 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2931 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2932 // fold (select X, X, Y) -> (or X, Y) 2933 // fold (select X, 1, Y) -> (or X, Y) 2934 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2935 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2936 // fold (select X, Y, X) -> (and X, Y) 2937 // fold (select X, Y, 0) -> (and X, Y) 2938 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2939 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2940 2941 // If we can fold this based on the true/false value, do so. 2942 if (SimplifySelectOps(N, N1, N2)) 2943 return SDValue(N, 0); // Don't revisit N. 2944 2945 // fold selects based on a setcc into other things, such as min/max/abs 2946 if (N0.getOpcode() == ISD::SETCC) { 2947 // FIXME: 2948 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2949 // having to say they don't support SELECT_CC on every type the DAG knows 2950 // about, since there is no way to mark an opcode illegal at all value types 2951 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 2952 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 2953 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2954 N0.getOperand(0), N0.getOperand(1), 2955 N1, N2, N0.getOperand(2)); 2956 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2957 } 2958 2959 return SDValue(); 2960} 2961 2962SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2963 SDValue N0 = N->getOperand(0); 2964 SDValue N1 = N->getOperand(1); 2965 SDValue N2 = N->getOperand(2); 2966 SDValue N3 = N->getOperand(3); 2967 SDValue N4 = N->getOperand(4); 2968 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2969 2970 // fold select_cc lhs, rhs, x, x, cc -> x 2971 if (N2 == N3) 2972 return N2; 2973 2974 // Determine if the condition we're dealing with is constant 2975 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2976 N0, N1, CC, N->getDebugLoc(), false); 2977 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2978 2979 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2980 if (!SCCC->isNullValue()) 2981 return N2; // cond always true -> true val 2982 else 2983 return N3; // cond always false -> false val 2984 } 2985 2986 // Fold to a simpler select_cc 2987 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2988 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2989 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2990 SCC.getOperand(2)); 2991 2992 // If we can fold this based on the true/false value, do so. 2993 if (SimplifySelectOps(N, N2, N3)) 2994 return SDValue(N, 0); // Don't revisit N. 2995 2996 // fold select_cc into other things, such as min/max/abs 2997 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2998} 2999 3000SDValue DAGCombiner::visitSETCC(SDNode *N) { 3001 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3002 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3003 N->getDebugLoc()); 3004} 3005 3006// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3007// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3008// transformation. Returns true if extension are possible and the above 3009// mentioned transformation is profitable. 3010static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3011 unsigned ExtOpc, 3012 SmallVector<SDNode*, 4> &ExtendNodes, 3013 const TargetLowering &TLI) { 3014 bool HasCopyToRegUses = false; 3015 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3016 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3017 UE = N0.getNode()->use_end(); 3018 UI != UE; ++UI) { 3019 SDNode *User = *UI; 3020 if (User == N) 3021 continue; 3022 if (UI.getUse().getResNo() != N0.getResNo()) 3023 continue; 3024 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3025 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3026 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3027 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3028 // Sign bits will be lost after a zext. 3029 return false; 3030 bool Add = false; 3031 for (unsigned i = 0; i != 2; ++i) { 3032 SDValue UseOp = User->getOperand(i); 3033 if (UseOp == N0) 3034 continue; 3035 if (!isa<ConstantSDNode>(UseOp)) 3036 return false; 3037 Add = true; 3038 } 3039 if (Add) 3040 ExtendNodes.push_back(User); 3041 continue; 3042 } 3043 // If truncates aren't free and there are users we can't 3044 // extend, it isn't worthwhile. 3045 if (!isTruncFree) 3046 return false; 3047 // Remember if this value is live-out. 3048 if (User->getOpcode() == ISD::CopyToReg) 3049 HasCopyToRegUses = true; 3050 } 3051 3052 if (HasCopyToRegUses) { 3053 bool BothLiveOut = false; 3054 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3055 UI != UE; ++UI) { 3056 SDUse &Use = UI.getUse(); 3057 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3058 BothLiveOut = true; 3059 break; 3060 } 3061 } 3062 if (BothLiveOut) 3063 // Both unextended and extended values are live out. There had better be 3064 // good a reason for the transformation. 3065 return ExtendNodes.size(); 3066 } 3067 return true; 3068} 3069 3070SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3071 SDValue N0 = N->getOperand(0); 3072 EVT VT = N->getValueType(0); 3073 3074 // fold (sext c1) -> c1 3075 if (isa<ConstantSDNode>(N0)) 3076 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3077 3078 // fold (sext (sext x)) -> (sext x) 3079 // fold (sext (aext x)) -> (sext x) 3080 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3081 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3082 N0.getOperand(0)); 3083 3084 if (N0.getOpcode() == ISD::TRUNCATE) { 3085 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3086 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3087 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3088 if (NarrowLoad.getNode()) { 3089 if (NarrowLoad.getNode() != N0.getNode()) 3090 CombineTo(N0.getNode(), NarrowLoad); 3091 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3092 } 3093 3094 // See if the value being truncated is already sign extended. If so, just 3095 // eliminate the trunc/sext pair. 3096 SDValue Op = N0.getOperand(0); 3097 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3098 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3099 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3100 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3101 3102 if (OpBits == DestBits) { 3103 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3104 // bits, it is already ready. 3105 if (NumSignBits > DestBits-MidBits) 3106 return Op; 3107 } else if (OpBits < DestBits) { 3108 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3109 // bits, just sext from i32. 3110 if (NumSignBits > OpBits-MidBits) 3111 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3112 } else { 3113 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3114 // bits, just truncate to i32. 3115 if (NumSignBits > OpBits-MidBits) 3116 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3117 } 3118 3119 // fold (sext (truncate x)) -> (sextinreg x). 3120 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3121 N0.getValueType())) { 3122 if (OpBits < DestBits) 3123 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3124 else if (OpBits > DestBits) 3125 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3126 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3127 DAG.getValueType(N0.getValueType())); 3128 } 3129 } 3130 3131 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3132 if (ISD::isNON_EXTLoad(N0.getNode()) && 3133 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3134 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3135 bool DoXform = true; 3136 SmallVector<SDNode*, 4> SetCCs; 3137 if (!N0.hasOneUse()) 3138 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3139 if (DoXform) { 3140 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3141 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3142 LN0->getChain(), 3143 LN0->getBasePtr(), LN0->getSrcValue(), 3144 LN0->getSrcValueOffset(), 3145 N0.getValueType(), 3146 LN0->isVolatile(), LN0->getAlignment()); 3147 CombineTo(N, ExtLoad); 3148 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3149 N0.getValueType(), ExtLoad); 3150 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3151 3152 // Extend SetCC uses if necessary. 3153 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3154 SDNode *SetCC = SetCCs[i]; 3155 SmallVector<SDValue, 4> Ops; 3156 3157 for (unsigned j = 0; j != 2; ++j) { 3158 SDValue SOp = SetCC->getOperand(j); 3159 if (SOp == Trunc) 3160 Ops.push_back(ExtLoad); 3161 else 3162 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3163 N->getDebugLoc(), VT, SOp)); 3164 } 3165 3166 Ops.push_back(SetCC->getOperand(2)); 3167 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3168 SetCC->getValueType(0), 3169 &Ops[0], Ops.size())); 3170 } 3171 3172 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3173 } 3174 } 3175 3176 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3177 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3178 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3179 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3180 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3181 EVT MemVT = LN0->getMemoryVT(); 3182 if ((!LegalOperations && !LN0->isVolatile()) || 3183 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3184 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3185 LN0->getChain(), 3186 LN0->getBasePtr(), LN0->getSrcValue(), 3187 LN0->getSrcValueOffset(), MemVT, 3188 LN0->isVolatile(), LN0->getAlignment()); 3189 CombineTo(N, ExtLoad); 3190 CombineTo(N0.getNode(), 3191 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3192 N0.getValueType(), ExtLoad), 3193 ExtLoad.getValue(1)); 3194 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3195 } 3196 } 3197 3198 if (N0.getOpcode() == ISD::SETCC) { 3199 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3200 if (VT.isVector() && 3201 // We know that the # elements of the results is the same as the 3202 // # elements of the compare (and the # elements of the compare result 3203 // for that matter). Check to see that they are the same size. If so, 3204 // we know that the element size of the sext'd result matches the 3205 // element size of the compare operands. 3206 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() && 3207 3208 // Only do this before legalize for now. 3209 !LegalOperations) { 3210 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3211 N0.getOperand(1), 3212 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3213 } 3214 3215 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3216 SDValue NegOne = 3217 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 3218 SDValue SCC = 3219 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3220 NegOne, DAG.getConstant(0, VT), 3221 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3222 if (SCC.getNode()) return SCC; 3223 } 3224 3225 3226 3227 // fold (sext x) -> (zext x) if the sign bit is known zero. 3228 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3229 DAG.SignBitIsZero(N0)) 3230 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3231 3232 return SDValue(); 3233} 3234 3235SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3236 SDValue N0 = N->getOperand(0); 3237 EVT VT = N->getValueType(0); 3238 3239 // fold (zext c1) -> c1 3240 if (isa<ConstantSDNode>(N0)) 3241 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3242 // fold (zext (zext x)) -> (zext x) 3243 // fold (zext (aext x)) -> (zext x) 3244 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3245 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3246 N0.getOperand(0)); 3247 3248 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3249 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3250 if (N0.getOpcode() == ISD::TRUNCATE) { 3251 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3252 if (NarrowLoad.getNode()) { 3253 if (NarrowLoad.getNode() != N0.getNode()) 3254 CombineTo(N0.getNode(), NarrowLoad); 3255 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3256 } 3257 } 3258 3259 // fold (zext (truncate x)) -> (and x, mask) 3260 if (N0.getOpcode() == ISD::TRUNCATE && 3261 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) && 3262 (!TLI.isTruncateFree(N0.getOperand(0).getValueType(), 3263 N0.getValueType()) || 3264 !TLI.isZExtFree(N0.getValueType(), VT))) { 3265 SDValue Op = N0.getOperand(0); 3266 if (Op.getValueType().bitsLT(VT)) { 3267 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3268 } else if (Op.getValueType().bitsGT(VT)) { 3269 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3270 } 3271 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3272 N0.getValueType().getScalarType()); 3273 } 3274 3275 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3276 // if either of the casts is not free. 3277 if (N0.getOpcode() == ISD::AND && 3278 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3279 N0.getOperand(1).getOpcode() == ISD::Constant && 3280 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3281 N0.getValueType()) || 3282 !TLI.isZExtFree(N0.getValueType(), VT))) { 3283 SDValue X = N0.getOperand(0).getOperand(0); 3284 if (X.getValueType().bitsLT(VT)) { 3285 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3286 } else if (X.getValueType().bitsGT(VT)) { 3287 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3288 } 3289 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3290 Mask.zext(VT.getSizeInBits()); 3291 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3292 X, DAG.getConstant(Mask, VT)); 3293 } 3294 3295 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3296 if (ISD::isNON_EXTLoad(N0.getNode()) && 3297 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3298 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3299 bool DoXform = true; 3300 SmallVector<SDNode*, 4> SetCCs; 3301 if (!N0.hasOneUse()) 3302 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3303 if (DoXform) { 3304 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3305 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3306 LN0->getChain(), 3307 LN0->getBasePtr(), LN0->getSrcValue(), 3308 LN0->getSrcValueOffset(), 3309 N0.getValueType(), 3310 LN0->isVolatile(), LN0->getAlignment()); 3311 CombineTo(N, ExtLoad); 3312 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3313 N0.getValueType(), ExtLoad); 3314 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3315 3316 // Extend SetCC uses if necessary. 3317 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3318 SDNode *SetCC = SetCCs[i]; 3319 SmallVector<SDValue, 4> Ops; 3320 3321 for (unsigned j = 0; j != 2; ++j) { 3322 SDValue SOp = SetCC->getOperand(j); 3323 if (SOp == Trunc) 3324 Ops.push_back(ExtLoad); 3325 else 3326 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3327 N->getDebugLoc(), VT, SOp)); 3328 } 3329 3330 Ops.push_back(SetCC->getOperand(2)); 3331 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3332 SetCC->getValueType(0), 3333 &Ops[0], Ops.size())); 3334 } 3335 3336 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3337 } 3338 } 3339 3340 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3341 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3342 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3343 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3344 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3345 EVT MemVT = LN0->getMemoryVT(); 3346 if ((!LegalOperations && !LN0->isVolatile()) || 3347 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3348 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3349 LN0->getChain(), 3350 LN0->getBasePtr(), LN0->getSrcValue(), 3351 LN0->getSrcValueOffset(), MemVT, 3352 LN0->isVolatile(), LN0->getAlignment()); 3353 CombineTo(N, ExtLoad); 3354 CombineTo(N0.getNode(), 3355 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3356 ExtLoad), 3357 ExtLoad.getValue(1)); 3358 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3359 } 3360 } 3361 3362 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3363 if (N0.getOpcode() == ISD::SETCC) { 3364 SDValue SCC = 3365 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3366 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3367 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3368 if (SCC.getNode()) return SCC; 3369 } 3370 3371 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3372 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3373 isa<ConstantSDNode>(N0.getOperand(1)) && 3374 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3375 N0.hasOneUse()) { 3376 if (N0.getOpcode() == ISD::SHL) { 3377 // If the original shl may be shifting out bits, do not perform this 3378 // transformation. 3379 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3380 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3381 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3382 if (ShAmt > KnownZeroBits) 3383 return SDValue(); 3384 } 3385 DebugLoc dl = N->getDebugLoc(); 3386 return DAG.getNode(N0.getOpcode(), dl, VT, 3387 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3388 DAG.getNode(ISD::ZERO_EXTEND, dl, 3389 N0.getOperand(1).getValueType(), 3390 N0.getOperand(1))); 3391 } 3392 3393 return SDValue(); 3394} 3395 3396SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3397 SDValue N0 = N->getOperand(0); 3398 EVT VT = N->getValueType(0); 3399 3400 // fold (aext c1) -> c1 3401 if (isa<ConstantSDNode>(N0)) 3402 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3403 // fold (aext (aext x)) -> (aext x) 3404 // fold (aext (zext x)) -> (zext x) 3405 // fold (aext (sext x)) -> (sext x) 3406 if (N0.getOpcode() == ISD::ANY_EXTEND || 3407 N0.getOpcode() == ISD::ZERO_EXTEND || 3408 N0.getOpcode() == ISD::SIGN_EXTEND) 3409 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3410 3411 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3412 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3413 if (N0.getOpcode() == ISD::TRUNCATE) { 3414 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3415 if (NarrowLoad.getNode()) { 3416 if (NarrowLoad.getNode() != N0.getNode()) 3417 CombineTo(N0.getNode(), NarrowLoad); 3418 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3419 } 3420 } 3421 3422 // fold (aext (truncate x)) 3423 if (N0.getOpcode() == ISD::TRUNCATE) { 3424 SDValue TruncOp = N0.getOperand(0); 3425 if (TruncOp.getValueType() == VT) 3426 return TruncOp; // x iff x size == zext size. 3427 if (TruncOp.getValueType().bitsGT(VT)) 3428 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3429 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3430 } 3431 3432 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3433 // if the trunc is not free. 3434 if (N0.getOpcode() == ISD::AND && 3435 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3436 N0.getOperand(1).getOpcode() == ISD::Constant && 3437 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3438 N0.getValueType())) { 3439 SDValue X = N0.getOperand(0).getOperand(0); 3440 if (X.getValueType().bitsLT(VT)) { 3441 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3442 } else if (X.getValueType().bitsGT(VT)) { 3443 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3444 } 3445 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3446 Mask.zext(VT.getSizeInBits()); 3447 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3448 X, DAG.getConstant(Mask, VT)); 3449 } 3450 3451 // fold (aext (load x)) -> (aext (truncate (extload x))) 3452 if (ISD::isNON_EXTLoad(N0.getNode()) && 3453 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3454 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3455 bool DoXform = true; 3456 SmallVector<SDNode*, 4> SetCCs; 3457 if (!N0.hasOneUse()) 3458 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3459 if (DoXform) { 3460 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3461 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3462 LN0->getChain(), 3463 LN0->getBasePtr(), LN0->getSrcValue(), 3464 LN0->getSrcValueOffset(), 3465 N0.getValueType(), 3466 LN0->isVolatile(), LN0->getAlignment()); 3467 CombineTo(N, ExtLoad); 3468 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3469 N0.getValueType(), ExtLoad); 3470 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3471 3472 // Extend SetCC uses if necessary. 3473 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3474 SDNode *SetCC = SetCCs[i]; 3475 SmallVector<SDValue, 4> Ops; 3476 3477 for (unsigned j = 0; j != 2; ++j) { 3478 SDValue SOp = SetCC->getOperand(j); 3479 if (SOp == Trunc) 3480 Ops.push_back(ExtLoad); 3481 else 3482 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3483 N->getDebugLoc(), VT, SOp)); 3484 } 3485 3486 Ops.push_back(SetCC->getOperand(2)); 3487 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3488 SetCC->getValueType(0), 3489 &Ops[0], Ops.size())); 3490 } 3491 3492 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3493 } 3494 } 3495 3496 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3497 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3498 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3499 if (N0.getOpcode() == ISD::LOAD && 3500 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3501 N0.hasOneUse()) { 3502 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3503 EVT MemVT = LN0->getMemoryVT(); 3504 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3505 VT, LN0->getChain(), LN0->getBasePtr(), 3506 LN0->getSrcValue(), 3507 LN0->getSrcValueOffset(), MemVT, 3508 LN0->isVolatile(), LN0->getAlignment()); 3509 CombineTo(N, ExtLoad); 3510 CombineTo(N0.getNode(), 3511 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3512 N0.getValueType(), ExtLoad), 3513 ExtLoad.getValue(1)); 3514 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3515 } 3516 3517 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3518 if (N0.getOpcode() == ISD::SETCC) { 3519 SDValue SCC = 3520 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3521 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3522 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3523 if (SCC.getNode()) 3524 return SCC; 3525 } 3526 3527 return SDValue(); 3528} 3529 3530/// GetDemandedBits - See if the specified operand can be simplified with the 3531/// knowledge that only the bits specified by Mask are used. If so, return the 3532/// simpler operand, otherwise return a null SDValue. 3533SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3534 switch (V.getOpcode()) { 3535 default: break; 3536 case ISD::OR: 3537 case ISD::XOR: 3538 // If the LHS or RHS don't contribute bits to the or, drop them. 3539 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3540 return V.getOperand(1); 3541 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3542 return V.getOperand(0); 3543 break; 3544 case ISD::SRL: 3545 // Only look at single-use SRLs. 3546 if (!V.getNode()->hasOneUse()) 3547 break; 3548 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3549 // See if we can recursively simplify the LHS. 3550 unsigned Amt = RHSC->getZExtValue(); 3551 3552 // Watch out for shift count overflow though. 3553 if (Amt >= Mask.getBitWidth()) break; 3554 APInt NewMask = Mask << Amt; 3555 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3556 if (SimplifyLHS.getNode()) 3557 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3558 SimplifyLHS, V.getOperand(1)); 3559 } 3560 } 3561 return SDValue(); 3562} 3563 3564/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3565/// bits and then truncated to a narrower type and where N is a multiple 3566/// of number of bits of the narrower type, transform it to a narrower load 3567/// from address + N / num of bits of new type. If the result is to be 3568/// extended, also fold the extension to form a extending load. 3569SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3570 unsigned Opc = N->getOpcode(); 3571 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3572 SDValue N0 = N->getOperand(0); 3573 EVT VT = N->getValueType(0); 3574 EVT ExtVT = VT; 3575 3576 // This transformation isn't valid for vector loads. 3577 if (VT.isVector()) 3578 return SDValue(); 3579 3580 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 3581 // extended to VT. 3582 if (Opc == ISD::SIGN_EXTEND_INREG) { 3583 ExtType = ISD::SEXTLOAD; 3584 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3585 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 3586 return SDValue(); 3587 } 3588 3589 unsigned EVTBits = ExtVT.getSizeInBits(); 3590 unsigned ShAmt = 0; 3591 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 3592 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3593 ShAmt = N01->getZExtValue(); 3594 // Is the shift amount a multiple of size of VT? 3595 if ((ShAmt & (EVTBits-1)) == 0) { 3596 N0 = N0.getOperand(0); 3597 // Is the load width a multiple of size of VT? 3598 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 3599 return SDValue(); 3600 } 3601 } 3602 } 3603 3604 // Do not generate loads of non-round integer types since these can 3605 // be expensive (and would be wrong if the type is not byte sized). 3606 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 3607 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3608 // Do not change the width of a volatile load. 3609 !cast<LoadSDNode>(N0)->isVolatile()) { 3610 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3611 EVT PtrType = N0.getOperand(1).getValueType(); 3612 3613 // For big endian targets, we need to adjust the offset to the pointer to 3614 // load the correct bytes. 3615 if (TLI.isBigEndian()) { 3616 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3617 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 3618 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3619 } 3620 3621 uint64_t PtrOff = ShAmt / 8; 3622 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3623 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3624 PtrType, LN0->getBasePtr(), 3625 DAG.getConstant(PtrOff, PtrType)); 3626 AddToWorkList(NewPtr.getNode()); 3627 3628 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3629 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3630 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3631 LN0->isVolatile(), NewAlign) 3632 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3633 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3634 ExtVT, LN0->isVolatile(), NewAlign); 3635 3636 // Replace the old load's chain with the new load's chain. 3637 WorkListRemover DeadNodes(*this); 3638 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3639 &DeadNodes); 3640 3641 // Return the new loaded value. 3642 return Load; 3643 } 3644 3645 return SDValue(); 3646} 3647 3648SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3649 SDValue N0 = N->getOperand(0); 3650 SDValue N1 = N->getOperand(1); 3651 EVT VT = N->getValueType(0); 3652 EVT EVT = cast<VTSDNode>(N1)->getVT(); 3653 unsigned VTBits = VT.getScalarType().getSizeInBits(); 3654 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 3655 3656 // fold (sext_in_reg c1) -> c1 3657 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3658 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3659 3660 // If the input is already sign extended, just drop the extension. 3661 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 3662 return N0; 3663 3664 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3665 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3666 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3667 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3668 N0.getOperand(0), N1); 3669 } 3670 3671 // fold (sext_in_reg (sext x)) -> (sext x) 3672 // fold (sext_in_reg (aext x)) -> (sext x) 3673 // if x is small enough. 3674 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3675 SDValue N00 = N0.getOperand(0); 3676 if (N00.getValueType().getScalarType().getSizeInBits() < EVTBits) 3677 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3678 } 3679 3680 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3681 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3682 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3683 3684 // fold operands of sext_in_reg based on knowledge that the top bits are not 3685 // demanded. 3686 if (SimplifyDemandedBits(SDValue(N, 0))) 3687 return SDValue(N, 0); 3688 3689 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3690 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3691 SDValue NarrowLoad = ReduceLoadWidth(N); 3692 if (NarrowLoad.getNode()) 3693 return NarrowLoad; 3694 3695 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3696 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3697 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3698 if (N0.getOpcode() == ISD::SRL) { 3699 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3700 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 3701 // We can turn this into an SRA iff the input to the SRL is already sign 3702 // extended enough. 3703 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3704 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3705 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3706 N0.getOperand(0), N0.getOperand(1)); 3707 } 3708 } 3709 3710 // fold (sext_inreg (extload x)) -> (sextload x) 3711 if (ISD::isEXTLoad(N0.getNode()) && 3712 ISD::isUNINDEXEDLoad(N0.getNode()) && 3713 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3714 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3715 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3716 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3717 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3718 LN0->getChain(), 3719 LN0->getBasePtr(), LN0->getSrcValue(), 3720 LN0->getSrcValueOffset(), EVT, 3721 LN0->isVolatile(), LN0->getAlignment()); 3722 CombineTo(N, ExtLoad); 3723 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3724 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3725 } 3726 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3727 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3728 N0.hasOneUse() && 3729 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3730 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3731 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3732 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3733 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3734 LN0->getChain(), 3735 LN0->getBasePtr(), LN0->getSrcValue(), 3736 LN0->getSrcValueOffset(), EVT, 3737 LN0->isVolatile(), LN0->getAlignment()); 3738 CombineTo(N, ExtLoad); 3739 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3740 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3741 } 3742 return SDValue(); 3743} 3744 3745SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3746 SDValue N0 = N->getOperand(0); 3747 EVT VT = N->getValueType(0); 3748 3749 // noop truncate 3750 if (N0.getValueType() == N->getValueType(0)) 3751 return N0; 3752 // fold (truncate c1) -> c1 3753 if (isa<ConstantSDNode>(N0)) 3754 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3755 // fold (truncate (truncate x)) -> (truncate x) 3756 if (N0.getOpcode() == ISD::TRUNCATE) 3757 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3758 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3759 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3760 N0.getOpcode() == ISD::ANY_EXTEND) { 3761 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3762 // if the source is smaller than the dest, we still need an extend 3763 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3764 N0.getOperand(0)); 3765 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3766 // if the source is larger than the dest, than we just need the truncate 3767 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3768 else 3769 // if the source and dest are the same type, we can drop both the extend 3770 // and the truncate. 3771 return N0.getOperand(0); 3772 } 3773 3774 // See if we can simplify the input to this truncate through knowledge that 3775 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3776 // -> trunc y 3777 SDValue Shorter = 3778 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3779 VT.getSizeInBits())); 3780 if (Shorter.getNode()) 3781 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3782 3783 // fold (truncate (load x)) -> (smaller load x) 3784 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3785 return ReduceLoadWidth(N); 3786} 3787 3788static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3789 SDValue Elt = N->getOperand(i); 3790 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3791 return Elt.getNode(); 3792 return Elt.getOperand(Elt.getResNo()).getNode(); 3793} 3794 3795/// CombineConsecutiveLoads - build_pair (load, load) -> load 3796/// if load locations are consecutive. 3797SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 3798 assert(N->getOpcode() == ISD::BUILD_PAIR); 3799 3800 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3801 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3802 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3803 return SDValue(); 3804 EVT LD1VT = LD1->getValueType(0); 3805 3806 if (ISD::isNON_EXTLoad(LD2) && 3807 LD2->hasOneUse() && 3808 // If both are volatile this would reduce the number of volatile loads. 3809 // If one is volatile it might be ok, but play conservative and bail out. 3810 !LD1->isVolatile() && 3811 !LD2->isVolatile() && 3812 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 3813 unsigned Align = LD1->getAlignment(); 3814 unsigned NewAlign = TLI.getTargetData()-> 3815 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3816 3817 if (NewAlign <= Align && 3818 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3819 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3820 LD1->getBasePtr(), LD1->getSrcValue(), 3821 LD1->getSrcValueOffset(), false, Align); 3822 } 3823 3824 return SDValue(); 3825} 3826 3827SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3828 SDValue N0 = N->getOperand(0); 3829 EVT VT = N->getValueType(0); 3830 3831 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3832 // Only do this before legalize, since afterward the target may be depending 3833 // on the bitconvert. 3834 // First check to see if this is all constant. 3835 if (!LegalTypes && 3836 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3837 VT.isVector()) { 3838 bool isSimple = true; 3839 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3840 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3841 N0.getOperand(i).getOpcode() != ISD::Constant && 3842 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3843 isSimple = false; 3844 break; 3845 } 3846 3847 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 3848 assert(!DestEltVT.isVector() && 3849 "Element type of vector ValueType must not be vector!"); 3850 if (isSimple) 3851 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3852 } 3853 3854 // If the input is a constant, let getNode fold it. 3855 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3856 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3857 if (Res.getNode() != N) { 3858 if (!LegalOperations || 3859 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 3860 return Res; 3861 3862 // Folding it resulted in an illegal node, and it's too late to 3863 // do that. Clean up the old node and forego the transformation. 3864 // Ideally this won't happen very often, because instcombine 3865 // and the earlier dagcombine runs (where illegal nodes are 3866 // permitted) should have folded most of them already. 3867 DAG.DeleteNode(Res.getNode()); 3868 } 3869 } 3870 3871 // (conv (conv x, t1), t2) -> (conv x, t2) 3872 if (N0.getOpcode() == ISD::BIT_CONVERT) 3873 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3874 N0.getOperand(0)); 3875 3876 // fold (conv (load x)) -> (load (conv*)x) 3877 // If the resultant load doesn't need a higher alignment than the original! 3878 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3879 // Do not change the width of a volatile load. 3880 !cast<LoadSDNode>(N0)->isVolatile() && 3881 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3882 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3883 unsigned Align = TLI.getTargetData()-> 3884 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3885 unsigned OrigAlign = LN0->getAlignment(); 3886 3887 if (Align <= OrigAlign) { 3888 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3889 LN0->getBasePtr(), 3890 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3891 LN0->isVolatile(), OrigAlign); 3892 AddToWorkList(N); 3893 CombineTo(N0.getNode(), 3894 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3895 N0.getValueType(), Load), 3896 Load.getValue(1)); 3897 return Load; 3898 } 3899 } 3900 3901 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3902 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3903 // This often reduces constant pool loads. 3904 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3905 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3906 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3907 N0.getOperand(0)); 3908 AddToWorkList(NewConv.getNode()); 3909 3910 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3911 if (N0.getOpcode() == ISD::FNEG) 3912 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3913 NewConv, DAG.getConstant(SignBit, VT)); 3914 assert(N0.getOpcode() == ISD::FABS); 3915 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3916 NewConv, DAG.getConstant(~SignBit, VT)); 3917 } 3918 3919 // fold (bitconvert (fcopysign cst, x)) -> 3920 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3921 // Note that we don't handle (copysign x, cst) because this can always be 3922 // folded to an fneg or fabs. 3923 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3924 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3925 VT.isInteger() && !VT.isVector()) { 3926 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3927 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 3928 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3929 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3930 IntXVT, N0.getOperand(1)); 3931 AddToWorkList(X.getNode()); 3932 3933 // If X has a different width than the result/lhs, sext it or truncate it. 3934 unsigned VTWidth = VT.getSizeInBits(); 3935 if (OrigXWidth < VTWidth) { 3936 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3937 AddToWorkList(X.getNode()); 3938 } else if (OrigXWidth > VTWidth) { 3939 // To get the sign bit in the right place, we have to shift it right 3940 // before truncating. 3941 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3942 X.getValueType(), X, 3943 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3944 AddToWorkList(X.getNode()); 3945 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3946 AddToWorkList(X.getNode()); 3947 } 3948 3949 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3950 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3951 X, DAG.getConstant(SignBit, VT)); 3952 AddToWorkList(X.getNode()); 3953 3954 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3955 VT, N0.getOperand(0)); 3956 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3957 Cst, DAG.getConstant(~SignBit, VT)); 3958 AddToWorkList(Cst.getNode()); 3959 3960 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3961 } 3962 } 3963 3964 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3965 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3966 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3967 if (CombineLD.getNode()) 3968 return CombineLD; 3969 } 3970 3971 return SDValue(); 3972} 3973 3974SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3975 EVT VT = N->getValueType(0); 3976 return CombineConsecutiveLoads(N, VT); 3977} 3978 3979/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3980/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3981/// destination element value type. 3982SDValue DAGCombiner:: 3983ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 3984 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 3985 3986 // If this is already the right type, we're done. 3987 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3988 3989 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3990 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3991 3992 // If this is a conversion of N elements of one type to N elements of another 3993 // type, convert each element. This handles FP<->INT cases. 3994 if (SrcBitSize == DstBitSize) { 3995 SmallVector<SDValue, 8> Ops; 3996 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3997 SDValue Op = BV->getOperand(i); 3998 // If the vector element type is not legal, the BUILD_VECTOR operands 3999 // are promoted and implicitly truncated. Make that explicit here. 4000 if (Op.getValueType() != SrcEltVT) 4001 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4002 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 4003 DstEltVT, Op)); 4004 AddToWorkList(Ops.back().getNode()); 4005 } 4006 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4007 BV->getValueType(0).getVectorNumElements()); 4008 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4009 &Ops[0], Ops.size()); 4010 } 4011 4012 // Otherwise, we're growing or shrinking the elements. To avoid having to 4013 // handle annoying details of growing/shrinking FP values, we convert them to 4014 // int first. 4015 if (SrcEltVT.isFloatingPoint()) { 4016 // Convert the input float vector to a int vector where the elements are the 4017 // same sizes. 4018 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4019 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4020 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 4021 SrcEltVT = IntVT; 4022 } 4023 4024 // Now we know the input is an integer vector. If the output is a FP type, 4025 // convert to integer first, then to FP of the right size. 4026 if (DstEltVT.isFloatingPoint()) { 4027 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4028 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4029 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 4030 4031 // Next, convert to FP elements of the same size. 4032 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 4033 } 4034 4035 // Okay, we know the src/dst types are both integers of differing types. 4036 // Handling growing first. 4037 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4038 if (SrcBitSize < DstBitSize) { 4039 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4040 4041 SmallVector<SDValue, 8> Ops; 4042 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4043 i += NumInputsPerOutput) { 4044 bool isLE = TLI.isLittleEndian(); 4045 APInt NewBits = APInt(DstBitSize, 0); 4046 bool EltIsUndef = true; 4047 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4048 // Shift the previously computed bits over. 4049 NewBits <<= SrcBitSize; 4050 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4051 if (Op.getOpcode() == ISD::UNDEF) continue; 4052 EltIsUndef = false; 4053 4054 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 4055 zextOrTrunc(SrcBitSize).zext(DstBitSize)); 4056 } 4057 4058 if (EltIsUndef) 4059 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4060 else 4061 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4062 } 4063 4064 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4065 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4066 &Ops[0], Ops.size()); 4067 } 4068 4069 // Finally, this must be the case where we are shrinking elements: each input 4070 // turns into multiple outputs. 4071 bool isS2V = ISD::isScalarToVector(BV); 4072 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4073 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4074 NumOutputsPerInput*BV->getNumOperands()); 4075 SmallVector<SDValue, 8> Ops; 4076 4077 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4078 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4079 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4080 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4081 continue; 4082 } 4083 4084 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 4085 getAPIntValue()).zextOrTrunc(SrcBitSize); 4086 4087 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4088 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 4089 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4090 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 4091 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4092 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4093 Ops[0]); 4094 OpVal = OpVal.lshr(DstBitSize); 4095 } 4096 4097 // For big endian targets, swap the order of the pieces of each element. 4098 if (TLI.isBigEndian()) 4099 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4100 } 4101 4102 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4103 &Ops[0], Ops.size()); 4104} 4105 4106SDValue DAGCombiner::visitFADD(SDNode *N) { 4107 SDValue N0 = N->getOperand(0); 4108 SDValue N1 = N->getOperand(1); 4109 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4110 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4111 EVT VT = N->getValueType(0); 4112 4113 // fold vector ops 4114 if (VT.isVector()) { 4115 SDValue FoldedVOp = SimplifyVBinOp(N); 4116 if (FoldedVOp.getNode()) return FoldedVOp; 4117 } 4118 4119 // fold (fadd c1, c2) -> (fadd c1, c2) 4120 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4121 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4122 // canonicalize constant to RHS 4123 if (N0CFP && !N1CFP) 4124 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4125 // fold (fadd A, 0) -> A 4126 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4127 return N0; 4128 // fold (fadd A, (fneg B)) -> (fsub A, B) 4129 if (isNegatibleForFree(N1, LegalOperations) == 2) 4130 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4131 GetNegatedExpression(N1, DAG, LegalOperations)); 4132 // fold (fadd (fneg A), B) -> (fsub B, A) 4133 if (isNegatibleForFree(N0, LegalOperations) == 2) 4134 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4135 GetNegatedExpression(N0, DAG, LegalOperations)); 4136 4137 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4138 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4139 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4140 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4141 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4142 N0.getOperand(1), N1)); 4143 4144 return SDValue(); 4145} 4146 4147SDValue DAGCombiner::visitFSUB(SDNode *N) { 4148 SDValue N0 = N->getOperand(0); 4149 SDValue N1 = N->getOperand(1); 4150 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4151 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4152 EVT VT = N->getValueType(0); 4153 4154 // fold vector ops 4155 if (VT.isVector()) { 4156 SDValue FoldedVOp = SimplifyVBinOp(N); 4157 if (FoldedVOp.getNode()) return FoldedVOp; 4158 } 4159 4160 // fold (fsub c1, c2) -> c1-c2 4161 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4162 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4163 // fold (fsub A, 0) -> A 4164 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4165 return N0; 4166 // fold (fsub 0, B) -> -B 4167 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4168 if (isNegatibleForFree(N1, LegalOperations)) 4169 return GetNegatedExpression(N1, DAG, LegalOperations); 4170 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4171 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4172 } 4173 // fold (fsub A, (fneg B)) -> (fadd A, B) 4174 if (isNegatibleForFree(N1, LegalOperations)) 4175 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4176 GetNegatedExpression(N1, DAG, LegalOperations)); 4177 4178 return SDValue(); 4179} 4180 4181SDValue DAGCombiner::visitFMUL(SDNode *N) { 4182 SDValue N0 = N->getOperand(0); 4183 SDValue N1 = N->getOperand(1); 4184 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4185 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4186 EVT VT = N->getValueType(0); 4187 4188 // fold vector ops 4189 if (VT.isVector()) { 4190 SDValue FoldedVOp = SimplifyVBinOp(N); 4191 if (FoldedVOp.getNode()) return FoldedVOp; 4192 } 4193 4194 // fold (fmul c1, c2) -> c1*c2 4195 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4196 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4197 // canonicalize constant to RHS 4198 if (N0CFP && !N1CFP) 4199 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4200 // fold (fmul A, 0) -> 0 4201 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4202 return N1; 4203 // fold (fmul A, 0) -> 0, vector edition. 4204 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4205 return N1; 4206 // fold (fmul X, 2.0) -> (fadd X, X) 4207 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4208 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4209 // fold (fmul X, -1.0) -> (fneg X) 4210 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4211 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4212 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4213 4214 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4215 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4216 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4217 // Both can be negated for free, check to see if at least one is cheaper 4218 // negated. 4219 if (LHSNeg == 2 || RHSNeg == 2) 4220 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4221 GetNegatedExpression(N0, DAG, LegalOperations), 4222 GetNegatedExpression(N1, DAG, LegalOperations)); 4223 } 4224 } 4225 4226 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4227 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4228 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4229 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4230 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4231 N0.getOperand(1), N1)); 4232 4233 return SDValue(); 4234} 4235 4236SDValue DAGCombiner::visitFDIV(SDNode *N) { 4237 SDValue N0 = N->getOperand(0); 4238 SDValue N1 = N->getOperand(1); 4239 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4240 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4241 EVT VT = N->getValueType(0); 4242 4243 // fold vector ops 4244 if (VT.isVector()) { 4245 SDValue FoldedVOp = SimplifyVBinOp(N); 4246 if (FoldedVOp.getNode()) return FoldedVOp; 4247 } 4248 4249 // fold (fdiv c1, c2) -> c1/c2 4250 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4251 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4252 4253 4254 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4255 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4256 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4257 // Both can be negated for free, check to see if at least one is cheaper 4258 // negated. 4259 if (LHSNeg == 2 || RHSNeg == 2) 4260 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4261 GetNegatedExpression(N0, DAG, LegalOperations), 4262 GetNegatedExpression(N1, DAG, LegalOperations)); 4263 } 4264 } 4265 4266 return SDValue(); 4267} 4268 4269SDValue DAGCombiner::visitFREM(SDNode *N) { 4270 SDValue N0 = N->getOperand(0); 4271 SDValue N1 = N->getOperand(1); 4272 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4273 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4274 EVT VT = N->getValueType(0); 4275 4276 // fold (frem c1, c2) -> fmod(c1,c2) 4277 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4278 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4279 4280 return SDValue(); 4281} 4282 4283SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4284 SDValue N0 = N->getOperand(0); 4285 SDValue N1 = N->getOperand(1); 4286 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4287 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4288 EVT VT = N->getValueType(0); 4289 4290 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4291 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4292 4293 if (N1CFP) { 4294 const APFloat& V = N1CFP->getValueAPF(); 4295 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4296 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4297 if (!V.isNegative()) { 4298 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4299 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4300 } else { 4301 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4302 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4303 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4304 } 4305 } 4306 4307 // copysign(fabs(x), y) -> copysign(x, y) 4308 // copysign(fneg(x), y) -> copysign(x, y) 4309 // copysign(copysign(x,z), y) -> copysign(x, y) 4310 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4311 N0.getOpcode() == ISD::FCOPYSIGN) 4312 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4313 N0.getOperand(0), N1); 4314 4315 // copysign(x, abs(y)) -> abs(x) 4316 if (N1.getOpcode() == ISD::FABS) 4317 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4318 4319 // copysign(x, copysign(y,z)) -> copysign(x, z) 4320 if (N1.getOpcode() == ISD::FCOPYSIGN) 4321 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4322 N0, N1.getOperand(1)); 4323 4324 // copysign(x, fp_extend(y)) -> copysign(x, y) 4325 // copysign(x, fp_round(y)) -> copysign(x, y) 4326 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4327 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4328 N0, N1.getOperand(0)); 4329 4330 return SDValue(); 4331} 4332 4333SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4334 SDValue N0 = N->getOperand(0); 4335 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4336 EVT VT = N->getValueType(0); 4337 EVT OpVT = N0.getValueType(); 4338 4339 // fold (sint_to_fp c1) -> c1fp 4340 if (N0C && OpVT != MVT::ppcf128) 4341 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4342 4343 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4344 // but UINT_TO_FP is legal on this target, try to convert. 4345 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4346 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4347 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4348 if (DAG.SignBitIsZero(N0)) 4349 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4350 } 4351 4352 return SDValue(); 4353} 4354 4355SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4356 SDValue N0 = N->getOperand(0); 4357 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4358 EVT VT = N->getValueType(0); 4359 EVT OpVT = N0.getValueType(); 4360 4361 // fold (uint_to_fp c1) -> c1fp 4362 if (N0C && OpVT != MVT::ppcf128) 4363 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4364 4365 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4366 // but SINT_TO_FP is legal on this target, try to convert. 4367 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4368 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4369 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4370 if (DAG.SignBitIsZero(N0)) 4371 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4372 } 4373 4374 return SDValue(); 4375} 4376 4377SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4378 SDValue N0 = N->getOperand(0); 4379 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4380 EVT VT = N->getValueType(0); 4381 4382 // fold (fp_to_sint c1fp) -> c1 4383 if (N0CFP) 4384 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4385 4386 return SDValue(); 4387} 4388 4389SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4390 SDValue N0 = N->getOperand(0); 4391 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4392 EVT VT = N->getValueType(0); 4393 4394 // fold (fp_to_uint c1fp) -> c1 4395 if (N0CFP && VT != MVT::ppcf128) 4396 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4397 4398 return SDValue(); 4399} 4400 4401SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4402 SDValue N0 = N->getOperand(0); 4403 SDValue N1 = N->getOperand(1); 4404 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4405 EVT VT = N->getValueType(0); 4406 4407 // fold (fp_round c1fp) -> c1fp 4408 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4409 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4410 4411 // fold (fp_round (fp_extend x)) -> x 4412 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4413 return N0.getOperand(0); 4414 4415 // fold (fp_round (fp_round x)) -> (fp_round x) 4416 if (N0.getOpcode() == ISD::FP_ROUND) { 4417 // This is a value preserving truncation if both round's are. 4418 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4419 N0.getNode()->getConstantOperandVal(1) == 1; 4420 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4421 DAG.getIntPtrConstant(IsTrunc)); 4422 } 4423 4424 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4425 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4426 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4427 N0.getOperand(0), N1); 4428 AddToWorkList(Tmp.getNode()); 4429 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4430 Tmp, N0.getOperand(1)); 4431 } 4432 4433 return SDValue(); 4434} 4435 4436SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4437 SDValue N0 = N->getOperand(0); 4438 EVT VT = N->getValueType(0); 4439 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4440 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4441 4442 // fold (fp_round_inreg c1fp) -> c1fp 4443 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4444 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4445 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4446 } 4447 4448 return SDValue(); 4449} 4450 4451SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4452 SDValue N0 = N->getOperand(0); 4453 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4454 EVT VT = N->getValueType(0); 4455 4456 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4457 if (N->hasOneUse() && 4458 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4459 return SDValue(); 4460 4461 // fold (fp_extend c1fp) -> c1fp 4462 if (N0CFP && VT != MVT::ppcf128) 4463 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4464 4465 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4466 // value of X. 4467 if (N0.getOpcode() == ISD::FP_ROUND 4468 && N0.getNode()->getConstantOperandVal(1) == 1) { 4469 SDValue In = N0.getOperand(0); 4470 if (In.getValueType() == VT) return In; 4471 if (VT.bitsLT(In.getValueType())) 4472 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4473 In, N0.getOperand(1)); 4474 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4475 } 4476 4477 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4478 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4479 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4480 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4481 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4482 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4483 LN0->getChain(), 4484 LN0->getBasePtr(), LN0->getSrcValue(), 4485 LN0->getSrcValueOffset(), 4486 N0.getValueType(), 4487 LN0->isVolatile(), LN0->getAlignment()); 4488 CombineTo(N, ExtLoad); 4489 CombineTo(N0.getNode(), 4490 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4491 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4492 ExtLoad.getValue(1)); 4493 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4494 } 4495 4496 return SDValue(); 4497} 4498 4499SDValue DAGCombiner::visitFNEG(SDNode *N) { 4500 SDValue N0 = N->getOperand(0); 4501 EVT VT = N->getValueType(0); 4502 4503 if (isNegatibleForFree(N0, LegalOperations)) 4504 return GetNegatedExpression(N0, DAG, LegalOperations); 4505 4506 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4507 // constant pool values. 4508 if (N0.getOpcode() == ISD::BIT_CONVERT && 4509 !VT.isVector() && 4510 N0.getNode()->hasOneUse() && 4511 N0.getOperand(0).getValueType().isInteger()) { 4512 SDValue Int = N0.getOperand(0); 4513 EVT IntVT = Int.getValueType(); 4514 if (IntVT.isInteger() && !IntVT.isVector()) { 4515 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4516 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4517 AddToWorkList(Int.getNode()); 4518 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4519 VT, Int); 4520 } 4521 } 4522 4523 return SDValue(); 4524} 4525 4526SDValue DAGCombiner::visitFABS(SDNode *N) { 4527 SDValue N0 = N->getOperand(0); 4528 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4529 EVT VT = N->getValueType(0); 4530 4531 // fold (fabs c1) -> fabs(c1) 4532 if (N0CFP && VT != MVT::ppcf128) 4533 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4534 // fold (fabs (fabs x)) -> (fabs x) 4535 if (N0.getOpcode() == ISD::FABS) 4536 return N->getOperand(0); 4537 // fold (fabs (fneg x)) -> (fabs x) 4538 // fold (fabs (fcopysign x, y)) -> (fabs x) 4539 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4540 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4541 4542 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4543 // constant pool values. 4544 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4545 N0.getOperand(0).getValueType().isInteger() && 4546 !N0.getOperand(0).getValueType().isVector()) { 4547 SDValue Int = N0.getOperand(0); 4548 EVT IntVT = Int.getValueType(); 4549 if (IntVT.isInteger() && !IntVT.isVector()) { 4550 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4551 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4552 AddToWorkList(Int.getNode()); 4553 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4554 N->getValueType(0), Int); 4555 } 4556 } 4557 4558 return SDValue(); 4559} 4560 4561SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4562 SDValue Chain = N->getOperand(0); 4563 SDValue N1 = N->getOperand(1); 4564 SDValue N2 = N->getOperand(2); 4565 4566 // If N is a constant we could fold this into a fallthrough or unconditional 4567 // branch. However that doesn't happen very often in normal code, because 4568 // Instcombine/SimplifyCFG should have handled the available opportunities. 4569 // If we did this folding here, it would be necessary to update the 4570 // MachineBasicBlock CFG, which is awkward. 4571 4572 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4573 // on the target. 4574 if (N1.getOpcode() == ISD::SETCC && 4575 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4576 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4577 Chain, N1.getOperand(2), 4578 N1.getOperand(0), N1.getOperand(1), N2); 4579 } 4580 4581 SDNode *Trunc = 0; 4582 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) { 4583 // Look pass truncate. 4584 Trunc = N1.getNode(); 4585 N1 = N1.getOperand(0); 4586 } 4587 4588 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4589 // Match this pattern so that we can generate simpler code: 4590 // 4591 // %a = ... 4592 // %b = and i32 %a, 2 4593 // %c = srl i32 %b, 1 4594 // brcond i32 %c ... 4595 // 4596 // into 4597 // 4598 // %a = ... 4599 // %b = and i32 %a, 2 4600 // %c = setcc eq %b, 0 4601 // brcond %c ... 4602 // 4603 // This applies only when the AND constant value has one bit set and the 4604 // SRL constant is equal to the log2 of the AND constant. The back-end is 4605 // smart enough to convert the result into a TEST/JMP sequence. 4606 SDValue Op0 = N1.getOperand(0); 4607 SDValue Op1 = N1.getOperand(1); 4608 4609 if (Op0.getOpcode() == ISD::AND && 4610 Op1.getOpcode() == ISD::Constant) { 4611 SDValue AndOp1 = Op0.getOperand(1); 4612 4613 if (AndOp1.getOpcode() == ISD::Constant) { 4614 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4615 4616 if (AndConst.isPowerOf2() && 4617 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4618 SDValue SetCC = 4619 DAG.getSetCC(N->getDebugLoc(), 4620 TLI.getSetCCResultType(Op0.getValueType()), 4621 Op0, DAG.getConstant(0, Op0.getValueType()), 4622 ISD::SETNE); 4623 4624 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4625 MVT::Other, Chain, SetCC, N2); 4626 // Don't add the new BRCond into the worklist or else SimplifySelectCC 4627 // will convert it back to (X & C1) >> C2. 4628 CombineTo(N, NewBRCond, false); 4629 // Truncate is dead. 4630 if (Trunc) { 4631 removeFromWorkList(Trunc); 4632 DAG.DeleteNode(Trunc); 4633 } 4634 // Replace the uses of SRL with SETCC 4635 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4636 removeFromWorkList(N1.getNode()); 4637 DAG.DeleteNode(N1.getNode()); 4638 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4639 } 4640 } 4641 } 4642 } 4643 4644 return SDValue(); 4645} 4646 4647// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4648// 4649SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4650 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4651 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4652 4653 // If N is a constant we could fold this into a fallthrough or unconditional 4654 // branch. However that doesn't happen very often in normal code, because 4655 // Instcombine/SimplifyCFG should have handled the available opportunities. 4656 // If we did this folding here, it would be necessary to update the 4657 // MachineBasicBlock CFG, which is awkward. 4658 4659 // Use SimplifySetCC to simplify SETCC's. 4660 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4661 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4662 false); 4663 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4664 4665 // fold to a simpler setcc 4666 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4667 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4668 N->getOperand(0), Simp.getOperand(2), 4669 Simp.getOperand(0), Simp.getOperand(1), 4670 N->getOperand(4)); 4671 4672 return SDValue(); 4673} 4674 4675/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4676/// pre-indexed load / store when the base pointer is an add or subtract 4677/// and it has other uses besides the load / store. After the 4678/// transformation, the new indexed load / store has effectively folded 4679/// the add / subtract in and all of its other uses are redirected to the 4680/// new load / store. 4681bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4682 if (!LegalOperations) 4683 return false; 4684 4685 bool isLoad = true; 4686 SDValue Ptr; 4687 EVT VT; 4688 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4689 if (LD->isIndexed()) 4690 return false; 4691 VT = LD->getMemoryVT(); 4692 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4693 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4694 return false; 4695 Ptr = LD->getBasePtr(); 4696 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4697 if (ST->isIndexed()) 4698 return false; 4699 VT = ST->getMemoryVT(); 4700 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4701 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4702 return false; 4703 Ptr = ST->getBasePtr(); 4704 isLoad = false; 4705 } else { 4706 return false; 4707 } 4708 4709 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4710 // out. There is no reason to make this a preinc/predec. 4711 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4712 Ptr.getNode()->hasOneUse()) 4713 return false; 4714 4715 // Ask the target to do addressing mode selection. 4716 SDValue BasePtr; 4717 SDValue Offset; 4718 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4719 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4720 return false; 4721 // Don't create a indexed load / store with zero offset. 4722 if (isa<ConstantSDNode>(Offset) && 4723 cast<ConstantSDNode>(Offset)->isNullValue()) 4724 return false; 4725 4726 // Try turning it into a pre-indexed load / store except when: 4727 // 1) The new base ptr is a frame index. 4728 // 2) If N is a store and the new base ptr is either the same as or is a 4729 // predecessor of the value being stored. 4730 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4731 // that would create a cycle. 4732 // 4) All uses are load / store ops that use it as old base ptr. 4733 4734 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4735 // (plus the implicit offset) to a register to preinc anyway. 4736 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4737 return false; 4738 4739 // Check #2. 4740 if (!isLoad) { 4741 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4742 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4743 return false; 4744 } 4745 4746 // Now check for #3 and #4. 4747 bool RealUse = false; 4748 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4749 E = Ptr.getNode()->use_end(); I != E; ++I) { 4750 SDNode *Use = *I; 4751 if (Use == N) 4752 continue; 4753 if (Use->isPredecessorOf(N)) 4754 return false; 4755 4756 if (!((Use->getOpcode() == ISD::LOAD && 4757 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4758 (Use->getOpcode() == ISD::STORE && 4759 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4760 RealUse = true; 4761 } 4762 4763 if (!RealUse) 4764 return false; 4765 4766 SDValue Result; 4767 if (isLoad) 4768 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4769 BasePtr, Offset, AM); 4770 else 4771 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4772 BasePtr, Offset, AM); 4773 ++PreIndexedNodes; 4774 ++NodesCombined; 4775 DEBUG(dbgs() << "\nReplacing.4 "; 4776 N->dump(&DAG); 4777 dbgs() << "\nWith: "; 4778 Result.getNode()->dump(&DAG); 4779 dbgs() << '\n'); 4780 WorkListRemover DeadNodes(*this); 4781 if (isLoad) { 4782 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4783 &DeadNodes); 4784 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4785 &DeadNodes); 4786 } else { 4787 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4788 &DeadNodes); 4789 } 4790 4791 // Finally, since the node is now dead, remove it from the graph. 4792 DAG.DeleteNode(N); 4793 4794 // Replace the uses of Ptr with uses of the updated base value. 4795 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4796 &DeadNodes); 4797 removeFromWorkList(Ptr.getNode()); 4798 DAG.DeleteNode(Ptr.getNode()); 4799 4800 return true; 4801} 4802 4803/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4804/// add / sub of the base pointer node into a post-indexed load / store. 4805/// The transformation folded the add / subtract into the new indexed 4806/// load / store effectively and all of its uses are redirected to the 4807/// new load / store. 4808bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4809 if (!LegalOperations) 4810 return false; 4811 4812 bool isLoad = true; 4813 SDValue Ptr; 4814 EVT VT; 4815 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4816 if (LD->isIndexed()) 4817 return false; 4818 VT = LD->getMemoryVT(); 4819 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4820 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4821 return false; 4822 Ptr = LD->getBasePtr(); 4823 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4824 if (ST->isIndexed()) 4825 return false; 4826 VT = ST->getMemoryVT(); 4827 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4828 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4829 return false; 4830 Ptr = ST->getBasePtr(); 4831 isLoad = false; 4832 } else { 4833 return false; 4834 } 4835 4836 if (Ptr.getNode()->hasOneUse()) 4837 return false; 4838 4839 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4840 E = Ptr.getNode()->use_end(); I != E; ++I) { 4841 SDNode *Op = *I; 4842 if (Op == N || 4843 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4844 continue; 4845 4846 SDValue BasePtr; 4847 SDValue Offset; 4848 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4849 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4850 if (Ptr == Offset && Op->getOpcode() == ISD::ADD) 4851 std::swap(BasePtr, Offset); 4852 if (Ptr != BasePtr) 4853 continue; 4854 // Don't create a indexed load / store with zero offset. 4855 if (isa<ConstantSDNode>(Offset) && 4856 cast<ConstantSDNode>(Offset)->isNullValue()) 4857 continue; 4858 4859 // Try turning it into a post-indexed load / store except when 4860 // 1) All uses are load / store ops that use it as base ptr. 4861 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4862 // nor a successor of N. Otherwise, if Op is folded that would 4863 // create a cycle. 4864 4865 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4866 continue; 4867 4868 // Check for #1. 4869 bool TryNext = false; 4870 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4871 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4872 SDNode *Use = *II; 4873 if (Use == Ptr.getNode()) 4874 continue; 4875 4876 // If all the uses are load / store addresses, then don't do the 4877 // transformation. 4878 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4879 bool RealUse = false; 4880 for (SDNode::use_iterator III = Use->use_begin(), 4881 EEE = Use->use_end(); III != EEE; ++III) { 4882 SDNode *UseUse = *III; 4883 if (!((UseUse->getOpcode() == ISD::LOAD && 4884 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4885 (UseUse->getOpcode() == ISD::STORE && 4886 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4887 RealUse = true; 4888 } 4889 4890 if (!RealUse) { 4891 TryNext = true; 4892 break; 4893 } 4894 } 4895 } 4896 4897 if (TryNext) 4898 continue; 4899 4900 // Check for #2 4901 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4902 SDValue Result = isLoad 4903 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4904 BasePtr, Offset, AM) 4905 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4906 BasePtr, Offset, AM); 4907 ++PostIndexedNodes; 4908 ++NodesCombined; 4909 DEBUG(dbgs() << "\nReplacing.5 "; 4910 N->dump(&DAG); 4911 dbgs() << "\nWith: "; 4912 Result.getNode()->dump(&DAG); 4913 dbgs() << '\n'); 4914 WorkListRemover DeadNodes(*this); 4915 if (isLoad) { 4916 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4917 &DeadNodes); 4918 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4919 &DeadNodes); 4920 } else { 4921 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4922 &DeadNodes); 4923 } 4924 4925 // Finally, since the node is now dead, remove it from the graph. 4926 DAG.DeleteNode(N); 4927 4928 // Replace the uses of Use with uses of the updated base value. 4929 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4930 Result.getValue(isLoad ? 1 : 0), 4931 &DeadNodes); 4932 removeFromWorkList(Op); 4933 DAG.DeleteNode(Op); 4934 return true; 4935 } 4936 } 4937 } 4938 4939 return false; 4940} 4941 4942SDValue DAGCombiner::visitLOAD(SDNode *N) { 4943 LoadSDNode *LD = cast<LoadSDNode>(N); 4944 SDValue Chain = LD->getChain(); 4945 SDValue Ptr = LD->getBasePtr(); 4946 4947 // Try to infer better alignment information than the load already has. 4948 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 4949 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 4950 if (Align > LD->getAlignment()) 4951 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4952 LD->getValueType(0), 4953 Chain, Ptr, LD->getSrcValue(), 4954 LD->getSrcValueOffset(), LD->getMemoryVT(), 4955 LD->isVolatile(), Align); 4956 } 4957 } 4958 4959 // If load is not volatile and there are no uses of the loaded value (and 4960 // the updated indexed value in case of indexed loads), change uses of the 4961 // chain value into uses of the chain input (i.e. delete the dead load). 4962 if (!LD->isVolatile()) { 4963 if (N->getValueType(1) == MVT::Other) { 4964 // Unindexed loads. 4965 if (N->hasNUsesOfValue(0, 0)) { 4966 // It's not safe to use the two value CombineTo variant here. e.g. 4967 // v1, chain2 = load chain1, loc 4968 // v2, chain3 = load chain2, loc 4969 // v3 = add v2, c 4970 // Now we replace use of chain2 with chain1. This makes the second load 4971 // isomorphic to the one we are deleting, and thus makes this load live. 4972 DEBUG(dbgs() << "\nReplacing.6 "; 4973 N->dump(&DAG); 4974 dbgs() << "\nWith chain: "; 4975 Chain.getNode()->dump(&DAG); 4976 dbgs() << "\n"); 4977 WorkListRemover DeadNodes(*this); 4978 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4979 4980 if (N->use_empty()) { 4981 removeFromWorkList(N); 4982 DAG.DeleteNode(N); 4983 } 4984 4985 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4986 } 4987 } else { 4988 // Indexed loads. 4989 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4990 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4991 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4992 DEBUG(dbgs() << "\nReplacing.6 "; 4993 N->dump(&DAG); 4994 dbgs() << "\nWith: "; 4995 Undef.getNode()->dump(&DAG); 4996 dbgs() << " and 2 other values\n"); 4997 WorkListRemover DeadNodes(*this); 4998 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4999 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5000 DAG.getUNDEF(N->getValueType(1)), 5001 &DeadNodes); 5002 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5003 removeFromWorkList(N); 5004 DAG.DeleteNode(N); 5005 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5006 } 5007 } 5008 } 5009 5010 // If this load is directly stored, replace the load value with the stored 5011 // value. 5012 // TODO: Handle store large -> read small portion. 5013 // TODO: Handle TRUNCSTORE/LOADEXT 5014 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 5015 !LD->isVolatile()) { 5016 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5017 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5018 if (PrevST->getBasePtr() == Ptr && 5019 PrevST->getValue().getValueType() == N->getValueType(0)) 5020 return CombineTo(N, Chain.getOperand(1), Chain); 5021 } 5022 } 5023 5024 if (CombinerAA) { 5025 // Walk up chain skipping non-aliasing memory nodes. 5026 SDValue BetterChain = FindBetterChain(N, Chain); 5027 5028 // If there is a better chain. 5029 if (Chain != BetterChain) { 5030 SDValue ReplLoad; 5031 5032 // Replace the chain to void dependency. 5033 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5034 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5035 BetterChain, Ptr, 5036 LD->getSrcValue(), LD->getSrcValueOffset(), 5037 LD->isVolatile(), LD->getAlignment()); 5038 } else { 5039 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5040 LD->getValueType(0), 5041 BetterChain, Ptr, LD->getSrcValue(), 5042 LD->getSrcValueOffset(), 5043 LD->getMemoryVT(), 5044 LD->isVolatile(), 5045 LD->getAlignment()); 5046 } 5047 5048 // Create token factor to keep old chain connected. 5049 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5050 MVT::Other, Chain, ReplLoad.getValue(1)); 5051 5052 // Make sure the new and old chains are cleaned up. 5053 AddToWorkList(Token.getNode()); 5054 5055 // Replace uses with load result and token factor. Don't add users 5056 // to work list. 5057 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5058 } 5059 } 5060 5061 // Try transforming N to an indexed load. 5062 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5063 return SDValue(N, 0); 5064 5065 return SDValue(); 5066} 5067 5068 5069/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 5070/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 5071/// of the loaded bits, try narrowing the load and store if it would end up 5072/// being a win for performance or code size. 5073SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 5074 StoreSDNode *ST = cast<StoreSDNode>(N); 5075 if (ST->isVolatile()) 5076 return SDValue(); 5077 5078 SDValue Chain = ST->getChain(); 5079 SDValue Value = ST->getValue(); 5080 SDValue Ptr = ST->getBasePtr(); 5081 EVT VT = Value.getValueType(); 5082 5083 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5084 return SDValue(); 5085 5086 unsigned Opc = Value.getOpcode(); 5087 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 5088 Value.getOperand(1).getOpcode() != ISD::Constant) 5089 return SDValue(); 5090 5091 SDValue N0 = Value.getOperand(0); 5092 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 5093 LoadSDNode *LD = cast<LoadSDNode>(N0); 5094 if (LD->getBasePtr() != Ptr) 5095 return SDValue(); 5096 5097 // Find the type to narrow it the load / op / store to. 5098 SDValue N1 = Value.getOperand(1); 5099 unsigned BitWidth = N1.getValueSizeInBits(); 5100 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5101 if (Opc == ISD::AND) 5102 Imm ^= APInt::getAllOnesValue(BitWidth); 5103 if (Imm == 0 || Imm.isAllOnesValue()) 5104 return SDValue(); 5105 unsigned ShAmt = Imm.countTrailingZeros(); 5106 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5107 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5108 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5109 while (NewBW < BitWidth && 5110 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5111 TLI.isNarrowingProfitable(VT, NewVT))) { 5112 NewBW = NextPowerOf2(NewBW); 5113 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5114 } 5115 if (NewBW >= BitWidth) 5116 return SDValue(); 5117 5118 // If the lsb changed does not start at the type bitwidth boundary, 5119 // start at the previous one. 5120 if (ShAmt % NewBW) 5121 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5122 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5123 if ((Imm & Mask) == Imm) { 5124 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5125 if (Opc == ISD::AND) 5126 NewImm ^= APInt::getAllOnesValue(NewBW); 5127 uint64_t PtrOff = ShAmt / 8; 5128 // For big endian targets, we need to adjust the offset to the pointer to 5129 // load the correct bytes. 5130 if (TLI.isBigEndian()) 5131 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5132 5133 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5134 if (NewAlign < 5135 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT(*DAG.getContext()))) 5136 return SDValue(); 5137 5138 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5139 Ptr.getValueType(), Ptr, 5140 DAG.getConstant(PtrOff, Ptr.getValueType())); 5141 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5142 LD->getChain(), NewPtr, 5143 LD->getSrcValue(), LD->getSrcValueOffset(), 5144 LD->isVolatile(), NewAlign); 5145 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5146 DAG.getConstant(NewImm, NewVT)); 5147 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5148 NewVal, NewPtr, 5149 ST->getSrcValue(), ST->getSrcValueOffset(), 5150 false, NewAlign); 5151 5152 AddToWorkList(NewPtr.getNode()); 5153 AddToWorkList(NewLD.getNode()); 5154 AddToWorkList(NewVal.getNode()); 5155 WorkListRemover DeadNodes(*this); 5156 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5157 &DeadNodes); 5158 ++OpsNarrowed; 5159 return NewST; 5160 } 5161 } 5162 5163 return SDValue(); 5164} 5165 5166SDValue DAGCombiner::visitSTORE(SDNode *N) { 5167 StoreSDNode *ST = cast<StoreSDNode>(N); 5168 SDValue Chain = ST->getChain(); 5169 SDValue Value = ST->getValue(); 5170 SDValue Ptr = ST->getBasePtr(); 5171 5172 // Try to infer better alignment information than the store already has. 5173 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5174 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5175 if (Align > ST->getAlignment()) 5176 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5177 Ptr, ST->getSrcValue(), 5178 ST->getSrcValueOffset(), ST->getMemoryVT(), 5179 ST->isVolatile(), Align); 5180 } 5181 } 5182 5183 // If this is a store of a bit convert, store the input value if the 5184 // resultant store does not need a higher alignment than the original. 5185 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5186 ST->isUnindexed()) { 5187 unsigned OrigAlign = ST->getAlignment(); 5188 EVT SVT = Value.getOperand(0).getValueType(); 5189 unsigned Align = TLI.getTargetData()-> 5190 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5191 if (Align <= OrigAlign && 5192 ((!LegalOperations && !ST->isVolatile()) || 5193 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5194 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5195 Ptr, ST->getSrcValue(), 5196 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 5197 } 5198 5199 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5200 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5201 // NOTE: If the original store is volatile, this transform must not increase 5202 // the number of stores. For example, on x86-32 an f64 can be stored in one 5203 // processor operation but an i64 (which is not legal) requires two. So the 5204 // transform should not be done in this case. 5205 if (Value.getOpcode() != ISD::TargetConstantFP) { 5206 SDValue Tmp; 5207 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5208 default: llvm_unreachable("Unknown FP type"); 5209 case MVT::f80: // We don't do this for these yet. 5210 case MVT::f128: 5211 case MVT::ppcf128: 5212 break; 5213 case MVT::f32: 5214 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5215 !ST->isVolatile()) || 5216 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5217 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5218 bitcastToAPInt().getZExtValue(), MVT::i32); 5219 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5220 Ptr, ST->getSrcValue(), 5221 ST->getSrcValueOffset(), ST->isVolatile(), 5222 ST->getAlignment()); 5223 } 5224 break; 5225 case MVT::f64: 5226 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5227 !ST->isVolatile()) || 5228 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5229 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5230 getZExtValue(), MVT::i64); 5231 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5232 Ptr, ST->getSrcValue(), 5233 ST->getSrcValueOffset(), ST->isVolatile(), 5234 ST->getAlignment()); 5235 } else if (!ST->isVolatile() && 5236 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5237 // Many FP stores are not made apparent until after legalize, e.g. for 5238 // argument passing. Since this is so common, custom legalize the 5239 // 64-bit integer store into two 32-bit stores. 5240 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5241 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5242 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5243 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5244 5245 int SVOffset = ST->getSrcValueOffset(); 5246 unsigned Alignment = ST->getAlignment(); 5247 bool isVolatile = ST->isVolatile(); 5248 5249 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5250 Ptr, ST->getSrcValue(), 5251 ST->getSrcValueOffset(), 5252 isVolatile, ST->getAlignment()); 5253 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5254 DAG.getConstant(4, Ptr.getValueType())); 5255 SVOffset += 4; 5256 Alignment = MinAlign(Alignment, 4U); 5257 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5258 Ptr, ST->getSrcValue(), 5259 SVOffset, isVolatile, Alignment); 5260 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5261 St0, St1); 5262 } 5263 5264 break; 5265 } 5266 } 5267 } 5268 5269 if (CombinerAA) { 5270 // Walk up chain skipping non-aliasing memory nodes. 5271 SDValue BetterChain = FindBetterChain(N, Chain); 5272 5273 // If there is a better chain. 5274 if (Chain != BetterChain) { 5275 SDValue ReplStore; 5276 5277 // Replace the chain to avoid dependency. 5278 if (ST->isTruncatingStore()) { 5279 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5280 ST->getSrcValue(),ST->getSrcValueOffset(), 5281 ST->getMemoryVT(), 5282 ST->isVolatile(), ST->getAlignment()); 5283 } else { 5284 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5285 ST->getSrcValue(), ST->getSrcValueOffset(), 5286 ST->isVolatile(), ST->getAlignment()); 5287 } 5288 5289 // Create token to keep both nodes around. 5290 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5291 MVT::Other, Chain, ReplStore); 5292 5293 // Make sure the new and old chains are cleaned up. 5294 AddToWorkList(Token.getNode()); 5295 5296 // Don't add users to work list. 5297 return CombineTo(N, Token, false); 5298 } 5299 } 5300 5301 // Try transforming N to an indexed store. 5302 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5303 return SDValue(N, 0); 5304 5305 // FIXME: is there such a thing as a truncating indexed store? 5306 if (ST->isTruncatingStore() && ST->isUnindexed() && 5307 Value.getValueType().isInteger()) { 5308 // See if we can simplify the input to this truncstore with knowledge that 5309 // only the low bits are being used. For example: 5310 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5311 SDValue Shorter = 5312 GetDemandedBits(Value, 5313 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5314 ST->getMemoryVT().getSizeInBits())); 5315 AddToWorkList(Value.getNode()); 5316 if (Shorter.getNode()) 5317 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5318 Ptr, ST->getSrcValue(), 5319 ST->getSrcValueOffset(), ST->getMemoryVT(), 5320 ST->isVolatile(), ST->getAlignment()); 5321 5322 // Otherwise, see if we can simplify the operation with 5323 // SimplifyDemandedBits, which only works if the value has a single use. 5324 if (SimplifyDemandedBits(Value, 5325 APInt::getLowBitsSet( 5326 Value.getValueType().getScalarType().getSizeInBits(), 5327 ST->getMemoryVT().getSizeInBits()))) 5328 return SDValue(N, 0); 5329 } 5330 5331 // If this is a load followed by a store to the same location, then the store 5332 // is dead/noop. 5333 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5334 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5335 ST->isUnindexed() && !ST->isVolatile() && 5336 // There can't be any side effects between the load and store, such as 5337 // a call or store. 5338 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5339 // The store is dead, remove it. 5340 return Chain; 5341 } 5342 } 5343 5344 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5345 // truncating store. We can do this even if this is already a truncstore. 5346 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5347 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5348 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5349 ST->getMemoryVT())) { 5350 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5351 Ptr, ST->getSrcValue(), 5352 ST->getSrcValueOffset(), ST->getMemoryVT(), 5353 ST->isVolatile(), ST->getAlignment()); 5354 } 5355 5356 return ReduceLoadOpStoreWidth(N); 5357} 5358 5359SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5360 SDValue InVec = N->getOperand(0); 5361 SDValue InVal = N->getOperand(1); 5362 SDValue EltNo = N->getOperand(2); 5363 5364 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5365 // vector with the inserted element. 5366 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5367 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5368 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5369 InVec.getNode()->op_end()); 5370 if (Elt < Ops.size()) 5371 Ops[Elt] = InVal; 5372 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5373 InVec.getValueType(), &Ops[0], Ops.size()); 5374 } 5375 // If the invec is an UNDEF and if EltNo is a constant, create a new 5376 // BUILD_VECTOR with undef elements and the inserted element. 5377 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5378 isa<ConstantSDNode>(EltNo)) { 5379 EVT VT = InVec.getValueType(); 5380 EVT EltVT = VT.getVectorElementType(); 5381 unsigned NElts = VT.getVectorNumElements(); 5382 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 5383 5384 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5385 if (Elt < Ops.size()) 5386 Ops[Elt] = InVal; 5387 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5388 InVec.getValueType(), &Ops[0], Ops.size()); 5389 } 5390 return SDValue(); 5391} 5392 5393SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5394 // (vextract (scalar_to_vector val, 0) -> val 5395 SDValue InVec = N->getOperand(0); 5396 5397 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5398 // If the operand is wider than the vector element type then it is implicitly 5399 // truncated. Make that explicit here. 5400 EVT EltVT = InVec.getValueType().getVectorElementType(); 5401 SDValue InOp = InVec.getOperand(0); 5402 if (InOp.getValueType() != EltVT) 5403 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp); 5404 return InOp; 5405 } 5406 5407 // Perform only after legalization to ensure build_vector / vector_shuffle 5408 // optimizations have already been done. 5409 if (!LegalOperations) return SDValue(); 5410 5411 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5412 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5413 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5414 SDValue EltNo = N->getOperand(1); 5415 5416 if (isa<ConstantSDNode>(EltNo)) { 5417 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5418 bool NewLoad = false; 5419 bool BCNumEltsChanged = false; 5420 EVT VT = InVec.getValueType(); 5421 EVT ExtVT = VT.getVectorElementType(); 5422 EVT LVT = ExtVT; 5423 5424 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5425 EVT BCVT = InVec.getOperand(0).getValueType(); 5426 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 5427 return SDValue(); 5428 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5429 BCNumEltsChanged = true; 5430 InVec = InVec.getOperand(0); 5431 ExtVT = BCVT.getVectorElementType(); 5432 NewLoad = true; 5433 } 5434 5435 LoadSDNode *LN0 = NULL; 5436 const ShuffleVectorSDNode *SVN = NULL; 5437 if (ISD::isNormalLoad(InVec.getNode())) { 5438 LN0 = cast<LoadSDNode>(InVec); 5439 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5440 InVec.getOperand(0).getValueType() == ExtVT && 5441 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5442 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5443 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5444 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5445 // => 5446 // (load $addr+1*size) 5447 5448 // If the bit convert changed the number of elements, it is unsafe 5449 // to examine the mask. 5450 if (BCNumEltsChanged) 5451 return SDValue(); 5452 5453 // Select the input vector, guarding against out of range extract vector. 5454 unsigned NumElems = VT.getVectorNumElements(); 5455 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5456 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5457 5458 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5459 InVec = InVec.getOperand(0); 5460 if (ISD::isNormalLoad(InVec.getNode())) { 5461 LN0 = cast<LoadSDNode>(InVec); 5462 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems; 5463 } 5464 } 5465 5466 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5467 return SDValue(); 5468 5469 unsigned Align = LN0->getAlignment(); 5470 if (NewLoad) { 5471 // Check the resultant load doesn't need a higher alignment than the 5472 // original load. 5473 unsigned NewAlign = 5474 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 5475 5476 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5477 return SDValue(); 5478 5479 Align = NewAlign; 5480 } 5481 5482 SDValue NewPtr = LN0->getBasePtr(); 5483 if (Elt) { 5484 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5485 EVT PtrType = NewPtr.getValueType(); 5486 if (TLI.isBigEndian()) 5487 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5488 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5489 DAG.getConstant(PtrOff, PtrType)); 5490 } 5491 5492 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5493 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5494 LN0->isVolatile(), Align); 5495 } 5496 5497 return SDValue(); 5498} 5499 5500SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5501 unsigned NumInScalars = N->getNumOperands(); 5502 EVT VT = N->getValueType(0); 5503 5504 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5505 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5506 // at most two distinct vectors, turn this into a shuffle node. 5507 SDValue VecIn1, VecIn2; 5508 for (unsigned i = 0; i != NumInScalars; ++i) { 5509 // Ignore undef inputs. 5510 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5511 5512 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5513 // constant index, bail out. 5514 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5515 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5516 VecIn1 = VecIn2 = SDValue(0, 0); 5517 break; 5518 } 5519 5520 // If the input vector type disagrees with the result of the build_vector, 5521 // we can't make a shuffle. 5522 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5523 if (ExtractedFromVec.getValueType() != VT) { 5524 VecIn1 = VecIn2 = SDValue(0, 0); 5525 break; 5526 } 5527 5528 // Otherwise, remember this. We allow up to two distinct input vectors. 5529 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5530 continue; 5531 5532 if (VecIn1.getNode() == 0) { 5533 VecIn1 = ExtractedFromVec; 5534 } else if (VecIn2.getNode() == 0) { 5535 VecIn2 = ExtractedFromVec; 5536 } else { 5537 // Too many inputs. 5538 VecIn1 = VecIn2 = SDValue(0, 0); 5539 break; 5540 } 5541 } 5542 5543 // If everything is good, we can make a shuffle operation. 5544 if (VecIn1.getNode()) { 5545 SmallVector<int, 8> Mask; 5546 for (unsigned i = 0; i != NumInScalars; ++i) { 5547 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5548 Mask.push_back(-1); 5549 continue; 5550 } 5551 5552 // If extracting from the first vector, just use the index directly. 5553 SDValue Extract = N->getOperand(i); 5554 SDValue ExtVal = Extract.getOperand(1); 5555 if (Extract.getOperand(0) == VecIn1) { 5556 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5557 if (ExtIndex > VT.getVectorNumElements()) 5558 return SDValue(); 5559 5560 Mask.push_back(ExtIndex); 5561 continue; 5562 } 5563 5564 // Otherwise, use InIdx + VecSize 5565 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5566 Mask.push_back(Idx+NumInScalars); 5567 } 5568 5569 // Add count and size info. 5570 if (!TLI.isTypeLegal(VT) && LegalTypes) 5571 return SDValue(); 5572 5573 // Return the new VECTOR_SHUFFLE node. 5574 SDValue Ops[2]; 5575 Ops[0] = VecIn1; 5576 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5577 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5578 } 5579 5580 return SDValue(); 5581} 5582 5583SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5584 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5585 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5586 // inputs come from at most two distinct vectors, turn this into a shuffle 5587 // node. 5588 5589 // If we only have one input vector, we don't need to do any concatenation. 5590 if (N->getNumOperands() == 1) 5591 return N->getOperand(0); 5592 5593 return SDValue(); 5594} 5595 5596SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5597 return SDValue(); 5598 5599 EVT VT = N->getValueType(0); 5600 unsigned NumElts = VT.getVectorNumElements(); 5601 5602 SDValue N0 = N->getOperand(0); 5603 5604 assert(N0.getValueType().getVectorNumElements() == NumElts && 5605 "Vector shuffle must be normalized in DAG"); 5606 5607 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5608 5609 // If it is a splat, check if the argument vector is a build_vector with 5610 // all scalar elements the same. 5611 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5612 SDNode *V = N0.getNode(); 5613 5614 5615 // If this is a bit convert that changes the element type of the vector but 5616 // not the number of vector elements, look through it. Be careful not to 5617 // look though conversions that change things like v4f32 to v2f64. 5618 if (V->getOpcode() == ISD::BIT_CONVERT) { 5619 SDValue ConvInput = V->getOperand(0); 5620 if (ConvInput.getValueType().isVector() && 5621 ConvInput.getValueType().getVectorNumElements() == NumElts) 5622 V = ConvInput.getNode(); 5623 } 5624 5625 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5626 unsigned NumElems = V->getNumOperands(); 5627 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5628 if (NumElems > BaseIdx) { 5629 SDValue Base; 5630 bool AllSame = true; 5631 for (unsigned i = 0; i != NumElems; ++i) { 5632 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5633 Base = V->getOperand(i); 5634 break; 5635 } 5636 } 5637 // Splat of <u, u, u, u>, return <u, u, u, u> 5638 if (!Base.getNode()) 5639 return N0; 5640 for (unsigned i = 0; i != NumElems; ++i) { 5641 if (V->getOperand(i) != Base) { 5642 AllSame = false; 5643 break; 5644 } 5645 } 5646 // Splat of <x, x, x, x>, return <x, x, x, x> 5647 if (AllSame) 5648 return N0; 5649 } 5650 } 5651 } 5652 return SDValue(); 5653} 5654 5655/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5656/// an AND to a vector_shuffle with the destination vector and a zero vector. 5657/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5658/// vector_shuffle V, Zero, <0, 4, 2, 4> 5659SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5660 EVT VT = N->getValueType(0); 5661 DebugLoc dl = N->getDebugLoc(); 5662 SDValue LHS = N->getOperand(0); 5663 SDValue RHS = N->getOperand(1); 5664 if (N->getOpcode() == ISD::AND) { 5665 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5666 RHS = RHS.getOperand(0); 5667 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5668 SmallVector<int, 8> Indices; 5669 unsigned NumElts = RHS.getNumOperands(); 5670 for (unsigned i = 0; i != NumElts; ++i) { 5671 SDValue Elt = RHS.getOperand(i); 5672 if (!isa<ConstantSDNode>(Elt)) 5673 return SDValue(); 5674 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5675 Indices.push_back(i); 5676 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5677 Indices.push_back(NumElts); 5678 else 5679 return SDValue(); 5680 } 5681 5682 // Let's see if the target supports this vector_shuffle. 5683 EVT RVT = RHS.getValueType(); 5684 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5685 return SDValue(); 5686 5687 // Return the new VECTOR_SHUFFLE node. 5688 EVT EltVT = RVT.getVectorElementType(); 5689 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5690 DAG.getConstant(0, EltVT)); 5691 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5692 RVT, &ZeroOps[0], ZeroOps.size()); 5693 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5694 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5695 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5696 } 5697 } 5698 5699 return SDValue(); 5700} 5701 5702/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5703SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5704 // After legalize, the target may be depending on adds and other 5705 // binary ops to provide legal ways to construct constants or other 5706 // things. Simplifying them may result in a loss of legality. 5707 if (LegalOperations) return SDValue(); 5708 5709 EVT VT = N->getValueType(0); 5710 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5711 5712 EVT EltType = VT.getVectorElementType(); 5713 SDValue LHS = N->getOperand(0); 5714 SDValue RHS = N->getOperand(1); 5715 SDValue Shuffle = XformToShuffleWithZero(N); 5716 if (Shuffle.getNode()) return Shuffle; 5717 5718 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5719 // this operation. 5720 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5721 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5722 SmallVector<SDValue, 8> Ops; 5723 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5724 SDValue LHSOp = LHS.getOperand(i); 5725 SDValue RHSOp = RHS.getOperand(i); 5726 // If these two elements can't be folded, bail out. 5727 if ((LHSOp.getOpcode() != ISD::UNDEF && 5728 LHSOp.getOpcode() != ISD::Constant && 5729 LHSOp.getOpcode() != ISD::ConstantFP) || 5730 (RHSOp.getOpcode() != ISD::UNDEF && 5731 RHSOp.getOpcode() != ISD::Constant && 5732 RHSOp.getOpcode() != ISD::ConstantFP)) 5733 break; 5734 5735 // Can't fold divide by zero. 5736 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5737 N->getOpcode() == ISD::FDIV) { 5738 if ((RHSOp.getOpcode() == ISD::Constant && 5739 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5740 (RHSOp.getOpcode() == ISD::ConstantFP && 5741 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5742 break; 5743 } 5744 5745 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5746 EltType, LHSOp, RHSOp)); 5747 AddToWorkList(Ops.back().getNode()); 5748 assert((Ops.back().getOpcode() == ISD::UNDEF || 5749 Ops.back().getOpcode() == ISD::Constant || 5750 Ops.back().getOpcode() == ISD::ConstantFP) && 5751 "Scalar binop didn't fold!"); 5752 } 5753 5754 if (Ops.size() == LHS.getNumOperands()) { 5755 EVT VT = LHS.getValueType(); 5756 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5757 &Ops[0], Ops.size()); 5758 } 5759 } 5760 5761 return SDValue(); 5762} 5763 5764SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5765 SDValue N1, SDValue N2){ 5766 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5767 5768 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5769 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5770 5771 // If we got a simplified select_cc node back from SimplifySelectCC, then 5772 // break it down into a new SETCC node, and a new SELECT node, and then return 5773 // the SELECT node, since we were called with a SELECT node. 5774 if (SCC.getNode()) { 5775 // Check to see if we got a select_cc back (to turn into setcc/select). 5776 // Otherwise, just return whatever node we got back, like fabs. 5777 if (SCC.getOpcode() == ISD::SELECT_CC) { 5778 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5779 N0.getValueType(), 5780 SCC.getOperand(0), SCC.getOperand(1), 5781 SCC.getOperand(4)); 5782 AddToWorkList(SETCC.getNode()); 5783 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5784 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5785 } 5786 5787 return SCC; 5788 } 5789 return SDValue(); 5790} 5791 5792/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5793/// are the two values being selected between, see if we can simplify the 5794/// select. Callers of this should assume that TheSelect is deleted if this 5795/// returns true. As such, they should return the appropriate thing (e.g. the 5796/// node) back to the top-level of the DAG combiner loop to avoid it being 5797/// looked at. 5798bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5799 SDValue RHS) { 5800 5801 // If this is a select from two identical things, try to pull the operation 5802 // through the select. 5803 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5804 // If this is a load and the token chain is identical, replace the select 5805 // of two loads with a load through a select of the address to load from. 5806 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5807 // constants have been dropped into the constant pool. 5808 if (LHS.getOpcode() == ISD::LOAD && 5809 // Do not let this transformation reduce the number of volatile loads. 5810 !cast<LoadSDNode>(LHS)->isVolatile() && 5811 !cast<LoadSDNode>(RHS)->isVolatile() && 5812 // Token chains must be identical. 5813 LHS.getOperand(0) == RHS.getOperand(0)) { 5814 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5815 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5816 5817 // If this is an EXTLOAD, the VT's must match. 5818 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5819 // FIXME: this discards src value information. This is 5820 // over-conservative. It would be beneficial to be able to remember 5821 // both potential memory locations. Since we are discarding 5822 // src value info, don't do the transformation if the memory 5823 // locations are not in the default address space. 5824 unsigned LLDAddrSpace = 0, RLDAddrSpace = 0; 5825 if (const Value *LLDVal = LLD->getMemOperand()->getValue()) { 5826 if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType())) 5827 LLDAddrSpace = PT->getAddressSpace(); 5828 } 5829 if (const Value *RLDVal = RLD->getMemOperand()->getValue()) { 5830 if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType())) 5831 RLDAddrSpace = PT->getAddressSpace(); 5832 } 5833 SDValue Addr; 5834 if (LLDAddrSpace == 0 && RLDAddrSpace == 0) { 5835 if (TheSelect->getOpcode() == ISD::SELECT) { 5836 // Check that the condition doesn't reach either load. If so, folding 5837 // this will induce a cycle into the DAG. 5838 if ((!LLD->hasAnyUseOfValue(1) || 5839 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) && 5840 (!RLD->hasAnyUseOfValue(1) || 5841 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) { 5842 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5843 LLD->getBasePtr().getValueType(), 5844 TheSelect->getOperand(0), LLD->getBasePtr(), 5845 RLD->getBasePtr()); 5846 } 5847 } else { 5848 // Check that the condition doesn't reach either load. If so, folding 5849 // this will induce a cycle into the DAG. 5850 if ((!LLD->hasAnyUseOfValue(1) || 5851 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5852 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) && 5853 (!RLD->hasAnyUseOfValue(1) || 5854 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5855 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) { 5856 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5857 LLD->getBasePtr().getValueType(), 5858 TheSelect->getOperand(0), 5859 TheSelect->getOperand(1), 5860 LLD->getBasePtr(), RLD->getBasePtr(), 5861 TheSelect->getOperand(4)); 5862 } 5863 } 5864 } 5865 5866 if (Addr.getNode()) { 5867 SDValue Load; 5868 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5869 Load = DAG.getLoad(TheSelect->getValueType(0), 5870 TheSelect->getDebugLoc(), 5871 LLD->getChain(), 5872 Addr, 0, 0, 5873 LLD->isVolatile(), 5874 LLD->getAlignment()); 5875 } else { 5876 Load = DAG.getExtLoad(LLD->getExtensionType(), 5877 TheSelect->getDebugLoc(), 5878 TheSelect->getValueType(0), 5879 LLD->getChain(), Addr, 0, 0, 5880 LLD->getMemoryVT(), 5881 LLD->isVolatile(), 5882 LLD->getAlignment()); 5883 } 5884 5885 // Users of the select now use the result of the load. 5886 CombineTo(TheSelect, Load); 5887 5888 // Users of the old loads now use the new load's chain. We know the 5889 // old-load value is dead now. 5890 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5891 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5892 return true; 5893 } 5894 } 5895 } 5896 } 5897 5898 return false; 5899} 5900 5901/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5902/// where 'cond' is the comparison specified by CC. 5903SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5904 SDValue N2, SDValue N3, 5905 ISD::CondCode CC, bool NotExtCompare) { 5906 // (x ? y : y) -> y. 5907 if (N2 == N3) return N2; 5908 5909 EVT VT = N2.getValueType(); 5910 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5911 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5912 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5913 5914 // Determine if the condition we're dealing with is constant 5915 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5916 N0, N1, CC, DL, false); 5917 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5918 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5919 5920 // fold select_cc true, x, y -> x 5921 if (SCCC && !SCCC->isNullValue()) 5922 return N2; 5923 // fold select_cc false, x, y -> y 5924 if (SCCC && SCCC->isNullValue()) 5925 return N3; 5926 5927 // Check to see if we can simplify the select into an fabs node 5928 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5929 // Allow either -0.0 or 0.0 5930 if (CFP->getValueAPF().isZero()) { 5931 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5932 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5933 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5934 N2 == N3.getOperand(0)) 5935 return DAG.getNode(ISD::FABS, DL, VT, N0); 5936 5937 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5938 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5939 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5940 N2.getOperand(0) == N3) 5941 return DAG.getNode(ISD::FABS, DL, VT, N3); 5942 } 5943 } 5944 5945 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5946 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5947 // in it. This is a win when the constant is not otherwise available because 5948 // it replaces two constant pool loads with one. We only do this if the FP 5949 // type is known to be legal, because if it isn't, then we are before legalize 5950 // types an we want the other legalization to happen first (e.g. to avoid 5951 // messing with soft float) and if the ConstantFP is not legal, because if 5952 // it is legal, we may not need to store the FP constant in a constant pool. 5953 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5954 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5955 if (TLI.isTypeLegal(N2.getValueType()) && 5956 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5957 TargetLowering::Legal) && 5958 // If both constants have multiple uses, then we won't need to do an 5959 // extra load, they are likely around in registers for other users. 5960 (TV->hasOneUse() || FV->hasOneUse())) { 5961 Constant *Elts[] = { 5962 const_cast<ConstantFP*>(FV->getConstantFPValue()), 5963 const_cast<ConstantFP*>(TV->getConstantFPValue()) 5964 }; 5965 const Type *FPTy = Elts[0]->getType(); 5966 const TargetData &TD = *TLI.getTargetData(); 5967 5968 // Create a ConstantArray of the two constants. 5969 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 5970 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5971 TD.getPrefTypeAlignment(FPTy)); 5972 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5973 5974 // Get the offsets to the 0 and 1 element of the array so that we can 5975 // select between them. 5976 SDValue Zero = DAG.getIntPtrConstant(0); 5977 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 5978 SDValue One = DAG.getIntPtrConstant(EltSize); 5979 5980 SDValue Cond = DAG.getSetCC(DL, 5981 TLI.getSetCCResultType(N0.getValueType()), 5982 N0, N1, CC); 5983 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5984 Cond, One, Zero); 5985 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5986 CstOffset); 5987 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5988 PseudoSourceValue::getConstantPool(), 0, false, 5989 Alignment); 5990 5991 } 5992 } 5993 5994 // Check to see if we can perform the "gzip trick", transforming 5995 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5996 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5997 N0.getValueType().isInteger() && 5998 N2.getValueType().isInteger() && 5999 (N1C->isNullValue() || // (a < 0) ? b : 0 6000 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 6001 EVT XType = N0.getValueType(); 6002 EVT AType = N2.getValueType(); 6003 if (XType.bitsGE(AType)) { 6004 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 6005 // single-bit constant. 6006 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 6007 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 6008 ShCtV = XType.getSizeInBits()-ShCtV-1; 6009 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 6010 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 6011 XType, N0, ShCt); 6012 AddToWorkList(Shift.getNode()); 6013 6014 if (XType.bitsGT(AType)) { 6015 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6016 AddToWorkList(Shift.getNode()); 6017 } 6018 6019 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6020 } 6021 6022 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 6023 XType, N0, 6024 DAG.getConstant(XType.getSizeInBits()-1, 6025 getShiftAmountTy())); 6026 AddToWorkList(Shift.getNode()); 6027 6028 if (XType.bitsGT(AType)) { 6029 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6030 AddToWorkList(Shift.getNode()); 6031 } 6032 6033 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6034 } 6035 } 6036 6037 // fold select C, 16, 0 -> shl C, 4 6038 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 6039 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 6040 6041 // If the caller doesn't want us to simplify this into a zext of a compare, 6042 // don't do it. 6043 if (NotExtCompare && N2C->getAPIntValue() == 1) 6044 return SDValue(); 6045 6046 // Get a SetCC of the condition 6047 // FIXME: Should probably make sure that setcc is legal if we ever have a 6048 // target where it isn't. 6049 SDValue Temp, SCC; 6050 // cast from setcc result type to select result type 6051 if (LegalTypes) { 6052 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 6053 N0, N1, CC); 6054 if (N2.getValueType().bitsLT(SCC.getValueType())) 6055 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 6056 else 6057 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6058 N2.getValueType(), SCC); 6059 } else { 6060 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 6061 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6062 N2.getValueType(), SCC); 6063 } 6064 6065 AddToWorkList(SCC.getNode()); 6066 AddToWorkList(Temp.getNode()); 6067 6068 if (N2C->getAPIntValue() == 1) 6069 return Temp; 6070 6071 // shl setcc result by log2 n2c 6072 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 6073 DAG.getConstant(N2C->getAPIntValue().logBase2(), 6074 getShiftAmountTy())); 6075 } 6076 6077 // Check to see if this is the equivalent of setcc 6078 // FIXME: Turn all of these into setcc if setcc if setcc is legal 6079 // otherwise, go ahead with the folds. 6080 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 6081 EVT XType = N0.getValueType(); 6082 if (!LegalOperations || 6083 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 6084 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 6085 if (Res.getValueType() != VT) 6086 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 6087 return Res; 6088 } 6089 6090 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 6091 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 6092 (!LegalOperations || 6093 TLI.isOperationLegal(ISD::CTLZ, XType))) { 6094 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 6095 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 6096 DAG.getConstant(Log2_32(XType.getSizeInBits()), 6097 getShiftAmountTy())); 6098 } 6099 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 6100 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 6101 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 6102 XType, DAG.getConstant(0, XType), N0); 6103 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 6104 return DAG.getNode(ISD::SRL, DL, XType, 6105 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 6106 DAG.getConstant(XType.getSizeInBits()-1, 6107 getShiftAmountTy())); 6108 } 6109 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 6110 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 6111 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 6112 DAG.getConstant(XType.getSizeInBits()-1, 6113 getShiftAmountTy())); 6114 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 6115 } 6116 } 6117 6118 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 6119 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6120 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 6121 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 6122 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 6123 EVT XType = N0.getValueType(); 6124 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 6125 DAG.getConstant(XType.getSizeInBits()-1, 6126 getShiftAmountTy())); 6127 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 6128 N0, Shift); 6129 AddToWorkList(Shift.getNode()); 6130 AddToWorkList(Add.getNode()); 6131 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6132 } 6133 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 6134 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6135 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 6136 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 6137 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 6138 EVT XType = N0.getValueType(); 6139 if (SubC->isNullValue() && XType.isInteger()) { 6140 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 6141 N0, 6142 DAG.getConstant(XType.getSizeInBits()-1, 6143 getShiftAmountTy())); 6144 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6145 XType, N0, Shift); 6146 AddToWorkList(Shift.getNode()); 6147 AddToWorkList(Add.getNode()); 6148 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6149 } 6150 } 6151 } 6152 6153 return SDValue(); 6154} 6155 6156/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6157SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 6158 SDValue N1, ISD::CondCode Cond, 6159 DebugLoc DL, bool foldBooleans) { 6160 TargetLowering::DAGCombinerInfo 6161 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6162 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6163} 6164 6165/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6166/// return a DAG expression to select that will generate the same value by 6167/// multiplying by a magic number. See: 6168/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6169SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6170 std::vector<SDNode*> Built; 6171 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6172 6173 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6174 ii != ee; ++ii) 6175 AddToWorkList(*ii); 6176 return S; 6177} 6178 6179/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6180/// return a DAG expression to select that will generate the same value by 6181/// multiplying by a magic number. See: 6182/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6183SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6184 std::vector<SDNode*> Built; 6185 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6186 6187 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6188 ii != ee; ++ii) 6189 AddToWorkList(*ii); 6190 return S; 6191} 6192 6193/// FindBaseOffset - Return true if base is a frame index, which is known not 6194// to alias with anything but itself. Provides base object and offset as results. 6195static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 6196 GlobalValue *&GV, void *&CV) { 6197 // Assume it is a primitive operation. 6198 Base = Ptr; Offset = 0; GV = 0; CV = 0; 6199 6200 // If it's an adding a simple constant then integrate the offset. 6201 if (Base.getOpcode() == ISD::ADD) { 6202 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6203 Base = Base.getOperand(0); 6204 Offset += C->getZExtValue(); 6205 } 6206 } 6207 6208 // Return the underlying GlobalValue, and update the Offset. Return false 6209 // for GlobalAddressSDNode since the same GlobalAddress may be represented 6210 // by multiple nodes with different offsets. 6211 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 6212 GV = G->getGlobal(); 6213 Offset += G->getOffset(); 6214 return false; 6215 } 6216 6217 // Return the underlying Constant value, and update the Offset. Return false 6218 // for ConstantSDNodes since the same constant pool entry may be represented 6219 // by multiple nodes with different offsets. 6220 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 6221 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 6222 : (void *)C->getConstVal(); 6223 Offset += C->getOffset(); 6224 return false; 6225 } 6226 // If it's any of the following then it can't alias with anything but itself. 6227 return isa<FrameIndexSDNode>(Base); 6228} 6229 6230/// isAlias - Return true if there is any possibility that the two addresses 6231/// overlap. 6232bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6233 const Value *SrcValue1, int SrcValueOffset1, 6234 unsigned SrcValueAlign1, 6235 SDValue Ptr2, int64_t Size2, 6236 const Value *SrcValue2, int SrcValueOffset2, 6237 unsigned SrcValueAlign2) const { 6238 // If they are the same then they must be aliases. 6239 if (Ptr1 == Ptr2) return true; 6240 6241 // Gather base node and offset information. 6242 SDValue Base1, Base2; 6243 int64_t Offset1, Offset2; 6244 GlobalValue *GV1, *GV2; 6245 void *CV1, *CV2; 6246 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 6247 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 6248 6249 // If they have a same base address then check to see if they overlap. 6250 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 6251 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6252 6253 // If we know what the bases are, and they aren't identical, then we know they 6254 // cannot alias. 6255 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 6256 return false; 6257 6258 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 6259 // compared to the size and offset of the access, we may be able to prove they 6260 // do not alias. This check is conservative for now to catch cases created by 6261 // splitting vector types. 6262 if ((SrcValueAlign1 == SrcValueAlign2) && 6263 (SrcValueOffset1 != SrcValueOffset2) && 6264 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 6265 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 6266 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 6267 6268 // There is no overlap between these relatively aligned accesses of similar 6269 // size, return no alias. 6270 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 6271 return false; 6272 } 6273 6274 if (CombinerGlobalAA) { 6275 // Use alias analysis information. 6276 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6277 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6278 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6279 AliasAnalysis::AliasResult AAResult = 6280 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6281 if (AAResult == AliasAnalysis::NoAlias) 6282 return false; 6283 } 6284 6285 // Otherwise we have to assume they alias. 6286 return true; 6287} 6288 6289/// FindAliasInfo - Extracts the relevant alias information from the memory 6290/// node. Returns true if the operand was a load. 6291bool DAGCombiner::FindAliasInfo(SDNode *N, 6292 SDValue &Ptr, int64_t &Size, 6293 const Value *&SrcValue, 6294 int &SrcValueOffset, 6295 unsigned &SrcValueAlign) const { 6296 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6297 Ptr = LD->getBasePtr(); 6298 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6299 SrcValue = LD->getSrcValue(); 6300 SrcValueOffset = LD->getSrcValueOffset(); 6301 SrcValueAlign = LD->getOriginalAlignment(); 6302 return true; 6303 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6304 Ptr = ST->getBasePtr(); 6305 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6306 SrcValue = ST->getSrcValue(); 6307 SrcValueOffset = ST->getSrcValueOffset(); 6308 SrcValueAlign = ST->getOriginalAlignment(); 6309 } else { 6310 llvm_unreachable("FindAliasInfo expected a memory operand"); 6311 } 6312 6313 return false; 6314} 6315 6316/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6317/// looking for aliasing nodes and adding them to the Aliases vector. 6318void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6319 SmallVector<SDValue, 8> &Aliases) { 6320 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6321 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 6322 6323 // Get alias information for node. 6324 SDValue Ptr; 6325 int64_t Size; 6326 const Value *SrcValue; 6327 int SrcValueOffset; 6328 unsigned SrcValueAlign; 6329 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 6330 SrcValueAlign); 6331 6332 // Starting off. 6333 Chains.push_back(OriginalChain); 6334 unsigned Depth = 0; 6335 6336 // Look at each chain and determine if it is an alias. If so, add it to the 6337 // aliases list. If not, then continue up the chain looking for the next 6338 // candidate. 6339 while (!Chains.empty()) { 6340 SDValue Chain = Chains.back(); 6341 Chains.pop_back(); 6342 6343 // For TokenFactor nodes, look at each operand and only continue up the 6344 // chain until we find two aliases. If we've seen two aliases, assume we'll 6345 // find more and revert to original chain since the xform is unlikely to be 6346 // profitable. 6347 // 6348 // FIXME: The depth check could be made to return the last non-aliasing 6349 // chain we found before we hit a tokenfactor rather than the original 6350 // chain. 6351 if (Depth > 6 || Aliases.size() == 2) { 6352 Aliases.clear(); 6353 Aliases.push_back(OriginalChain); 6354 break; 6355 } 6356 6357 // Don't bother if we've been before. 6358 if (!Visited.insert(Chain.getNode())) 6359 continue; 6360 6361 switch (Chain.getOpcode()) { 6362 case ISD::EntryToken: 6363 // Entry token is ideal chain operand, but handled in FindBetterChain. 6364 break; 6365 6366 case ISD::LOAD: 6367 case ISD::STORE: { 6368 // Get alias information for Chain. 6369 SDValue OpPtr; 6370 int64_t OpSize; 6371 const Value *OpSrcValue; 6372 int OpSrcValueOffset; 6373 unsigned OpSrcValueAlign; 6374 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6375 OpSrcValue, OpSrcValueOffset, 6376 OpSrcValueAlign); 6377 6378 // If chain is alias then stop here. 6379 if (!(IsLoad && IsOpLoad) && 6380 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 6381 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 6382 OpSrcValueAlign)) { 6383 Aliases.push_back(Chain); 6384 } else { 6385 // Look further up the chain. 6386 Chains.push_back(Chain.getOperand(0)); 6387 ++Depth; 6388 } 6389 break; 6390 } 6391 6392 case ISD::TokenFactor: 6393 // We have to check each of the operands of the token factor for "small" 6394 // token factors, so we queue them up. Adding the operands to the queue 6395 // (stack) in reverse order maintains the original order and increases the 6396 // likelihood that getNode will find a matching token factor (CSE.) 6397 if (Chain.getNumOperands() > 16) { 6398 Aliases.push_back(Chain); 6399 break; 6400 } 6401 for (unsigned n = Chain.getNumOperands(); n;) 6402 Chains.push_back(Chain.getOperand(--n)); 6403 ++Depth; 6404 break; 6405 6406 default: 6407 // For all other instructions we will just have to take what we can get. 6408 Aliases.push_back(Chain); 6409 break; 6410 } 6411 } 6412} 6413 6414/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6415/// for a better chain (aliasing node.) 6416SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6417 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6418 6419 // Accumulate all the aliases to this node. 6420 GatherAllAliases(N, OldChain, Aliases); 6421 6422 if (Aliases.size() == 0) { 6423 // If no operands then chain to entry token. 6424 return DAG.getEntryNode(); 6425 } else if (Aliases.size() == 1) { 6426 // If a single operand then chain to it. We don't need to revisit it. 6427 return Aliases[0]; 6428 } 6429 6430 // Construct a custom tailored token factor. 6431 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6432 &Aliases[0], Aliases.size()); 6433} 6434 6435// SelectionDAG::Combine - This is the entry point for the file. 6436// 6437void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6438 CodeGenOpt::Level OptLevel) { 6439 /// run - This is the main entry point to this class. 6440 /// 6441 DAGCombiner(*this, AA, OptLevel).Run(Level); 6442} 6443