MachineVerifier.cpp revision 199481
1//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Pass to verify generated machine code. The following is checked: 11// 12// Operand counts: All explicit operands must be present. 13// 14// Register classes: All physical and virtual register operands must be 15// compatible with the register class required by the instruction descriptor. 16// 17// Register live intervals: Registers must be defined only once, and must be 18// defined before use. 19// 20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the 21// command-line option -verify-machineinstrs, or by defining the environment 22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive 23// the verifier errors. 24//===----------------------------------------------------------------------===// 25 26#include "llvm/Function.h" 27#include "llvm/CodeGen/LiveVariables.h" 28#include "llvm/CodeGen/MachineFunctionPass.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineMemOperand.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/Passes.h" 33#include "llvm/Target/TargetMachine.h" 34#include "llvm/Target/TargetRegisterInfo.h" 35#include "llvm/Target/TargetInstrInfo.h" 36#include "llvm/ADT/DenseSet.h" 37#include "llvm/ADT/SetOperations.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/Support/Debug.h" 40#include "llvm/Support/ErrorHandling.h" 41#include "llvm/Support/raw_ostream.h" 42using namespace llvm; 43 44namespace { 45 struct MachineVerifier : public MachineFunctionPass { 46 static char ID; // Pass ID, replacement for typeid 47 48 MachineVerifier(bool allowDoubleDefs = false) : 49 MachineFunctionPass(&ID), 50 allowVirtDoubleDefs(allowDoubleDefs), 51 allowPhysDoubleDefs(allowDoubleDefs), 52 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS")) 53 {} 54 55 void getAnalysisUsage(AnalysisUsage &AU) const { 56 AU.setPreservesAll(); 57 MachineFunctionPass::getAnalysisUsage(AU); 58 } 59 60 bool runOnMachineFunction(MachineFunction &MF); 61 62 const bool allowVirtDoubleDefs; 63 const bool allowPhysDoubleDefs; 64 65 const char *const OutFileName; 66 raw_ostream *OS; 67 const MachineFunction *MF; 68 const TargetMachine *TM; 69 const TargetRegisterInfo *TRI; 70 const MachineRegisterInfo *MRI; 71 72 unsigned foundErrors; 73 74 typedef SmallVector<unsigned, 16> RegVector; 75 typedef DenseSet<unsigned> RegSet; 76 typedef DenseMap<unsigned, const MachineInstr*> RegMap; 77 78 BitVector regsReserved; 79 RegSet regsLive; 80 RegVector regsDefined, regsDead, regsKilled; 81 RegSet regsLiveInButUnused; 82 83 // Add Reg and any sub-registers to RV 84 void addRegWithSubRegs(RegVector &RV, unsigned Reg) { 85 RV.push_back(Reg); 86 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 87 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++) 88 RV.push_back(*R); 89 } 90 91 struct BBInfo { 92 // Is this MBB reachable from the MF entry point? 93 bool reachable; 94 95 // Vregs that must be live in because they are used without being 96 // defined. Map value is the user. 97 RegMap vregsLiveIn; 98 99 // Vregs that must be dead in because they are defined without being 100 // killed first. Map value is the defining instruction. 101 RegMap vregsDeadIn; 102 103 // Regs killed in MBB. They may be defined again, and will then be in both 104 // regsKilled and regsLiveOut. 105 RegSet regsKilled; 106 107 // Regs defined in MBB and live out. Note that vregs passing through may 108 // be live out without being mentioned here. 109 RegSet regsLiveOut; 110 111 // Vregs that pass through MBB untouched. This set is disjoint from 112 // regsKilled and regsLiveOut. 113 RegSet vregsPassed; 114 115 BBInfo() : reachable(false) {} 116 117 // Add register to vregsPassed if it belongs there. Return true if 118 // anything changed. 119 bool addPassed(unsigned Reg) { 120 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 121 return false; 122 if (regsKilled.count(Reg) || regsLiveOut.count(Reg)) 123 return false; 124 return vregsPassed.insert(Reg).second; 125 } 126 127 // Same for a full set. 128 bool addPassed(const RegSet &RS) { 129 bool changed = false; 130 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) 131 if (addPassed(*I)) 132 changed = true; 133 return changed; 134 } 135 136 // Live-out registers are either in regsLiveOut or vregsPassed. 137 bool isLiveOut(unsigned Reg) const { 138 return regsLiveOut.count(Reg) || vregsPassed.count(Reg); 139 } 140 }; 141 142 // Extra register info per MBB. 143 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap; 144 145 bool isReserved(unsigned Reg) { 146 return Reg < regsReserved.size() && regsReserved.test(Reg); 147 } 148 149 void visitMachineFunctionBefore(); 150 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB); 151 void visitMachineInstrBefore(const MachineInstr *MI); 152 void visitMachineOperand(const MachineOperand *MO, unsigned MONum); 153 void visitMachineInstrAfter(const MachineInstr *MI); 154 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB); 155 void visitMachineFunctionAfter(); 156 157 void report(const char *msg, const MachineFunction *MF); 158 void report(const char *msg, const MachineBasicBlock *MBB); 159 void report(const char *msg, const MachineInstr *MI); 160 void report(const char *msg, const MachineOperand *MO, unsigned MONum); 161 162 void markReachable(const MachineBasicBlock *MBB); 163 void calcMaxRegsPassed(); 164 void calcMinRegsPassed(); 165 void checkPHIOps(const MachineBasicBlock *MBB); 166 }; 167} 168 169char MachineVerifier::ID = 0; 170static RegisterPass<MachineVerifier> 171MachineVer("machineverifier", "Verify generated machine code"); 172static const PassInfo *const MachineVerifyID = &MachineVer; 173 174FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) { 175 return new MachineVerifier(allowPhysDoubleDefs); 176} 177 178void MachineFunction::verify() const { 179 MachineVerifier().runOnMachineFunction(const_cast<MachineFunction&>(*this)); 180} 181 182bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) { 183 raw_ostream *OutFile = 0; 184 if (OutFileName) { 185 std::string ErrorInfo; 186 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo, 187 raw_fd_ostream::F_Append); 188 if (!ErrorInfo.empty()) { 189 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n'; 190 exit(1); 191 } 192 193 OS = OutFile; 194 } else { 195 OS = &errs(); 196 } 197 198 foundErrors = 0; 199 200 this->MF = &MF; 201 TM = &MF.getTarget(); 202 TRI = TM->getRegisterInfo(); 203 MRI = &MF.getRegInfo(); 204 205 visitMachineFunctionBefore(); 206 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end(); 207 MFI!=MFE; ++MFI) { 208 visitMachineBasicBlockBefore(MFI); 209 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(), 210 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) { 211 visitMachineInstrBefore(MBBI); 212 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) 213 visitMachineOperand(&MBBI->getOperand(I), I); 214 visitMachineInstrAfter(MBBI); 215 } 216 visitMachineBasicBlockAfter(MFI); 217 } 218 visitMachineFunctionAfter(); 219 220 if (OutFile) 221 delete OutFile; 222 else if (foundErrors) 223 llvm_report_error("Found "+Twine(foundErrors)+" machine code errors."); 224 225 // Clean up. 226 regsLive.clear(); 227 regsDefined.clear(); 228 regsDead.clear(); 229 regsKilled.clear(); 230 regsLiveInButUnused.clear(); 231 MBBInfoMap.clear(); 232 233 return false; // no changes 234} 235 236void MachineVerifier::report(const char *msg, const MachineFunction *MF) { 237 assert(MF); 238 *OS << '\n'; 239 if (!foundErrors++) 240 MF->print(*OS); 241 *OS << "*** Bad machine code: " << msg << " ***\n" 242 << "- function: " << MF->getFunction()->getNameStr() << "\n"; 243} 244 245void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) { 246 assert(MBB); 247 report(msg, MBB->getParent()); 248 *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr() 249 << " " << (void*)MBB 250 << " (BB#" << MBB->getNumber() << ")\n"; 251} 252 253void MachineVerifier::report(const char *msg, const MachineInstr *MI) { 254 assert(MI); 255 report(msg, MI->getParent()); 256 *OS << "- instruction: "; 257 MI->print(*OS, TM); 258} 259 260void MachineVerifier::report(const char *msg, 261 const MachineOperand *MO, unsigned MONum) { 262 assert(MO); 263 report(msg, MO->getParent()); 264 *OS << "- operand " << MONum << ": "; 265 MO->print(*OS, TM); 266 *OS << "\n"; 267} 268 269void MachineVerifier::markReachable(const MachineBasicBlock *MBB) { 270 BBInfo &MInfo = MBBInfoMap[MBB]; 271 if (!MInfo.reachable) { 272 MInfo.reachable = true; 273 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), 274 SuE = MBB->succ_end(); SuI != SuE; ++SuI) 275 markReachable(*SuI); 276 } 277} 278 279void MachineVerifier::visitMachineFunctionBefore() { 280 regsReserved = TRI->getReservedRegs(*MF); 281 282 // A sub-register of a reserved register is also reserved 283 for (int Reg = regsReserved.find_first(); Reg>=0; 284 Reg = regsReserved.find_next(Reg)) { 285 for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) { 286 // FIXME: This should probably be: 287 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register"); 288 regsReserved.set(*Sub); 289 } 290 } 291 markReachable(&MF->front()); 292} 293 294// Does iterator point to a and b as the first two elements? 295bool matchPair(MachineBasicBlock::const_succ_iterator i, 296 const MachineBasicBlock *a, const MachineBasicBlock *b) { 297 if (*i == a) 298 return *++i == b; 299 if (*i == b) 300 return *++i == a; 301 return false; 302} 303 304void 305MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { 306 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 307 308 // Start with minimal CFG sanity checks. 309 MachineFunction::const_iterator MBBI = MBB; 310 ++MBBI; 311 if (MBBI != MF->end()) { 312 // Block is not last in function. 313 if (!MBB->isSuccessor(MBBI)) { 314 // Block does not fall through. 315 if (MBB->empty()) { 316 report("MBB doesn't fall through but is empty!", MBB); 317 } 318 } 319 if (TII->BlockHasNoFallThrough(*MBB)) { 320 if (MBB->empty()) { 321 report("TargetInstrInfo says the block has no fall through, but the " 322 "block is empty!", MBB); 323 } else if (!MBB->back().getDesc().isBarrier()) { 324 report("TargetInstrInfo says the block has no fall through, but the " 325 "block does not end in a barrier!", MBB); 326 } 327 } 328 } else { 329 // Block is last in function. 330 if (MBB->empty()) { 331 report("MBB is last in function but is empty!", MBB); 332 } 333 } 334 335 // Call AnalyzeBranch. If it succeeds, there several more conditions to check. 336 MachineBasicBlock *TBB = 0, *FBB = 0; 337 SmallVector<MachineOperand, 4> Cond; 338 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB), 339 TBB, FBB, Cond)) { 340 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's 341 // check whether its answers match up with reality. 342 if (!TBB && !FBB) { 343 // Block falls through to its successor. 344 MachineFunction::const_iterator MBBI = MBB; 345 ++MBBI; 346 if (MBBI == MF->end()) { 347 // It's possible that the block legitimately ends with a noreturn 348 // call or an unreachable, in which case it won't actually fall 349 // out the bottom of the function. 350 } else if (MBB->succ_empty()) { 351 // It's possible that the block legitimately ends with a noreturn 352 // call or an unreachable, in which case it won't actuall fall 353 // out of the block. 354 } else if (MBB->succ_size() != 1) { 355 report("MBB exits via unconditional fall-through but doesn't have " 356 "exactly one CFG successor!", MBB); 357 } else if (MBB->succ_begin()[0] != MBBI) { 358 report("MBB exits via unconditional fall-through but its successor " 359 "differs from its CFG successor!", MBB); 360 } 361 if (!MBB->empty() && MBB->back().getDesc().isBarrier()) { 362 report("MBB exits via unconditional fall-through but ends with a " 363 "barrier instruction!", MBB); 364 } 365 if (!Cond.empty()) { 366 report("MBB exits via unconditional fall-through but has a condition!", 367 MBB); 368 } 369 } else if (TBB && !FBB && Cond.empty()) { 370 // Block unconditionally branches somewhere. 371 if (MBB->succ_size() != 1) { 372 report("MBB exits via unconditional branch but doesn't have " 373 "exactly one CFG successor!", MBB); 374 } else if (MBB->succ_begin()[0] != TBB) { 375 report("MBB exits via unconditional branch but the CFG " 376 "successor doesn't match the actual successor!", MBB); 377 } 378 if (MBB->empty()) { 379 report("MBB exits via unconditional branch but doesn't contain " 380 "any instructions!", MBB); 381 } else if (!MBB->back().getDesc().isBarrier()) { 382 report("MBB exits via unconditional branch but doesn't end with a " 383 "barrier instruction!", MBB); 384 } else if (!MBB->back().getDesc().isTerminator()) { 385 report("MBB exits via unconditional branch but the branch isn't a " 386 "terminator instruction!", MBB); 387 } 388 } else if (TBB && !FBB && !Cond.empty()) { 389 // Block conditionally branches somewhere, otherwise falls through. 390 MachineFunction::const_iterator MBBI = MBB; 391 ++MBBI; 392 if (MBBI == MF->end()) { 393 report("MBB conditionally falls through out of function!", MBB); 394 } if (MBB->succ_size() != 2) { 395 report("MBB exits via conditional branch/fall-through but doesn't have " 396 "exactly two CFG successors!", MBB); 397 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) { 398 report("MBB exits via conditional branch/fall-through but the CFG " 399 "successors don't match the actual successors!", MBB); 400 } 401 if (MBB->empty()) { 402 report("MBB exits via conditional branch/fall-through but doesn't " 403 "contain any instructions!", MBB); 404 } else if (MBB->back().getDesc().isBarrier()) { 405 report("MBB exits via conditional branch/fall-through but ends with a " 406 "barrier instruction!", MBB); 407 } else if (!MBB->back().getDesc().isTerminator()) { 408 report("MBB exits via conditional branch/fall-through but the branch " 409 "isn't a terminator instruction!", MBB); 410 } 411 } else if (TBB && FBB) { 412 // Block conditionally branches somewhere, otherwise branches 413 // somewhere else. 414 if (MBB->succ_size() != 2) { 415 report("MBB exits via conditional branch/branch but doesn't have " 416 "exactly two CFG successors!", MBB); 417 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) { 418 report("MBB exits via conditional branch/branch but the CFG " 419 "successors don't match the actual successors!", MBB); 420 } 421 if (MBB->empty()) { 422 report("MBB exits via conditional branch/branch but doesn't " 423 "contain any instructions!", MBB); 424 } else if (!MBB->back().getDesc().isBarrier()) { 425 report("MBB exits via conditional branch/branch but doesn't end with a " 426 "barrier instruction!", MBB); 427 } else if (!MBB->back().getDesc().isTerminator()) { 428 report("MBB exits via conditional branch/branch but the branch " 429 "isn't a terminator instruction!", MBB); 430 } 431 if (Cond.empty()) { 432 report("MBB exits via conditinal branch/branch but there's no " 433 "condition!", MBB); 434 } 435 } else { 436 report("AnalyzeBranch returned invalid data!", MBB); 437 } 438 } 439 440 regsLive.clear(); 441 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(), 442 E = MBB->livein_end(); I != E; ++I) { 443 if (!TargetRegisterInfo::isPhysicalRegister(*I)) { 444 report("MBB live-in list contains non-physical register", MBB); 445 continue; 446 } 447 regsLive.insert(*I); 448 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++) 449 regsLive.insert(*R); 450 } 451 regsLiveInButUnused = regsLive; 452 453 const MachineFrameInfo *MFI = MF->getFrameInfo(); 454 assert(MFI && "Function has no frame info"); 455 BitVector PR = MFI->getPristineRegs(MBB); 456 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) { 457 regsLive.insert(I); 458 for (const unsigned *R = TRI->getSubRegisters(I); *R; R++) 459 regsLive.insert(*R); 460 } 461 462 regsKilled.clear(); 463 regsDefined.clear(); 464} 465 466void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { 467 const TargetInstrDesc &TI = MI->getDesc(); 468 if (MI->getNumOperands() < TI.getNumOperands()) { 469 report("Too few operands", MI); 470 *OS << TI.getNumOperands() << " operands expected, but " 471 << MI->getNumExplicitOperands() << " given.\n"; 472 } 473 474 // Check the MachineMemOperands for basic consistency. 475 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), 476 E = MI->memoperands_end(); I != E; ++I) { 477 if ((*I)->isLoad() && !TI.mayLoad()) 478 report("Missing mayLoad flag", MI); 479 if ((*I)->isStore() && !TI.mayStore()) 480 report("Missing mayStore flag", MI); 481 } 482} 483 484void 485MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { 486 const MachineInstr *MI = MO->getParent(); 487 const TargetInstrDesc &TI = MI->getDesc(); 488 489 // The first TI.NumDefs operands must be explicit register defines 490 if (MONum < TI.getNumDefs()) { 491 if (!MO->isReg()) 492 report("Explicit definition must be a register", MO, MONum); 493 else if (!MO->isDef()) 494 report("Explicit definition marked as use", MO, MONum); 495 else if (MO->isImplicit()) 496 report("Explicit definition marked as implicit", MO, MONum); 497 } else if (MONum < TI.getNumOperands()) { 498 if (MO->isReg()) { 499 if (MO->isDef()) 500 report("Explicit operand marked as def", MO, MONum); 501 if (MO->isImplicit()) 502 report("Explicit operand marked as implicit", MO, MONum); 503 } 504 } else { 505 if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic()) 506 report("Extra explicit operand on non-variadic instruction", MO, MONum); 507 } 508 509 switch (MO->getType()) { 510 case MachineOperand::MO_Register: { 511 const unsigned Reg = MO->getReg(); 512 if (!Reg) 513 return; 514 515 // Check Live Variables. 516 if (MO->isUndef()) { 517 // An <undef> doesn't refer to any register, so just skip it. 518 } else if (MO->isUse()) { 519 regsLiveInButUnused.erase(Reg); 520 521 if (MO->isKill()) { 522 addRegWithSubRegs(regsKilled, Reg); 523 // Tied operands on two-address instuctions MUST NOT have a <kill> flag. 524 if (MI->isRegTiedToDefOperand(MONum)) 525 report("Illegal kill flag on two-address instruction operand", 526 MO, MONum); 527 } else { 528 // TwoAddress instr modifying a reg is treated as kill+def. 529 unsigned defIdx; 530 if (MI->isRegTiedToDefOperand(MONum, &defIdx) && 531 MI->getOperand(defIdx).getReg() == Reg) 532 addRegWithSubRegs(regsKilled, Reg); 533 } 534 // Use of a dead register. 535 if (!regsLive.count(Reg)) { 536 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 537 // Reserved registers may be used even when 'dead'. 538 if (!isReserved(Reg)) 539 report("Using an undefined physical register", MO, MONum); 540 } else { 541 BBInfo &MInfo = MBBInfoMap[MI->getParent()]; 542 // We don't know which virtual registers are live in, so only complain 543 // if vreg was killed in this MBB. Otherwise keep track of vregs that 544 // must be live in. PHI instructions are handled separately. 545 if (MInfo.regsKilled.count(Reg)) 546 report("Using a killed virtual register", MO, MONum); 547 else if (MI->getOpcode() != TargetInstrInfo::PHI) 548 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI)); 549 } 550 } 551 } else { 552 assert(MO->isDef()); 553 // Register defined. 554 // TODO: verify that earlyclobber ops are not used. 555 if (MO->isDead()) 556 addRegWithSubRegs(regsDead, Reg); 557 else 558 addRegWithSubRegs(regsDefined, Reg); 559 } 560 561 // Check register classes. 562 if (MONum < TI.getNumOperands() && !MO->isImplicit()) { 563 const TargetOperandInfo &TOI = TI.OpInfo[MONum]; 564 unsigned SubIdx = MO->getSubReg(); 565 566 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 567 unsigned sr = Reg; 568 if (SubIdx) { 569 unsigned s = TRI->getSubReg(Reg, SubIdx); 570 if (!s) { 571 report("Invalid subregister index for physical register", 572 MO, MONum); 573 return; 574 } 575 sr = s; 576 } 577 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) { 578 if (!DRC->contains(sr)) { 579 report("Illegal physical register for instruction", MO, MONum); 580 *OS << TRI->getName(sr) << " is not a " 581 << DRC->getName() << " register.\n"; 582 } 583 } 584 } else { 585 // Virtual register. 586 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 587 if (SubIdx) { 588 if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) { 589 report("Invalid subregister index for virtual register", MO, MONum); 590 return; 591 } 592 RC = *(RC->subregclasses_begin()+SubIdx); 593 } 594 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) { 595 if (RC != DRC && !RC->hasSuperClass(DRC)) { 596 report("Illegal virtual register for instruction", MO, MONum); 597 *OS << "Expected a " << DRC->getName() << " register, but got a " 598 << RC->getName() << " register\n"; 599 } 600 } 601 } 602 } 603 break; 604 } 605 606 case MachineOperand::MO_MachineBasicBlock: 607 if (MI->getOpcode() == TargetInstrInfo::PHI) { 608 if (!MO->getMBB()->isSuccessor(MI->getParent())) 609 report("PHI operand is not in the CFG", MO, MONum); 610 } 611 break; 612 613 default: 614 break; 615 } 616} 617 618void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) { 619 BBInfo &MInfo = MBBInfoMap[MI->getParent()]; 620 set_union(MInfo.regsKilled, regsKilled); 621 set_subtract(regsLive, regsKilled); 622 regsKilled.clear(); 623 624 // Verify that both <def> and <def,dead> operands refer to dead registers. 625 RegVector defs(regsDefined); 626 defs.append(regsDead.begin(), regsDead.end()); 627 628 for (RegVector::const_iterator I = defs.begin(), E = defs.end(); 629 I != E; ++I) { 630 if (regsLive.count(*I)) { 631 if (TargetRegisterInfo::isPhysicalRegister(*I)) { 632 if (!allowPhysDoubleDefs && !isReserved(*I) && 633 !regsLiveInButUnused.count(*I)) { 634 report("Redefining a live physical register", MI); 635 *OS << "Register " << TRI->getName(*I) 636 << " was defined but already live.\n"; 637 } 638 } else { 639 if (!allowVirtDoubleDefs) { 640 report("Redefining a live virtual register", MI); 641 *OS << "Virtual register %reg" << *I 642 << " was defined but already live.\n"; 643 } 644 } 645 } else if (TargetRegisterInfo::isVirtualRegister(*I) && 646 !MInfo.regsKilled.count(*I)) { 647 // Virtual register defined without being killed first must be dead on 648 // entry. 649 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI)); 650 } 651 } 652 653 set_subtract(regsLive, regsDead); regsDead.clear(); 654 set_union(regsLive, regsDefined); regsDefined.clear(); 655} 656 657void 658MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) { 659 MBBInfoMap[MBB].regsLiveOut = regsLive; 660 regsLive.clear(); 661} 662 663// Calculate the largest possible vregsPassed sets. These are the registers that 664// can pass through an MBB live, but may not be live every time. It is assumed 665// that all vregsPassed sets are empty before the call. 666void MachineVerifier::calcMaxRegsPassed() { 667 // First push live-out regs to successors' vregsPassed. Remember the MBBs that 668 // have any vregsPassed. 669 DenseSet<const MachineBasicBlock*> todo; 670 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 671 MFI != MFE; ++MFI) { 672 const MachineBasicBlock &MBB(*MFI); 673 BBInfo &MInfo = MBBInfoMap[&MBB]; 674 if (!MInfo.reachable) 675 continue; 676 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(), 677 SuE = MBB.succ_end(); SuI != SuE; ++SuI) { 678 BBInfo &SInfo = MBBInfoMap[*SuI]; 679 if (SInfo.addPassed(MInfo.regsLiveOut)) 680 todo.insert(*SuI); 681 } 682 } 683 684 // Iteratively push vregsPassed to successors. This will converge to the same 685 // final state regardless of DenseSet iteration order. 686 while (!todo.empty()) { 687 const MachineBasicBlock *MBB = *todo.begin(); 688 todo.erase(MBB); 689 BBInfo &MInfo = MBBInfoMap[MBB]; 690 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), 691 SuE = MBB->succ_end(); SuI != SuE; ++SuI) { 692 if (*SuI == MBB) 693 continue; 694 BBInfo &SInfo = MBBInfoMap[*SuI]; 695 if (SInfo.addPassed(MInfo.vregsPassed)) 696 todo.insert(*SuI); 697 } 698 } 699} 700 701// Calculate the minimum vregsPassed set. These are the registers that always 702// pass live through an MBB. The calculation assumes that calcMaxRegsPassed has 703// been called earlier. 704void MachineVerifier::calcMinRegsPassed() { 705 DenseSet<const MachineBasicBlock*> todo; 706 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 707 MFI != MFE; ++MFI) 708 todo.insert(MFI); 709 710 while (!todo.empty()) { 711 const MachineBasicBlock *MBB = *todo.begin(); 712 todo.erase(MBB); 713 BBInfo &MInfo = MBBInfoMap[MBB]; 714 715 // Remove entries from vRegsPassed that are not live out from all 716 // reachable predecessors. 717 RegSet dead; 718 for (RegSet::iterator I = MInfo.vregsPassed.begin(), 719 E = MInfo.vregsPassed.end(); I != E; ++I) { 720 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), 721 PrE = MBB->pred_end(); PrI != PrE; ++PrI) { 722 BBInfo &PrInfo = MBBInfoMap[*PrI]; 723 if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) { 724 dead.insert(*I); 725 break; 726 } 727 } 728 } 729 // If any regs removed, we need to recheck successors. 730 if (!dead.empty()) { 731 set_subtract(MInfo.vregsPassed, dead); 732 todo.insert(MBB->succ_begin(), MBB->succ_end()); 733 } 734 } 735} 736 737// Check PHI instructions at the beginning of MBB. It is assumed that 738// calcMinRegsPassed has been run so BBInfo::isLiveOut is valid. 739void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) { 740 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end(); 741 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) { 742 DenseSet<const MachineBasicBlock*> seen; 743 744 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) { 745 unsigned Reg = BBI->getOperand(i).getReg(); 746 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB(); 747 if (!Pre->isSuccessor(MBB)) 748 continue; 749 seen.insert(Pre); 750 BBInfo &PrInfo = MBBInfoMap[Pre]; 751 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg)) 752 report("PHI operand is not live-out from predecessor", 753 &BBI->getOperand(i), i); 754 } 755 756 // Did we see all predecessors? 757 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), 758 PrE = MBB->pred_end(); PrI != PrE; ++PrI) { 759 if (!seen.count(*PrI)) { 760 report("Missing PHI operand", BBI); 761 *OS << "BB#" << (*PrI)->getNumber() 762 << " is a predecessor according to the CFG.\n"; 763 } 764 } 765 } 766} 767 768void MachineVerifier::visitMachineFunctionAfter() { 769 calcMaxRegsPassed(); 770 771 // With the maximal set of vregsPassed we can verify dead-in registers. 772 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 773 MFI != MFE; ++MFI) { 774 BBInfo &MInfo = MBBInfoMap[MFI]; 775 776 // Skip unreachable MBBs. 777 if (!MInfo.reachable) 778 continue; 779 780 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(), 781 PrE = MFI->pred_end(); PrI != PrE; ++PrI) { 782 BBInfo &PrInfo = MBBInfoMap[*PrI]; 783 if (!PrInfo.reachable) 784 continue; 785 786 // Verify physical live-ins. EH landing pads have magic live-ins so we 787 // ignore them. 788 if (!MFI->isLandingPad()) { 789 for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(), 790 E = MFI->livein_end(); I != E; ++I) { 791 if (TargetRegisterInfo::isPhysicalRegister(*I) && 792 !isReserved (*I) && !PrInfo.isLiveOut(*I)) { 793 report("Live-in physical register is not live-out from predecessor", 794 MFI); 795 *OS << "Register " << TRI->getName(*I) 796 << " is not live-out from BB#" << (*PrI)->getNumber() 797 << ".\n"; 798 } 799 } 800 } 801 802 803 // Verify dead-in virtual registers. 804 if (!allowVirtDoubleDefs) { 805 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(), 806 E = MInfo.vregsDeadIn.end(); I != E; ++I) { 807 // DeadIn register must be in neither regsLiveOut or vregsPassed of 808 // any predecessor. 809 if (PrInfo.isLiveOut(I->first)) { 810 report("Live-in virtual register redefined", I->second); 811 *OS << "Register %reg" << I->first 812 << " was live-out from predecessor MBB #" 813 << (*PrI)->getNumber() << ".\n"; 814 } 815 } 816 } 817 } 818 } 819 820 calcMinRegsPassed(); 821 822 // With the minimal set of vregsPassed we can verify live-in virtual 823 // registers, including PHI instructions. 824 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 825 MFI != MFE; ++MFI) { 826 BBInfo &MInfo = MBBInfoMap[MFI]; 827 828 // Skip unreachable MBBs. 829 if (!MInfo.reachable) 830 continue; 831 832 checkPHIOps(MFI); 833 834 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(), 835 PrE = MFI->pred_end(); PrI != PrE; ++PrI) { 836 BBInfo &PrInfo = MBBInfoMap[*PrI]; 837 if (!PrInfo.reachable) 838 continue; 839 840 for (RegMap::iterator I = MInfo.vregsLiveIn.begin(), 841 E = MInfo.vregsLiveIn.end(); I != E; ++I) { 842 if (!PrInfo.isLiveOut(I->first)) { 843 report("Used virtual register is not live-in", I->second); 844 *OS << "Register %reg" << I->first 845 << " is not live-out from predecessor MBB #" 846 << (*PrI)->getNumber() 847 << ".\n"; 848 } 849 } 850 } 851 } 852} 853