MachineVerifier.cpp revision 198892
1//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Pass to verify generated machine code. The following is checked: 11// 12// Operand counts: All explicit operands must be present. 13// 14// Register classes: All physical and virtual register operands must be 15// compatible with the register class required by the instruction descriptor. 16// 17// Register live intervals: Registers must be defined only once, and must be 18// defined before use. 19// 20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the 21// command-line option -verify-machineinstrs, or by defining the environment 22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive 23// the verifier errors. 24//===----------------------------------------------------------------------===// 25 26#include "llvm/Function.h" 27#include "llvm/CodeGen/LiveVariables.h" 28#include "llvm/CodeGen/MachineFunctionPass.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineMemOperand.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/Passes.h" 33#include "llvm/Target/TargetMachine.h" 34#include "llvm/Target/TargetRegisterInfo.h" 35#include "llvm/Target/TargetInstrInfo.h" 36#include "llvm/ADT/DenseSet.h" 37#include "llvm/ADT/SetOperations.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/Support/Debug.h" 40#include "llvm/Support/ErrorHandling.h" 41#include "llvm/Support/raw_ostream.h" 42using namespace llvm; 43 44namespace { 45 struct MachineVerifier : public MachineFunctionPass { 46 static char ID; // Pass ID, replacement for typeid 47 48 MachineVerifier(bool allowDoubleDefs = false) : 49 MachineFunctionPass(&ID), 50 allowVirtDoubleDefs(allowDoubleDefs), 51 allowPhysDoubleDefs(allowDoubleDefs), 52 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS")) 53 {} 54 55 void getAnalysisUsage(AnalysisUsage &AU) const { 56 AU.setPreservesAll(); 57 MachineFunctionPass::getAnalysisUsage(AU); 58 } 59 60 bool runOnMachineFunction(MachineFunction &MF); 61 62 const bool allowVirtDoubleDefs; 63 const bool allowPhysDoubleDefs; 64 65 const char *const OutFileName; 66 raw_ostream *OS; 67 const MachineFunction *MF; 68 const TargetMachine *TM; 69 const TargetRegisterInfo *TRI; 70 const MachineRegisterInfo *MRI; 71 72 unsigned foundErrors; 73 74 typedef SmallVector<unsigned, 16> RegVector; 75 typedef DenseSet<unsigned> RegSet; 76 typedef DenseMap<unsigned, const MachineInstr*> RegMap; 77 78 BitVector regsReserved; 79 RegSet regsLive; 80 RegVector regsDefined, regsDead, regsKilled; 81 RegSet regsLiveInButUnused; 82 83 // Add Reg and any sub-registers to RV 84 void addRegWithSubRegs(RegVector &RV, unsigned Reg) { 85 RV.push_back(Reg); 86 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 87 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++) 88 RV.push_back(*R); 89 } 90 91 struct BBInfo { 92 // Is this MBB reachable from the MF entry point? 93 bool reachable; 94 95 // Vregs that must be live in because they are used without being 96 // defined. Map value is the user. 97 RegMap vregsLiveIn; 98 99 // Vregs that must be dead in because they are defined without being 100 // killed first. Map value is the defining instruction. 101 RegMap vregsDeadIn; 102 103 // Regs killed in MBB. They may be defined again, and will then be in both 104 // regsKilled and regsLiveOut. 105 RegSet regsKilled; 106 107 // Regs defined in MBB and live out. Note that vregs passing through may 108 // be live out without being mentioned here. 109 RegSet regsLiveOut; 110 111 // Vregs that pass through MBB untouched. This set is disjoint from 112 // regsKilled and regsLiveOut. 113 RegSet vregsPassed; 114 115 BBInfo() : reachable(false) {} 116 117 // Add register to vregsPassed if it belongs there. Return true if 118 // anything changed. 119 bool addPassed(unsigned Reg) { 120 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 121 return false; 122 if (regsKilled.count(Reg) || regsLiveOut.count(Reg)) 123 return false; 124 return vregsPassed.insert(Reg).second; 125 } 126 127 // Same for a full set. 128 bool addPassed(const RegSet &RS) { 129 bool changed = false; 130 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) 131 if (addPassed(*I)) 132 changed = true; 133 return changed; 134 } 135 136 // Live-out registers are either in regsLiveOut or vregsPassed. 137 bool isLiveOut(unsigned Reg) const { 138 return regsLiveOut.count(Reg) || vregsPassed.count(Reg); 139 } 140 }; 141 142 // Extra register info per MBB. 143 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap; 144 145 bool isReserved(unsigned Reg) { 146 return Reg < regsReserved.size() && regsReserved.test(Reg); 147 } 148 149 void visitMachineFunctionBefore(); 150 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB); 151 void visitMachineInstrBefore(const MachineInstr *MI); 152 void visitMachineOperand(const MachineOperand *MO, unsigned MONum); 153 void visitMachineInstrAfter(const MachineInstr *MI); 154 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB); 155 void visitMachineFunctionAfter(); 156 157 void report(const char *msg, const MachineFunction *MF); 158 void report(const char *msg, const MachineBasicBlock *MBB); 159 void report(const char *msg, const MachineInstr *MI); 160 void report(const char *msg, const MachineOperand *MO, unsigned MONum); 161 162 void markReachable(const MachineBasicBlock *MBB); 163 void calcMaxRegsPassed(); 164 void calcMinRegsPassed(); 165 void checkPHIOps(const MachineBasicBlock *MBB); 166 }; 167} 168 169char MachineVerifier::ID = 0; 170static RegisterPass<MachineVerifier> 171MachineVer("machineverifier", "Verify generated machine code"); 172static const PassInfo *const MachineVerifyID = &MachineVer; 173 174FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) { 175 return new MachineVerifier(allowPhysDoubleDefs); 176} 177 178bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) { 179 raw_ostream *OutFile = 0; 180 if (OutFileName) { 181 std::string ErrorInfo; 182 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo, 183 raw_fd_ostream::F_Append); 184 if (!ErrorInfo.empty()) { 185 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n'; 186 exit(1); 187 } 188 189 OS = OutFile; 190 } else { 191 OS = &errs(); 192 } 193 194 foundErrors = 0; 195 196 this->MF = &MF; 197 TM = &MF.getTarget(); 198 TRI = TM->getRegisterInfo(); 199 MRI = &MF.getRegInfo(); 200 201 visitMachineFunctionBefore(); 202 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end(); 203 MFI!=MFE; ++MFI) { 204 visitMachineBasicBlockBefore(MFI); 205 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(), 206 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) { 207 visitMachineInstrBefore(MBBI); 208 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) 209 visitMachineOperand(&MBBI->getOperand(I), I); 210 visitMachineInstrAfter(MBBI); 211 } 212 visitMachineBasicBlockAfter(MFI); 213 } 214 visitMachineFunctionAfter(); 215 216 if (OutFile) 217 delete OutFile; 218 else if (foundErrors) 219 llvm_report_error("Found "+Twine(foundErrors)+" machine code errors."); 220 221 // Clean up. 222 regsLive.clear(); 223 regsDefined.clear(); 224 regsDead.clear(); 225 regsKilled.clear(); 226 regsLiveInButUnused.clear(); 227 MBBInfoMap.clear(); 228 229 return false; // no changes 230} 231 232void MachineVerifier::report(const char *msg, const MachineFunction *MF) { 233 assert(MF); 234 *OS << '\n'; 235 if (!foundErrors++) 236 MF->print(*OS); 237 *OS << "*** Bad machine code: " << msg << " ***\n" 238 << "- function: " << MF->getFunction()->getNameStr() << "\n"; 239} 240 241void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) { 242 assert(MBB); 243 report(msg, MBB->getParent()); 244 *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr() 245 << " " << (void*)MBB 246 << " (BB#" << MBB->getNumber() << ")\n"; 247} 248 249void MachineVerifier::report(const char *msg, const MachineInstr *MI) { 250 assert(MI); 251 report(msg, MI->getParent()); 252 *OS << "- instruction: "; 253 MI->print(*OS, TM); 254} 255 256void MachineVerifier::report(const char *msg, 257 const MachineOperand *MO, unsigned MONum) { 258 assert(MO); 259 report(msg, MO->getParent()); 260 *OS << "- operand " << MONum << ": "; 261 MO->print(*OS, TM); 262 *OS << "\n"; 263} 264 265void MachineVerifier::markReachable(const MachineBasicBlock *MBB) { 266 BBInfo &MInfo = MBBInfoMap[MBB]; 267 if (!MInfo.reachable) { 268 MInfo.reachable = true; 269 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), 270 SuE = MBB->succ_end(); SuI != SuE; ++SuI) 271 markReachable(*SuI); 272 } 273} 274 275void MachineVerifier::visitMachineFunctionBefore() { 276 regsReserved = TRI->getReservedRegs(*MF); 277 278 // A sub-register of a reserved register is also reserved 279 for (int Reg = regsReserved.find_first(); Reg>=0; 280 Reg = regsReserved.find_next(Reg)) { 281 for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) { 282 // FIXME: This should probably be: 283 // assert(regsReserved.test(*Sub) && "Non-reserved sub-register"); 284 regsReserved.set(*Sub); 285 } 286 } 287 markReachable(&MF->front()); 288} 289 290void MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { 291 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 292 293 // Start with minimal CFG sanity checks. 294 MachineFunction::const_iterator MBBI = MBB; 295 ++MBBI; 296 if (MBBI != MF->end()) { 297 // Block is not last in function. 298 if (!MBB->isSuccessor(MBBI)) { 299 // Block does not fall through. 300 if (MBB->empty()) { 301 report("MBB doesn't fall through but is empty!", MBB); 302 } 303 } 304 if (TII->BlockHasNoFallThrough(*MBB)) { 305 if (MBB->empty()) { 306 report("TargetInstrInfo says the block has no fall through, but the " 307 "block is empty!", MBB); 308 } else if (!MBB->back().getDesc().isBarrier()) { 309 report("TargetInstrInfo says the block has no fall through, but the " 310 "block does not end in a barrier!", MBB); 311 } 312 } 313 } else { 314 // Block is last in function. 315 if (MBB->empty()) { 316 report("MBB is last in function but is empty!", MBB); 317 } 318 } 319 320 // Call AnalyzeBranch. If it succeeds, there several more conditions to check. 321 MachineBasicBlock *TBB = 0, *FBB = 0; 322 SmallVector<MachineOperand, 4> Cond; 323 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB), 324 TBB, FBB, Cond)) { 325 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's 326 // check whether its answers match up with reality. 327 if (!TBB && !FBB) { 328 // Block falls through to its successor. 329 MachineFunction::const_iterator MBBI = MBB; 330 ++MBBI; 331 if (MBBI == MF->end()) { 332 // It's possible that the block legitimately ends with a noreturn 333 // call or an unreachable, in which case it won't actually fall 334 // out the bottom of the function. 335 } else if (MBB->succ_empty()) { 336 // It's possible that the block legitimately ends with a noreturn 337 // call or an unreachable, in which case it won't actuall fall 338 // out of the block. 339 } else if (MBB->succ_size() != 1) { 340 report("MBB exits via unconditional fall-through but doesn't have " 341 "exactly one CFG successor!", MBB); 342 } else if (MBB->succ_begin()[0] != MBBI) { 343 report("MBB exits via unconditional fall-through but its successor " 344 "differs from its CFG successor!", MBB); 345 } 346 if (!MBB->empty() && MBB->back().getDesc().isBarrier()) { 347 report("MBB exits via unconditional fall-through but ends with a " 348 "barrier instruction!", MBB); 349 } 350 if (!Cond.empty()) { 351 report("MBB exits via unconditional fall-through but has a condition!", 352 MBB); 353 } 354 } else if (TBB && !FBB && Cond.empty()) { 355 // Block unconditionally branches somewhere. 356 if (MBB->succ_size() != 1) { 357 report("MBB exits via unconditional branch but doesn't have " 358 "exactly one CFG successor!", MBB); 359 } else if (MBB->succ_begin()[0] != TBB) { 360 report("MBB exits via unconditional branch but the CFG " 361 "successor doesn't match the actual successor!", MBB); 362 } 363 if (MBB->empty()) { 364 report("MBB exits via unconditional branch but doesn't contain " 365 "any instructions!", MBB); 366 } else if (!MBB->back().getDesc().isBarrier()) { 367 report("MBB exits via unconditional branch but doesn't end with a " 368 "barrier instruction!", MBB); 369 } else if (!MBB->back().getDesc().isTerminator()) { 370 report("MBB exits via unconditional branch but the branch isn't a " 371 "terminator instruction!", MBB); 372 } 373 } else if (TBB && !FBB && !Cond.empty()) { 374 // Block conditionally branches somewhere, otherwise falls through. 375 MachineFunction::const_iterator MBBI = MBB; 376 ++MBBI; 377 if (MBBI == MF->end()) { 378 report("MBB conditionally falls through out of function!", MBB); 379 } if (MBB->succ_size() != 2) { 380 report("MBB exits via conditional branch/fall-through but doesn't have " 381 "exactly two CFG successors!", MBB); 382 } else if ((MBB->succ_begin()[0] == TBB && MBB->succ_end()[1] == MBBI) || 383 (MBB->succ_begin()[1] == TBB && MBB->succ_end()[0] == MBBI)) { 384 report("MBB exits via conditional branch/fall-through but the CFG " 385 "successors don't match the actual successors!", MBB); 386 } 387 if (MBB->empty()) { 388 report("MBB exits via conditional branch/fall-through but doesn't " 389 "contain any instructions!", MBB); 390 } else if (MBB->back().getDesc().isBarrier()) { 391 report("MBB exits via conditional branch/fall-through but ends with a " 392 "barrier instruction!", MBB); 393 } else if (!MBB->back().getDesc().isTerminator()) { 394 report("MBB exits via conditional branch/fall-through but the branch " 395 "isn't a terminator instruction!", MBB); 396 } 397 } else if (TBB && FBB) { 398 // Block conditionally branches somewhere, otherwise branches 399 // somewhere else. 400 if (MBB->succ_size() != 2) { 401 report("MBB exits via conditional branch/branch but doesn't have " 402 "exactly two CFG successors!", MBB); 403 } else if ((MBB->succ_begin()[0] == TBB && MBB->succ_end()[1] == FBB) || 404 (MBB->succ_begin()[1] == TBB && MBB->succ_end()[0] == FBB)) { 405 report("MBB exits via conditional branch/branch but the CFG " 406 "successors don't match the actual successors!", MBB); 407 } 408 if (MBB->empty()) { 409 report("MBB exits via conditional branch/branch but doesn't " 410 "contain any instructions!", MBB); 411 } else if (!MBB->back().getDesc().isBarrier()) { 412 report("MBB exits via conditional branch/branch but doesn't end with a " 413 "barrier instruction!", MBB); 414 } else if (!MBB->back().getDesc().isTerminator()) { 415 report("MBB exits via conditional branch/branch but the branch " 416 "isn't a terminator instruction!", MBB); 417 } 418 if (Cond.empty()) { 419 report("MBB exits via conditinal branch/branch but there's no " 420 "condition!", MBB); 421 } 422 } else { 423 report("AnalyzeBranch returned invalid data!", MBB); 424 } 425 } 426 427 regsLive.clear(); 428 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(), 429 E = MBB->livein_end(); I != E; ++I) { 430 if (!TargetRegisterInfo::isPhysicalRegister(*I)) { 431 report("MBB live-in list contains non-physical register", MBB); 432 continue; 433 } 434 regsLive.insert(*I); 435 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++) 436 regsLive.insert(*R); 437 } 438 regsLiveInButUnused = regsLive; 439 440 const MachineFrameInfo *MFI = MF->getFrameInfo(); 441 assert(MFI && "Function has no frame info"); 442 BitVector PR = MFI->getPristineRegs(MBB); 443 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) { 444 regsLive.insert(I); 445 for (const unsigned *R = TRI->getSubRegisters(I); *R; R++) 446 regsLive.insert(*R); 447 } 448 449 regsKilled.clear(); 450 regsDefined.clear(); 451} 452 453void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { 454 const TargetInstrDesc &TI = MI->getDesc(); 455 if (MI->getNumOperands() < TI.getNumOperands()) { 456 report("Too few operands", MI); 457 *OS << TI.getNumOperands() << " operands expected, but " 458 << MI->getNumExplicitOperands() << " given.\n"; 459 } 460 461 // Check the MachineMemOperands for basic consistency. 462 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), 463 E = MI->memoperands_end(); I != E; ++I) { 464 if ((*I)->isLoad() && !TI.mayLoad()) 465 report("Missing mayLoad flag", MI); 466 if ((*I)->isStore() && !TI.mayStore()) 467 report("Missing mayStore flag", MI); 468 } 469} 470 471void 472MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { 473 const MachineInstr *MI = MO->getParent(); 474 const TargetInstrDesc &TI = MI->getDesc(); 475 476 // The first TI.NumDefs operands must be explicit register defines 477 if (MONum < TI.getNumDefs()) { 478 if (!MO->isReg()) 479 report("Explicit definition must be a register", MO, MONum); 480 else if (!MO->isDef()) 481 report("Explicit definition marked as use", MO, MONum); 482 else if (MO->isImplicit()) 483 report("Explicit definition marked as implicit", MO, MONum); 484 } else if (MONum < TI.getNumOperands()) { 485 if (MO->isReg()) { 486 if (MO->isDef()) 487 report("Explicit operand marked as def", MO, MONum); 488 if (MO->isImplicit()) 489 report("Explicit operand marked as implicit", MO, MONum); 490 } 491 } else { 492 if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic()) 493 report("Extra explicit operand on non-variadic instruction", MO, MONum); 494 } 495 496 switch (MO->getType()) { 497 case MachineOperand::MO_Register: { 498 const unsigned Reg = MO->getReg(); 499 if (!Reg) 500 return; 501 502 // Check Live Variables. 503 if (MO->isUndef()) { 504 // An <undef> doesn't refer to any register, so just skip it. 505 } else if (MO->isUse()) { 506 regsLiveInButUnused.erase(Reg); 507 508 if (MO->isKill()) { 509 addRegWithSubRegs(regsKilled, Reg); 510 // Tied operands on two-address instuctions MUST NOT have a <kill> flag. 511 if (MI->isRegTiedToDefOperand(MONum)) 512 report("Illegal kill flag on two-address instruction operand", 513 MO, MONum); 514 } else { 515 // TwoAddress instr modifying a reg is treated as kill+def. 516 unsigned defIdx; 517 if (MI->isRegTiedToDefOperand(MONum, &defIdx) && 518 MI->getOperand(defIdx).getReg() == Reg) 519 addRegWithSubRegs(regsKilled, Reg); 520 } 521 // Use of a dead register. 522 if (!regsLive.count(Reg)) { 523 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 524 // Reserved registers may be used even when 'dead'. 525 if (!isReserved(Reg)) 526 report("Using an undefined physical register", MO, MONum); 527 } else { 528 BBInfo &MInfo = MBBInfoMap[MI->getParent()]; 529 // We don't know which virtual registers are live in, so only complain 530 // if vreg was killed in this MBB. Otherwise keep track of vregs that 531 // must be live in. PHI instructions are handled separately. 532 if (MInfo.regsKilled.count(Reg)) 533 report("Using a killed virtual register", MO, MONum); 534 else if (MI->getOpcode() != TargetInstrInfo::PHI) 535 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI)); 536 } 537 } 538 } else { 539 assert(MO->isDef()); 540 // Register defined. 541 // TODO: verify that earlyclobber ops are not used. 542 if (MO->isDead()) 543 addRegWithSubRegs(regsDead, Reg); 544 else 545 addRegWithSubRegs(regsDefined, Reg); 546 } 547 548 // Check register classes. 549 if (MONum < TI.getNumOperands() && !MO->isImplicit()) { 550 const TargetOperandInfo &TOI = TI.OpInfo[MONum]; 551 unsigned SubIdx = MO->getSubReg(); 552 553 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 554 unsigned sr = Reg; 555 if (SubIdx) { 556 unsigned s = TRI->getSubReg(Reg, SubIdx); 557 if (!s) { 558 report("Invalid subregister index for physical register", 559 MO, MONum); 560 return; 561 } 562 sr = s; 563 } 564 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) { 565 if (!DRC->contains(sr)) { 566 report("Illegal physical register for instruction", MO, MONum); 567 *OS << TRI->getName(sr) << " is not a " 568 << DRC->getName() << " register.\n"; 569 } 570 } 571 } else { 572 // Virtual register. 573 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 574 if (SubIdx) { 575 if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) { 576 report("Invalid subregister index for virtual register", MO, MONum); 577 return; 578 } 579 RC = *(RC->subregclasses_begin()+SubIdx); 580 } 581 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) { 582 if (RC != DRC && !RC->hasSuperClass(DRC)) { 583 report("Illegal virtual register for instruction", MO, MONum); 584 *OS << "Expected a " << DRC->getName() << " register, but got a " 585 << RC->getName() << " register\n"; 586 } 587 } 588 } 589 } 590 break; 591 } 592 593 case MachineOperand::MO_MachineBasicBlock: 594 if (MI->getOpcode() == TargetInstrInfo::PHI) { 595 if (!MO->getMBB()->isSuccessor(MI->getParent())) 596 report("PHI operand is not in the CFG", MO, MONum); 597 } 598 break; 599 600 default: 601 break; 602 } 603} 604 605void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) { 606 BBInfo &MInfo = MBBInfoMap[MI->getParent()]; 607 set_union(MInfo.regsKilled, regsKilled); 608 set_subtract(regsLive, regsKilled); 609 regsKilled.clear(); 610 611 // Verify that both <def> and <def,dead> operands refer to dead registers. 612 RegVector defs(regsDefined); 613 defs.append(regsDead.begin(), regsDead.end()); 614 615 for (RegVector::const_iterator I = defs.begin(), E = defs.end(); 616 I != E; ++I) { 617 if (regsLive.count(*I)) { 618 if (TargetRegisterInfo::isPhysicalRegister(*I)) { 619 if (!allowPhysDoubleDefs && !isReserved(*I) && 620 !regsLiveInButUnused.count(*I)) { 621 report("Redefining a live physical register", MI); 622 *OS << "Register " << TRI->getName(*I) 623 << " was defined but already live.\n"; 624 } 625 } else { 626 if (!allowVirtDoubleDefs) { 627 report("Redefining a live virtual register", MI); 628 *OS << "Virtual register %reg" << *I 629 << " was defined but already live.\n"; 630 } 631 } 632 } else if (TargetRegisterInfo::isVirtualRegister(*I) && 633 !MInfo.regsKilled.count(*I)) { 634 // Virtual register defined without being killed first must be dead on 635 // entry. 636 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI)); 637 } 638 } 639 640 set_subtract(regsLive, regsDead); regsDead.clear(); 641 set_union(regsLive, regsDefined); regsDefined.clear(); 642} 643 644void 645MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) { 646 MBBInfoMap[MBB].regsLiveOut = regsLive; 647 regsLive.clear(); 648} 649 650// Calculate the largest possible vregsPassed sets. These are the registers that 651// can pass through an MBB live, but may not be live every time. It is assumed 652// that all vregsPassed sets are empty before the call. 653void MachineVerifier::calcMaxRegsPassed() { 654 // First push live-out regs to successors' vregsPassed. Remember the MBBs that 655 // have any vregsPassed. 656 DenseSet<const MachineBasicBlock*> todo; 657 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 658 MFI != MFE; ++MFI) { 659 const MachineBasicBlock &MBB(*MFI); 660 BBInfo &MInfo = MBBInfoMap[&MBB]; 661 if (!MInfo.reachable) 662 continue; 663 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(), 664 SuE = MBB.succ_end(); SuI != SuE; ++SuI) { 665 BBInfo &SInfo = MBBInfoMap[*SuI]; 666 if (SInfo.addPassed(MInfo.regsLiveOut)) 667 todo.insert(*SuI); 668 } 669 } 670 671 // Iteratively push vregsPassed to successors. This will converge to the same 672 // final state regardless of DenseSet iteration order. 673 while (!todo.empty()) { 674 const MachineBasicBlock *MBB = *todo.begin(); 675 todo.erase(MBB); 676 BBInfo &MInfo = MBBInfoMap[MBB]; 677 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), 678 SuE = MBB->succ_end(); SuI != SuE; ++SuI) { 679 if (*SuI == MBB) 680 continue; 681 BBInfo &SInfo = MBBInfoMap[*SuI]; 682 if (SInfo.addPassed(MInfo.vregsPassed)) 683 todo.insert(*SuI); 684 } 685 } 686} 687 688// Calculate the minimum vregsPassed set. These are the registers that always 689// pass live through an MBB. The calculation assumes that calcMaxRegsPassed has 690// been called earlier. 691void MachineVerifier::calcMinRegsPassed() { 692 DenseSet<const MachineBasicBlock*> todo; 693 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 694 MFI != MFE; ++MFI) 695 todo.insert(MFI); 696 697 while (!todo.empty()) { 698 const MachineBasicBlock *MBB = *todo.begin(); 699 todo.erase(MBB); 700 BBInfo &MInfo = MBBInfoMap[MBB]; 701 702 // Remove entries from vRegsPassed that are not live out from all 703 // reachable predecessors. 704 RegSet dead; 705 for (RegSet::iterator I = MInfo.vregsPassed.begin(), 706 E = MInfo.vregsPassed.end(); I != E; ++I) { 707 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), 708 PrE = MBB->pred_end(); PrI != PrE; ++PrI) { 709 BBInfo &PrInfo = MBBInfoMap[*PrI]; 710 if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) { 711 dead.insert(*I); 712 break; 713 } 714 } 715 } 716 // If any regs removed, we need to recheck successors. 717 if (!dead.empty()) { 718 set_subtract(MInfo.vregsPassed, dead); 719 todo.insert(MBB->succ_begin(), MBB->succ_end()); 720 } 721 } 722} 723 724// Check PHI instructions at the beginning of MBB. It is assumed that 725// calcMinRegsPassed has been run so BBInfo::isLiveOut is valid. 726void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) { 727 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end(); 728 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) { 729 DenseSet<const MachineBasicBlock*> seen; 730 731 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) { 732 unsigned Reg = BBI->getOperand(i).getReg(); 733 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB(); 734 if (!Pre->isSuccessor(MBB)) 735 continue; 736 seen.insert(Pre); 737 BBInfo &PrInfo = MBBInfoMap[Pre]; 738 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg)) 739 report("PHI operand is not live-out from predecessor", 740 &BBI->getOperand(i), i); 741 } 742 743 // Did we see all predecessors? 744 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), 745 PrE = MBB->pred_end(); PrI != PrE; ++PrI) { 746 if (!seen.count(*PrI)) { 747 report("Missing PHI operand", BBI); 748 *OS << "BB#" << (*PrI)->getNumber() 749 << " is a predecessor according to the CFG.\n"; 750 } 751 } 752 } 753} 754 755void MachineVerifier::visitMachineFunctionAfter() { 756 calcMaxRegsPassed(); 757 758 // With the maximal set of vregsPassed we can verify dead-in registers. 759 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 760 MFI != MFE; ++MFI) { 761 BBInfo &MInfo = MBBInfoMap[MFI]; 762 763 // Skip unreachable MBBs. 764 if (!MInfo.reachable) 765 continue; 766 767 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(), 768 PrE = MFI->pred_end(); PrI != PrE; ++PrI) { 769 BBInfo &PrInfo = MBBInfoMap[*PrI]; 770 if (!PrInfo.reachable) 771 continue; 772 773 // Verify physical live-ins. EH landing pads have magic live-ins so we 774 // ignore them. 775 if (!MFI->isLandingPad()) { 776 for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(), 777 E = MFI->livein_end(); I != E; ++I) { 778 if (TargetRegisterInfo::isPhysicalRegister(*I) && 779 !isReserved (*I) && !PrInfo.isLiveOut(*I)) { 780 report("Live-in physical register is not live-out from predecessor", 781 MFI); 782 *OS << "Register " << TRI->getName(*I) 783 << " is not live-out from BB#" << (*PrI)->getNumber() 784 << ".\n"; 785 } 786 } 787 } 788 789 790 // Verify dead-in virtual registers. 791 if (!allowVirtDoubleDefs) { 792 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(), 793 E = MInfo.vregsDeadIn.end(); I != E; ++I) { 794 // DeadIn register must be in neither regsLiveOut or vregsPassed of 795 // any predecessor. 796 if (PrInfo.isLiveOut(I->first)) { 797 report("Live-in virtual register redefined", I->second); 798 *OS << "Register %reg" << I->first 799 << " was live-out from predecessor MBB #" 800 << (*PrI)->getNumber() << ".\n"; 801 } 802 } 803 } 804 } 805 } 806 807 calcMinRegsPassed(); 808 809 // With the minimal set of vregsPassed we can verify live-in virtual 810 // registers, including PHI instructions. 811 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 812 MFI != MFE; ++MFI) { 813 BBInfo &MInfo = MBBInfoMap[MFI]; 814 815 // Skip unreachable MBBs. 816 if (!MInfo.reachable) 817 continue; 818 819 checkPHIOps(MFI); 820 821 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(), 822 PrE = MFI->pred_end(); PrI != PrE; ++PrI) { 823 BBInfo &PrInfo = MBBInfoMap[*PrI]; 824 if (!PrInfo.reachable) 825 continue; 826 827 for (RegMap::iterator I = MInfo.vregsLiveIn.begin(), 828 E = MInfo.vregsLiveIn.end(); I != E; ++I) { 829 if (!PrInfo.isLiveOut(I->first)) { 830 report("Used virtual register is not live-in", I->second); 831 *OS << "Register %reg" << I->first 832 << " is not live-out from predecessor MBB #" 833 << (*PrI)->getNumber() 834 << ".\n"; 835 } 836 } 837 } 838 } 839} 840