MachineVerifier.cpp revision 207618
1193323Sed//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// Pass to verify generated machine code. The following is checked: 11193323Sed// 12193323Sed// Operand counts: All explicit operands must be present. 13193323Sed// 14193323Sed// Register classes: All physical and virtual register operands must be 15193323Sed// compatible with the register class required by the instruction descriptor. 16193323Sed// 17193323Sed// Register live intervals: Registers must be defined only once, and must be 18193323Sed// defined before use. 19193323Sed// 20193323Sed// The machine code verifier is enabled from LLVMTargetMachine.cpp with the 21193323Sed// command-line option -verify-machineinstrs, or by defining the environment 22193323Sed// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive 23193323Sed// the verifier errors. 24193323Sed//===----------------------------------------------------------------------===// 25193323Sed 26193323Sed#include "llvm/Function.h" 27193323Sed#include "llvm/CodeGen/LiveVariables.h" 28193323Sed#include "llvm/CodeGen/MachineFunctionPass.h" 29198090Srdivacky#include "llvm/CodeGen/MachineFrameInfo.h" 30198090Srdivacky#include "llvm/CodeGen/MachineMemOperand.h" 31193323Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 32193323Sed#include "llvm/CodeGen/Passes.h" 33193323Sed#include "llvm/Target/TargetMachine.h" 34193323Sed#include "llvm/Target/TargetRegisterInfo.h" 35193323Sed#include "llvm/Target/TargetInstrInfo.h" 36198090Srdivacky#include "llvm/ADT/DenseSet.h" 37198090Srdivacky#include "llvm/ADT/SetOperations.h" 38198090Srdivacky#include "llvm/ADT/SmallVector.h" 39193323Sed#include "llvm/Support/Debug.h" 40198090Srdivacky#include "llvm/Support/ErrorHandling.h" 41198090Srdivacky#include "llvm/Support/raw_ostream.h" 42193323Sedusing namespace llvm; 43193323Sed 44193323Sednamespace { 45199511Srdivacky struct MachineVerifier { 46193323Sed 47199511Srdivacky MachineVerifier(Pass *pass, bool allowDoubleDefs) : 48199511Srdivacky PASS(pass), 49193323Sed allowVirtDoubleDefs(allowDoubleDefs), 50193323Sed allowPhysDoubleDefs(allowDoubleDefs), 51193323Sed OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS")) 52199511Srdivacky {} 53193323Sed 54193323Sed bool runOnMachineFunction(MachineFunction &MF); 55193323Sed 56199511Srdivacky Pass *const PASS; 57193323Sed const bool allowVirtDoubleDefs; 58193323Sed const bool allowPhysDoubleDefs; 59193323Sed 60193323Sed const char *const OutFileName; 61198090Srdivacky raw_ostream *OS; 62193323Sed const MachineFunction *MF; 63193323Sed const TargetMachine *TM; 64193323Sed const TargetRegisterInfo *TRI; 65193323Sed const MachineRegisterInfo *MRI; 66193323Sed 67193323Sed unsigned foundErrors; 68193323Sed 69193323Sed typedef SmallVector<unsigned, 16> RegVector; 70193323Sed typedef DenseSet<unsigned> RegSet; 71193323Sed typedef DenseMap<unsigned, const MachineInstr*> RegMap; 72193323Sed 73193323Sed BitVector regsReserved; 74193323Sed RegSet regsLive; 75198090Srdivacky RegVector regsDefined, regsDead, regsKilled; 76198090Srdivacky RegSet regsLiveInButUnused; 77193323Sed 78193323Sed // Add Reg and any sub-registers to RV 79193323Sed void addRegWithSubRegs(RegVector &RV, unsigned Reg) { 80193323Sed RV.push_back(Reg); 81193323Sed if (TargetRegisterInfo::isPhysicalRegister(Reg)) 82193323Sed for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++) 83193323Sed RV.push_back(*R); 84193323Sed } 85193323Sed 86193323Sed struct BBInfo { 87193323Sed // Is this MBB reachable from the MF entry point? 88193323Sed bool reachable; 89193323Sed 90193323Sed // Vregs that must be live in because they are used without being 91193323Sed // defined. Map value is the user. 92193323Sed RegMap vregsLiveIn; 93193323Sed 94193323Sed // Vregs that must be dead in because they are defined without being 95193323Sed // killed first. Map value is the defining instruction. 96193323Sed RegMap vregsDeadIn; 97193323Sed 98193323Sed // Regs killed in MBB. They may be defined again, and will then be in both 99193323Sed // regsKilled and regsLiveOut. 100193323Sed RegSet regsKilled; 101193323Sed 102193323Sed // Regs defined in MBB and live out. Note that vregs passing through may 103193323Sed // be live out without being mentioned here. 104193323Sed RegSet regsLiveOut; 105193323Sed 106193323Sed // Vregs that pass through MBB untouched. This set is disjoint from 107193323Sed // regsKilled and regsLiveOut. 108193323Sed RegSet vregsPassed; 109193323Sed 110199511Srdivacky // Vregs that must pass through MBB because they are needed by a successor 111199511Srdivacky // block. This set is disjoint from regsLiveOut. 112199511Srdivacky RegSet vregsRequired; 113199511Srdivacky 114193323Sed BBInfo() : reachable(false) {} 115193323Sed 116193323Sed // Add register to vregsPassed if it belongs there. Return true if 117193323Sed // anything changed. 118193323Sed bool addPassed(unsigned Reg) { 119193323Sed if (!TargetRegisterInfo::isVirtualRegister(Reg)) 120193323Sed return false; 121193323Sed if (regsKilled.count(Reg) || regsLiveOut.count(Reg)) 122193323Sed return false; 123193323Sed return vregsPassed.insert(Reg).second; 124193323Sed } 125193323Sed 126193323Sed // Same for a full set. 127193323Sed bool addPassed(const RegSet &RS) { 128193323Sed bool changed = false; 129193323Sed for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) 130193323Sed if (addPassed(*I)) 131193323Sed changed = true; 132193323Sed return changed; 133193323Sed } 134193323Sed 135199511Srdivacky // Add register to vregsRequired if it belongs there. Return true if 136199511Srdivacky // anything changed. 137199511Srdivacky bool addRequired(unsigned Reg) { 138199511Srdivacky if (!TargetRegisterInfo::isVirtualRegister(Reg)) 139199511Srdivacky return false; 140199511Srdivacky if (regsLiveOut.count(Reg)) 141199511Srdivacky return false; 142199511Srdivacky return vregsRequired.insert(Reg).second; 143199511Srdivacky } 144199511Srdivacky 145199511Srdivacky // Same for a full set. 146199511Srdivacky bool addRequired(const RegSet &RS) { 147199511Srdivacky bool changed = false; 148199511Srdivacky for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) 149199511Srdivacky if (addRequired(*I)) 150199511Srdivacky changed = true; 151199511Srdivacky return changed; 152199511Srdivacky } 153199511Srdivacky 154199511Srdivacky // Same for a full map. 155199511Srdivacky bool addRequired(const RegMap &RM) { 156199511Srdivacky bool changed = false; 157199511Srdivacky for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I) 158199511Srdivacky if (addRequired(I->first)) 159199511Srdivacky changed = true; 160199511Srdivacky return changed; 161199511Srdivacky } 162199511Srdivacky 163193323Sed // Live-out registers are either in regsLiveOut or vregsPassed. 164193323Sed bool isLiveOut(unsigned Reg) const { 165193323Sed return regsLiveOut.count(Reg) || vregsPassed.count(Reg); 166193323Sed } 167193323Sed }; 168193323Sed 169193323Sed // Extra register info per MBB. 170193323Sed DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap; 171193323Sed 172193323Sed bool isReserved(unsigned Reg) { 173198090Srdivacky return Reg < regsReserved.size() && regsReserved.test(Reg); 174193323Sed } 175193323Sed 176199511Srdivacky // Analysis information if available 177199511Srdivacky LiveVariables *LiveVars; 178199511Srdivacky 179193323Sed void visitMachineFunctionBefore(); 180193323Sed void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB); 181193323Sed void visitMachineInstrBefore(const MachineInstr *MI); 182193323Sed void visitMachineOperand(const MachineOperand *MO, unsigned MONum); 183193323Sed void visitMachineInstrAfter(const MachineInstr *MI); 184193323Sed void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB); 185193323Sed void visitMachineFunctionAfter(); 186193323Sed 187193323Sed void report(const char *msg, const MachineFunction *MF); 188193323Sed void report(const char *msg, const MachineBasicBlock *MBB); 189193323Sed void report(const char *msg, const MachineInstr *MI); 190193323Sed void report(const char *msg, const MachineOperand *MO, unsigned MONum); 191193323Sed 192193323Sed void markReachable(const MachineBasicBlock *MBB); 193202375Srdivacky void calcRegsPassed(); 194193323Sed void checkPHIOps(const MachineBasicBlock *MBB); 195199511Srdivacky 196199511Srdivacky void calcRegsRequired(); 197199511Srdivacky void verifyLiveVariables(); 198193323Sed }; 199199511Srdivacky 200199511Srdivacky struct MachineVerifierPass : public MachineFunctionPass { 201199511Srdivacky static char ID; // Pass ID, replacement for typeid 202199511Srdivacky bool AllowDoubleDefs; 203199511Srdivacky 204199511Srdivacky explicit MachineVerifierPass(bool allowDoubleDefs = false) 205199511Srdivacky : MachineFunctionPass(&ID), 206199511Srdivacky AllowDoubleDefs(allowDoubleDefs) {} 207199511Srdivacky 208199511Srdivacky void getAnalysisUsage(AnalysisUsage &AU) const { 209199511Srdivacky AU.setPreservesAll(); 210199511Srdivacky MachineFunctionPass::getAnalysisUsage(AU); 211199511Srdivacky } 212199511Srdivacky 213199511Srdivacky bool runOnMachineFunction(MachineFunction &MF) { 214199511Srdivacky MF.verify(this, AllowDoubleDefs); 215199511Srdivacky return false; 216199511Srdivacky } 217199511Srdivacky }; 218199511Srdivacky 219193323Sed} 220193323Sed 221199511Srdivackychar MachineVerifierPass::ID = 0; 222199511Srdivackystatic RegisterPass<MachineVerifierPass> 223193323SedMachineVer("machineverifier", "Verify generated machine code"); 224193323Sedstatic const PassInfo *const MachineVerifyID = &MachineVer; 225193323Sed 226198090SrdivackyFunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) { 227199511Srdivacky return new MachineVerifierPass(allowPhysDoubleDefs); 228193323Sed} 229193323Sed 230199511Srdivackyvoid MachineFunction::verify(Pass *p, bool allowDoubleDefs) const { 231199511Srdivacky MachineVerifier(p, allowDoubleDefs) 232199511Srdivacky .runOnMachineFunction(const_cast<MachineFunction&>(*this)); 233199481Srdivacky} 234199481Srdivacky 235198090Srdivackybool MachineVerifier::runOnMachineFunction(MachineFunction &MF) { 236198090Srdivacky raw_ostream *OutFile = 0; 237193323Sed if (OutFileName) { 238198090Srdivacky std::string ErrorInfo; 239198090Srdivacky OutFile = new raw_fd_ostream(OutFileName, ErrorInfo, 240198090Srdivacky raw_fd_ostream::F_Append); 241198090Srdivacky if (!ErrorInfo.empty()) { 242198090Srdivacky errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n'; 243198090Srdivacky exit(1); 244198090Srdivacky } 245198090Srdivacky 246198090Srdivacky OS = OutFile; 247193323Sed } else { 248198090Srdivacky OS = &errs(); 249193323Sed } 250193323Sed 251193323Sed foundErrors = 0; 252193323Sed 253193323Sed this->MF = &MF; 254193323Sed TM = &MF.getTarget(); 255193323Sed TRI = TM->getRegisterInfo(); 256193323Sed MRI = &MF.getRegInfo(); 257193323Sed 258199511Srdivacky if (PASS) { 259199511Srdivacky LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>(); 260199511Srdivacky } else { 261199511Srdivacky LiveVars = NULL; 262199511Srdivacky } 263199511Srdivacky 264193323Sed visitMachineFunctionBefore(); 265193323Sed for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end(); 266193323Sed MFI!=MFE; ++MFI) { 267193323Sed visitMachineBasicBlockBefore(MFI); 268193323Sed for (MachineBasicBlock::const_iterator MBBI = MFI->begin(), 269193323Sed MBBE = MFI->end(); MBBI != MBBE; ++MBBI) { 270193323Sed visitMachineInstrBefore(MBBI); 271193323Sed for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) 272193323Sed visitMachineOperand(&MBBI->getOperand(I), I); 273193323Sed visitMachineInstrAfter(MBBI); 274193323Sed } 275193323Sed visitMachineBasicBlockAfter(MFI); 276193323Sed } 277193323Sed visitMachineFunctionAfter(); 278193323Sed 279198090Srdivacky if (OutFile) 280198090Srdivacky delete OutFile; 281198090Srdivacky else if (foundErrors) 282207618Srdivacky report_fatal_error("Found "+Twine(foundErrors)+" machine code errors."); 283193323Sed 284198090Srdivacky // Clean up. 285198090Srdivacky regsLive.clear(); 286198090Srdivacky regsDefined.clear(); 287198090Srdivacky regsDead.clear(); 288198090Srdivacky regsKilled.clear(); 289198090Srdivacky regsLiveInButUnused.clear(); 290198090Srdivacky MBBInfoMap.clear(); 291193323Sed 292193323Sed return false; // no changes 293193323Sed} 294193323Sed 295198090Srdivackyvoid MachineVerifier::report(const char *msg, const MachineFunction *MF) { 296193323Sed assert(MF); 297198090Srdivacky *OS << '\n'; 298193323Sed if (!foundErrors++) 299198090Srdivacky MF->print(*OS); 300193323Sed *OS << "*** Bad machine code: " << msg << " ***\n" 301198090Srdivacky << "- function: " << MF->getFunction()->getNameStr() << "\n"; 302193323Sed} 303193323Sed 304198090Srdivackyvoid MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) { 305193323Sed assert(MBB); 306193323Sed report(msg, MBB->getParent()); 307199989Srdivacky *OS << "- basic block: " << MBB->getName() 308193323Sed << " " << (void*)MBB 309198892Srdivacky << " (BB#" << MBB->getNumber() << ")\n"; 310193323Sed} 311193323Sed 312198090Srdivackyvoid MachineVerifier::report(const char *msg, const MachineInstr *MI) { 313193323Sed assert(MI); 314193323Sed report(msg, MI->getParent()); 315193323Sed *OS << "- instruction: "; 316198090Srdivacky MI->print(*OS, TM); 317193323Sed} 318193323Sed 319198090Srdivackyvoid MachineVerifier::report(const char *msg, 320198090Srdivacky const MachineOperand *MO, unsigned MONum) { 321193323Sed assert(MO); 322193323Sed report(msg, MO->getParent()); 323193323Sed *OS << "- operand " << MONum << ": "; 324193323Sed MO->print(*OS, TM); 325193323Sed *OS << "\n"; 326193323Sed} 327193323Sed 328198090Srdivackyvoid MachineVerifier::markReachable(const MachineBasicBlock *MBB) { 329193323Sed BBInfo &MInfo = MBBInfoMap[MBB]; 330193323Sed if (!MInfo.reachable) { 331193323Sed MInfo.reachable = true; 332193323Sed for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), 333193323Sed SuE = MBB->succ_end(); SuI != SuE; ++SuI) 334193323Sed markReachable(*SuI); 335193323Sed } 336193323Sed} 337193323Sed 338198090Srdivackyvoid MachineVerifier::visitMachineFunctionBefore() { 339193323Sed regsReserved = TRI->getReservedRegs(*MF); 340198090Srdivacky 341198090Srdivacky // A sub-register of a reserved register is also reserved 342198090Srdivacky for (int Reg = regsReserved.find_first(); Reg>=0; 343198090Srdivacky Reg = regsReserved.find_next(Reg)) { 344198090Srdivacky for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) { 345198090Srdivacky // FIXME: This should probably be: 346198090Srdivacky // assert(regsReserved.test(*Sub) && "Non-reserved sub-register"); 347198090Srdivacky regsReserved.set(*Sub); 348198090Srdivacky } 349198090Srdivacky } 350193323Sed markReachable(&MF->front()); 351193323Sed} 352193323Sed 353199481Srdivacky// Does iterator point to a and b as the first two elements? 354207618Srdivackystatic bool matchPair(MachineBasicBlock::const_succ_iterator i, 355207618Srdivacky const MachineBasicBlock *a, const MachineBasicBlock *b) { 356199481Srdivacky if (*i == a) 357199481Srdivacky return *++i == b; 358199481Srdivacky if (*i == b) 359199481Srdivacky return *++i == a; 360199481Srdivacky return false; 361199481Srdivacky} 362199481Srdivacky 363199481Srdivackyvoid 364199481SrdivackyMachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { 365198090Srdivacky const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 366198090Srdivacky 367198090Srdivacky // Call AnalyzeBranch. If it succeeds, there several more conditions to check. 368198090Srdivacky MachineBasicBlock *TBB = 0, *FBB = 0; 369198090Srdivacky SmallVector<MachineOperand, 4> Cond; 370198090Srdivacky if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB), 371198090Srdivacky TBB, FBB, Cond)) { 372198090Srdivacky // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's 373198090Srdivacky // check whether its answers match up with reality. 374198090Srdivacky if (!TBB && !FBB) { 375198090Srdivacky // Block falls through to its successor. 376198090Srdivacky MachineFunction::const_iterator MBBI = MBB; 377198090Srdivacky ++MBBI; 378198090Srdivacky if (MBBI == MF->end()) { 379198090Srdivacky // It's possible that the block legitimately ends with a noreturn 380198090Srdivacky // call or an unreachable, in which case it won't actually fall 381198090Srdivacky // out the bottom of the function. 382198090Srdivacky } else if (MBB->succ_empty()) { 383198090Srdivacky // It's possible that the block legitimately ends with a noreturn 384198090Srdivacky // call or an unreachable, in which case it won't actuall fall 385198090Srdivacky // out of the block. 386198090Srdivacky } else if (MBB->succ_size() != 1) { 387198090Srdivacky report("MBB exits via unconditional fall-through but doesn't have " 388198090Srdivacky "exactly one CFG successor!", MBB); 389198090Srdivacky } else if (MBB->succ_begin()[0] != MBBI) { 390198090Srdivacky report("MBB exits via unconditional fall-through but its successor " 391198090Srdivacky "differs from its CFG successor!", MBB); 392198090Srdivacky } 393198090Srdivacky if (!MBB->empty() && MBB->back().getDesc().isBarrier()) { 394198090Srdivacky report("MBB exits via unconditional fall-through but ends with a " 395198090Srdivacky "barrier instruction!", MBB); 396198090Srdivacky } 397198090Srdivacky if (!Cond.empty()) { 398198090Srdivacky report("MBB exits via unconditional fall-through but has a condition!", 399198090Srdivacky MBB); 400198090Srdivacky } 401198090Srdivacky } else if (TBB && !FBB && Cond.empty()) { 402198090Srdivacky // Block unconditionally branches somewhere. 403198090Srdivacky if (MBB->succ_size() != 1) { 404198090Srdivacky report("MBB exits via unconditional branch but doesn't have " 405198090Srdivacky "exactly one CFG successor!", MBB); 406198090Srdivacky } else if (MBB->succ_begin()[0] != TBB) { 407198090Srdivacky report("MBB exits via unconditional branch but the CFG " 408198090Srdivacky "successor doesn't match the actual successor!", MBB); 409198090Srdivacky } 410198090Srdivacky if (MBB->empty()) { 411198090Srdivacky report("MBB exits via unconditional branch but doesn't contain " 412198090Srdivacky "any instructions!", MBB); 413198090Srdivacky } else if (!MBB->back().getDesc().isBarrier()) { 414198090Srdivacky report("MBB exits via unconditional branch but doesn't end with a " 415198090Srdivacky "barrier instruction!", MBB); 416198090Srdivacky } else if (!MBB->back().getDesc().isTerminator()) { 417198090Srdivacky report("MBB exits via unconditional branch but the branch isn't a " 418198090Srdivacky "terminator instruction!", MBB); 419198090Srdivacky } 420198090Srdivacky } else if (TBB && !FBB && !Cond.empty()) { 421198090Srdivacky // Block conditionally branches somewhere, otherwise falls through. 422198090Srdivacky MachineFunction::const_iterator MBBI = MBB; 423198090Srdivacky ++MBBI; 424198090Srdivacky if (MBBI == MF->end()) { 425198090Srdivacky report("MBB conditionally falls through out of function!", MBB); 426198090Srdivacky } if (MBB->succ_size() != 2) { 427198090Srdivacky report("MBB exits via conditional branch/fall-through but doesn't have " 428198090Srdivacky "exactly two CFG successors!", MBB); 429199481Srdivacky } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) { 430198090Srdivacky report("MBB exits via conditional branch/fall-through but the CFG " 431198090Srdivacky "successors don't match the actual successors!", MBB); 432198090Srdivacky } 433198090Srdivacky if (MBB->empty()) { 434198090Srdivacky report("MBB exits via conditional branch/fall-through but doesn't " 435198090Srdivacky "contain any instructions!", MBB); 436198090Srdivacky } else if (MBB->back().getDesc().isBarrier()) { 437198090Srdivacky report("MBB exits via conditional branch/fall-through but ends with a " 438198090Srdivacky "barrier instruction!", MBB); 439198090Srdivacky } else if (!MBB->back().getDesc().isTerminator()) { 440198090Srdivacky report("MBB exits via conditional branch/fall-through but the branch " 441198090Srdivacky "isn't a terminator instruction!", MBB); 442198090Srdivacky } 443198090Srdivacky } else if (TBB && FBB) { 444198090Srdivacky // Block conditionally branches somewhere, otherwise branches 445198090Srdivacky // somewhere else. 446198090Srdivacky if (MBB->succ_size() != 2) { 447198090Srdivacky report("MBB exits via conditional branch/branch but doesn't have " 448198090Srdivacky "exactly two CFG successors!", MBB); 449199481Srdivacky } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) { 450198090Srdivacky report("MBB exits via conditional branch/branch but the CFG " 451198090Srdivacky "successors don't match the actual successors!", MBB); 452198090Srdivacky } 453198090Srdivacky if (MBB->empty()) { 454198090Srdivacky report("MBB exits via conditional branch/branch but doesn't " 455198090Srdivacky "contain any instructions!", MBB); 456198090Srdivacky } else if (!MBB->back().getDesc().isBarrier()) { 457198090Srdivacky report("MBB exits via conditional branch/branch but doesn't end with a " 458198090Srdivacky "barrier instruction!", MBB); 459198090Srdivacky } else if (!MBB->back().getDesc().isTerminator()) { 460198090Srdivacky report("MBB exits via conditional branch/branch but the branch " 461198090Srdivacky "isn't a terminator instruction!", MBB); 462198090Srdivacky } 463198090Srdivacky if (Cond.empty()) { 464198090Srdivacky report("MBB exits via conditinal branch/branch but there's no " 465198090Srdivacky "condition!", MBB); 466198090Srdivacky } 467198090Srdivacky } else { 468198090Srdivacky report("AnalyzeBranch returned invalid data!", MBB); 469198090Srdivacky } 470198090Srdivacky } 471198090Srdivacky 472193323Sed regsLive.clear(); 473207618Srdivacky for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), 474193323Sed E = MBB->livein_end(); I != E; ++I) { 475193323Sed if (!TargetRegisterInfo::isPhysicalRegister(*I)) { 476193323Sed report("MBB live-in list contains non-physical register", MBB); 477193323Sed continue; 478193323Sed } 479193323Sed regsLive.insert(*I); 480193323Sed for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++) 481193323Sed regsLive.insert(*R); 482193323Sed } 483198090Srdivacky regsLiveInButUnused = regsLive; 484198090Srdivacky 485198090Srdivacky const MachineFrameInfo *MFI = MF->getFrameInfo(); 486198090Srdivacky assert(MFI && "Function has no frame info"); 487198090Srdivacky BitVector PR = MFI->getPristineRegs(MBB); 488198090Srdivacky for (int I = PR.find_first(); I>0; I = PR.find_next(I)) { 489198090Srdivacky regsLive.insert(I); 490198090Srdivacky for (const unsigned *R = TRI->getSubRegisters(I); *R; R++) 491198090Srdivacky regsLive.insert(*R); 492198090Srdivacky } 493198090Srdivacky 494193323Sed regsKilled.clear(); 495193323Sed regsDefined.clear(); 496193323Sed} 497193323Sed 498198090Srdivackyvoid MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { 499193323Sed const TargetInstrDesc &TI = MI->getDesc(); 500198090Srdivacky if (MI->getNumOperands() < TI.getNumOperands()) { 501193323Sed report("Too few operands", MI); 502193323Sed *OS << TI.getNumOperands() << " operands expected, but " 503193323Sed << MI->getNumExplicitOperands() << " given.\n"; 504193323Sed } 505198090Srdivacky 506198090Srdivacky // Check the MachineMemOperands for basic consistency. 507198090Srdivacky for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), 508198090Srdivacky E = MI->memoperands_end(); I != E; ++I) { 509198090Srdivacky if ((*I)->isLoad() && !TI.mayLoad()) 510198090Srdivacky report("Missing mayLoad flag", MI); 511198090Srdivacky if ((*I)->isStore() && !TI.mayStore()) 512198090Srdivacky report("Missing mayStore flag", MI); 513193323Sed } 514193323Sed} 515193323Sed 516193323Sedvoid 517198090SrdivackyMachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { 518193323Sed const MachineInstr *MI = MO->getParent(); 519193323Sed const TargetInstrDesc &TI = MI->getDesc(); 520193323Sed 521193323Sed // The first TI.NumDefs operands must be explicit register defines 522193323Sed if (MONum < TI.getNumDefs()) { 523193323Sed if (!MO->isReg()) 524193323Sed report("Explicit definition must be a register", MO, MONum); 525193323Sed else if (!MO->isDef()) 526193323Sed report("Explicit definition marked as use", MO, MONum); 527193323Sed else if (MO->isImplicit()) 528193323Sed report("Explicit definition marked as implicit", MO, MONum); 529198090Srdivacky } else if (MONum < TI.getNumOperands()) { 530198090Srdivacky if (MO->isReg()) { 531198090Srdivacky if (MO->isDef()) 532198090Srdivacky report("Explicit operand marked as def", MO, MONum); 533198090Srdivacky if (MO->isImplicit()) 534198090Srdivacky report("Explicit operand marked as implicit", MO, MONum); 535198090Srdivacky } 536198090Srdivacky } else { 537201360Srdivacky // ARM adds %reg0 operands to indicate predicates. We'll allow that. 538201360Srdivacky if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg()) 539198090Srdivacky report("Extra explicit operand on non-variadic instruction", MO, MONum); 540193323Sed } 541193323Sed 542193323Sed switch (MO->getType()) { 543193323Sed case MachineOperand::MO_Register: { 544193323Sed const unsigned Reg = MO->getReg(); 545193323Sed if (!Reg) 546193323Sed return; 547193323Sed 548193323Sed // Check Live Variables. 549198090Srdivacky if (MO->isUndef()) { 550198090Srdivacky // An <undef> doesn't refer to any register, so just skip it. 551198090Srdivacky } else if (MO->isUse()) { 552198090Srdivacky regsLiveInButUnused.erase(Reg); 553198090Srdivacky 554199511Srdivacky bool isKill = false; 555193323Sed if (MO->isKill()) { 556199511Srdivacky isKill = true; 557198090Srdivacky // Tied operands on two-address instuctions MUST NOT have a <kill> flag. 558198090Srdivacky if (MI->isRegTiedToDefOperand(MONum)) 559198090Srdivacky report("Illegal kill flag on two-address instruction operand", 560198090Srdivacky MO, MONum); 561193323Sed } else { 562198090Srdivacky // TwoAddress instr modifying a reg is treated as kill+def. 563193323Sed unsigned defIdx; 564193323Sed if (MI->isRegTiedToDefOperand(MONum, &defIdx) && 565193323Sed MI->getOperand(defIdx).getReg() == Reg) 566199511Srdivacky isKill = true; 567193323Sed } 568199511Srdivacky if (isKill) { 569199511Srdivacky addRegWithSubRegs(regsKilled, Reg); 570199511Srdivacky 571199511Srdivacky // Check that LiveVars knows this kill 572199511Srdivacky if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg)) { 573199511Srdivacky LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); 574199511Srdivacky if (std::find(VI.Kills.begin(), 575199511Srdivacky VI.Kills.end(), MI) == VI.Kills.end()) 576199511Srdivacky report("Kill missing from LiveVariables", MO, MONum); 577199511Srdivacky } 578199511Srdivacky } 579199511Srdivacky 580198090Srdivacky // Use of a dead register. 581198090Srdivacky if (!regsLive.count(Reg)) { 582193323Sed if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 583193323Sed // Reserved registers may be used even when 'dead'. 584193323Sed if (!isReserved(Reg)) 585193323Sed report("Using an undefined physical register", MO, MONum); 586193323Sed } else { 587193323Sed BBInfo &MInfo = MBBInfoMap[MI->getParent()]; 588193323Sed // We don't know which virtual registers are live in, so only complain 589193323Sed // if vreg was killed in this MBB. Otherwise keep track of vregs that 590193323Sed // must be live in. PHI instructions are handled separately. 591193323Sed if (MInfo.regsKilled.count(Reg)) 592193323Sed report("Using a killed virtual register", MO, MONum); 593203954Srdivacky else if (!MI->isPHI()) 594193323Sed MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI)); 595193323Sed } 596193323Sed } 597193323Sed } else { 598198090Srdivacky assert(MO->isDef()); 599193323Sed // Register defined. 600193323Sed // TODO: verify that earlyclobber ops are not used. 601198090Srdivacky if (MO->isDead()) 602198090Srdivacky addRegWithSubRegs(regsDead, Reg); 603193323Sed else 604193323Sed addRegWithSubRegs(regsDefined, Reg); 605193323Sed } 606193323Sed 607193323Sed // Check register classes. 608193323Sed if (MONum < TI.getNumOperands() && !MO->isImplicit()) { 609193323Sed const TargetOperandInfo &TOI = TI.OpInfo[MONum]; 610193323Sed unsigned SubIdx = MO->getSubReg(); 611193323Sed 612193323Sed if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 613193323Sed unsigned sr = Reg; 614193323Sed if (SubIdx) { 615193323Sed unsigned s = TRI->getSubReg(Reg, SubIdx); 616193323Sed if (!s) { 617193323Sed report("Invalid subregister index for physical register", 618193323Sed MO, MONum); 619193323Sed return; 620193323Sed } 621193323Sed sr = s; 622193323Sed } 623198090Srdivacky if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) { 624193323Sed if (!DRC->contains(sr)) { 625193323Sed report("Illegal physical register for instruction", MO, MONum); 626193323Sed *OS << TRI->getName(sr) << " is not a " 627193323Sed << DRC->getName() << " register.\n"; 628193323Sed } 629193323Sed } 630193323Sed } else { 631193323Sed // Virtual register. 632193323Sed const TargetRegisterClass *RC = MRI->getRegClass(Reg); 633193323Sed if (SubIdx) { 634193323Sed if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) { 635193323Sed report("Invalid subregister index for virtual register", MO, MONum); 636193323Sed return; 637193323Sed } 638193323Sed RC = *(RC->subregclasses_begin()+SubIdx); 639193323Sed } 640198090Srdivacky if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) { 641193323Sed if (RC != DRC && !RC->hasSuperClass(DRC)) { 642193323Sed report("Illegal virtual register for instruction", MO, MONum); 643193323Sed *OS << "Expected a " << DRC->getName() << " register, but got a " 644193323Sed << RC->getName() << " register\n"; 645193323Sed } 646193323Sed } 647193323Sed } 648193323Sed } 649193323Sed break; 650193323Sed } 651198090Srdivacky 652198090Srdivacky case MachineOperand::MO_MachineBasicBlock: 653203954Srdivacky if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent())) 654203954Srdivacky report("PHI operand is not in the CFG", MO, MONum); 655198090Srdivacky break; 656198090Srdivacky 657193323Sed default: 658193323Sed break; 659193323Sed } 660193323Sed} 661193323Sed 662198090Srdivackyvoid MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) { 663193323Sed BBInfo &MInfo = MBBInfoMap[MI->getParent()]; 664193323Sed set_union(MInfo.regsKilled, regsKilled); 665193323Sed set_subtract(regsLive, regsKilled); 666193323Sed regsKilled.clear(); 667193323Sed 668198090Srdivacky // Verify that both <def> and <def,dead> operands refer to dead registers. 669198090Srdivacky RegVector defs(regsDefined); 670198090Srdivacky defs.append(regsDead.begin(), regsDead.end()); 671198090Srdivacky 672198090Srdivacky for (RegVector::const_iterator I = defs.begin(), E = defs.end(); 673198090Srdivacky I != E; ++I) { 674193323Sed if (regsLive.count(*I)) { 675193323Sed if (TargetRegisterInfo::isPhysicalRegister(*I)) { 676193323Sed if (!allowPhysDoubleDefs && !isReserved(*I) && 677198090Srdivacky !regsLiveInButUnused.count(*I)) { 678193323Sed report("Redefining a live physical register", MI); 679193323Sed *OS << "Register " << TRI->getName(*I) 680193323Sed << " was defined but already live.\n"; 681193323Sed } 682193323Sed } else { 683193323Sed if (!allowVirtDoubleDefs) { 684193323Sed report("Redefining a live virtual register", MI); 685193323Sed *OS << "Virtual register %reg" << *I 686193323Sed << " was defined but already live.\n"; 687193323Sed } 688193323Sed } 689193323Sed } else if (TargetRegisterInfo::isVirtualRegister(*I) && 690193323Sed !MInfo.regsKilled.count(*I)) { 691193323Sed // Virtual register defined without being killed first must be dead on 692193323Sed // entry. 693193323Sed MInfo.vregsDeadIn.insert(std::make_pair(*I, MI)); 694193323Sed } 695193323Sed } 696193323Sed 697198090Srdivacky set_subtract(regsLive, regsDead); regsDead.clear(); 698193323Sed set_union(regsLive, regsDefined); regsDefined.clear(); 699193323Sed} 700193323Sed 701193323Sedvoid 702198090SrdivackyMachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) { 703193323Sed MBBInfoMap[MBB].regsLiveOut = regsLive; 704193323Sed regsLive.clear(); 705193323Sed} 706193323Sed 707193323Sed// Calculate the largest possible vregsPassed sets. These are the registers that 708193323Sed// can pass through an MBB live, but may not be live every time. It is assumed 709193323Sed// that all vregsPassed sets are empty before the call. 710202375Srdivackyvoid MachineVerifier::calcRegsPassed() { 711193323Sed // First push live-out regs to successors' vregsPassed. Remember the MBBs that 712193323Sed // have any vregsPassed. 713193323Sed DenseSet<const MachineBasicBlock*> todo; 714193323Sed for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 715193323Sed MFI != MFE; ++MFI) { 716193323Sed const MachineBasicBlock &MBB(*MFI); 717193323Sed BBInfo &MInfo = MBBInfoMap[&MBB]; 718193323Sed if (!MInfo.reachable) 719193323Sed continue; 720193323Sed for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(), 721193323Sed SuE = MBB.succ_end(); SuI != SuE; ++SuI) { 722193323Sed BBInfo &SInfo = MBBInfoMap[*SuI]; 723193323Sed if (SInfo.addPassed(MInfo.regsLiveOut)) 724193323Sed todo.insert(*SuI); 725193323Sed } 726193323Sed } 727193323Sed 728193323Sed // Iteratively push vregsPassed to successors. This will converge to the same 729193323Sed // final state regardless of DenseSet iteration order. 730193323Sed while (!todo.empty()) { 731193323Sed const MachineBasicBlock *MBB = *todo.begin(); 732193323Sed todo.erase(MBB); 733193323Sed BBInfo &MInfo = MBBInfoMap[MBB]; 734193323Sed for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), 735193323Sed SuE = MBB->succ_end(); SuI != SuE; ++SuI) { 736193323Sed if (*SuI == MBB) 737193323Sed continue; 738193323Sed BBInfo &SInfo = MBBInfoMap[*SuI]; 739193323Sed if (SInfo.addPassed(MInfo.vregsPassed)) 740193323Sed todo.insert(*SuI); 741193323Sed } 742193323Sed } 743193323Sed} 744193323Sed 745199511Srdivacky// Calculate the set of virtual registers that must be passed through each basic 746199511Srdivacky// block in order to satisfy the requirements of successor blocks. This is very 747202375Srdivacky// similar to calcRegsPassed, only backwards. 748199511Srdivackyvoid MachineVerifier::calcRegsRequired() { 749199511Srdivacky // First push live-in regs to predecessors' vregsRequired. 750199511Srdivacky DenseSet<const MachineBasicBlock*> todo; 751199511Srdivacky for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 752199511Srdivacky MFI != MFE; ++MFI) { 753199511Srdivacky const MachineBasicBlock &MBB(*MFI); 754199511Srdivacky BBInfo &MInfo = MBBInfoMap[&MBB]; 755199511Srdivacky for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(), 756199511Srdivacky PrE = MBB.pred_end(); PrI != PrE; ++PrI) { 757199511Srdivacky BBInfo &PInfo = MBBInfoMap[*PrI]; 758199511Srdivacky if (PInfo.addRequired(MInfo.vregsLiveIn)) 759199511Srdivacky todo.insert(*PrI); 760199511Srdivacky } 761199511Srdivacky } 762199511Srdivacky 763199511Srdivacky // Iteratively push vregsRequired to predecessors. This will converge to the 764199511Srdivacky // same final state regardless of DenseSet iteration order. 765199511Srdivacky while (!todo.empty()) { 766199511Srdivacky const MachineBasicBlock *MBB = *todo.begin(); 767199511Srdivacky todo.erase(MBB); 768199511Srdivacky BBInfo &MInfo = MBBInfoMap[MBB]; 769199511Srdivacky for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), 770199511Srdivacky PrE = MBB->pred_end(); PrI != PrE; ++PrI) { 771199511Srdivacky if (*PrI == MBB) 772199511Srdivacky continue; 773199511Srdivacky BBInfo &SInfo = MBBInfoMap[*PrI]; 774199511Srdivacky if (SInfo.addRequired(MInfo.vregsRequired)) 775199511Srdivacky todo.insert(*PrI); 776199511Srdivacky } 777199511Srdivacky } 778199511Srdivacky} 779199511Srdivacky 780193323Sed// Check PHI instructions at the beginning of MBB. It is assumed that 781202375Srdivacky// calcRegsPassed has been run so BBInfo::isLiveOut is valid. 782198090Srdivackyvoid MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) { 783193323Sed for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end(); 784203954Srdivacky BBI != BBE && BBI->isPHI(); ++BBI) { 785193323Sed DenseSet<const MachineBasicBlock*> seen; 786193323Sed 787193323Sed for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) { 788193323Sed unsigned Reg = BBI->getOperand(i).getReg(); 789193323Sed const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB(); 790193323Sed if (!Pre->isSuccessor(MBB)) 791193323Sed continue; 792193323Sed seen.insert(Pre); 793193323Sed BBInfo &PrInfo = MBBInfoMap[Pre]; 794193323Sed if (PrInfo.reachable && !PrInfo.isLiveOut(Reg)) 795193323Sed report("PHI operand is not live-out from predecessor", 796193323Sed &BBI->getOperand(i), i); 797193323Sed } 798193323Sed 799193323Sed // Did we see all predecessors? 800193323Sed for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), 801193323Sed PrE = MBB->pred_end(); PrI != PrE; ++PrI) { 802193323Sed if (!seen.count(*PrI)) { 803193323Sed report("Missing PHI operand", BBI); 804198892Srdivacky *OS << "BB#" << (*PrI)->getNumber() 805193323Sed << " is a predecessor according to the CFG.\n"; 806193323Sed } 807193323Sed } 808193323Sed } 809193323Sed} 810193323Sed 811198090Srdivackyvoid MachineVerifier::visitMachineFunctionAfter() { 812202375Srdivacky calcRegsPassed(); 813193323Sed 814193323Sed for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 815193323Sed MFI != MFE; ++MFI) { 816193323Sed BBInfo &MInfo = MBBInfoMap[MFI]; 817193323Sed 818193323Sed // Skip unreachable MBBs. 819193323Sed if (!MInfo.reachable) 820193323Sed continue; 821193323Sed 822202375Srdivacky checkPHIOps(MFI); 823193323Sed 824202375Srdivacky // Verify dead-in virtual registers. 825202375Srdivacky if (!allowVirtDoubleDefs) { 826202375Srdivacky for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(), 827202375Srdivacky PrE = MFI->pred_end(); PrI != PrE; ++PrI) { 828202375Srdivacky BBInfo &PrInfo = MBBInfoMap[*PrI]; 829202375Srdivacky if (!PrInfo.reachable) 830202375Srdivacky continue; 831193323Sed 832193323Sed for (RegMap::iterator I = MInfo.vregsDeadIn.begin(), 833193323Sed E = MInfo.vregsDeadIn.end(); I != E; ++I) { 834193323Sed // DeadIn register must be in neither regsLiveOut or vregsPassed of 835193323Sed // any predecessor. 836193323Sed if (PrInfo.isLiveOut(I->first)) { 837193323Sed report("Live-in virtual register redefined", I->second); 838193323Sed *OS << "Register %reg" << I->first 839193323Sed << " was live-out from predecessor MBB #" 840193323Sed << (*PrI)->getNumber() << ".\n"; 841193323Sed } 842193323Sed } 843193323Sed } 844193323Sed } 845193323Sed } 846193323Sed 847199511Srdivacky // Now check LiveVariables info if available 848199511Srdivacky if (LiveVars) { 849199511Srdivacky calcRegsRequired(); 850199511Srdivacky verifyLiveVariables(); 851199511Srdivacky } 852193323Sed} 853199511Srdivacky 854199511Srdivackyvoid MachineVerifier::verifyLiveVariables() { 855199511Srdivacky assert(LiveVars && "Don't call verifyLiveVariables without LiveVars"); 856199511Srdivacky for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister, 857199511Srdivacky RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) { 858199511Srdivacky LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); 859199511Srdivacky for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 860199511Srdivacky MFI != MFE; ++MFI) { 861199511Srdivacky BBInfo &MInfo = MBBInfoMap[MFI]; 862199511Srdivacky 863199511Srdivacky // Our vregsRequired should be identical to LiveVariables' AliveBlocks 864199511Srdivacky if (MInfo.vregsRequired.count(Reg)) { 865199511Srdivacky if (!VI.AliveBlocks.test(MFI->getNumber())) { 866199511Srdivacky report("LiveVariables: Block missing from AliveBlocks", MFI); 867199511Srdivacky *OS << "Virtual register %reg" << Reg 868199511Srdivacky << " must be live through the block.\n"; 869199511Srdivacky } 870199511Srdivacky } else { 871199511Srdivacky if (VI.AliveBlocks.test(MFI->getNumber())) { 872199511Srdivacky report("LiveVariables: Block should not be in AliveBlocks", MFI); 873199511Srdivacky *OS << "Virtual register %reg" << Reg 874199511Srdivacky << " is not needed live through the block.\n"; 875199511Srdivacky } 876199511Srdivacky } 877199511Srdivacky } 878199511Srdivacky } 879199511Srdivacky} 880199511Srdivacky 881199511Srdivacky 882