TargetOpcodes.h revision 207618
1104477Ssam//===-- llvm/Target/TargetOpcodes.h - Target Indep Opcodes ------*- C++ -*-===// 2104477Ssam// 3104477Ssam// The LLVM Compiler Infrastructure 4104477Ssam// 5104477Ssam// This file is distributed under the University of Illinois Open Source 6104477Ssam// License. See LICENSE.TXT for details. 7104477Ssam// 8104477Ssam//===----------------------------------------------------------------------===// 9120915Ssam// 10104477Ssam// This file defines the target independent instruction opcodes. 11104477Ssam// 12104477Ssam//===----------------------------------------------------------------------===// 13104477Ssam 14104477Ssam#ifndef LLVM_TARGET_TARGETOPCODES_H 15104477Ssam#define LLVM_TARGET_TARGETOPCODES_H 16104477Ssam 17104477Ssamnamespace llvm { 18104477Ssam 19104477Ssam/// Invariant opcodes: All instruction sets have these as their low opcodes. 20104477Ssamnamespace TargetOpcode { 21104477Ssam enum { 22104477Ssam PHI = 0, 23104477Ssam INLINEASM = 1, 24104477Ssam DBG_LABEL = 2, 25104477Ssam EH_LABEL = 3, 26104477Ssam GC_LABEL = 4, 27104477Ssam 28104477Ssam /// KILL - This instruction is a noop that is used only to adjust the 29104477Ssam /// liveness of registers. This can be useful when dealing with 30104477Ssam /// sub-registers. 31104477Ssam KILL = 5, 32104477Ssam 33104477Ssam /// EXTRACT_SUBREG - This instruction takes two operands: a register 34104477Ssam /// that has subregisters, and a subregister index. It returns the 35104477Ssam /// extracted subregister value. This is commonly used to implement 36104477Ssam /// truncation operations on target architectures which support it. 37104477Ssam EXTRACT_SUBREG = 6, 38104477Ssam 39104477Ssam /// INSERT_SUBREG - This instruction takes three operands: a register 40104477Ssam /// that has subregisters, a register providing an insert value, and a 41104477Ssam /// subregister index. It returns the value of the first register with 42104477Ssam /// the value of the second register inserted. The first register is 43119418Sobrien /// often defined by an IMPLICIT_DEF, as is commonly used to implement 44119418Sobrien /// anyext operations on target architectures which support it. 45119418Sobrien INSERT_SUBREG = 7, 46104477Ssam 47120915Ssam /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 48104477Ssam IMPLICIT_DEF = 8, 49112124Ssam 50104477Ssam /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except 51104477Ssam /// that the first operand is an immediate integer constant. This constant 52104477Ssam /// is often zero, as is commonly used to implement zext operations on 53104477Ssam /// target architectures which support it, such as with x86-64 (with 54104477Ssam /// zext from i32 to i64 via implicit zero-extension). 55104477Ssam SUBREG_TO_REG = 9, 56104477Ssam 57129879Sphk /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 58104477Ssam /// register-to-register copy into a specific register class. This is only 59104477Ssam /// used between instruction selection and MachineInstr creation, before 60104477Ssam /// virtual registers have been created for all the instructions, and it's 61104477Ssam /// only needed in cases where the register classes implied by the 62104477Ssam /// instructions are insufficient. The actual MachineInstrs to perform 63104477Ssam /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. 64104477Ssam COPY_TO_REGCLASS = 10, 65104477Ssam 66104477Ssam /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 67104477Ssam DBG_VALUE = 11, 68104477Ssam 69104477Ssam /// REG_SEQUENCE - This variadic instruction is used to form a register that 70104477Ssam /// represent a consecutive sequence of sub-registers. It's used as register 71104477Ssam /// coalescing / allocation aid and must be eliminated before code emission. 72104477Ssam /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 73104477Ssam /// After register coalescing references of v1024 should be replace with 74104477Ssam /// v1027:3, v1025 with v1027:4, etc. 75119280Simp REG_SEQUENCE = 12 76119280Simp }; 77112124Ssam} // end namespace TargetOpcode 78112124Ssam} // end namespace llvm 79112124Ssam 80112124Ssam#endif 81104477Ssam