1193323Sed//===-- Passes.h - Target independent code generation passes ----*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines interfaces to access the target independent code generation 11193323Sed// passes provided by the LLVM backend. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#ifndef LLVM_CODEGEN_PASSES_H 16193323Sed#define LLVM_CODEGEN_PASSES_H 17193323Sed 18235633Sdim#include "llvm/Pass.h" 19198396Srdivacky#include "llvm/Target/TargetMachine.h" 20193323Sed#include <string> 21193323Sed 22193323Sednamespace llvm { 23193323Sed 24263509Sdimclass FunctionPass; 25263509Sdimclass MachineFunctionPass; 26263509Sdimclass PassConfigImpl; 27263509Sdimclass PassInfo; 28263509Sdimclass ScheduleDAGInstrs; 29263509Sdimclass TargetLowering; 30263509Sdimclass TargetLoweringBase; 31263509Sdimclass TargetRegisterClass; 32263509Sdimclass raw_ostream; 33263509Sdimstruct MachineSchedContext; 34263509Sdim 35263509Sdim// The old pass manager infrastructure is hidden in a legacy namespace now. 36263509Sdimnamespace legacy { 37263509Sdimclass PassManagerBase; 38235633Sdim} 39263509Sdimusing legacy::PassManagerBase; 40193323Sed 41252723Sdim/// Discriminated union of Pass ID types. 42252723Sdim/// 43252723Sdim/// The PassConfig API prefers dealing with IDs because they are safer and more 44252723Sdim/// efficient. IDs decouple configuration from instantiation. This way, when a 45252723Sdim/// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to 46252723Sdim/// refer to a Pass pointer after adding it to a pass manager, which deletes 47252723Sdim/// redundant pass instances. 48252723Sdim/// 49252723Sdim/// However, it is convient to directly instantiate target passes with 50252723Sdim/// non-default ctors. These often don't have a registered PassInfo. Rather than 51252723Sdim/// force all target passes to implement the pass registry boilerplate, allow 52252723Sdim/// the PassConfig API to handle either type. 53252723Sdim/// 54252723Sdim/// AnalysisID is sadly char*, so PointerIntPair won't work. 55252723Sdimclass IdentifyingPassPtr { 56252723Sdim union { 57252723Sdim AnalysisID ID; 58252723Sdim Pass *P; 59252723Sdim }; 60252723Sdim bool IsInstance; 61252723Sdimpublic: 62252723Sdim IdentifyingPassPtr() : P(0), IsInstance(false) {} 63252723Sdim IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {} 64252723Sdim IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {} 65252723Sdim 66252723Sdim bool isValid() const { return P; } 67252723Sdim bool isInstance() const { return IsInstance; } 68252723Sdim 69252723Sdim AnalysisID getID() const { 70252723Sdim assert(!IsInstance && "Not a Pass ID"); 71252723Sdim return ID; 72252723Sdim } 73252723Sdim Pass *getInstance() const { 74252723Sdim assert(IsInstance && "Not a Pass Instance"); 75252723Sdim return P; 76252723Sdim } 77252723Sdim}; 78252723Sdim 79252723Sdimtemplate <> struct isPodLike<IdentifyingPassPtr> { 80252723Sdim static const bool value = true; 81252723Sdim}; 82252723Sdim 83235633Sdim/// Target-Independent Code Generator Pass Configuration Options. 84235633Sdim/// 85235633Sdim/// This is an ImmutablePass solely for the purpose of exposing CodeGen options 86235633Sdim/// to the internals of other CodeGen passes. 87235633Sdimclass TargetPassConfig : public ImmutablePass { 88235633Sdimpublic: 89235633Sdim /// Pseudo Pass IDs. These are defined within TargetPassConfig because they 90235633Sdim /// are unregistered pass IDs. They are only useful for use with 91235633Sdim /// TargetPassConfig APIs to identify multiple occurrences of the same pass. 92235633Sdim /// 93235633Sdim 94235633Sdim /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early 95235633Sdim /// during codegen, on SSA form. 96235633Sdim static char EarlyTailDuplicateID; 97235633Sdim 98235633Sdim /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine 99235633Sdim /// optimization after regalloc. 100235633Sdim static char PostRAMachineLICMID; 101235633Sdim 102245431Sdimprivate: 103245431Sdim PassManagerBase *PM; 104245431Sdim AnalysisID StartAfter; 105245431Sdim AnalysisID StopAfter; 106245431Sdim bool Started; 107245431Sdim bool Stopped; 108245431Sdim 109235633Sdimprotected: 110235633Sdim TargetMachine *TM; 111235633Sdim PassConfigImpl *Impl; // Internal data structures 112235633Sdim bool Initialized; // Flagged after all passes are configured. 113235633Sdim 114235633Sdim // Target Pass Options 115235633Sdim // Targets provide a default setting, user flags override. 116235633Sdim // 117235633Sdim bool DisableVerify; 118235633Sdim 119235633Sdim /// Default setting for -enable-tail-merge on this target. 120235633Sdim bool EnableTailMerge; 121235633Sdim 122235633Sdimpublic: 123235633Sdim TargetPassConfig(TargetMachine *tm, PassManagerBase &pm); 124235633Sdim // Dummy constructor. 125235633Sdim TargetPassConfig(); 126235633Sdim 127235633Sdim virtual ~TargetPassConfig(); 128235633Sdim 129235633Sdim static char ID; 130235633Sdim 131235633Sdim /// Get the right type of TargetMachine for this target. 132235633Sdim template<typename TMC> TMC &getTM() const { 133235633Sdim return *static_cast<TMC*>(TM); 134235633Sdim } 135235633Sdim 136235633Sdim const TargetLowering *getTargetLowering() const { 137235633Sdim return TM->getTargetLowering(); 138235633Sdim } 139235633Sdim 140235633Sdim // 141235633Sdim void setInitialized() { Initialized = true; } 142235633Sdim 143235633Sdim CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); } 144235633Sdim 145245431Sdim /// setStartStopPasses - Set the StartAfter and StopAfter passes to allow 146245431Sdim /// running only a portion of the normal code-gen pass sequence. If the 147245431Sdim /// Start pass ID is zero, then compilation will begin at the normal point; 148245431Sdim /// otherwise, clear the Started flag to indicate that passes should not be 149245431Sdim /// added until the starting pass is seen. If the Stop pass ID is zero, 150245431Sdim /// then compilation will continue to the end. 151245431Sdim void setStartStopPasses(AnalysisID Start, AnalysisID Stop) { 152245431Sdim StartAfter = Start; 153245431Sdim StopAfter = Stop; 154245431Sdim Started = (StartAfter == 0); 155245431Sdim } 156245431Sdim 157235633Sdim void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); } 158235633Sdim 159235633Sdim bool getEnableTailMerge() const { return EnableTailMerge; } 160235633Sdim void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); } 161235633Sdim 162235633Sdim /// Allow the target to override a specific pass without overriding the pass 163235633Sdim /// pipeline. When passes are added to the standard pipeline at the 164245431Sdim /// point where StandardID is expected, add TargetID in its place. 165252723Sdim void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID); 166235633Sdim 167245431Sdim /// Insert InsertedPassID pass after TargetPassID pass. 168252723Sdim void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID); 169245431Sdim 170235633Sdim /// Allow the target to enable a specific standard pass by default. 171245431Sdim void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); } 172235633Sdim 173235633Sdim /// Allow the target to disable a specific standard pass by default. 174252723Sdim void disablePass(AnalysisID PassID) { 175252723Sdim substitutePass(PassID, IdentifyingPassPtr()); 176252723Sdim } 177235633Sdim 178245431Sdim /// Return the pass substituted for StandardID by the target. 179235633Sdim /// If no substitution exists, return StandardID. 180252723Sdim IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const; 181235633Sdim 182235633Sdim /// Return true if the optimized regalloc pipeline is enabled. 183235633Sdim bool getOptimizeRegAlloc() const; 184235633Sdim 185235633Sdim /// Add common target configurable passes that perform LLVM IR to IR 186235633Sdim /// transforms following machine independent optimization. 187235633Sdim virtual void addIRPasses(); 188235633Sdim 189245431Sdim /// Add passes to lower exception handling for the code generator. 190245431Sdim void addPassesToHandleExceptions(); 191245431Sdim 192252723Sdim /// Add pass to prepare the LLVM IR for code generation. This should be done 193252723Sdim /// before exception handling preparation passes. 194252723Sdim virtual void addCodeGenPrepare(); 195252723Sdim 196235633Sdim /// Add common passes that perform LLVM IR to IR transforms in preparation for 197235633Sdim /// instruction selection. 198235633Sdim virtual void addISelPrepare(); 199235633Sdim 200235633Sdim /// addInstSelector - This method should install an instruction selector pass, 201235633Sdim /// which converts from LLVM code to machine instructions. 202235633Sdim virtual bool addInstSelector() { 203235633Sdim return true; 204235633Sdim } 205235633Sdim 206235633Sdim /// Add the complete, standard set of LLVM CodeGen passes. 207235633Sdim /// Fully developed targets will not generally override this. 208235633Sdim virtual void addMachinePasses(); 209235633Sdim 210263509Sdim /// createTargetScheduler - Create an instance of ScheduleDAGInstrs to be run 211263509Sdim /// within the standard MachineScheduler pass for this function and target at 212263509Sdim /// the current optimization level. 213263509Sdim /// 214263509Sdim /// This can also be used to plug a new MachineSchedStrategy into an instance 215263509Sdim /// of the standard ScheduleDAGMI: 216263509Sdim /// return new ScheduleDAGMI(C, new MyStrategy(C)) 217263509Sdim /// 218263509Sdim /// Return NULL to select the default (generic) machine scheduler. 219263509Sdim virtual ScheduleDAGInstrs * 220263509Sdim createMachineScheduler(MachineSchedContext *C) const { 221263509Sdim return 0; 222263509Sdim } 223263509Sdim 224235633Sdimprotected: 225235633Sdim // Helper to verify the analysis is really immutable. 226235633Sdim void setOpt(bool &Opt, bool Val); 227235633Sdim 228235633Sdim /// Methods with trivial inline returns are convenient points in the common 229235633Sdim /// codegen pass pipeline where targets may insert passes. Methods with 230235633Sdim /// out-of-line standard implementations are major CodeGen stages called by 231235633Sdim /// addMachinePasses. Some targets may override major stages when inserting 232235633Sdim /// passes is insufficient, but maintaining overriden stages is more work. 233235633Sdim /// 234235633Sdim 235235633Sdim /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM 236235633Sdim /// passes (which are run just before instruction selector). 237235633Sdim virtual bool addPreISel() { 238235633Sdim return true; 239235633Sdim } 240235633Sdim 241235633Sdim /// addMachineSSAOptimization - Add standard passes that optimize machine 242235633Sdim /// instructions in SSA form. 243235633Sdim virtual void addMachineSSAOptimization(); 244235633Sdim 245252723Sdim /// Add passes that optimize instruction level parallelism for out-of-order 246252723Sdim /// targets. These passes are run while the machine code is still in SSA 247252723Sdim /// form, so they can use MachineTraceMetrics to control their heuristics. 248252723Sdim /// 249252723Sdim /// All passes added here should preserve the MachineDominatorTree, 250252723Sdim /// MachineLoopInfo, and MachineTraceMetrics analyses. 251252723Sdim virtual bool addILPOpts() { 252252723Sdim return false; 253252723Sdim } 254252723Sdim 255235633Sdim /// addPreRegAlloc - This method may be implemented by targets that want to 256235633Sdim /// run passes immediately before register allocation. This should return 257235633Sdim /// true if -print-machineinstrs should print after these passes. 258235633Sdim virtual bool addPreRegAlloc() { 259235633Sdim return false; 260235633Sdim } 261235633Sdim 262235633Sdim /// createTargetRegisterAllocator - Create the register allocator pass for 263235633Sdim /// this target at the current optimization level. 264235633Sdim virtual FunctionPass *createTargetRegisterAllocator(bool Optimized); 265235633Sdim 266235633Sdim /// addFastRegAlloc - Add the minimum set of target-independent passes that 267235633Sdim /// are required for fast register allocation. 268235633Sdim virtual void addFastRegAlloc(FunctionPass *RegAllocPass); 269235633Sdim 270235633Sdim /// addOptimizedRegAlloc - Add passes related to register allocation. 271235633Sdim /// LLVMTargetMachine provides standard regalloc passes for most targets. 272235633Sdim virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass); 273235633Sdim 274245431Sdim /// addPreRewrite - Add passes to the optimized register allocation pipeline 275245431Sdim /// after register allocation is complete, but before virtual registers are 276245431Sdim /// rewritten to physical registers. 277245431Sdim /// 278245431Sdim /// These passes must preserve VirtRegMap and LiveIntervals, and when running 279245431Sdim /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. 280245431Sdim /// When these passes run, VirtRegMap contains legal physreg assignments for 281245431Sdim /// all virtual registers. 282245431Sdim virtual bool addPreRewrite() { 283245431Sdim return false; 284245431Sdim } 285245431Sdim 286235633Sdim /// addPostRegAlloc - This method may be implemented by targets that want to 287235633Sdim /// run passes after register allocation pass pipeline but before 288235633Sdim /// prolog-epilog insertion. This should return true if -print-machineinstrs 289235633Sdim /// should print after these passes. 290235633Sdim virtual bool addPostRegAlloc() { 291235633Sdim return false; 292235633Sdim } 293235633Sdim 294235633Sdim /// Add passes that optimize machine instructions after register allocation. 295235633Sdim virtual void addMachineLateOptimization(); 296235633Sdim 297235633Sdim /// addPreSched2 - This method may be implemented by targets that want to 298235633Sdim /// run passes after prolog-epilog insertion and before the second instruction 299235633Sdim /// scheduling pass. This should return true if -print-machineinstrs should 300235633Sdim /// print after these passes. 301235633Sdim virtual bool addPreSched2() { 302235633Sdim return false; 303235633Sdim } 304235633Sdim 305252723Sdim /// addGCPasses - Add late codegen passes that analyze code for garbage 306252723Sdim /// collection. This should return true if GC info should be printed after 307252723Sdim /// these passes. 308252723Sdim virtual bool addGCPasses(); 309252723Sdim 310235633Sdim /// Add standard basic block placement passes. 311235633Sdim virtual void addBlockPlacement(); 312235633Sdim 313235633Sdim /// addPreEmitPass - This pass may be implemented by targets that want to run 314235633Sdim /// passes immediately before machine code is emitted. This should return 315235633Sdim /// true if -print-machineinstrs should print out the code after the passes. 316235633Sdim virtual bool addPreEmitPass() { 317235633Sdim return false; 318235633Sdim } 319235633Sdim 320235633Sdim /// Utilities for targets to add passes to the pass manager. 321235633Sdim /// 322235633Sdim 323235633Sdim /// Add a CodeGen pass at this point in the pipeline after checking overrides. 324245431Sdim /// Return the pass that was added, or zero if no pass was added. 325245431Sdim AnalysisID addPass(AnalysisID PassID); 326235633Sdim 327245431Sdim /// Add a pass to the PassManager if that pass is supposed to be run, as 328263509Sdim /// determined by the StartAfter and StopAfter options. Takes ownership of the 329263509Sdim /// pass. 330245431Sdim void addPass(Pass *P); 331245431Sdim 332235633Sdim /// addMachinePasses helper to create the target-selected or overriden 333235633Sdim /// regalloc pass. 334235633Sdim FunctionPass *createRegAllocPass(bool Optimized); 335235633Sdim 336235633Sdim /// printAndVerify - Add a pass to dump then verify the machine function, if 337235633Sdim /// those steps are enabled. 338235633Sdim /// 339245431Sdim void printAndVerify(const char *Banner); 340235633Sdim}; 341235633Sdim} // namespace llvm 342235633Sdim 343235633Sdim/// List of target independent CodeGen pass IDs. 344235633Sdimnamespace llvm { 345252723Sdim /// \brief Create a basic TargetTransformInfo analysis pass. 346252723Sdim /// 347252723Sdim /// This pass implements the target transform info analysis using the target 348252723Sdim /// independent information available to the LLVM code generator. 349252723Sdim ImmutablePass * 350263509Sdim createBasicTargetTransformInfoPass(const TargetMachine *TM); 351252723Sdim 352193323Sed /// createUnreachableBlockEliminationPass - The LLVM code generator does not 353193323Sed /// work well with unreachable basic blocks (what live ranges make sense for a 354193323Sed /// block that cannot be reached?). As such, a code generator should either 355212904Sdim /// not instruction select unreachable blocks, or run this pass as its 356193323Sed /// last LLVM modifying pass to clean up blocks that are not reachable from 357193323Sed /// the entry block. 358193323Sed FunctionPass *createUnreachableBlockEliminationPass(); 359193323Sed 360193323Sed /// MachineFunctionPrinter pass - This pass prints out the machine function to 361212904Sdim /// the given stream as a debugging tool. 362206124Srdivacky MachineFunctionPass * 363206124Srdivacky createMachineFunctionPrinterPass(raw_ostream &OS, 364206124Srdivacky const std::string &Banner =""); 365193323Sed 366235633Sdim /// MachineLoopInfo - This pass is a loop analysis pass. 367212904Sdim extern char &MachineLoopInfoID; 368193323Sed 369235633Sdim /// MachineDominators - This pass is a machine dominators analysis pass. 370212904Sdim extern char &MachineDominatorsID; 371193323Sed 372218893Sdim /// EdgeBundles analysis - Bundle machine CFG edges. 373218893Sdim extern char &EdgeBundlesID; 374218893Sdim 375235633Sdim /// LiveVariables pass - This pass computes the set of blocks in which each 376235633Sdim /// variable is life and sets machine operand kill flags. 377235633Sdim extern char &LiveVariablesID; 378235633Sdim 379235633Sdim /// PHIElimination - This pass eliminates machine instruction PHI nodes 380193323Sed /// by inserting copy instructions. This destroys SSA information, but is the 381193323Sed /// desired input for some register allocators. This pass is "required" by 382193323Sed /// these register allocator like this: AU.addRequiredID(PHIEliminationID); 383212904Sdim extern char &PHIEliminationID; 384212904Sdim 385245431Sdim /// LiveIntervals - This analysis keeps track of the live ranges of virtual 386245431Sdim /// and physical registers. 387245431Sdim extern char &LiveIntervalsID; 388245431Sdim 389218893Sdim /// LiveStacks pass. An analysis keeping track of the liveness of stack slots. 390218893Sdim extern char &LiveStacksID; 391218893Sdim 392235633Sdim /// TwoAddressInstruction - This pass reduces two-address instructions to 393193323Sed /// use two operands. This destroys SSA information but it is desired by 394193323Sed /// register allocators. 395212904Sdim extern char &TwoAddressInstructionPassID; 396193323Sed 397235633Sdim /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs. 398235633Sdim extern char &ProcessImplicitDefsID; 399226890Sdim 400235633Sdim /// RegisterCoalescer - This pass merges live ranges to eliminate copies. 401235633Sdim extern char &RegisterCoalescerID; 402235633Sdim 403235633Sdim /// MachineScheduler - This pass schedules machine instructions. 404235633Sdim extern char &MachineSchedulerID; 405235633Sdim 406218893Sdim /// SpillPlacement analysis. Suggest optimal placement of spill code between 407218893Sdim /// basic blocks. 408218893Sdim extern char &SpillPlacementID; 409218893Sdim 410245431Sdim /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as 411245431Sdim /// assigned in VirtRegMap. 412245431Sdim extern char &VirtRegRewriterID; 413245431Sdim 414235633Sdim /// UnreachableMachineBlockElimination - This pass removes unreachable 415193323Sed /// machine basic blocks. 416212904Sdim extern char &UnreachableMachineBlockElimID; 417193323Sed 418235633Sdim /// DeadMachineInstructionElim - This pass removes dead machine instructions. 419235633Sdim extern char &DeadMachineInstructionElimID; 420193323Sed 421207618Srdivacky /// FastRegisterAllocation Pass - This pass register allocates as fast as 422207618Srdivacky /// possible. It is best suited for debug code where live ranges are short. 423207618Srdivacky /// 424207618Srdivacky FunctionPass *createFastRegisterAllocator(); 425207618Srdivacky 426218893Sdim /// BasicRegisterAllocation Pass - This pass implements a degenerate global 427218893Sdim /// register allocator using the basic regalloc framework. 428218893Sdim /// 429218893Sdim FunctionPass *createBasicRegisterAllocator(); 430218893Sdim 431218893Sdim /// Greedy register allocation pass - This pass implements a global register 432218893Sdim /// allocator for optimized builds. 433218893Sdim /// 434218893Sdim FunctionPass *createGreedyRegisterAllocator(); 435218893Sdim 436193323Sed /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean 437193323Sed /// Quadratic Prograaming (PBQP) based register allocator. 438193323Sed /// 439218893Sdim FunctionPass *createDefaultPBQPRegisterAllocator(); 440193323Sed 441235633Sdim /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code, 442193323Sed /// and eliminates abstract frame references. 443235633Sdim extern char &PrologEpilogCodeInserterID; 444212904Sdim 445235633Sdim /// ExpandPostRAPseudos - This pass expands pseudo instructions after 446226890Sdim /// register allocation. 447235633Sdim extern char &ExpandPostRAPseudosID; 448193323Sed 449198396Srdivacky /// createPostRAScheduler - This pass performs post register allocation 450198396Srdivacky /// scheduling. 451235633Sdim extern char &PostRASchedulerID; 452193323Sed 453235633Sdim /// BranchFolding - This pass performs machine code CFG based 454193323Sed /// optimizations to delete branches to branches, eliminate branches to 455193323Sed /// successor blocks (creating fall throughs), and eliminating branches over 456193323Sed /// branches. 457235633Sdim extern char &BranchFolderPassID; 458193323Sed 459245431Sdim /// MachineFunctionPrinterPass - This pass prints out MachineInstr's. 460245431Sdim extern char &MachineFunctionPrinterPassID; 461245431Sdim 462235633Sdim /// TailDuplicate - Duplicate blocks with unconditional branches 463199989Srdivacky /// into tails of their predecessors. 464235633Sdim extern char &TailDuplicateID; 465199989Srdivacky 466245431Sdim /// MachineTraceMetrics - This pass computes critical path and CPU resource 467245431Sdim /// usage in an ensemble of traces. 468245431Sdim extern char &MachineTraceMetricsID; 469245431Sdim 470245431Sdim /// EarlyIfConverter - This pass performs if-conversion on SSA form by 471245431Sdim /// inserting cmov instructions. 472245431Sdim extern char &EarlyIfConverterID; 473245431Sdim 474245431Sdim /// StackSlotColoring - This pass performs stack coloring and merging. 475245431Sdim /// It merges disjoint allocas to reduce the stack size. 476245431Sdim extern char &StackColoringID; 477245431Sdim 478235633Sdim /// IfConverter - This pass performs machine code if conversion. 479235633Sdim extern char &IfConverterID; 480193323Sed 481235633Sdim /// MachineBlockPlacement - This pass places basic blocks based on branch 482235633Sdim /// probabilities. 483235633Sdim extern char &MachineBlockPlacementID; 484235633Sdim 485235633Sdim /// MachineBlockPlacementStats - This pass collects statistics about the 486235633Sdim /// basic block placement using branch probabilities and block frequency 487235633Sdim /// information. 488235633Sdim extern char &MachineBlockPlacementStatsID; 489235633Sdim 490235633Sdim /// GCLowering Pass - Performs target-independent LLVM IR transformations for 491235633Sdim /// highly portable strategies. 492235633Sdim /// 493193323Sed FunctionPass *createGCLoweringPass(); 494212904Sdim 495235633Sdim /// GCMachineCodeAnalysis - Target-independent pass to mark safe points 496235633Sdim /// in machine code. Must be added very late during code generation, just 497235633Sdim /// prior to output, and importantly after all CFG transformations (such as 498235633Sdim /// branch folding). 499235633Sdim extern char &GCMachineCodeAnalysisID; 500212904Sdim 501193323Sed /// Creates a pass to print GC metadata. 502212904Sdim /// 503198090Srdivacky FunctionPass *createGCInfoPrinter(raw_ostream &OS); 504212904Sdim 505235633Sdim /// MachineCSE - This pass performs global CSE on machine instructions. 506235633Sdim extern char &MachineCSEID; 507204642Srdivacky 508235633Sdim /// MachineLICM - This pass performs LICM on machine instructions. 509235633Sdim extern char &MachineLICMID; 510193323Sed 511235633Sdim /// MachineSinking - This pass performs sinking on machine instructions. 512235633Sdim extern char &MachineSinkingID; 513193323Sed 514235633Sdim /// MachineCopyPropagation - This pass performs copy propagation on 515235633Sdim /// machine instructions. 516235633Sdim extern char &MachineCopyPropagationID; 517235633Sdim 518235633Sdim /// PeepholeOptimizer - This pass performs peephole optimizations - 519212904Sdim /// like extension and comparison eliminations. 520235633Sdim extern char &PeepholeOptimizerID; 521202375Srdivacky 522235633Sdim /// OptimizePHIs - This pass optimizes machine instruction PHIs 523203954Srdivacky /// to take advantage of opportunities created during DAG legalization. 524235633Sdim extern char &OptimizePHIsID; 525203954Srdivacky 526235633Sdim /// StackSlotColoring - This pass performs stack slot coloring. 527235633Sdim extern char &StackSlotColoringID; 528193323Sed 529193323Sed /// createStackProtectorPass - This pass adds stack protectors to functions. 530235633Sdim /// 531263509Sdim FunctionPass *createStackProtectorPass(const TargetMachine *TM); 532193323Sed 533193323Sed /// createMachineVerifierPass - This pass verifies cenerated machine code 534193323Sed /// instructions for correctness. 535235633Sdim /// 536218893Sdim FunctionPass *createMachineVerifierPass(const char *Banner = 0); 537193323Sed 538193323Sed /// createDwarfEHPass - This pass mulches exception handling code into a form 539193323Sed /// adapted to code generation. Required if using dwarf exception handling. 540263509Sdim FunctionPass *createDwarfEHPass(const TargetMachine *TM); 541193323Sed 542235633Sdim /// createSjLjEHPreparePass - This pass adapts exception handling code to use 543198090Srdivacky /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow. 544235633Sdim /// 545263509Sdim FunctionPass *createSjLjEHPreparePass(const TargetMachine *TM); 546198090Srdivacky 547235633Sdim /// LocalStackSlotAllocation - This pass assigns local frame indices to stack 548235633Sdim /// slots relative to one another and allocates base registers to access them 549235633Sdim /// when it is estimated by the target to be out of range of normal frame 550235633Sdim /// pointer or stack pointer index addressing. 551235633Sdim extern char &LocalStackSlotAllocationID; 552212904Sdim 553235633Sdim /// ExpandISelPseudos - This pass expands pseudo-instructions. 554235633Sdim extern char &ExpandISelPseudosID; 555218893Sdim 556226890Sdim /// createExecutionDependencyFixPass - This pass fixes execution time 557226890Sdim /// problems with dependent instructions, such as switching execution 558226890Sdim /// domains to match. 559226890Sdim /// 560226890Sdim /// The pass will examine instructions using and defining registers in RC. 561226890Sdim /// 562226890Sdim FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC); 563226890Sdim 564235633Sdim /// UnpackMachineBundles - This pass unpack machine instruction bundles. 565235633Sdim extern char &UnpackMachineBundlesID; 566235633Sdim 567235633Sdim /// FinalizeMachineBundles - This pass finalize machine instruction 568235633Sdim /// bundles (created earlier, e.g. during pre-RA scheduling). 569235633Sdim extern char &FinalizeMachineBundlesID; 570235633Sdim 571193323Sed} // End llvm namespace 572193323Sed 573193323Sed#endif 574