rs6000-tdep.c revision 161537
1105197Ssam/* Target-dependent code for GDB, the GNU debugger. 2105197Ssam 3105197Ssam Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 4139823Simp 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software 5105197Ssam Foundation, Inc. 6105197Ssam 7105197Ssam This file is part of GDB. 8105197Ssam 9105197Ssam This program is free software; you can redistribute it and/or modify 10105197Ssam it under the terms of the GNU General Public License as published by 11105197Ssam the Free Software Foundation; either version 2 of the License, or 12105197Ssam (at your option) any later version. 13105197Ssam 14105197Ssam This program is distributed in the hope that it will be useful, 15105197Ssam but WITHOUT ANY WARRANTY; without even the implied warranty of 16105197Ssam MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17105197Ssam GNU General Public License for more details. 18105197Ssam 19105197Ssam You should have received a copy of the GNU General Public License 20105197Ssam along with this program; if not, write to the Free Software 21105197Ssam Foundation, Inc., 59 Temple Place - Suite 330, 22105197Ssam Boston, MA 02111-1307, USA. */ 23105197Ssam 24105197Ssam#include "defs.h" 25105197Ssam#include "frame.h" 26105197Ssam#include "inferior.h" 27105197Ssam#include "symtab.h" 28105197Ssam#include "target.h" 29105197Ssam#include "gdbcore.h" 30105197Ssam#include "gdbcmd.h" 31105197Ssam#include "objfiles.h" 32105197Ssam#include "arch-utils.h" 33105197Ssam#include "regcache.h" 34105197Ssam#include "doublest.h" 35105197Ssam#include "value.h" 36105197Ssam#include "parser-defs.h" 37105197Ssam#include "osabi.h" 38105197Ssam 39105197Ssam#include "libbfd.h" /* for bfd_default_set_arch_mach */ 40105197Ssam#include "coff/internal.h" /* for libcoff.h */ 41105197Ssam#include "libcoff.h" /* for xcoff_data */ 42105197Ssam#include "coff/xcoff.h" 43105197Ssam#include "libxcoff.h" 44105197Ssam 45119643Ssam#include "elf-bfd.h" 46119643Ssam 47105197Ssam#include "solib-svr4.h" 48105197Ssam#include "ppc-tdep.h" 49105197Ssam 50105197Ssam#include "gdb_assert.h" 51105197Ssam#include "dis-asm.h" 52105197Ssam 53105197Ssam/* If the kernel has to deliver a signal, it pushes a sigcontext 54105197Ssam structure on the stack and then calls the signal handler, passing 55105197Ssam the address of the sigcontext in an argument register. Usually 56105197Ssam the signal handler doesn't save this register, so we have to 57158767Spjd access the sigcontext structure via an offset from the signal handler 58105197Ssam frame. 59105197Ssam The following constants were determined by experimentation on AIX 3.2. */ 60105197Ssam#define SIG_FRAME_PC_OFFSET 96 61105197Ssam#define SIG_FRAME_LR_OFFSET 108 62105197Ssam#define SIG_FRAME_FP_OFFSET 284 63105197Ssam 64105197Ssam/* To be used by skip_prologue. */ 65105197Ssam 66105197Ssamstruct rs6000_framedata 67105197Ssam { 68105197Ssam int offset; /* total size of frame --- the distance 69105197Ssam by which we decrement sp to allocate 70105197Ssam the frame */ 71105197Ssam int saved_gpr; /* smallest # of saved gpr */ 72105197Ssam int saved_fpr; /* smallest # of saved fpr */ 73105197Ssam int saved_vr; /* smallest # of saved vr */ 74105197Ssam int saved_ev; /* smallest # of saved ev */ 75105197Ssam int alloca_reg; /* alloca register number (frame ptr) */ 76105197Ssam char frameless; /* true if frameless functions. */ 77105197Ssam char nosavedpc; /* true if pc not saved. */ 78105197Ssam int gpr_offset; /* offset of saved gprs from prev sp */ 79105197Ssam int fpr_offset; /* offset of saved fprs from prev sp */ 80105197Ssam int vr_offset; /* offset of saved vrs from prev sp */ 81105197Ssam int ev_offset; /* offset of saved evs from prev sp */ 82105197Ssam int lr_offset; /* offset of saved lr */ 83105197Ssam int cr_offset; /* offset of saved cr */ 84105197Ssam int vrsave_offset; /* offset of saved vrsave register */ 85105197Ssam }; 86105197Ssam 87105197Ssam/* Description of a single register. */ 88105197Ssam 89105197Ssamstruct reg 90105197Ssam { 91105197Ssam char *name; /* name of register */ 92105197Ssam unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */ 93105197Ssam unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */ 94105197Ssam unsigned char fpr; /* whether register is floating-point */ 95105197Ssam unsigned char pseudo; /* whether register is pseudo */ 96105197Ssam }; 97105197Ssam 98105197Ssam/* Breakpoint shadows for the single step instructions will be kept here. */ 99105197Ssam 100105197Ssamstatic struct sstep_breaks 101105197Ssam { 102105197Ssam /* Address, or 0 if this is not in use. */ 103105197Ssam CORE_ADDR address; 104105197Ssam /* Shadow contents. */ 105105197Ssam char data[4]; 106105197Ssam } 107105197SsamstepBreaks[2]; 108105197Ssam 109105197Ssam/* Hook for determining the TOC address when calling functions in the 110105197Ssam inferior under AIX. The initialization code in rs6000-nat.c sets 111105197Ssam this hook to point to find_toc_address. */ 112105197Ssam 113105197SsamCORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; 114105197Ssam 115105197Ssam/* Hook to set the current architecture when starting a child process. 116105197Ssam rs6000-nat.c sets this. */ 117105197Ssam 118105197Ssamvoid (*rs6000_set_host_arch_hook) (int) = NULL; 119105197Ssam 120105197Ssam/* Static function prototypes */ 121105197Ssam 122105197Ssamstatic CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc, 123125876Sguido CORE_ADDR safety); 124105197Ssamstatic CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, 125105197Ssam struct rs6000_framedata *); 126105197Ssamstatic void frame_get_saved_regs (struct frame_info * fi, 127105197Ssam struct rs6000_framedata * fdatap); 128119643Ssamstatic CORE_ADDR frame_initial_stack_address (struct frame_info *); 129120585Ssam 130120585Ssam/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ 131120585Ssamint 132120585Ssamaltivec_register_p (int regno) 133120585Ssam{ 134120585Ssam struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 135120585Ssam if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) 136120585Ssam return 0; 137105197Ssam else 138119643Ssam return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); 139120585Ssam} 140120585Ssam 141120585Ssam/* Use the architectures FP registers? */ 142120585Ssamint 143120585Ssamppc_floating_point_unit_p (struct gdbarch *gdbarch) 144120585Ssam{ 145120585Ssam const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); 146120585Ssam if (info->arch == bfd_arch_powerpc) 147119643Ssam return (info->mach != bfd_mach_ppc_e500); 148105197Ssam if (info->arch == bfd_arch_rs6000) 149119643Ssam return 1; 150120585Ssam return 0; 151120585Ssam} 152120585Ssam 153120585Ssam/* Read a LEN-byte address from debugged memory address MEMADDR. */ 154120585Ssam 155120585Ssamstatic CORE_ADDR 156120585Ssamread_memory_addr (CORE_ADDR memaddr, int len) 157105197Ssam{ 158119643Ssam return read_memory_unsigned_integer (memaddr, len); 159120585Ssam} 160120585Ssam 161120585Ssamstatic CORE_ADDR 162120585Ssamrs6000_skip_prologue (CORE_ADDR pc) 163120585Ssam{ 164120585Ssam struct rs6000_framedata frame; 165120585Ssam pc = skip_prologue (pc, 0, &frame); 166105197Ssam return pc; 167119643Ssam} 168120585Ssam 169120585Ssam 170120585Ssam/* Fill in fi->saved_regs */ 171120585Ssam 172120585Ssamstruct frame_extra_info 173120585Ssam{ 174120585Ssam /* Functions calling alloca() change the value of the stack 175105197Ssam pointer. We need to use initial stack pointer (which is saved in 176105197Ssam r31 by gcc) in such cases. If a compiler emits traceback table, 177128856Ssam then we should use the alloca register specified in traceback 178105197Ssam table. FIXME. */ 179105197Ssam CORE_ADDR initial_sp; /* initial stack pointer. */ 180128856Ssam}; 181128856Ssam 182128856Ssamvoid 183105197Ssamrs6000_init_extra_frame_info (int fromleaf, struct frame_info *fi) 184105197Ssam{ 185105197Ssam struct frame_extra_info *extra_info = 186105197Ssam frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); 187105197Ssam extra_info->initial_sp = 0; 188105197Ssam if (get_next_frame (fi) != NULL 189105197Ssam && get_frame_pc (fi) < TEXT_SEGMENT_BASE) 190105197Ssam /* We're in get_prev_frame */ 191105197Ssam /* and this is a special signal frame. */ 192105197Ssam /* (fi->pc will be some low address in the kernel, */ 193105197Ssam /* to which the signal handler returns). */ 194105197Ssam deprecated_set_frame_type (fi, SIGTRAMP_FRAME); 195105197Ssam} 196105197Ssam 197105197Ssam/* Put here the code to store, into a struct frame_saved_regs, 198105197Ssam the addresses of the saved registers of frame described by FRAME_INFO. 199105197Ssam This includes special registers such as pc and fp saved in special 200105197Ssam ways in the stack frame. sp is even more special: 201105197Ssam the address we return for it IS the sp for the next frame. */ 202105197Ssam 203105197Ssam/* In this implementation for RS/6000, we do *not* save sp. I am 204105197Ssam not sure if it will be needed. The following function takes care of gpr's 205105197Ssam and fpr's only. */ 206105197Ssam 207105197Ssamvoid 208105197Ssamrs6000_frame_init_saved_regs (struct frame_info *fi) 209105197Ssam{ 210105197Ssam frame_get_saved_regs (fi, NULL); 211105197Ssam} 212105197Ssam 213105197Ssamstatic CORE_ADDR 214105197Ssamrs6000_frame_args_address (struct frame_info *fi) 215105197Ssam{ 216105197Ssam struct frame_extra_info *extra_info = get_frame_extra_info (fi); 217105197Ssam if (extra_info->initial_sp != 0) 218105197Ssam return extra_info->initial_sp; 219105197Ssam else 220105197Ssam return frame_initial_stack_address (fi); 221105197Ssam} 222105197Ssam 223105197Ssam/* Immediately after a function call, return the saved pc. 224105197Ssam Can't go through the frames for this because on some machines 225105197Ssam the new frame is not set up until the new function executes 226105197Ssam some instructions. */ 227105197Ssam 228105197Ssamstatic CORE_ADDR 229105197Ssamrs6000_saved_pc_after_call (struct frame_info *fi) 230105197Ssam{ 231105197Ssam return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); 232105197Ssam} 233105197Ssam 234105197Ssam/* Get the ith function argument for the current function. */ 235105197Ssamstatic CORE_ADDR 236105197Ssamrs6000_fetch_pointer_argument (struct frame_info *frame, int argi, 237105197Ssam struct type *type) 238105197Ssam{ 239105197Ssam CORE_ADDR addr; 240105197Ssam get_frame_register (frame, 3 + argi, &addr); 241105197Ssam return addr; 242105197Ssam} 243105197Ssam 244105197Ssam/* Calculate the destination of a branch/jump. Return -1 if not a branch. */ 245105197Ssam 246105197Ssamstatic CORE_ADDR 247105197Ssambranch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety) 248105197Ssam{ 249105197Ssam CORE_ADDR dest; 250105197Ssam int immediate; 251105197Ssam int absolute; 252105197Ssam int ext_op; 253105197Ssam 254105197Ssam absolute = (int) ((instr >> 1) & 1); 255105197Ssam 256105197Ssam switch (opcode) 257105197Ssam { 258105197Ssam case 18: 259105197Ssam immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ 260105197Ssam if (absolute) 261105197Ssam dest = immediate; 262105197Ssam else 263105197Ssam dest = pc + immediate; 264105197Ssam break; 265105197Ssam 266105197Ssam case 16: 267105197Ssam immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ 268105197Ssam if (absolute) 269105197Ssam dest = immediate; 270105197Ssam else 271105197Ssam dest = pc + immediate; 272105197Ssam break; 273105197Ssam 274105197Ssam case 19: 275105197Ssam ext_op = (instr >> 1) & 0x3ff; 276105197Ssam 277105197Ssam if (ext_op == 16) /* br conditional register */ 278105197Ssam { 279105197Ssam dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; 280105197Ssam 281105197Ssam /* If we are about to return from a signal handler, dest is 282105197Ssam something like 0x3c90. The current frame is a signal handler 283105197Ssam caller frame, upon completion of the sigreturn system call 284105197Ssam execution will return to the saved PC in the frame. */ 285105197Ssam if (dest < TEXT_SEGMENT_BASE) 286105197Ssam { 287105197Ssam struct frame_info *fi; 288105197Ssam 289125876Sguido fi = get_current_frame (); 290125876Sguido if (fi != NULL) 291105197Ssam dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, 292105197Ssam gdbarch_tdep (current_gdbarch)->wordsize); 293105197Ssam } 294105197Ssam } 295105197Ssam 296105197Ssam else if (ext_op == 528) /* br cond to count reg */ 297105197Ssam { 298105197Ssam dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3; 299105197Ssam 300105197Ssam /* If we are about to execute a system call, dest is something 301105197Ssam like 0x22fc or 0x3b00. Upon completion the system call 302105197Ssam will return to the address in the link register. */ 303105197Ssam if (dest < TEXT_SEGMENT_BASE) 304105197Ssam dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; 305105197Ssam } 306105197Ssam else 307105197Ssam return -1; 308105197Ssam break; 309105197Ssam 310105197Ssam default: 311105197Ssam return -1; 312105197Ssam } 313105197Ssam return (dest < TEXT_SEGMENT_BASE) ? safety : dest; 314105197Ssam} 315105197Ssam 316105197Ssam 317105197Ssam/* Sequence of bytes for breakpoint instruction. */ 318105197Ssam 319105197Ssamconst static unsigned char * 320105197Ssamrs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) 321105197Ssam{ 322105197Ssam static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; 323105197Ssam static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; 324119643Ssam *bp_size = 4; 325119643Ssam if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 326119643Ssam return big_breakpoint; 327119643Ssam else 328119643Ssam return little_breakpoint; 329119643Ssam} 330119643Ssam 331105197Ssam 332105197Ssam/* AIX does not support PT_STEP. Simulate it. */ 333105197Ssam 334105197Ssamvoid 335105197Ssamrs6000_software_single_step (enum target_signal signal, 336105197Ssam int insert_breakpoints_p) 337105197Ssam{ 338105197Ssam CORE_ADDR dummy; 339105197Ssam int breakp_sz; 340105197Ssam const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); 341105197Ssam int ii, insn; 342105197Ssam CORE_ADDR loc; 343105197Ssam CORE_ADDR breaks[2]; 344105197Ssam int opcode; 345105197Ssam 346105197Ssam if (insert_breakpoints_p) 347105197Ssam { 348105197Ssam 349105197Ssam loc = read_pc (); 350105197Ssam 351105197Ssam insn = read_memory_integer (loc, 4); 352105197Ssam 353105197Ssam breaks[0] = loc + breakp_sz; 354105197Ssam opcode = insn >> 26; 355105197Ssam breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); 356105197Ssam 357105197Ssam /* Don't put two breakpoints on the same address. */ 358105197Ssam if (breaks[1] == breaks[0]) 359105197Ssam breaks[1] = -1; 360105197Ssam 361105197Ssam stepBreaks[1].address = 0; 362105197Ssam 363105197Ssam for (ii = 0; ii < 2; ++ii) 364105197Ssam { 365105197Ssam 366105197Ssam /* ignore invalid breakpoint. */ 367105197Ssam if (breaks[ii] == -1) 368105197Ssam continue; 369105197Ssam target_insert_breakpoint (breaks[ii], stepBreaks[ii].data); 370105197Ssam stepBreaks[ii].address = breaks[ii]; 371105197Ssam } 372105197Ssam 373105197Ssam } 374105197Ssam else 375105197Ssam { 376105197Ssam 377105197Ssam /* remove step breakpoints. */ 378119643Ssam for (ii = 0; ii < 2; ++ii) 379105197Ssam if (stepBreaks[ii].address != 0) 380105197Ssam target_remove_breakpoint (stepBreaks[ii].address, 381105197Ssam stepBreaks[ii].data); 382105197Ssam } 383105197Ssam errno = 0; /* FIXME, don't ignore errors! */ 384105197Ssam /* What errors? {read,write}_memory call error(). */ 385105197Ssam} 386105197Ssam 387105197Ssam 388105197Ssam/* return pc value after skipping a function prologue and also return 389105197Ssam information about a function frame. 390105197Ssam 391105197Ssam in struct rs6000_framedata fdata: 392105197Ssam - frameless is TRUE, if function does not have a frame. 393105197Ssam - nosavedpc is TRUE, if function does not save %pc value in its frame. 394105197Ssam - offset is the initial size of this stack frame --- the amount by 395105197Ssam which we decrement the sp to allocate the frame. 396105197Ssam - saved_gpr is the number of the first saved gpr. 397105197Ssam - saved_fpr is the number of the first saved fpr. 398105197Ssam - saved_vr is the number of the first saved vr. 399105197Ssam - saved_ev is the number of the first saved ev. 400105197Ssam - alloca_reg is the number of the register used for alloca() handling. 401105197Ssam Otherwise -1. 402105197Ssam - gpr_offset is the offset of the first saved gpr from the previous frame. 403105197Ssam - fpr_offset is the offset of the first saved fpr from the previous frame. 404105197Ssam - vr_offset is the offset of the first saved vr from the previous frame. 405105197Ssam - ev_offset is the offset of the first saved ev from the previous frame. 406105197Ssam - lr_offset is the offset of the saved lr 407105197Ssam - cr_offset is the offset of the saved cr 408105197Ssam - vrsave_offset is the offset of the saved vrsave register 409105197Ssam */ 410105197Ssam 411105197Ssam#define SIGNED_SHORT(x) \ 412105197Ssam ((sizeof (short) == 2) \ 413105197Ssam ? ((int)(short)(x)) \ 414105197Ssam : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) 415105197Ssam 416105197Ssam#define GET_SRC_REG(x) (((x) >> 21) & 0x1f) 417105197Ssam 418105197Ssam/* Limit the number of skipped non-prologue instructions, as the examining 419105197Ssam of the prologue is expensive. */ 420105197Ssamstatic int max_skip_non_prologue_insns = 10; 421105197Ssam 422105197Ssam/* Given PC representing the starting address of a function, and 423105197Ssam LIM_PC which is the (sloppy) limit to which to scan when looking 424157123Sgnn for a prologue, attempt to further refine this limit by using 425157123Sgnn the line data in the symbol table. If successful, a better guess 426157123Sgnn on where the prologue ends is returned, otherwise the previous 427157123Sgnn value of lim_pc is returned. */ 428105197Ssam 429105197Ssam/* FIXME: cagney/2004-02-14: This function and logic have largely been 430105197Ssam superseded by skip_prologue_using_sal. */ 431105197Ssam 432105197Ssamstatic CORE_ADDR 433105197Ssamrefine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc) 434105197Ssam{ 435105197Ssam struct symtab_and_line prologue_sal; 436105197Ssam 437105197Ssam prologue_sal = find_pc_line (pc, 0); 438105197Ssam if (prologue_sal.line != 0) 439105197Ssam { 440105197Ssam int i; 441105197Ssam CORE_ADDR addr = prologue_sal.end; 442105197Ssam 443105197Ssam /* Handle the case in which compiler's optimizer/scheduler 444105197Ssam has moved instructions into the prologue. We scan ahead 445105197Ssam in the function looking for address ranges whose corresponding 446105197Ssam line number is less than or equal to the first one that we 447105197Ssam found for the function. (It can be less than when the 448105197Ssam scheduler puts a body instruction before the first prologue 449105197Ssam instruction.) */ 450105197Ssam for (i = 2 * max_skip_non_prologue_insns; 451105197Ssam i > 0 && (lim_pc == 0 || addr < lim_pc); 452105197Ssam i--) 453105197Ssam { 454105197Ssam struct symtab_and_line sal; 455105197Ssam 456105197Ssam sal = find_pc_line (addr, 0); 457105197Ssam if (sal.line == 0) 458105197Ssam break; 459105197Ssam if (sal.line <= prologue_sal.line 460105197Ssam && sal.symtab == prologue_sal.symtab) 461105197Ssam { 462105197Ssam prologue_sal = sal; 463105197Ssam } 464105197Ssam addr = sal.end; 465105197Ssam } 466105197Ssam 467105197Ssam if (lim_pc == 0 || prologue_sal.end < lim_pc) 468105197Ssam lim_pc = prologue_sal.end; 469105197Ssam } 470105197Ssam return lim_pc; 471105197Ssam} 472105197Ssam 473105197Ssam 474105197Ssamstatic CORE_ADDR 475105197Ssamskip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) 476105197Ssam{ 477105197Ssam CORE_ADDR orig_pc = pc; 478105197Ssam CORE_ADDR last_prologue_pc = pc; 479105197Ssam CORE_ADDR li_found_pc = 0; 480105197Ssam char buf[4]; 481105197Ssam unsigned long op; 482105197Ssam long offset = 0; 483105197Ssam long vr_saved_offset = 0; 484105197Ssam int lr_reg = -1; 485105197Ssam int cr_reg = -1; 486105197Ssam int vr_reg = -1; 487105197Ssam int ev_reg = -1; 488105197Ssam long ev_offset = 0; 489105197Ssam int vrsave_reg = -1; 490105197Ssam int reg; 491105197Ssam int framep = 0; 492105197Ssam int minimal_toc_loaded = 0; 493105197Ssam int prev_insn_was_prologue_insn = 1; 494105197Ssam int num_skip_non_prologue_insns = 0; 495157123Sgnn const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); 496157123Sgnn struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 497157123Sgnn 498157123Sgnn /* Attempt to find the end of the prologue when no limit is specified. 499105197Ssam Note that refine_prologue_limit() has been written so that it may 500105197Ssam be used to "refine" the limits of non-zero PC values too, but this 501105197Ssam is only safe if we 1) trust the line information provided by the 502105197Ssam compiler and 2) iterate enough to actually find the end of the 503105197Ssam prologue. 504105197Ssam 505105197Ssam It may become a good idea at some point (for both performance and 506158767Spjd accuracy) to unconditionally call refine_prologue_limit(). But, 507158767Spjd until we can make a clear determination that this is beneficial, 508158767Spjd we'll play it safe and only use it to obtain a limit when none 509105197Ssam has been specified. */ 510158767Spjd if (lim_pc == 0) 511158767Spjd lim_pc = refine_prologue_limit (pc, lim_pc); 512158767Spjd 513158767Spjd memset (fdata, 0, sizeof (struct rs6000_framedata)); 514158767Spjd fdata->saved_gpr = -1; 515158767Spjd fdata->saved_fpr = -1; 516158767Spjd fdata->saved_vr = -1; 517158767Spjd fdata->saved_ev = -1; 518158767Spjd fdata->alloca_reg = -1; 519158767Spjd fdata->frameless = 1; 520158767Spjd fdata->nosavedpc = 1; 521158767Spjd 522158767Spjd for (;; pc += 4) 523158767Spjd { 524158767Spjd /* Sometimes it isn't clear if an instruction is a prologue 525158767Spjd instruction or not. When we encounter one of these ambiguous 526158767Spjd cases, we'll set prev_insn_was_prologue_insn to 0 (false). 527105197Ssam Otherwise, we'll assume that it really is a prologue instruction. */ 528105197Ssam if (prev_insn_was_prologue_insn) 529120585Ssam last_prologue_pc = pc; 530105197Ssam 531105197Ssam /* Stop scanning if we've hit the limit. */ 532120585Ssam if (lim_pc != 0 && pc >= lim_pc) 533105197Ssam break; 534105197Ssam 535135947Ssam prev_insn_was_prologue_insn = 1; 536105197Ssam 537105197Ssam /* Fetch the instruction and convert it to an integer. */ 538135947Ssam if (target_read_memory (pc, buf, 4)) 539135947Ssam break; 540135947Ssam op = extract_signed_integer (buf, 4); 541135947Ssam 542135947Ssam if ((op & 0xfc1fffff) == 0x7c0802a6) 543135947Ssam { /* mflr Rx */ 544135947Ssam lr_reg = (op & 0x03e00000); 545135947Ssam continue; 546135947Ssam 547135947Ssam } 548135947Ssam else if ((op & 0xfc1fffff) == 0x7c000026) 549105197Ssam { /* mfcr Rx */ 550105197Ssam cr_reg = (op & 0x03e00000); 551105197Ssam continue; 552105197Ssam 553105197Ssam } 554105197Ssam else if ((op & 0xfc1f0000) == 0xd8010000) 555105197Ssam { /* stfd Rx,NUM(r1) */ 556105197Ssam reg = GET_SRC_REG (op); 557105197Ssam if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) 558105197Ssam { 559105197Ssam fdata->saved_fpr = reg; 560105197Ssam fdata->fpr_offset = SIGNED_SHORT (op) + offset; 561105197Ssam } 562105197Ssam continue; 563105197Ssam 564105197Ssam } 565105197Ssam else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ 566105197Ssam (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ 567105197Ssam (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ 568105197Ssam (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ 569105197Ssam { 570105197Ssam 571105197Ssam reg = GET_SRC_REG (op); 572120585Ssam if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) 573120585Ssam { 574120585Ssam fdata->saved_gpr = reg; 575105197Ssam if ((op & 0xfc1f0003) == 0xf8010000) 576105197Ssam op &= ~3UL; 577120585Ssam fdata->gpr_offset = SIGNED_SHORT (op) + offset; 578105197Ssam } 579105197Ssam continue; 580105197Ssam 581105197Ssam } 582105197Ssam else if ((op & 0xffff0000) == 0x60000000) 583105197Ssam { 584120585Ssam /* nop */ 585105197Ssam /* Allow nops in the prologue, but do not consider them to 586105197Ssam be part of the prologue unless followed by other prologue 587105197Ssam instructions. */ 588105197Ssam prev_insn_was_prologue_insn = 0; 589105197Ssam continue; 590105197Ssam 591105197Ssam } 592105197Ssam else if ((op & 0xffff0000) == 0x3c000000) 593105197Ssam { /* addis 0,0,NUM, used 594105197Ssam for >= 32k frames */ 595105197Ssam fdata->offset = (op & 0x0000ffff) << 16; 596105197Ssam fdata->frameless = 0; 597105197Ssam continue; 598105197Ssam 599120585Ssam } 600105197Ssam else if ((op & 0xffff0000) == 0x60000000) 601105197Ssam { /* ori 0,0,NUM, 2nd ha 602105197Ssam lf of >= 32k frames */ 603105197Ssam fdata->offset |= (op & 0x0000ffff); 604105197Ssam fdata->frameless = 0; 605120585Ssam continue; 606105197Ssam 607105197Ssam } 608120585Ssam else if (lr_reg != -1 && 609105197Ssam /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ 610105197Ssam (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || 611105197Ssam /* stw Rx, NUM(r1) */ 612105197Ssam ((op & 0xffff0000) == (lr_reg | 0x90010000)) || 613105197Ssam /* stwu Rx, NUM(r1) */ 614105197Ssam ((op & 0xffff0000) == (lr_reg | 0x94010000)))) 615105197Ssam { /* where Rx == lr */ 616105197Ssam fdata->lr_offset = offset; 617105197Ssam fdata->nosavedpc = 0; 618105197Ssam lr_reg = 0; 619105197Ssam if ((op & 0xfc000003) == 0xf8000000 || /* std */ 620105197Ssam (op & 0xfc000000) == 0x90000000) /* stw */ 621105197Ssam { 622105197Ssam /* Does not update r1, so add displacement to lr_offset. */ 623105197Ssam fdata->lr_offset += SIGNED_SHORT (op); 624105197Ssam } 625105197Ssam continue; 626105197Ssam 627105197Ssam } 628120585Ssam else if (cr_reg != -1 && 629120585Ssam /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ 630120585Ssam (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || 631105197Ssam /* stw Rx, NUM(r1) */ 632105197Ssam ((op & 0xffff0000) == (cr_reg | 0x90010000)) || 633120585Ssam /* stwu Rx, NUM(r1) */ 634105197Ssam ((op & 0xffff0000) == (cr_reg | 0x94010000)))) 635105197Ssam { /* where Rx == cr */ 636105197Ssam fdata->cr_offset = offset; 637105197Ssam cr_reg = 0; 638105197Ssam if ((op & 0xfc000003) == 0xf8000000 || 639105197Ssam (op & 0xfc000000) == 0x90000000) 640105197Ssam { 641120585Ssam /* Does not update r1, so add displacement to cr_offset. */ 642105197Ssam fdata->cr_offset += SIGNED_SHORT (op); 643105197Ssam } 644105197Ssam continue; 645105197Ssam 646105197Ssam } 647105197Ssam else if (op == 0x48000005) 648105197Ssam { /* bl .+4 used in 649105197Ssam -mrelocatable */ 650105197Ssam continue; 651105197Ssam 652105197Ssam } 653105197Ssam else if (op == 0x48000004) 654105197Ssam { /* b .+4 (xlc) */ 655105197Ssam break; 656105197Ssam 657105197Ssam } 658105197Ssam else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used 659105197Ssam in V.4 -mminimal-toc */ 660105197Ssam (op & 0xffff0000) == 0x3bde0000) 661105197Ssam { /* addi 30,30,foo@l */ 662120585Ssam continue; 663105197Ssam 664105197Ssam } 665105197Ssam else if ((op & 0xfc000001) == 0x48000001) 666105197Ssam { /* bl foo, 667105197Ssam to save fprs??? */ 668120585Ssam 669105197Ssam fdata->frameless = 0; 670105197Ssam /* Don't skip over the subroutine call if it is not within 671120585Ssam the first three instructions of the prologue. */ 672105197Ssam if ((pc - orig_pc) > 8) 673105197Ssam break; 674105197Ssam 675105197Ssam op = read_memory_integer (pc + 4, 4); 676105197Ssam 677105197Ssam /* At this point, make sure this is not a trampoline 678105197Ssam function (a function that simply calls another functions, 679105197Ssam and nothing else). If the next is not a nop, this branch 680105197Ssam was part of the function prologue. */ 681105197Ssam 682105197Ssam if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ 683105197Ssam break; /* don't skip over 684105197Ssam this branch */ 685105197Ssam continue; 686105197Ssam 687105197Ssam } 688105197Ssam /* update stack pointer */ 689105197Ssam else if ((op & 0xfc1f0000) == 0x94010000) 690105197Ssam { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ 691105197Ssam fdata->frameless = 0; 692105197Ssam fdata->offset = SIGNED_SHORT (op); 693120585Ssam offset = fdata->offset; 694105197Ssam continue; 695105197Ssam } 696120585Ssam else if ((op & 0xfc1f016a) == 0x7c01016e) 697120585Ssam { /* stwux rX,r1,rY */ 698105197Ssam /* no way to figure out what r1 is going to be */ 699105197Ssam fdata->frameless = 0; 700105197Ssam offset = fdata->offset; 701105197Ssam continue; 702120585Ssam } 703105197Ssam else if ((op & 0xfc1f0003) == 0xf8010001) 704105197Ssam { /* stdu rX,NUM(r1) */ 705105197Ssam fdata->frameless = 0; 706105197Ssam fdata->offset = SIGNED_SHORT (op & ~3UL); 707105197Ssam offset = fdata->offset; 708105197Ssam continue; 709105197Ssam } 710105197Ssam else if ((op & 0xfc1f016a) == 0x7c01016a) 711105197Ssam { /* stdux rX,r1,rY */ 712105197Ssam /* no way to figure out what r1 is going to be */ 713105197Ssam fdata->frameless = 0; 714105197Ssam offset = fdata->offset; 715105197Ssam continue; 716105197Ssam } 717105197Ssam /* Load up minimal toc pointer */ 718105197Ssam else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ 719105197Ssam (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ 720105197Ssam && !minimal_toc_loaded) 721105197Ssam { 722105197Ssam minimal_toc_loaded = 1; 723105197Ssam continue; 724105197Ssam 725105197Ssam /* move parameters from argument registers to local variable 726105197Ssam registers */ 727105197Ssam } 728105197Ssam else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ 729105197Ssam (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ 730105197Ssam (((op >> 21) & 31) <= 10) && 731105197Ssam ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ 732105197Ssam { 733105197Ssam continue; 734105197Ssam 735105197Ssam /* store parameters in stack */ 736105197Ssam } 737105197Ssam else if ((op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */ 738105197Ssam (op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */ 739105197Ssam (op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ 740105197Ssam { 741105197Ssam continue; 742105197Ssam 743105197Ssam /* store parameters in stack via frame pointer */ 744120585Ssam } 745105197Ssam else if (framep && 746105197Ssam ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r1) */ 747120585Ssam (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r1) */ 748105197Ssam (op & 0xfc1f0000) == 0xfc1f0000)) 749105197Ssam { /* frsp, fp?,NUM(r1) */ 750105197Ssam continue; 751105197Ssam 752105197Ssam /* Set up frame pointer */ 753105197Ssam } 754105197Ssam else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ 755105197Ssam || op == 0x7c3f0b78) 756105197Ssam { /* mr r31, r1 */ 757105197Ssam fdata->frameless = 0; 758105197Ssam framep = 1; 759105197Ssam fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); 760105197Ssam continue; 761105197Ssam 762105197Ssam /* Another way to set up the frame pointer. */ 763105197Ssam } 764120585Ssam else if ((op & 0xfc1fffff) == 0x38010000) 765120585Ssam { /* addi rX, r1, 0x0 */ 766120585Ssam fdata->frameless = 0; 767105197Ssam framep = 1; 768120585Ssam fdata->alloca_reg = (tdep->ppc_gp0_regnum 769105197Ssam + ((op & ~0x38010000) >> 21)); 770105197Ssam continue; 771105197Ssam } 772105197Ssam /* AltiVec related instructions. */ 773105197Ssam /* Store the vrsave register (spr 256) in another register for 774105197Ssam later manipulation, or load a register into the vrsave 775105197Ssam register. 2 instructions are used: mfvrsave and 776120585Ssam mtvrsave. They are shorthand notation for mfspr Rn, SPR256 777119643Ssam and mtspr SPR256, Rn. */ 778119643Ssam /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 779119643Ssam mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ 780105197Ssam else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ 781105197Ssam { 782105197Ssam vrsave_reg = GET_SRC_REG (op); 783105197Ssam continue; 784105197Ssam } 785105197Ssam else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ 786105197Ssam { 787120585Ssam continue; 788105197Ssam } 789105197Ssam /* Store the register where vrsave was saved to onto the stack: 790105197Ssam rS is the register where vrsave was stored in a previous 791105197Ssam instruction. */ 792105197Ssam /* 100100 sssss 00001 dddddddd dddddddd */ 793105197Ssam else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ 794105197Ssam { 795105197Ssam if (vrsave_reg == GET_SRC_REG (op)) 796105197Ssam { 797105197Ssam fdata->vrsave_offset = SIGNED_SHORT (op) + offset; 798105197Ssam vrsave_reg = -1; 799105197Ssam } 800105197Ssam continue; 801105197Ssam } 802105197Ssam /* Compute the new value of vrsave, by modifying the register 803105197Ssam where vrsave was saved to. */ 804105197Ssam else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ 805105197Ssam || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ 806105197Ssam { 807105197Ssam continue; 808105197Ssam } 809105197Ssam /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first 810105197Ssam in a pair of insns to save the vector registers on the 811105197Ssam stack. */ 812105197Ssam /* 001110 00000 00000 iiii iiii iiii iiii */ 813105197Ssam /* 001110 01110 00000 iiii iiii iiii iiii */ 814105197Ssam else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ 815105197Ssam || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ 816105197Ssam { 817105197Ssam li_found_pc = pc; 818105197Ssam vr_saved_offset = SIGNED_SHORT (op); 819105197Ssam } 820105197Ssam /* Store vector register S at (r31+r0) aligned to 16 bytes. */ 821105197Ssam /* 011111 sssss 11111 00000 00111001110 */ 822105197Ssam else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ 823105197Ssam { 824105197Ssam if (pc == (li_found_pc + 4)) 825105197Ssam { 826105197Ssam vr_reg = GET_SRC_REG (op); 827105197Ssam /* If this is the first vector reg to be saved, or if 828105197Ssam it has a lower number than others previously seen, 829105197Ssam reupdate the frame info. */ 830105197Ssam if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) 831105197Ssam { 832120585Ssam fdata->saved_vr = vr_reg; 833120585Ssam fdata->vr_offset = vr_saved_offset + offset; 834105197Ssam } 835105197Ssam vr_saved_offset = -1; 836105197Ssam vr_reg = -1; 837105197Ssam li_found_pc = 0; 838105197Ssam } 839120585Ssam } 840105197Ssam /* End AltiVec related instructions. */ 841105197Ssam 842105197Ssam /* Start BookE related instructions. */ 843105197Ssam /* Store gen register S at (r31+uimm). 844105197Ssam Any register less than r13 is volatile, so we don't care. */ 845105197Ssam /* 000100 sssss 11111 iiiii 01100100001 */ 846105197Ssam else if (arch_info->mach == bfd_mach_ppc_e500 847105197Ssam && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ 848105197Ssam { 849105197Ssam if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ 850105197Ssam { 851105197Ssam unsigned int imm; 852105197Ssam ev_reg = GET_SRC_REG (op); 853105197Ssam imm = (op >> 11) & 0x1f; 854105197Ssam ev_offset = imm * 8; 855128856Ssam /* If this is the first vector reg to be saved, or if 856105197Ssam it has a lower number than others previously seen, 857105197Ssam reupdate the frame info. */ 858128856Ssam if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 859128856Ssam { 860105197Ssam fdata->saved_ev = ev_reg; 861120585Ssam fdata->ev_offset = ev_offset + offset; 862105197Ssam } 863105197Ssam } 864105197Ssam continue; 865119643Ssam } 866128856Ssam /* Store gen register rS at (r1+rB). */ 867128856Ssam /* 000100 sssss 00001 bbbbb 01100100000 */ 868128856Ssam else if (arch_info->mach == bfd_mach_ppc_e500 869128856Ssam && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ 870128856Ssam { 871128856Ssam if (pc == (li_found_pc + 4)) 872128856Ssam { 873120585Ssam ev_reg = GET_SRC_REG (op); 874105197Ssam /* If this is the first vector reg to be saved, or if 875119643Ssam it has a lower number than others previously seen, 876105197Ssam reupdate the frame info. */ 877120585Ssam /* We know the contents of rB from the previous instruction. */ 878105197Ssam if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 879105197Ssam { 880105197Ssam fdata->saved_ev = ev_reg; 881105197Ssam fdata->ev_offset = vr_saved_offset + offset; 882105197Ssam } 883128856Ssam vr_saved_offset = -1; 884128856Ssam ev_reg = -1; 885105197Ssam li_found_pc = 0; 886105197Ssam } 887105197Ssam continue; 888105197Ssam } 889105197Ssam /* Store gen register r31 at (rA+uimm). */ 890128856Ssam /* 000100 11111 aaaaa iiiii 01100100001 */ 891105197Ssam else if (arch_info->mach == bfd_mach_ppc_e500 892105197Ssam && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ 893105197Ssam { 894105197Ssam /* Wwe know that the source register is 31 already, but 895105197Ssam it can't hurt to compute it. */ 896105197Ssam ev_reg = GET_SRC_REG (op); 897105197Ssam ev_offset = ((op >> 11) & 0x1f) * 8; 898105197Ssam /* If this is the first vector reg to be saved, or if 899105197Ssam it has a lower number than others previously seen, 900105197Ssam reupdate the frame info. */ 901105197Ssam if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 902105197Ssam { 903105197Ssam fdata->saved_ev = ev_reg; 904105197Ssam fdata->ev_offset = ev_offset + offset; 905105197Ssam } 906105197Ssam 907105197Ssam continue; 908120585Ssam } 909105197Ssam /* Store gen register S at (r31+r0). 910105197Ssam Store param on stack when offset from SP bigger than 4 bytes. */ 911105197Ssam /* 000100 sssss 11111 00000 01100100000 */ 912105197Ssam else if (arch_info->mach == bfd_mach_ppc_e500 913105197Ssam && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ 914105197Ssam { 915105197Ssam if (pc == (li_found_pc + 4)) 916120585Ssam { 917105197Ssam if ((op & 0x03e00000) >= 0x01a00000) 918105197Ssam { 919105197Ssam ev_reg = GET_SRC_REG (op); 920105197Ssam /* If this is the first vector reg to be saved, or if 921105197Ssam it has a lower number than others previously seen, 922105197Ssam reupdate the frame info. */ 923105197Ssam /* We know the contents of r0 from the previous 924105197Ssam instruction. */ 925105197Ssam if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 926120585Ssam { 927120585Ssam fdata->saved_ev = ev_reg; 928120585Ssam fdata->ev_offset = vr_saved_offset + offset; 929105197Ssam } 930105197Ssam ev_reg = -1; 931125876Sguido } 932157123Sgnn vr_saved_offset = -1; 933157123Sgnn li_found_pc = 0; 934105197Ssam continue; 935105197Ssam } 936105197Ssam } 937105197Ssam /* End BookE related instructions. */ 938105197Ssam 939105197Ssam else 940125876Sguido { 941157123Sgnn /* Not a recognized prologue instruction. 942157123Sgnn Handle optimizer code motions into the prologue by continuing 943105197Ssam the search if we have no valid frame yet or if the return 944105197Ssam address is not yet saved in the frame. */ 945105197Ssam if (fdata->frameless == 0 946105197Ssam && (lr_reg == -1 || fdata->nosavedpc == 0)) 947105197Ssam break; 948105197Ssam 949105197Ssam if (op == 0x4e800020 /* blr */ 950105197Ssam || op == 0x4e800420) /* bctr */ 951105197Ssam /* Do not scan past epilogue in frameless functions or 952105197Ssam trampolines. */ 953177553Sbz break; 954105197Ssam if ((op & 0xf4000000) == 0x40000000) /* bxx */ 955125508Ssam /* Never skip branches. */ 956105197Ssam break; 957105197Ssam 958105197Ssam if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) 959120585Ssam /* Do not scan too many insns, scanning insns is expensive with 960125508Ssam remote targets. */ 961125508Ssam break; 962125508Ssam 963125508Ssam /* Continue scanning. */ 964125508Ssam prev_insn_was_prologue_insn = 0; 965105197Ssam continue; 966125508Ssam } 967105197Ssam } 968105197Ssam 969105197Ssam#if 0 970105197Ssam/* I have problems with skipping over __main() that I need to address 971105197Ssam * sometime. Previously, I used to use misc_function_vector which 972105197Ssam * didn't work as well as I wanted to be. -MGO */ 973105197Ssam 974105197Ssam /* If the first thing after skipping a prolog is a branch to a function, 975105197Ssam this might be a call to an initializer in main(), introduced by gcc2. 976105197Ssam We'd like to skip over it as well. Fortunately, xlc does some extra 977105197Ssam work before calling a function right after a prologue, thus we can 978105197Ssam single out such gcc2 behaviour. */ 979105197Ssam 980105197Ssam 981105197Ssam if ((op & 0xfc000001) == 0x48000001) 982128860Ssam { /* bl foo, an initializer function? */ 983128860Ssam op = read_memory_integer (pc + 4, 4); 984105197Ssam 985105197Ssam if (op == 0x4def7b82) 986105197Ssam { /* cror 0xf, 0xf, 0xf (nop) */ 987105197Ssam 988105197Ssam /* Check and see if we are in main. If so, skip over this 989105197Ssam initializer function as well. */ 990105197Ssam 991105197Ssam tmp = find_pc_misc_function (pc); 992105197Ssam if (tmp >= 0 993105197Ssam && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) 994105197Ssam return pc + 8; 995105197Ssam } 996105197Ssam } 997105197Ssam#endif /* 0 */ 998105197Ssam 999105197Ssam fdata->offset = -fdata->offset; 1000105197Ssam return last_prologue_pc; 1001105197Ssam} 1002105197Ssam 1003105197Ssam 1004105197Ssam/************************************************************************* 1005105197Ssam Support for creating pushing a dummy frame into the stack, and popping 1006105197Ssam frames, etc. 1007105197Ssam*************************************************************************/ 1008105197Ssam 1009105197Ssam 1010105197Ssam/* Pop the innermost frame, go back to the caller. */ 1011105197Ssam 1012105197Ssamstatic void 1013105197Ssamrs6000_pop_frame (void) 1014105197Ssam{ 1015105197Ssam CORE_ADDR pc, lr, sp, prev_sp, addr; /* %pc, %lr, %sp */ 1016158767Spjd struct rs6000_framedata fdata; 1017105197Ssam struct frame_info *frame = get_current_frame (); 1018120585Ssam int ii, wordsize; 1019120585Ssam 1020105197Ssam pc = read_pc (); 1021120585Ssam sp = get_frame_base (frame); 1022119643Ssam 1023105197Ssam if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), 1024105197Ssam get_frame_base (frame), 1025105197Ssam get_frame_base (frame))) 1026105197Ssam { 1027105197Ssam generic_pop_dummy_frame (); 1028105197Ssam flush_cached_frames (); 1029105197Ssam return; 1030105197Ssam } 1031105197Ssam 1032105197Ssam /* Make sure that all registers are valid. */ 1033105197Ssam deprecated_read_register_bytes (0, NULL, DEPRECATED_REGISTER_BYTES); 1034105197Ssam 1035105197Ssam /* Figure out previous %pc value. If the function is frameless, it is 1036105197Ssam still in the link register, otherwise walk the frames and retrieve the 1037105197Ssam saved %pc value in the previous frame. */ 1038105197Ssam 1039105197Ssam addr = get_frame_func (frame); 1040105197Ssam (void) skip_prologue (addr, get_frame_pc (frame), &fdata); 1041105197Ssam 1042105197Ssam wordsize = gdbarch_tdep (current_gdbarch)->wordsize; 1043105197Ssam if (fdata.frameless) 1044105197Ssam prev_sp = sp; 1045105197Ssam else 1046105197Ssam prev_sp = read_memory_addr (sp, wordsize); 1047105197Ssam if (fdata.lr_offset == 0) 1048105197Ssam lr = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); 1049105197Ssam else 1050128856Ssam lr = read_memory_addr (prev_sp + fdata.lr_offset, wordsize); 1051128856Ssam 1052105197Ssam /* reset %pc value. */ 1053120585Ssam write_register (PC_REGNUM, lr); 1054105197Ssam 1055105197Ssam /* reset register values if any was saved earlier. */ 1056120585Ssam 1057105197Ssam if (fdata.saved_gpr != -1) 1058105197Ssam { 1059105197Ssam addr = prev_sp + fdata.gpr_offset; 1060105197Ssam for (ii = fdata.saved_gpr; ii <= 31; ++ii) 1061105197Ssam { 1062105197Ssam read_memory (addr, &deprecated_registers[DEPRECATED_REGISTER_BYTE (ii)], 1063105197Ssam wordsize); 1064120585Ssam addr += wordsize; 1065128856Ssam } 1066128856Ssam } 1067128856Ssam 1068128856Ssam if (fdata.saved_fpr != -1) 1069128856Ssam { 1070128856Ssam addr = prev_sp + fdata.fpr_offset; 1071128856Ssam for (ii = fdata.saved_fpr; ii <= 31; ++ii) 1072105197Ssam { 1073105197Ssam read_memory (addr, &deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + FP0_REGNUM)], 8); 1074128856Ssam addr += 8; 1075105197Ssam } 1076105197Ssam } 1077105197Ssam 1078120585Ssam write_register (SP_REGNUM, prev_sp); 1079105197Ssam target_store_registers (-1); 1080105197Ssam flush_cached_frames (); 1081105197Ssam} 1082105197Ssam 1083105197Ssam/* All the ABI's require 16 byte alignment. */ 1084105197Ssamstatic CORE_ADDR 1085105197Ssamrs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) 1086105197Ssam{ 1087105197Ssam return (addr & -16); 1088105197Ssam} 1089105197Ssam 1090105197Ssam/* Pass the arguments in either registers, or in the stack. In RS/6000, 1091105197Ssam the first eight words of the argument list (that might be less than 1092105197Ssam eight parameters if some parameters occupy more than one word) are 1093105197Ssam passed in r3..r10 registers. float and double parameters are 1094105197Ssam passed in fpr's, in addition to that. Rest of the parameters if any 1095158767Spjd are passed in user stack. There might be cases in which half of the 1096105197Ssam parameter is copied into registers, the other half is pushed into 1097105197Ssam stack. 1098105197Ssam 1099105197Ssam Stack must be aligned on 64-bit boundaries when synthesizing 1100105197Ssam function calls. 1101105197Ssam 1102120585Ssam If the function is returning a structure, then the return address is passed 1103105197Ssam in r3, then the first 7 words of the parameters can be passed in registers, 1104105197Ssam starting from r4. */ 1105120585Ssam 1106105197Ssamstatic CORE_ADDR 1107105197Ssamrs6000_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, 1108105197Ssam struct regcache *regcache, CORE_ADDR bp_addr, 1109105197Ssam int nargs, struct value **args, CORE_ADDR sp, 1110105197Ssam int struct_return, CORE_ADDR struct_addr) 1111105197Ssam{ 1112105197Ssam struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1113105197Ssam int ii; 1114105197Ssam int len = 0; 1115105197Ssam int argno; /* current argument number */ 1116105197Ssam int argbytes; /* current argument byte */ 1117105197Ssam char tmp_buffer[50]; 1118105197Ssam int f_argno = 0; /* current floating point argno */ 1119120585Ssam int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; 1120105197Ssam 1121120585Ssam struct value *arg = 0; 1122105197Ssam struct type *type; 1123105197Ssam 1124105197Ssam CORE_ADDR saved_sp; 1125120585Ssam 1126120585Ssam /* The first eight words of ther arguments are passed in registers. 1127105197Ssam Copy them appropriately. */ 1128105197Ssam ii = 0; 1129105197Ssam 1130105197Ssam /* If the function is returning a `struct', then the first word 1131105197Ssam (which will be passed in r3) is used for struct return address. 1132120585Ssam In that case we should advance one word and start from r4 1133105197Ssam register to copy parameters. */ 1134105197Ssam if (struct_return) 1135105197Ssam { 1136105197Ssam regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, 1137105197Ssam struct_addr); 1138105197Ssam ii++; 1139105197Ssam } 1140105197Ssam 1141105197Ssam/* 1142120585Ssam effectively indirect call... gcc does... 1143105197Ssam 1144105197Ssam return_val example( float, int); 1145105197Ssam 1146105197Ssam eabi: 1147105197Ssam float in fp0, int in r3 1148105197Ssam offset of stack on overflow 8/16 1149105197Ssam for varargs, must go by type. 1150105197Ssam power open: 1151105197Ssam float in r3&r4, int in r5 1152105197Ssam offset of stack on overflow different 1153105197Ssam both: 1154105197Ssam return in r3 or f0. If no float, must study how gcc emulates floats; 1155105197Ssam pay attention to arg promotion. 1156105197Ssam User may have to cast\args to handle promotion correctly 1157105197Ssam since gdb won't know if prototype supplied or not. 1158105197Ssam */ 1159105197Ssam 1160105197Ssam for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) 1161105197Ssam { 1162105197Ssam int reg_size = DEPRECATED_REGISTER_RAW_SIZE (ii + 3); 1163105197Ssam 1164105197Ssam arg = args[argno]; 1165105197Ssam type = check_typedef (VALUE_TYPE (arg)); 1166105197Ssam len = TYPE_LENGTH (type); 1167105197Ssam 1168105197Ssam if (TYPE_CODE (type) == TYPE_CODE_FLT) 1169105197Ssam { 1170105197Ssam 1171105197Ssam /* Floating point arguments are passed in fpr's, as well as gpr's. 1172105197Ssam There are 13 fpr's reserved for passing parameters. At this point 1173105197Ssam there is no way we would run out of them. */ 1174105197Ssam 1175105197Ssam if (len > 8) 1176105197Ssam printf_unfiltered ( 1177105197Ssam "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno); 1178105197Ssam 1179105197Ssam memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)], 1180105197Ssam VALUE_CONTENTS (arg), 1181105197Ssam len); 1182120585Ssam ++f_argno; 1183120585Ssam } 1184105197Ssam 1185105197Ssam if (len > reg_size) 1186105197Ssam { 1187105197Ssam 1188105197Ssam /* Argument takes more than one register. */ 1189105197Ssam while (argbytes < len) 1190105197Ssam { 1191120585Ssam memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, 1192105197Ssam reg_size); 1193105197Ssam memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 1194105197Ssam ((char *) VALUE_CONTENTS (arg)) + argbytes, 1195105197Ssam (len - argbytes) > reg_size 1196105197Ssam ? reg_size : len - argbytes); 1197120585Ssam ++ii, argbytes += reg_size; 1198120585Ssam 1199105197Ssam if (ii >= 8) 1200105197Ssam goto ran_out_of_registers_for_arguments; 1201105197Ssam } 1202105197Ssam argbytes = 0; 1203105197Ssam --ii; 1204105197Ssam } 1205105197Ssam else 1206105197Ssam { 1207105197Ssam /* Argument can fit in one register. No problem. */ 1208105197Ssam int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0; 1209105197Ssam memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, reg_size); 1210105197Ssam memcpy ((char *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)] + adj, 1211105197Ssam VALUE_CONTENTS (arg), len); 1212120585Ssam } 1213105197Ssam ++argno; 1214158767Spjd } 1215158767Spjd 1216158767Spjdran_out_of_registers_for_arguments: 1217158767Spjd 1218105197Ssam saved_sp = read_sp (); 1219105197Ssam 1220158767Spjd /* Location for 8 parameters are always reserved. */ 1221158767Spjd sp -= wordsize * 8; 1222158767Spjd 1223158767Spjd /* Another six words for back chain, TOC register, link register, etc. */ 1224105197Ssam sp -= wordsize * 6; 1225105197Ssam 1226105197Ssam /* Stack pointer must be quadword aligned. */ 1227105197Ssam sp &= -16; 1228105197Ssam 1229105197Ssam /* If there are more arguments, allocate space for them in 1230105197Ssam the stack, then push them starting from the ninth one. */ 1231105197Ssam 1232105197Ssam if ((argno < nargs) || argbytes) 1233105197Ssam { 1234119643Ssam int space = 0, jj; 1235105197Ssam 1236120585Ssam if (argbytes) 1237120585Ssam { 1238105197Ssam space += ((len - argbytes + 3) & -4); 1239105197Ssam jj = argno + 1; 1240105197Ssam } 1241120585Ssam else 1242120585Ssam jj = argno; 1243105197Ssam 1244105197Ssam for (; jj < nargs; ++jj) 1245105197Ssam { 1246105197Ssam struct value *val = args[jj]; 1247105197Ssam space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4; 1248119643Ssam } 1249105197Ssam 1250105197Ssam /* Add location required for the rest of the parameters. */ 1251105197Ssam space = (space + 15) & -16; 1252105197Ssam sp -= space; 1253105197Ssam 1254105197Ssam /* This is another instance we need to be concerned about 1255119643Ssam securing our stack space. If we write anything underneath %sp 1256105197Ssam (r1), we might conflict with the kernel who thinks he is free 1257119643Ssam to use this area. So, update %sp first before doing anything 1258105197Ssam else. */ 1259105197Ssam 1260105197Ssam regcache_raw_write_signed (regcache, SP_REGNUM, sp); 1261105197Ssam 1262105197Ssam /* If the last argument copied into the registers didn't fit there 1263105197Ssam completely, push the rest of it into stack. */ 1264105197Ssam 1265105197Ssam if (argbytes) 1266105197Ssam { 1267105197Ssam write_memory (sp + 24 + (ii * 4), 1268105197Ssam ((char *) VALUE_CONTENTS (arg)) + argbytes, 1269105197Ssam len - argbytes); 1270120585Ssam ++argno; 1271105197Ssam ii += ((len - argbytes + 3) & -4) / 4; 1272120585Ssam } 1273105197Ssam 1274105197Ssam /* Push the rest of the arguments into stack. */ 1275105197Ssam for (; argno < nargs; ++argno) 1276105197Ssam { 1277105197Ssam 1278119643Ssam arg = args[argno]; 1279105197Ssam type = check_typedef (VALUE_TYPE (arg)); 1280105197Ssam len = TYPE_LENGTH (type); 1281120585Ssam 1282105197Ssam 1283119643Ssam /* Float types should be passed in fpr's, as well as in the 1284105197Ssam stack. */ 1285105197Ssam if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) 1286105197Ssam { 1287105197Ssam 1288105197Ssam if (len > 8) 1289105197Ssam printf_unfiltered ( 1290105197Ssam "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno); 1291105197Ssam 1292105197Ssam memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)], 1293105197Ssam VALUE_CONTENTS (arg), 1294105197Ssam len); 1295105197Ssam ++f_argno; 1296120585Ssam } 1297105197Ssam 1298105197Ssam write_memory (sp + 24 + (ii * 4), (char *) VALUE_CONTENTS (arg), len); 1299105197Ssam ii += ((len + 3) & -4) / 4; 1300105197Ssam } 1301105197Ssam } 1302119643Ssam 1303105197Ssam /* Set the stack pointer. According to the ABI, the SP is meant to 1304105197Ssam be set _before_ the corresponding stack space is used. On AIX, 1305105197Ssam this even applies when the target has been completely stopped! 1306105197Ssam Not doing this can lead to conflicts with the kernel which thinks 1307105197Ssam that it still has control over this not-yet-allocated stack 1308105197Ssam region. */ 1309105197Ssam regcache_raw_write_signed (regcache, SP_REGNUM, sp); 1310105197Ssam 1311119643Ssam /* Set back chain properly. */ 1312105197Ssam store_unsigned_integer (tmp_buffer, 4, saved_sp); 1313105197Ssam write_memory (sp, tmp_buffer, 4); 1314119643Ssam 1315120585Ssam /* Point the inferior function call's return address at the dummy's 1316105197Ssam breakpoint. */ 1317119643Ssam regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); 1318105197Ssam 1319105197Ssam /* Set the TOC register, get the value from the objfile reader 1320105197Ssam which, in turn, gets it from the VMAP table. */ 1321105197Ssam if (rs6000_find_toc_address_hook != NULL) 1322105197Ssam { 1323105197Ssam CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr); 1324105197Ssam regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue); 1325105197Ssam } 1326119643Ssam 1327105197Ssam target_store_registers (-1); 1328120585Ssam return sp; 1329105197Ssam} 1330105197Ssam 1331105197Ssam/* PowerOpen always puts structures in memory. Vectors, which were 1332105197Ssam added later, do get returned in a register though. */ 1333105197Ssam 1334120585Ssamstatic int 1335105197Ssamrs6000_use_struct_convention (int gcc_p, struct type *value_type) 1336105197Ssam{ 1337105197Ssam if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8) 1338105197Ssam && TYPE_VECTOR (value_type)) 1339119643Ssam return 0; 1340119643Ssam return 1; 1341119643Ssam} 1342120585Ssam 1343119643Ssamstatic void 1344119643Ssamrs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf) 1345119643Ssam{ 1346105197Ssam int offset = 0; 1347105197Ssam struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1348105197Ssam 1349105197Ssam if (TYPE_CODE (valtype) == TYPE_CODE_FLT) 1350105197Ssam { 1351105197Ssam 1352105197Ssam double dd; 1353105197Ssam float ff; 1354105197Ssam /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes. 1355105197Ssam We need to truncate the return value into float size (4 byte) if 1356105197Ssam necessary. */ 1357105197Ssam 1358105197Ssam if (TYPE_LENGTH (valtype) > 4) /* this is a double */ 1359120585Ssam memcpy (valbuf, 1360127972Spjd ®buf[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1)], 1361120585Ssam TYPE_LENGTH (valtype)); 1362105197Ssam else 1363120585Ssam { /* float */ 1364105197Ssam memcpy (&dd, ®buf[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1)], 8); 1365105197Ssam ff = (float) dd; 1366105197Ssam memcpy (valbuf, &ff, sizeof (float)); 1367105197Ssam } 1368105197Ssam } 1369105197Ssam else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY 1370105197Ssam && TYPE_LENGTH (valtype) == 16 1371105197Ssam && TYPE_VECTOR (valtype)) 1372105197Ssam { 1373105197Ssam memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), 1374105197Ssam TYPE_LENGTH (valtype)); 1375105197Ssam } 1376105197Ssam else 1377105197Ssam { 1378105197Ssam /* return value is copied starting from r3. */ 1379105197Ssam if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG 1380105197Ssam && TYPE_LENGTH (valtype) < DEPRECATED_REGISTER_RAW_SIZE (3)) 1381105197Ssam offset = DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype); 1382105197Ssam 1383105197Ssam memcpy (valbuf, 1384105197Ssam regbuf + DEPRECATED_REGISTER_BYTE (3) + offset, 1385105197Ssam TYPE_LENGTH (valtype)); 1386105197Ssam } 1387105197Ssam} 1388105197Ssam 1389105197Ssam/* Return whether handle_inferior_event() should proceed through code 1390105197Ssam starting at PC in function NAME when stepping. 1391105197Ssam 1392105197Ssam The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to 1393120585Ssam handle memory references that are too distant to fit in instructions 1394120585Ssam generated by the compiler. For example, if 'foo' in the following 1395105197Ssam instruction: 1396105197Ssam 1397105197Ssam lwz r9,foo(r2) 1398105197Ssam 1399105197Ssam is greater than 32767, the linker might replace the lwz with a branch to 1400105197Ssam somewhere in @FIX1 that does the load in 2 instructions and then branches 1401105197Ssam back to where execution should continue. 1402105197Ssam 1403105197Ssam GDB should silently step over @FIX code, just like AIX dbx does. 1404105197Ssam Unfortunately, the linker uses the "b" instruction for the branches, 1405105197Ssam meaning that the link register doesn't get set. Therefore, GDB's usual 1406120585Ssam step_over_function() mechanism won't work. 1407120585Ssam 1408105197Ssam Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks 1409105197Ssam in handle_inferior_event() to skip past @FIX code. */ 1410105197Ssam 1411105197Ssamint 1412105197Ssamrs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) 1413105197Ssam{ 1414119643Ssam return name && !strncmp (name, "@FIX", 4); 1415119643Ssam} 1416105197Ssam 1417105197Ssam/* Skip code that the user doesn't want to see when stepping: 1418120585Ssam 1419105197Ssam 1. Indirect function calls use a piece of trampoline code to do context 1420105197Ssam switching, i.e. to set the new TOC table. Skip such code if we are on 1421105197Ssam its first instruction (as when we have single-stepped to here). 1422105197Ssam 1423105197Ssam 2. Skip shared library trampoline code (which is different from 1424105197Ssam indirect function call trampolines). 1425105197Ssam 1426105197Ssam 3. Skip bigtoc fixup code. 1427105197Ssam 1428105197Ssam Result is desired PC to step until, or NULL if we are not in 1429105197Ssam code that should be skipped. */ 1430105197Ssam 1431105197SsamCORE_ADDR 1432120585Ssamrs6000_skip_trampoline_code (CORE_ADDR pc) 1433105197Ssam{ 1434105197Ssam unsigned int ii, op; 1435105197Ssam int rel; 1436105197Ssam CORE_ADDR solib_target_pc; 1437105197Ssam struct minimal_symbol *msymbol; 1438105197Ssam 1439105197Ssam static unsigned trampoline_code[] = 1440105197Ssam { 1441105197Ssam 0x800b0000, /* l r0,0x0(r11) */ 1442105197Ssam 0x90410014, /* st r2,0x14(r1) */ 1443105197Ssam 0x7c0903a6, /* mtctr r0 */ 1444105197Ssam 0x804b0004, /* l r2,0x4(r11) */ 1445105197Ssam 0x816b0008, /* l r11,0x8(r11) */ 1446105197Ssam 0x4e800420, /* bctr */ 1447120585Ssam 0x4e800020, /* br */ 1448105197Ssam 0 1449105197Ssam }; 1450105197Ssam 1451105197Ssam /* Check for bigtoc fixup code. */ 1452105197Ssam msymbol = lookup_minimal_symbol_by_pc (pc); 1453105197Ssam if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol))) 1454105197Ssam { 1455105197Ssam /* Double-check that the third instruction from PC is relative "b". */ 1456105197Ssam op = read_memory_integer (pc + 8, 4); 1457105197Ssam if ((op & 0xfc000003) == 0x48000000) 1458105197Ssam { 1459105197Ssam /* Extract bits 6-29 as a signed 24-bit relative word address and 1460105197Ssam add it to the containing PC. */ 1461105197Ssam rel = ((int)(op << 6) >> 6); 1462105197Ssam return pc + 8 + rel; 1463105197Ssam } 1464105197Ssam } 1465105197Ssam 1466105197Ssam /* If pc is in a shared library trampoline, return its target. */ 1467105197Ssam solib_target_pc = find_solib_trampoline_target (pc); 1468105197Ssam if (solib_target_pc) 1469120585Ssam return solib_target_pc; 1470105197Ssam 1471120585Ssam for (ii = 0; trampoline_code[ii]; ++ii) 1472105197Ssam { 1473105197Ssam op = read_memory_integer (pc + (ii * 4), 4); 1474105197Ssam if (op != trampoline_code[ii]) 1475105197Ssam return 0; 1476105197Ssam } 1477105197Ssam ii = read_register (11); /* r11 holds destination addr */ 1478105197Ssam pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ 1479105197Ssam return pc; 1480105197Ssam} 1481105197Ssam 1482105197Ssam/* Determines whether the function FI has a frame on the stack or not. */ 1483105197Ssam 1484105197Ssamint 1485105197Ssamrs6000_frameless_function_invocation (struct frame_info *fi) 1486105197Ssam{ 1487105197Ssam CORE_ADDR func_start; 1488105197Ssam struct rs6000_framedata fdata; 1489105197Ssam 1490105197Ssam /* Don't even think about framelessness except on the innermost frame 1491105197Ssam or if the function was interrupted by a signal. */ 1492105197Ssam if (get_next_frame (fi) != NULL 1493105197Ssam && !(get_frame_type (get_next_frame (fi)) == SIGTRAMP_FRAME)) 1494120585Ssam return 0; 1495120585Ssam 1496105197Ssam func_start = get_frame_func (fi); 1497105197Ssam 1498105197Ssam /* If we failed to find the start of the function, it is a mistake 1499105197Ssam to inspect the instructions. */ 1500105197Ssam 1501105197Ssam if (!func_start) 1502105197Ssam { 1503105197Ssam /* A frame with a zero PC is usually created by dereferencing a NULL 1504105197Ssam function pointer, normally causing an immediate core dump of the 1505105197Ssam inferior. Mark function as frameless, as the inferior has no chance 1506105197Ssam of setting up a stack frame. */ 1507105197Ssam if (get_frame_pc (fi) == 0) 1508105197Ssam return 1; 1509105197Ssam else 1510105197Ssam return 0; 1511105197Ssam } 1512120585Ssam 1513120585Ssam (void) skip_prologue (func_start, get_frame_pc (fi), &fdata); 1514120585Ssam return fdata.frameless; 1515105197Ssam} 1516105197Ssam 1517105197Ssam/* Return the PC saved in a frame. */ 1518105197Ssam 1519105197SsamCORE_ADDR 1520105197Ssamrs6000_frame_saved_pc (struct frame_info *fi) 1521105197Ssam{ 1522105197Ssam CORE_ADDR func_start; 1523105197Ssam struct rs6000_framedata fdata; 1524105197Ssam struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1525105197Ssam int wordsize = tdep->wordsize; 1526105197Ssam 1527105197Ssam if ((get_frame_type (fi) == SIGTRAMP_FRAME)) 1528120585Ssam return read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, 1529120585Ssam wordsize); 1530120585Ssam 1531105197Ssam if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 1532105197Ssam get_frame_base (fi), 1533105197Ssam get_frame_base (fi))) 1534105197Ssam return deprecated_read_register_dummy (get_frame_pc (fi), 1535105197Ssam get_frame_base (fi), PC_REGNUM); 1536105197Ssam 1537105197Ssam func_start = get_frame_func (fi); 1538105197Ssam 1539105197Ssam /* If we failed to find the start of the function, it is a mistake 1540105197Ssam to inspect the instructions. */ 1541105197Ssam if (!func_start) 1542105197Ssam return 0; 1543105197Ssam 1544105197Ssam (void) skip_prologue (func_start, get_frame_pc (fi), &fdata); 1545105197Ssam 1546105197Ssam if (fdata.lr_offset == 0 && get_next_frame (fi) != NULL) 1547120585Ssam { 1548120585Ssam if ((get_frame_type (get_next_frame (fi)) == SIGTRAMP_FRAME)) 1549105197Ssam return read_memory_addr ((get_frame_base (get_next_frame (fi)) 1550105197Ssam + SIG_FRAME_LR_OFFSET), 1551105197Ssam wordsize); 1552105197Ssam else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0)) 1553105197Ssam /* The link register wasn't saved by this frame and the next 1554105197Ssam (inner, newer) frame is a dummy. Get the link register 1555105197Ssam value by unwinding it from that [dummy] frame. */ 1556105197Ssam { 1557105197Ssam ULONGEST lr; 1558105197Ssam frame_unwind_unsigned_register (get_next_frame (fi), 1559105197Ssam tdep->ppc_lr_regnum, &lr); 1560120585Ssam return lr; 1561105197Ssam } 1562105197Ssam else 1563105197Ssam return read_memory_addr (DEPRECATED_FRAME_CHAIN (fi) 1564105197Ssam + tdep->lr_frame_offset, 1565105197Ssam wordsize); 1566105197Ssam } 1567105197Ssam 1568105197Ssam if (fdata.lr_offset == 0) 1569105197Ssam return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); 1570105197Ssam 1571105197Ssam return read_memory_addr (DEPRECATED_FRAME_CHAIN (fi) + fdata.lr_offset, 1572105197Ssam wordsize); 1573105197Ssam} 1574105197Ssam 1575105197Ssam/* If saved registers of frame FI are not known yet, read and cache them. 1576105197Ssam &FDATAP contains rs6000_framedata; TDATAP can be NULL, 1577105197Ssam in which case the framedata are read. */ 1578105197Ssam 1579105197Ssamstatic void 1580105197Ssamframe_get_saved_regs (struct frame_info *fi, struct rs6000_framedata *fdatap) 1581105197Ssam{ 1582105197Ssam CORE_ADDR frame_addr; 1583105197Ssam struct rs6000_framedata work_fdata; 1584105197Ssam struct gdbarch_tdep * tdep = gdbarch_tdep (current_gdbarch); 1585105197Ssam int wordsize = tdep->wordsize; 1586105197Ssam 1587105197Ssam if (deprecated_get_frame_saved_regs (fi)) 1588105197Ssam return; 1589105197Ssam 1590105197Ssam if (fdatap == NULL) 1591105197Ssam { 1592105197Ssam fdatap = &work_fdata; 1593105197Ssam (void) skip_prologue (get_frame_func (fi), get_frame_pc (fi), fdatap); 1594105197Ssam } 1595120585Ssam 1596105197Ssam frame_saved_regs_zalloc (fi); 1597105197Ssam 1598105197Ssam /* If there were any saved registers, figure out parent's stack 1599105197Ssam pointer. */ 1600105197Ssam /* The following is true only if the frame doesn't have a call to 1601105197Ssam alloca(), FIXME. */ 1602105197Ssam 1603105197Ssam if (fdatap->saved_fpr == 0 1604105197Ssam && fdatap->saved_gpr == 0 1605105197Ssam && fdatap->saved_vr == 0 1606105197Ssam && fdatap->saved_ev == 0 1607105197Ssam && fdatap->lr_offset == 0 1608105197Ssam && fdatap->cr_offset == 0 1609105197Ssam && fdatap->vr_offset == 0 1610105197Ssam && fdatap->ev_offset == 0) 1611105197Ssam frame_addr = 0; 1612105197Ssam else 1613105197Ssam /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most 1614105197Ssam address of the current frame. Things might be easier if the 1615105197Ssam ->frame pointed to the outer-most address of the frame. In the 1616105197Ssam mean time, the address of the prev frame is used as the base 1617105197Ssam address of this frame. */ 1618105197Ssam frame_addr = DEPRECATED_FRAME_CHAIN (fi); 1619105197Ssam 1620105197Ssam /* if != -1, fdatap->saved_fpr is the smallest number of saved_fpr. 1621105197Ssam All fpr's from saved_fpr to fp31 are saved. */ 1622105197Ssam 1623105197Ssam if (fdatap->saved_fpr >= 0) 1624105197Ssam { 1625105197Ssam int i; 1626105197Ssam CORE_ADDR fpr_addr = frame_addr + fdatap->fpr_offset; 1627105197Ssam for (i = fdatap->saved_fpr; i < 32; i++) 1628105197Ssam { 1629105197Ssam deprecated_get_frame_saved_regs (fi)[FP0_REGNUM + i] = fpr_addr; 1630105197Ssam fpr_addr += 8; 1631105197Ssam } 1632105197Ssam } 1633105197Ssam 1634105197Ssam /* if != -1, fdatap->saved_gpr is the smallest number of saved_gpr. 1635105197Ssam All gpr's from saved_gpr to gpr31 are saved. */ 1636105197Ssam 1637105197Ssam if (fdatap->saved_gpr >= 0) 1638105197Ssam { 1639105197Ssam int i; 1640105197Ssam CORE_ADDR gpr_addr = frame_addr + fdatap->gpr_offset; 1641105197Ssam for (i = fdatap->saved_gpr; i < 32; i++) 1642105197Ssam { 1643105197Ssam deprecated_get_frame_saved_regs (fi)[tdep->ppc_gp0_regnum + i] = gpr_addr; 1644105197Ssam gpr_addr += wordsize; 1645105197Ssam } 1646105197Ssam } 1647105197Ssam 1648105197Ssam /* if != -1, fdatap->saved_vr is the smallest number of saved_vr. 1649105197Ssam All vr's from saved_vr to vr31 are saved. */ 1650105197Ssam if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) 1651105197Ssam { 1652105197Ssam if (fdatap->saved_vr >= 0) 1653105197Ssam { 1654105197Ssam int i; 1655105197Ssam CORE_ADDR vr_addr = frame_addr + fdatap->vr_offset; 1656105197Ssam for (i = fdatap->saved_vr; i < 32; i++) 1657105197Ssam { 1658105197Ssam deprecated_get_frame_saved_regs (fi)[tdep->ppc_vr0_regnum + i] = vr_addr; 1659105197Ssam vr_addr += DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); 1660105197Ssam } 1661105197Ssam } 1662105197Ssam } 1663105197Ssam 1664105197Ssam /* if != -1, fdatap->saved_ev is the smallest number of saved_ev. 1665105197Ssam All vr's from saved_ev to ev31 are saved. ????? */ 1666105197Ssam if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) 1667105197Ssam { 1668120585Ssam if (fdatap->saved_ev >= 0) 1669120585Ssam { 1670105197Ssam int i; 1671105197Ssam CORE_ADDR ev_addr = frame_addr + fdatap->ev_offset; 1672105197Ssam for (i = fdatap->saved_ev; i < 32; i++) 1673105197Ssam { 1674105197Ssam deprecated_get_frame_saved_regs (fi)[tdep->ppc_ev0_regnum + i] = ev_addr; 1675105197Ssam deprecated_get_frame_saved_regs (fi)[tdep->ppc_gp0_regnum + i] = ev_addr + 4; 1676105197Ssam ev_addr += DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_ev0_regnum); 1677105197Ssam } 1678105197Ssam } 1679105197Ssam } 1680105197Ssam 1681105197Ssam /* If != 0, fdatap->cr_offset is the offset from the frame that holds 1682105197Ssam the CR. */ 1683105197Ssam if (fdatap->cr_offset != 0) 1684105197Ssam deprecated_get_frame_saved_regs (fi)[tdep->ppc_cr_regnum] = frame_addr + fdatap->cr_offset; 1685120585Ssam 1686120585Ssam /* If != 0, fdatap->lr_offset is the offset from the frame that holds 1687120585Ssam the LR. */ 1688111119Simp if (fdatap->lr_offset != 0) 1689105197Ssam deprecated_get_frame_saved_regs (fi)[tdep->ppc_lr_regnum] = frame_addr + fdatap->lr_offset; 1690105197Ssam 1691105197Ssam /* If != 0, fdatap->vrsave_offset is the offset from the frame that holds 1692105197Ssam the VRSAVE. */ 1693105197Ssam if (fdatap->vrsave_offset != 0) 1694105197Ssam deprecated_get_frame_saved_regs (fi)[tdep->ppc_vrsave_regnum] = frame_addr + fdatap->vrsave_offset; 1695105197Ssam} 1696105197Ssam 1697105197Ssam/* Return the address of a frame. This is the inital %sp value when the frame 1698105197Ssam was first allocated. For functions calling alloca(), it might be saved in 1699105197Ssam an alloca register. */ 1700105197Ssam 1701105197Ssamstatic CORE_ADDR 1702105197Ssamframe_initial_stack_address (struct frame_info *fi) 1703105197Ssam{ 1704105197Ssam CORE_ADDR tmpaddr; 1705105197Ssam struct rs6000_framedata fdata; 1706105197Ssam struct frame_info *callee_fi; 1707111119Simp 1708105197Ssam /* If the initial stack pointer (frame address) of this frame is known, 1709105197Ssam just return it. */ 1710105197Ssam 1711105197Ssam if (get_frame_extra_info (fi)->initial_sp) 1712105197Ssam return get_frame_extra_info (fi)->initial_sp; 1713105197Ssam 1714105197Ssam /* Find out if this function is using an alloca register. */ 1715105197Ssam 1716105197Ssam (void) skip_prologue (get_frame_func (fi), get_frame_pc (fi), &fdata); 1717105197Ssam 1718105197Ssam /* If saved registers of this frame are not known yet, read and 1719105197Ssam cache them. */ 1720105197Ssam 1721105197Ssam if (!deprecated_get_frame_saved_regs (fi)) 1722105197Ssam frame_get_saved_regs (fi, &fdata); 1723105197Ssam 1724105197Ssam /* If no alloca register used, then fi->frame is the value of the %sp for 1725105197Ssam this frame, and it is good enough. */ 1726105197Ssam 1727105197Ssam if (fdata.alloca_reg < 0) 1728105197Ssam { 1729105197Ssam get_frame_extra_info (fi)->initial_sp = get_frame_base (fi); 1730105197Ssam return get_frame_extra_info (fi)->initial_sp; 1731105197Ssam } 1732105197Ssam 1733105197Ssam /* There is an alloca register, use its value, in the current frame, 1734108533Sschweikh as the initial stack pointer. */ 1735105197Ssam { 1736105197Ssam char tmpbuf[MAX_REGISTER_SIZE]; 1737105197Ssam if (frame_register_read (fi, fdata.alloca_reg, tmpbuf)) 1738105197Ssam { 1739105197Ssam get_frame_extra_info (fi)->initial_sp 1740105197Ssam = extract_unsigned_integer (tmpbuf, 1741105197Ssam DEPRECATED_REGISTER_RAW_SIZE (fdata.alloca_reg)); 1742105197Ssam } 1743105197Ssam else 1744105197Ssam /* NOTE: cagney/2002-04-17: At present the only time 1745105197Ssam frame_register_read will fail is when the register isn't 1746105197Ssam available. If that does happen, use the frame. */ 1747105197Ssam get_frame_extra_info (fi)->initial_sp = get_frame_base (fi); 1748105197Ssam } 1749105197Ssam return get_frame_extra_info (fi)->initial_sp; 1750105197Ssam} 1751105197Ssam 1752105197Ssam/* Describe the pointer in each stack frame to the previous stack frame 1753105197Ssam (its caller). */ 1754105197Ssam 1755105197Ssam/* DEPRECATED_FRAME_CHAIN takes a frame's nominal address and produces 1756105197Ssam the frame's chain-pointer. */ 1757105197Ssam 1758105197Ssam/* In the case of the RS/6000, the frame's nominal address 1759105197Ssam is the address of a 4-byte word containing the calling frame's address. */ 1760105197Ssam 1761120585SsamCORE_ADDR 1762120585Ssamrs6000_frame_chain (struct frame_info *thisframe) 1763120585Ssam{ 1764120585Ssam CORE_ADDR fp, fpp, lr; 1765105197Ssam int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; 1766105197Ssam 1767105197Ssam if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (thisframe), 1768105197Ssam get_frame_base (thisframe), 1769105197Ssam get_frame_base (thisframe))) 1770105197Ssam /* A dummy frame always correctly chains back to the previous 1771105197Ssam frame. */ 1772105197Ssam return read_memory_addr (get_frame_base (thisframe), wordsize); 1773105197Ssam 1774105197Ssam if (deprecated_inside_entry_file (get_frame_pc (thisframe)) 1775120585Ssam || get_frame_pc (thisframe) == entry_point_address ()) 1776120585Ssam return 0; 1777105197Ssam 1778105197Ssam if ((get_frame_type (thisframe) == SIGTRAMP_FRAME)) 1779105197Ssam fp = read_memory_addr (get_frame_base (thisframe) + SIG_FRAME_FP_OFFSET, 1780105197Ssam wordsize); 1781105197Ssam else if (get_next_frame (thisframe) != NULL 1782120585Ssam && (get_frame_type (get_next_frame (thisframe)) == SIGTRAMP_FRAME) 1783120585Ssam && (DEPRECATED_FRAMELESS_FUNCTION_INVOCATION_P () 1784105197Ssam && DEPRECATED_FRAMELESS_FUNCTION_INVOCATION (thisframe))) 1785105197Ssam /* A frameless function interrupted by a signal did not change the 1786105197Ssam frame pointer. */ 1787105197Ssam fp = get_frame_base (thisframe); 1788105197Ssam else 1789105197Ssam fp = read_memory_addr (get_frame_base (thisframe), wordsize); 1790105197Ssam return fp; 1791105197Ssam} 1792105197Ssam 1793105197Ssam/* Return the size of register REG when words are WORDSIZE bytes long. If REG 1794105197Ssam isn't available with that word size, return 0. */ 1795105197Ssam 1796105197Ssamstatic int 1797105197Ssamregsize (const struct reg *reg, int wordsize) 1798105197Ssam{ 1799105197Ssam return wordsize == 8 ? reg->sz64 : reg->sz32; 1800105197Ssam} 1801105197Ssam 1802105197Ssam/* Return the name of register number N, or null if no such register exists 1803105197Ssam in the current architecture. */ 1804105197Ssam 1805105197Ssamstatic const char * 1806105197Ssamrs6000_register_name (int n) 1807105197Ssam{ 1808105197Ssam struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1809120585Ssam const struct reg *reg = tdep->regs + n; 1810105197Ssam 1811105197Ssam if (!regsize (reg, tdep->wordsize)) 1812105197Ssam return NULL; 1813105197Ssam return reg->name; 1814105197Ssam} 1815105197Ssam 1816105197Ssam/* Index within `registers' of the first byte of the space for 1817105197Ssam register N. */ 1818120585Ssam 1819105197Ssamstatic int 1820105197Ssamrs6000_register_byte (int n) 1821105197Ssam{ 1822105197Ssam return gdbarch_tdep (current_gdbarch)->regoff[n]; 1823105197Ssam} 1824105197Ssam 1825105197Ssam/* Return the number of bytes of storage in the actual machine representation 1826120585Ssam for register N if that register is available, else return 0. */ 1827120585Ssam 1828105197Ssamstatic int 1829105197Ssamrs6000_register_raw_size (int n) 1830105197Ssam{ 1831105197Ssam struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1832105197Ssam const struct reg *reg = tdep->regs + n; 1833105197Ssam return regsize (reg, tdep->wordsize); 1834105197Ssam} 1835105197Ssam 1836105197Ssam/* Return the GDB type object for the "standard" data type 1837105197Ssam of data in register N. */ 1838105197Ssam 1839105197Ssamstatic struct type * 1840105197Ssamrs6000_register_virtual_type (int n) 1841105197Ssam{ 1842105197Ssam struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1843105197Ssam const struct reg *reg = tdep->regs + n; 1844105197Ssam 1845105197Ssam if (reg->fpr) 1846120585Ssam return builtin_type_double; 1847120585Ssam else 1848105197Ssam { 1849105197Ssam int size = regsize (reg, tdep->wordsize); 1850105197Ssam switch (size) 1851105197Ssam { 1852105197Ssam case 0: 1853105197Ssam return builtin_type_int0; 1854105197Ssam case 4: 1855105197Ssam return builtin_type_int32; 1856105197Ssam case 8: 1857105197Ssam if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) 1858119643Ssam return builtin_type_vec64; 1859105197Ssam else 1860105197Ssam return builtin_type_int64; 1861105197Ssam break; 1862105197Ssam case 16: 1863105197Ssam return builtin_type_vec128; 1864105197Ssam break; 1865105197Ssam default: 1866105197Ssam internal_error (__FILE__, __LINE__, "Register %d size %d unknown", 1867105197Ssam n, size); 1868105197Ssam } 1869105197Ssam } 1870105197Ssam} 1871105197Ssam 1872105197Ssam/* Return whether register N requires conversion when moving from raw format 1873105197Ssam to virtual format. 1874119643Ssam 1875105197Ssam The register format for RS/6000 floating point registers is always 1876105197Ssam double, we need a conversion if the memory format is float. */ 1877105197Ssam 1878105197Ssamstatic int 1879119643Ssamrs6000_register_convertible (int n) 1880105197Ssam{ 1881105197Ssam const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + n; 1882105197Ssam return reg->fpr; 1883105197Ssam} 1884105197Ssam 1885105197Ssam/* Convert data from raw format for register N in buffer FROM 1886105197Ssam to virtual format with type TYPE in buffer TO. */ 1887119643Ssam 1888105197Ssamstatic void 1889105197Ssamrs6000_register_convert_to_virtual (int n, struct type *type, 1890105197Ssam char *from, char *to) 1891105197Ssam{ 1892105197Ssam if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n)) 1893105197Ssam { 1894105197Ssam double val = deprecated_extract_floating (from, DEPRECATED_REGISTER_RAW_SIZE (n)); 1895119643Ssam deprecated_store_floating (to, TYPE_LENGTH (type), val); 1896105197Ssam } 1897105197Ssam else 1898105197Ssam memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n)); 1899105197Ssam} 1900105197Ssam 1901105197Ssam/* Convert data from virtual format with type TYPE in buffer FROM 1902105197Ssam to raw format for register N in buffer TO. */ 1903105197Ssam 1904105197Ssamstatic void 1905105197Ssamrs6000_register_convert_to_raw (struct type *type, int n, 1906105197Ssam const char *from, char *to) 1907105197Ssam{ 1908105197Ssam if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n)) 1909105197Ssam { 1910105197Ssam double val = deprecated_extract_floating (from, TYPE_LENGTH (type)); 1911105197Ssam deprecated_store_floating (to, DEPRECATED_REGISTER_RAW_SIZE (n), val); 1912119643Ssam } 1913119643Ssam else 1914105197Ssam memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n)); 1915105197Ssam} 1916105197Ssam 1917120585Ssamstatic void 1918105197Ssame500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 1919105197Ssam int reg_nr, void *buffer) 1920105197Ssam{ 1921105197Ssam int base_regnum; 1922105197Ssam int offset = 0; 1923105197Ssam char temp_buffer[MAX_REGISTER_SIZE]; 1924105197Ssam struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1925105197Ssam 1926105197Ssam if (reg_nr >= tdep->ppc_gp0_regnum 1927105197Ssam && reg_nr <= tdep->ppc_gplast_regnum) 1928105197Ssam { 1929105197Ssam base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; 1930105197Ssam 1931105197Ssam /* Build the value in the provided buffer. */ 1932105197Ssam /* Read the raw register of which this one is the lower portion. */ 1933105197Ssam regcache_raw_read (regcache, base_regnum, temp_buffer); 1934105197Ssam if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 1935105197Ssam offset = 4; 1936105197Ssam memcpy ((char *) buffer, temp_buffer + offset, 4); 1937105197Ssam } 1938105197Ssam} 1939105197Ssam 1940105197Ssamstatic void 1941105197Ssame500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 1942105197Ssam int reg_nr, const void *buffer) 1943105197Ssam{ 1944105197Ssam int base_regnum; 1945105197Ssam int offset = 0; 1946105197Ssam char temp_buffer[MAX_REGISTER_SIZE]; 1947105197Ssam struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1948105197Ssam 1949105197Ssam if (reg_nr >= tdep->ppc_gp0_regnum 1950105197Ssam && reg_nr <= tdep->ppc_gplast_regnum) 1951105197Ssam { 1952105197Ssam base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; 1953105197Ssam /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ 1954105197Ssam if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 1955105197Ssam offset = 4; 1956105197Ssam 1957105197Ssam /* Let's read the value of the base register into a temporary 1958105197Ssam buffer, so that overwriting the last four bytes with the new 1959105197Ssam value of the pseudo will leave the upper 4 bytes unchanged. */ 1960105197Ssam regcache_raw_read (regcache, base_regnum, temp_buffer); 1961105197Ssam 1962105197Ssam /* Write as an 8 byte quantity. */ 1963105197Ssam memcpy (temp_buffer + offset, (char *) buffer, 4); 1964105197Ssam regcache_raw_write (regcache, base_regnum, temp_buffer); 1965105197Ssam } 1966105197Ssam} 1967105197Ssam 1968105197Ssam/* Convert a dwarf2 register number to a gdb REGNUM. */ 1969105197Ssamstatic int 1970105197Ssame500_dwarf2_reg_to_regnum (int num) 1971105197Ssam{ 1972105197Ssam int regnum; 1973105197Ssam if (0 <= num && num <= 31) 1974105197Ssam return num + gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum; 1975105197Ssam else 1976105197Ssam return num; 1977105197Ssam} 1978105197Ssam 1979105197Ssam/* Convert a dbx stab register number (from `r' declaration) to a gdb 1980105197Ssam REGNUM. */ 1981105197Ssamstatic int 1982105197Ssamrs6000_stab_reg_to_regnum (int num) 1983105197Ssam{ 1984105197Ssam int regnum; 1985105197Ssam switch (num) 1986105197Ssam { 1987105197Ssam case 64: 1988105197Ssam regnum = gdbarch_tdep (current_gdbarch)->ppc_mq_regnum; 1989105197Ssam break; 1990105197Ssam case 65: 1991120585Ssam regnum = gdbarch_tdep (current_gdbarch)->ppc_lr_regnum; 1992120585Ssam break; 1993105197Ssam case 66: 1994105197Ssam regnum = gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum; 1995105197Ssam break; 1996105197Ssam case 76: 1997105197Ssam regnum = gdbarch_tdep (current_gdbarch)->ppc_xer_regnum; 1998105197Ssam break; 1999105197Ssam default: 2000105197Ssam regnum = num; 2001105197Ssam break; 2002105197Ssam } 2003105197Ssam return regnum; 2004105197Ssam} 2005105197Ssam 2006105197Ssamstatic void 2007105197Ssamrs6000_store_return_value (struct type *type, char *valbuf) 2008105197Ssam{ 2009105197Ssam struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2010105197Ssam 2011105197Ssam if (TYPE_CODE (type) == TYPE_CODE_FLT) 2012105197Ssam 2013105197Ssam /* Floating point values are returned starting from FPR1 and up. 2014105197Ssam Say a double_double_double type could be returned in 2015105197Ssam FPR1/FPR2/FPR3 triple. */ 2016105197Ssam 2017105197Ssam deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1), valbuf, 2018105197Ssam TYPE_LENGTH (type)); 2019105197Ssam else if (TYPE_CODE (type) == TYPE_CODE_ARRAY) 2020105197Ssam { 2021105197Ssam if (TYPE_LENGTH (type) == 16 2022120585Ssam && TYPE_VECTOR (type)) 2023120585Ssam deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), 2024120585Ssam valbuf, TYPE_LENGTH (type)); 2025120585Ssam } 2026105197Ssam else 2027105197Ssam /* Everything else is returned in GPR3 and up. */ 2028105197Ssam deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3), 2029105197Ssam valbuf, TYPE_LENGTH (type)); 2030120585Ssam} 2031120585Ssam 2032105197Ssam/* Extract from an array REGBUF containing the (raw) register state 2033105197Ssam the address in which a function should return its structure value, 2034105197Ssam as a CORE_ADDR (or an expression that can be used as one). */ 2035105197Ssam 2036105197Ssamstatic CORE_ADDR 2037120585Ssamrs6000_extract_struct_value_address (struct regcache *regcache) 2038120585Ssam{ 2039105197Ssam /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior 2040105197Ssam function call GDB knows the address of the struct return value 2041105197Ssam and hence, should not need to call this function. Unfortunately, 2042105197Ssam the current call_function_by_hand() code only saves the most 2043105197Ssam recent struct address leading to occasional calls. The code 2044105197Ssam should instead maintain a stack of such addresses (in the dummy 2045105197Ssam frame object). */ 2046105197Ssam /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've 2047105197Ssam really got no idea where the return value is being stored. While 2048105197Ssam r3, on function entry, contained the address it will have since 2049105197Ssam been reused (scratch) and hence wouldn't be valid */ 2050105197Ssam return 0; 2051105197Ssam} 2052105197Ssam 2053105197Ssam/* Hook called when a new child process is started. */ 2054105197Ssam 2055105197Ssamvoid 2056105197Ssamrs6000_create_inferior (int pid) 2057105197Ssam{ 2058105197Ssam if (rs6000_set_host_arch_hook) 2059105197Ssam rs6000_set_host_arch_hook (pid); 2060105197Ssam} 2061105197Ssam 2062120585Ssam/* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG). 2063105197Ssam 2064105197Ssam Usually a function pointer's representation is simply the address 2065105197Ssam of the function. On the RS/6000 however, a function pointer is 2066105197Ssam represented by a pointer to a TOC entry. This TOC entry contains 2067105197Ssam three words, the first word is the address of the function, the 2068120585Ssam second word is the TOC pointer (r2), and the third word is the 2069105197Ssam static chain value. Throughout GDB it is currently assumed that a 2070105197Ssam function pointer contains the address of the function, which is not 2071105197Ssam easy to fix. In addition, the conversion of a function address to 2072105197Ssam a function pointer would require allocation of a TOC entry in the 2073105197Ssam inferior's memory space, with all its drawbacks. To be able to 2074105197Ssam call C++ virtual methods in the inferior (which are called via 2075105197Ssam function pointers), find_function_addr uses this function to get the 2076105197Ssam function address from a function pointer. */ 2077105197Ssam 2078105197Ssam/* Return real function address if ADDR (a function pointer) is in the data 2079105197Ssam space and is therefore a special function pointer. */ 2080105197Ssam 2081105197Ssamstatic CORE_ADDR 2082105197Ssamrs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, 2083105197Ssam CORE_ADDR addr, 2084105197Ssam struct target_ops *targ) 2085105197Ssam{ 2086105197Ssam struct obj_section *s; 2087105197Ssam 2088105197Ssam s = find_pc_section (addr); 2089105197Ssam if (s && s->the_bfd_section->flags & SEC_CODE) 2090105197Ssam return addr; 2091105197Ssam 2092105197Ssam /* ADDR is in the data space, so it's a special function pointer. */ 2093105197Ssam return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize); 2094105197Ssam} 2095105197Ssam 2096105197Ssam 2097105197Ssam/* Handling the various POWER/PowerPC variants. */ 2098105197Ssam 2099105197Ssam 2100105197Ssam/* The arrays here called registers_MUMBLE hold information about available 2101105197Ssam registers. 2102105197Ssam 2103105197Ssam For each family of PPC variants, I've tried to isolate out the 2104105197Ssam common registers and put them up front, so that as long as you get 2105105197Ssam the general family right, GDB will correctly identify the registers 2106105197Ssam common to that family. The common register sets are: 2107105197Ssam 2108105197Ssam For the 60x family: hid0 hid1 iabr dabr pir 2109105197Ssam 2110105197Ssam For the 505 and 860 family: eie eid nri 2111105197Ssam 2112105197Ssam For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi 2113105197Ssam tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 2114105197Ssam pbu1 pbl2 pbu2 2115105197Ssam 2116105197Ssam Most of these register groups aren't anything formal. I arrived at 2117105197Ssam them by looking at the registers that occurred in more than one 2118120585Ssam processor. 2119120585Ssam 2120120585Ssam Note: kevinb/2002-04-30: Support for the fpscr register was added 2121120585Ssam during April, 2002. Slot 70 is being used for PowerPC and slot 71 2122105197Ssam for Power. For PowerPC, slot 70 was unused and was already in the 2123105197Ssam PPC_UISA_SPRS which is ideally where fpscr should go. For Power, 2124105197Ssam slot 70 was being used for "mq", so the next available slot (71) 2125120585Ssam was chosen. It would have been nice to be able to make the 2126170803Sbz register numbers the same across processor cores, but this wasn't 2127105197Ssam possible without either 1) renumbering some registers for some 2128105197Ssam processors or 2) assigning fpscr to a really high slot that's 2129105197Ssam larger than any current register number. Doing (1) is bad because 2130105197Ssam existing stubs would break. Doing (2) is undesirable because it 2131105197Ssam would introduce a really large gap between fpscr and the rest of 2132105197Ssam the registers for most processors. */ 2133120585Ssam 2134170803Sbz/* Convenience macros for populating register arrays. */ 2135105197Ssam 2136105197Ssam/* Within another macro, convert S to a string. */ 2137105197Ssam 2138105197Ssam#define STR(s) #s 2139105197Ssam 2140105197Ssam/* Return a struct reg defining register NAME that's 32 bits on 32-bit systems 2141105197Ssam and 64 bits on 64-bit systems. */ 2142105197Ssam#define R(name) { STR(name), 4, 8, 0, 0 } 2143105197Ssam 2144105197Ssam/* Return a struct reg defining register NAME that's 32 bits on all 2145105197Ssam systems. */ 2146105197Ssam#define R4(name) { STR(name), 4, 4, 0, 0 } 2147105197Ssam 2148111119Simp/* Return a struct reg defining register NAME that's 64 bits on all 2149105197Ssam systems. */ 2150111119Simp#define R8(name) { STR(name), 8, 8, 0, 0 } 2151105197Ssam 2152105197Ssam/* Return a struct reg defining register NAME that's 128 bits on all 2153105197Ssam systems. */ 2154105197Ssam#define R16(name) { STR(name), 16, 16, 0, 0 } 2155105197Ssam 2156105197Ssam/* Return a struct reg defining floating-point register NAME. */ 2157105197Ssam#define F(name) { STR(name), 8, 8, 1, 0 } 2158105197Ssam 2159105197Ssam/* Return a struct reg defining a pseudo register NAME. */ 2160105197Ssam#define P(name) { STR(name), 4, 8, 0, 1} 2161105197Ssam 2162105197Ssam/* Return a struct reg defining register NAME that's 32 bits on 32-bit 2163105197Ssam systems and that doesn't exist on 64-bit systems. */ 2164105197Ssam#define R32(name) { STR(name), 4, 0, 0, 0 } 2165105197Ssam 2166120585Ssam/* Return a struct reg defining register NAME that's 64 bits on 64-bit 2167120585Ssam systems and that doesn't exist on 32-bit systems. */ 2168105197Ssam#define R64(name) { STR(name), 0, 8, 0, 0 } 2169105197Ssam 2170111119Simp/* Return a struct reg placeholder for a register that doesn't exist. */ 2171105197Ssam#define R0 { 0, 0, 0, 0, 0 } 2172105197Ssam 2173105197Ssam/* UISA registers common across all architectures, including POWER. */ 2174105197Ssam 2175105197Ssam#define COMMON_UISA_REGS \ 2176105197Ssam /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ 2177105197Ssam /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ 2178105197Ssam /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ 2179105197Ssam /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ 2180105197Ssam /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ 2181105197Ssam /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ 2182105197Ssam /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ 2183105197Ssam /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ 2184105197Ssam /* 64 */ R(pc), R(ps) 2185105197Ssam 2186105197Ssam#define COMMON_UISA_NOFP_REGS \ 2187105197Ssam /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ 2188105197Ssam /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ 2189105197Ssam /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ 2190105197Ssam /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ 2191105197Ssam /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \ 2192105197Ssam /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \ 2193105197Ssam /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \ 2194105197Ssam /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \ 2195105197Ssam /* 64 */ R(pc), R(ps) 2196105197Ssam 2197105197Ssam/* UISA-level SPRs for PowerPC. */ 2198105197Ssam#define PPC_UISA_SPRS \ 2199105197Ssam /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr) 2200105197Ssam 2201105197Ssam/* UISA-level SPRs for PowerPC without floating point support. */ 2202105197Ssam#define PPC_UISA_NOFP_SPRS \ 2203105197Ssam /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0 2204105197Ssam 2205105197Ssam/* Segment registers, for PowerPC. */ 2206105197Ssam#define PPC_SEGMENT_REGS \ 2207105197Ssam /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ 2208105197Ssam /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ 2209105197Ssam /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ 2210105197Ssam /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) 2211120585Ssam 2212120585Ssam/* OEA SPRs for PowerPC. */ 2213120585Ssam#define PPC_OEA_SPRS \ 2214120585Ssam /* 87 */ R4(pvr), \ 2215105197Ssam /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \ 2216105197Ssam /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \ 2217105197Ssam /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \ 2218120585Ssam /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \ 2219120585Ssam /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \ 2220105197Ssam /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \ 2221105197Ssam /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \ 2222105197Ssam /* 116 */ R4(dec), R(dabr), R4(ear) 2223105197Ssam 2224105197Ssam/* AltiVec registers. */ 2225105197Ssam#define PPC_ALTIVEC_REGS \ 2226105197Ssam /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ 2227120585Ssam /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ 2228105197Ssam /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ 2229105197Ssam /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ 2230105197Ssam /*151*/R4(vscr), R4(vrsave) 2231105197Ssam 2232105197Ssam/* Vectors of hi-lo general purpose registers. */ 2233105197Ssam#define PPC_EV_REGS \ 2234105197Ssam /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \ 2235105197Ssam /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \ 2236105197Ssam /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \ 2237105197Ssam /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31) 2238105197Ssam 2239105197Ssam/* Lower half of the EV registers. */ 2240105197Ssam#define PPC_GPRS_PSEUDO_REGS \ 2241105197Ssam /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \ 2242105197Ssam /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \ 2243105197Ssam /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \ 2244105197Ssam /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31) 2245105197Ssam 2246105197Ssam/* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover 2247105197Ssam user-level SPR's. */ 2248105197Ssamstatic const struct reg registers_power[] = 2249105197Ssam{ 2250105197Ssam COMMON_UISA_REGS, 2251105197Ssam /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq), 2252105197Ssam /* 71 */ R4(fpscr) 2253105197Ssam}; 2254105197Ssam 2255105197Ssam/* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only 2256105197Ssam view of the PowerPC. */ 2257105197Ssamstatic const struct reg registers_powerpc[] = 2258105197Ssam{ 2259105197Ssam COMMON_UISA_REGS, 2260105197Ssam PPC_UISA_SPRS, 2261120585Ssam PPC_ALTIVEC_REGS 2262120585Ssam}; 2263120585Ssam 2264120585Ssam/* PowerPC UISA - a PPC processor as viewed by user-level 2265105197Ssam code, but without floating point registers. */ 2266108533Sschweikhstatic const struct reg registers_powerpc_nofp[] = 2267119643Ssam{ 2268119643Ssam COMMON_UISA_NOFP_REGS, 2269105197Ssam PPC_UISA_SPRS 2270105197Ssam}; 2271105197Ssam 2272105197Ssam/* IBM PowerPC 403. */ 2273105197Ssamstatic const struct reg registers_403[] = 2274105197Ssam{ 2275105197Ssam COMMON_UISA_REGS, 2276105197Ssam PPC_UISA_SPRS, 2277120585Ssam PPC_SEGMENT_REGS, 2278105197Ssam PPC_OEA_SPRS, 2279105197Ssam /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), 2280119643Ssam /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), 2281119643Ssam /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), 2282105197Ssam /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), 2283105197Ssam /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), 2284105197Ssam /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2) 2285105197Ssam}; 2286105197Ssam 2287170805Sbz/* IBM PowerPC 403GC. */ 2288170805Sbzstatic const struct reg registers_403GC[] = 2289170805Sbz{ 2290105197Ssam COMMON_UISA_REGS, 2291105197Ssam PPC_UISA_SPRS, 2292105197Ssam PPC_SEGMENT_REGS, 2293105197Ssam PPC_OEA_SPRS, 2294105197Ssam /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), 2295105197Ssam /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), 2296105197Ssam /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), 2297105197Ssam /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), 2298105197Ssam /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), 2299105197Ssam /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2), 2300105197Ssam /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr), 2301105197Ssam /* 147 */ R(tbhu), R(tblu) 2302105197Ssam}; 2303105197Ssam 2304105197Ssam/* Motorola PowerPC 505. */ 2305105197Ssamstatic const struct reg registers_505[] = 2306105197Ssam{ 2307105197Ssam COMMON_UISA_REGS, 2308105197Ssam PPC_UISA_SPRS, 2309105197Ssam PPC_SEGMENT_REGS, 2310105197Ssam PPC_OEA_SPRS, 2311105197Ssam /* 119 */ R(eie), R(eid), R(nri) 2312105197Ssam}; 2313105197Ssam 2314105197Ssam/* Motorola PowerPC 860 or 850. */ 2315105197Ssamstatic const struct reg registers_860[] = 2316105197Ssam{ 2317105197Ssam COMMON_UISA_REGS, 2318105197Ssam PPC_UISA_SPRS, 2319105197Ssam PPC_SEGMENT_REGS, 2320105197Ssam PPC_OEA_SPRS, 2321105197Ssam /* 119 */ R(eie), R(eid), R(nri), R(cmpa), 2322105197Ssam /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr), 2323105197Ssam /* 127 */ R(der), R(counta), R(countb), R(cmpe), 2324120585Ssam /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1), 2325120585Ssam /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst), 2326120585Ssam /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr), 2327120585Ssam /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr), 2328105197Ssam /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc), 2329105197Ssam /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap), 2330105197Ssam /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn), 2331105197Ssam /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1), 2332105197Ssam /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1) 2333120585Ssam}; 2334120585Ssam 2335105197Ssam/* Motorola PowerPC 601. Note that the 601 has different register numbers 2336120585Ssam for reading and writing RTCU and RTCL. However, how one reads and writes a 2337105197Ssam register is the stub's problem. */ 2338105197Ssamstatic const struct reg registers_601[] = 2339105197Ssam{ 2340120585Ssam COMMON_UISA_REGS, 2341105197Ssam PPC_UISA_SPRS, 2342105197Ssam PPC_SEGMENT_REGS, 2343105197Ssam PPC_OEA_SPRS, 2344105197Ssam /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), 2345105197Ssam /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl) 2346105197Ssam}; 2347105197Ssam 2348105197Ssam/* Motorola PowerPC 602. */ 2349105197Ssamstatic const struct reg registers_602[] = 2350105197Ssam{ 2351105197Ssam COMMON_UISA_REGS, 2352105197Ssam PPC_UISA_SPRS, 2353105197Ssam PPC_SEGMENT_REGS, 2354105197Ssam PPC_OEA_SPRS, 2355105197Ssam /* 119 */ R(hid0), R(hid1), R(iabr), R0, 2356105197Ssam /* 123 */ R0, R(tcr), R(ibr), R(esassr), 2357105197Ssam /* 127 */ R(sebr), R(ser), R(sp), R(lt) 2358105197Ssam}; 2359105197Ssam 2360105197Ssam/* Motorola/IBM PowerPC 603 or 603e. */ 2361105197Ssamstatic const struct reg registers_603[] = 2362105197Ssam{ 2363105197Ssam COMMON_UISA_REGS, 2364105197Ssam PPC_UISA_SPRS, 2365105197Ssam PPC_SEGMENT_REGS, 2366105197Ssam PPC_OEA_SPRS, 2367105197Ssam /* 119 */ R(hid0), R(hid1), R(iabr), R0, 2368105197Ssam /* 123 */ R0, R(dmiss), R(dcmp), R(hash1), 2369105197Ssam /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa) 2370105197Ssam}; 2371105197Ssam 2372105197Ssam/* Motorola PowerPC 604 or 604e. */ 2373105197Ssamstatic const struct reg registers_604[] = 2374105197Ssam{ 2375105197Ssam COMMON_UISA_REGS, 2376105197Ssam PPC_UISA_SPRS, 2377120585Ssam PPC_SEGMENT_REGS, 2378120585Ssam PPC_OEA_SPRS, 2379120585Ssam /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), 2380120585Ssam /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2), 2381105197Ssam /* 127 */ R(sia), R(sda) 2382105197Ssam}; 2383105197Ssam 2384105197Ssam/* Motorola/IBM PowerPC 750 or 740. */ 2385105197Ssamstatic const struct reg registers_750[] = 2386105197Ssam{ 2387105197Ssam COMMON_UISA_REGS, 2388105197Ssam PPC_UISA_SPRS, 2389105197Ssam PPC_SEGMENT_REGS, 2390105197Ssam PPC_OEA_SPRS, 2391105197Ssam /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), 2392105197Ssam /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2), 2393105197Ssam /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4), 2394105197Ssam /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia), 2395105197Ssam /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr), 2396105197Ssam /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3) 2397105197Ssam}; 2398105197Ssam 2399105197Ssam 2400105197Ssam/* Motorola PowerPC 7400. */ 2401105197Ssamstatic const struct reg registers_7400[] = 2402105197Ssam{ 2403105197Ssam /* gpr0-gpr31, fpr0-fpr31 */ 2404105197Ssam COMMON_UISA_REGS, 2405105197Ssam /* ctr, xre, lr, cr */ 2406105197Ssam PPC_UISA_SPRS, 2407105197Ssam /* sr0-sr15 */ 2408105197Ssam PPC_SEGMENT_REGS, 2409105197Ssam PPC_OEA_SPRS, 2410105197Ssam /* vr0-vr31, vrsave, vscr */ 2411105197Ssam PPC_ALTIVEC_REGS 2412105197Ssam /* FIXME? Add more registers? */ 2413105197Ssam}; 2414105197Ssam 2415105197Ssam/* Motorola e500. */ 2416105197Ssamstatic const struct reg registers_e500[] = 2417105197Ssam{ 2418105197Ssam R(pc), R(ps), 2419105197Ssam /* cr, lr, ctr, xer, "" */ 2420105197Ssam PPC_UISA_NOFP_SPRS, 2421105197Ssam /* 7...38 */ 2422105197Ssam PPC_EV_REGS, 2423105197Ssam R8(acc), R(spefscr), 2424105197Ssam /* NOTE: Add new registers here the end of the raw register 2425105197Ssam list and just before the first pseudo register. */ 2426105197Ssam /* 39...70 */ 2427105197Ssam PPC_GPRS_PSEUDO_REGS 2428105197Ssam}; 2429105197Ssam 2430105197Ssam/* Information about a particular processor variant. */ 2431105197Ssam 2432105197Ssamstruct variant 2433105197Ssam { 2434105197Ssam /* Name of this variant. */ 2435105197Ssam char *name; 2436105197Ssam 2437105197Ssam /* English description of the variant. */ 2438105197Ssam char *description; 2439105197Ssam 2440105197Ssam /* bfd_arch_info.arch corresponding to variant. */ 2441105197Ssam enum bfd_architecture arch; 2442105197Ssam 2443105197Ssam /* bfd_arch_info.mach corresponding to variant. */ 2444105197Ssam unsigned long mach; 2445105197Ssam 2446105197Ssam /* Number of real registers. */ 2447105197Ssam int nregs; 2448105197Ssam 2449105197Ssam /* Number of pseudo registers. */ 2450105197Ssam int npregs; 2451105197Ssam 2452105197Ssam /* Number of total registers (the sum of nregs and npregs). */ 2453105197Ssam int num_tot_regs; 2454105197Ssam 2455105197Ssam /* Table of register names; registers[R] is the name of the register 2456105197Ssam number R. */ 2457105197Ssam const struct reg *regs; 2458105197Ssam }; 2459105197Ssam 2460105197Ssam#define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) 2461105197Ssam 2462105197Ssamstatic int 2463105197Ssamnum_registers (const struct reg *reg_list, int num_tot_regs) 2464105197Ssam{ 2465105197Ssam int i; 2466105197Ssam int nregs = 0; 2467105197Ssam 2468105197Ssam for (i = 0; i < num_tot_regs; i++) 2469105197Ssam if (!reg_list[i].pseudo) 2470105197Ssam nregs++; 2471105197Ssam 2472105197Ssam return nregs; 2473105197Ssam} 2474105197Ssam 2475105197Ssamstatic int 2476105197Ssamnum_pseudo_registers (const struct reg *reg_list, int num_tot_regs) 2477105197Ssam{ 2478105197Ssam int i; 2479105197Ssam int npregs = 0; 2480105197Ssam 2481105197Ssam for (i = 0; i < num_tot_regs; i++) 2482105197Ssam if (reg_list[i].pseudo) 2483105197Ssam npregs ++; 2484105197Ssam 2485105197Ssam return npregs; 2486105197Ssam} 2487105197Ssam 2488105197Ssam/* Information in this table comes from the following web sites: 2489105197Ssam IBM: http://www.chips.ibm.com:80/products/embedded/ 2490105197Ssam Motorola: http://www.mot.com/SPS/PowerPC/ 2491105197Ssam 2492105197Ssam I'm sure I've got some of the variant descriptions not quite right. 2493105197Ssam Please report any inaccuracies you find to GDB's maintainer. 2494105197Ssam 2495105197Ssam If you add entries to this table, please be sure to allow the new 2496105197Ssam value as an argument to the --with-cpu flag, in configure.in. */ 2497105197Ssam 2498105197Ssamstatic struct variant variants[] = 2499105197Ssam{ 2500105197Ssam 2501105197Ssam {"powerpc", "PowerPC user-level", bfd_arch_powerpc, 2502105197Ssam bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), 2503105197Ssam registers_powerpc}, 2504105197Ssam {"power", "POWER user-level", bfd_arch_rs6000, 2505105197Ssam bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), 2506105197Ssam registers_power}, 2507105197Ssam {"403", "IBM PowerPC 403", bfd_arch_powerpc, 2508105197Ssam bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), 2509105197Ssam registers_403}, 2510105197Ssam {"601", "Motorola PowerPC 601", bfd_arch_powerpc, 2511105197Ssam bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), 2512105197Ssam registers_601}, 2513105197Ssam {"602", "Motorola PowerPC 602", bfd_arch_powerpc, 2514105197Ssam bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), 2515120585Ssam registers_602}, 2516105197Ssam {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, 2517105197Ssam bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), 2518105197Ssam registers_603}, 2519105197Ssam {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, 2520105197Ssam 604, -1, -1, tot_num_registers (registers_604), 2521105197Ssam registers_604}, 2522105197Ssam {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, 2523105197Ssam bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), 2524105197Ssam registers_403GC}, 2525105197Ssam {"505", "Motorola PowerPC 505", bfd_arch_powerpc, 2526105197Ssam bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), 2527105197Ssam registers_505}, 2528105197Ssam {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, 2529105197Ssam bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), 2530105197Ssam registers_860}, 2531105197Ssam {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, 2532105197Ssam bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), 2533105197Ssam registers_750}, 2534105197Ssam {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, 2535105197Ssam bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), 2536105197Ssam registers_7400}, 2537105197Ssam {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, 2538105197Ssam bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), 2539105197Ssam registers_e500}, 2540105197Ssam 2541105197Ssam /* 64-bit */ 2542105197Ssam {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, 2543105197Ssam bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), 2544105197Ssam registers_powerpc}, 2545105197Ssam {"620", "Motorola PowerPC 620", bfd_arch_powerpc, 2546105197Ssam bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), 2547105197Ssam registers_powerpc}, 2548105197Ssam {"630", "Motorola PowerPC 630", bfd_arch_powerpc, 2549105197Ssam bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), 2550105197Ssam registers_powerpc}, 2551105197Ssam {"a35", "PowerPC A35", bfd_arch_powerpc, 2552105197Ssam bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), 2553105197Ssam registers_powerpc}, 2554105197Ssam {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, 2555105197Ssam bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), 2556105197Ssam registers_powerpc}, 2557105197Ssam {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, 2558105197Ssam bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), 2559105197Ssam registers_powerpc}, 2560105197Ssam 2561105197Ssam /* FIXME: I haven't checked the register sets of the following. */ 2562105197Ssam {"rs1", "IBM POWER RS1", bfd_arch_rs6000, 2563105197Ssam bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), 2564105197Ssam registers_power}, 2565105197Ssam {"rsc", "IBM POWER RSC", bfd_arch_rs6000, 2566105197Ssam bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), 2567105197Ssam registers_power}, 2568105197Ssam {"rs2", "IBM POWER RS2", bfd_arch_rs6000, 2569105197Ssam bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), 2570105197Ssam registers_power}, 2571105197Ssam 2572105197Ssam {0, 0, 0, 0, 0, 0, 0, 0} 2573105197Ssam}; 2574105197Ssam 2575105197Ssam/* Initialize the number of registers and pseudo registers in each variant. */ 2576105197Ssam 2577105197Ssamstatic void 2578105197Ssaminit_variants (void) 2579105197Ssam{ 2580105197Ssam struct variant *v; 2581105197Ssam 2582105197Ssam for (v = variants; v->name; v++) 2583105197Ssam { 2584105197Ssam if (v->nregs == -1) 2585105197Ssam v->nregs = num_registers (v->regs, v->num_tot_regs); 2586105197Ssam if (v->npregs == -1) 2587105197Ssam v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); 2588105197Ssam } 2589105197Ssam} 2590105197Ssam 2591105197Ssam/* Return the variant corresponding to architecture ARCH and machine number 2592105197Ssam MACH. If no such variant exists, return null. */ 2593105197Ssam 2594105197Ssamstatic const struct variant * 2595105197Ssamfind_variant_by_arch (enum bfd_architecture arch, unsigned long mach) 2596105197Ssam{ 2597105197Ssam const struct variant *v; 2598105197Ssam 2599105197Ssam for (v = variants; v->name; v++) 2600105197Ssam if (arch == v->arch && mach == v->mach) 2601105197Ssam return v; 2602105197Ssam 2603105197Ssam return NULL; 2604105197Ssam} 2605105197Ssam 2606105197Ssamstatic int 2607105197Ssamgdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) 2608105197Ssam{ 2609105197Ssam if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 2610105197Ssam return print_insn_big_powerpc (memaddr, info); 2611105197Ssam else 2612105197Ssam return print_insn_little_powerpc (memaddr, info); 2613105197Ssam} 2614105197Ssam 2615105197Ssam/* Initialize the current architecture based on INFO. If possible, re-use an 2616105197Ssam architecture from ARCHES, which is a list of architectures already created 2617105197Ssam during this debugging session. 2618105197Ssam 2619120585Ssam Called e.g. at program startup, when reading a core file, and when reading 2620105197Ssam a binary file. */ 2621119643Ssam 2622105197Ssamstatic struct gdbarch * 2623105197Ssamrs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2624105197Ssam{ 2625105197Ssam struct gdbarch *gdbarch; 2626105197Ssam struct gdbarch_tdep *tdep; 2627105197Ssam int wordsize, from_xcoff_exec, from_elf_exec, power, i, off; 2628105197Ssam struct reg *regs; 2629105197Ssam const struct variant *v; 2630119643Ssam enum bfd_architecture arch; 2631120585Ssam unsigned long mach; 2632105197Ssam bfd abfd; 2633120585Ssam int sysv_abi; 2634105197Ssam asection *sect; 2635105197Ssam 2636105197Ssam from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && 2637105197Ssam bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; 2638105197Ssam 2639105197Ssam from_elf_exec = info.abfd && info.abfd->format == bfd_object && 2640105197Ssam bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; 2641105197Ssam 2642105197Ssam sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; 2643105197Ssam 2644105197Ssam /* Check word size. If INFO is from a binary file, infer it from 2645105197Ssam that, else choose a likely default. */ 2646120585Ssam if (from_xcoff_exec) 2647105197Ssam { 2648105197Ssam if (bfd_xcoff_is_xcoff64 (info.abfd)) 2649120585Ssam wordsize = 8; 2650120585Ssam else 2651105197Ssam wordsize = 4; 2652105197Ssam } 2653105197Ssam else if (from_elf_exec) 2654105197Ssam { 2655105197Ssam if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) 2656120585Ssam wordsize = 8; 2657120585Ssam else 2658105197Ssam wordsize = 4; 2659105197Ssam } 2660120585Ssam else 2661105197Ssam { 2662105197Ssam if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) 2663105197Ssam wordsize = info.bfd_arch_info->bits_per_word / 2664105197Ssam info.bfd_arch_info->bits_per_byte; 2665105197Ssam else 2666105197Ssam wordsize = 4; 2667105197Ssam } 2668120585Ssam 2669120585Ssam /* Find a candidate among extant architectures. */ 2670120585Ssam for (arches = gdbarch_list_lookup_by_info (arches, &info); 2671120585Ssam arches != NULL; 2672120585Ssam arches = gdbarch_list_lookup_by_info (arches->next, &info)) 2673120585Ssam { 2674120585Ssam /* Word size in the various PowerPC bfd_arch_info structs isn't 2675120585Ssam meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform 2676120585Ssam separate word size check. */ 2677105197Ssam tdep = gdbarch_tdep (arches->gdbarch); 2678105197Ssam if (tdep && tdep->wordsize == wordsize) 2679105197Ssam return arches->gdbarch; 2680105197Ssam } 2681105197Ssam 2682105197Ssam /* None found, create a new architecture from INFO, whose bfd_arch_info 2683105197Ssam validity depends on the source: 2684105197Ssam - executable useless 2685105197Ssam - rs6000_host_arch() good 2686105197Ssam - core file good 2687105197Ssam - "set arch" trust blindly 2688105197Ssam - GDB startup useless but harmless */ 2689105197Ssam 2690105197Ssam if (!from_xcoff_exec) 2691105197Ssam { 2692105197Ssam arch = info.bfd_arch_info->arch; 2693105197Ssam mach = info.bfd_arch_info->mach; 2694105197Ssam } 2695105197Ssam else 2696105197Ssam { 2697105197Ssam arch = bfd_arch_powerpc; 2698105197Ssam bfd_default_set_arch_mach (&abfd, arch, 0); 2699105197Ssam info.bfd_arch_info = bfd_get_arch_info (&abfd); 2700105197Ssam mach = info.bfd_arch_info->mach; 2701105197Ssam } 2702105197Ssam tdep = xmalloc (sizeof (struct gdbarch_tdep)); 2703105197Ssam tdep->wordsize = wordsize; 2704120585Ssam 2705120585Ssam /* For e500 executables, the apuinfo section is of help here. Such 2706120585Ssam section contains the identifier and revision number of each 2707120585Ssam Application-specific Processing Unit that is present on the 2708105197Ssam chip. The content of the section is determined by the assembler 2709119643Ssam which looks at each instruction and determines which unit (and 2710105197Ssam which version of it) can execute it. In our case we just look for 2711120585Ssam the existance of the section. */ 2712105197Ssam 2713105197Ssam if (info.abfd) 2714105197Ssam { 2715105197Ssam sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); 2716105197Ssam if (sect) 2717105197Ssam { 2718105197Ssam arch = info.bfd_arch_info->arch; 2719105197Ssam mach = bfd_mach_ppc_e500; 2720105197Ssam bfd_default_set_arch_mach (&abfd, arch, mach); 2721105197Ssam info.bfd_arch_info = bfd_get_arch_info (&abfd); 2722105197Ssam } 2723105197Ssam } 2724105197Ssam 2725105197Ssam gdbarch = gdbarch_alloc (&info, tdep); 2726105197Ssam power = arch == bfd_arch_rs6000; 2727105197Ssam 2728105197Ssam /* Initialize the number of real and pseudo registers in each variant. */ 2729105197Ssam init_variants (); 2730105197Ssam 2731105197Ssam /* Choose variant. */ 2732105197Ssam v = find_variant_by_arch (arch, mach); 2733119643Ssam if (!v) 2734119643Ssam return NULL; 2735120585Ssam 2736120585Ssam tdep->regs = v->regs; 2737105197Ssam 2738105197Ssam tdep->ppc_gp0_regnum = 0; 2739105197Ssam tdep->ppc_gplast_regnum = 31; 2740105197Ssam tdep->ppc_toc_regnum = 2; 2741105197Ssam tdep->ppc_ps_regnum = 65; 2742105197Ssam tdep->ppc_cr_regnum = 66; 2743105197Ssam tdep->ppc_lr_regnum = 67; 2744105197Ssam tdep->ppc_ctr_regnum = 68; 2745119643Ssam tdep->ppc_xer_regnum = 69; 2746119643Ssam if (v->mach == bfd_mach_ppc_601) 2747105197Ssam tdep->ppc_mq_regnum = 124; 2748105197Ssam else if (power) 2749105197Ssam tdep->ppc_mq_regnum = 70; 2750105197Ssam else 2751119643Ssam tdep->ppc_mq_regnum = -1; 2752105197Ssam tdep->ppc_fpscr_regnum = power ? 71 : 70; 2753105197Ssam 2754105197Ssam set_gdbarch_pc_regnum (gdbarch, 64); 2755105197Ssam set_gdbarch_sp_regnum (gdbarch, 1); 2756119643Ssam set_gdbarch_deprecated_fp_regnum (gdbarch, 1); 2757119643Ssam if (sysv_abi && wordsize == 8) 2758105197Ssam set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); 2759105197Ssam else if (sysv_abi && wordsize == 4) 2760105197Ssam set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); 2761105197Ssam else 2762120585Ssam { 2763119643Ssam set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value); 2764105197Ssam set_gdbarch_deprecated_store_return_value (gdbarch, rs6000_store_return_value); 2765105197Ssam } 2766105197Ssam 2767105197Ssam if (v->arch == bfd_arch_powerpc) 2768105197Ssam switch (v->mach) 2769105197Ssam { 2770158767Spjd case bfd_mach_ppc: 2771105197Ssam tdep->ppc_vr0_regnum = 71; 2772119643Ssam tdep->ppc_vrsave_regnum = 104; 2773119643Ssam tdep->ppc_ev0_regnum = -1; 2774105197Ssam tdep->ppc_ev31_regnum = -1; 2775105197Ssam break; 2776105197Ssam case bfd_mach_ppc_7400: 2777105197Ssam tdep->ppc_vr0_regnum = 119; 2778120585Ssam tdep->ppc_vrsave_regnum = 152; 2779105197Ssam tdep->ppc_ev0_regnum = -1; 2780105197Ssam tdep->ppc_ev31_regnum = -1; 2781105197Ssam break; 2782105197Ssam case bfd_mach_ppc_e500: 2783105197Ssam tdep->ppc_gp0_regnum = 41; 2784105197Ssam tdep->ppc_gplast_regnum = tdep->ppc_gp0_regnum + 32 - 1; 2785105197Ssam tdep->ppc_toc_regnum = -1; 2786105197Ssam tdep->ppc_ps_regnum = 1; 2787105197Ssam tdep->ppc_cr_regnum = 2; 2788119643Ssam tdep->ppc_lr_regnum = 3; 2789105197Ssam tdep->ppc_ctr_regnum = 4; 2790117051Ssam tdep->ppc_xer_regnum = 5; 2791117051Ssam tdep->ppc_ev0_regnum = 7; 2792117051Ssam tdep->ppc_ev31_regnum = 38; 2793117051Ssam set_gdbarch_pc_regnum (gdbarch, 0); 2794117051Ssam set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); 2795117051Ssam set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); 2796117051Ssam set_gdbarch_dwarf2_reg_to_regnum (gdbarch, e500_dwarf2_reg_to_regnum); 2797117051Ssam set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); 2798120585Ssam set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); 2799117051Ssam break; 2800157123Sgnn default: 2801117051Ssam tdep->ppc_vr0_regnum = -1; 2802157123Sgnn tdep->ppc_vrsave_regnum = -1; 2803117051Ssam tdep->ppc_ev0_regnum = -1; 2804105197Ssam tdep->ppc_ev31_regnum = -1; 2805157123Sgnn break; 2806157123Sgnn } 2807119643Ssam 2808105197Ssam /* Sanity check on registers. */ 2809105197Ssam gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); 2810105197Ssam 2811157123Sgnn /* Set lr_frame_offset. */ 2812157123Sgnn if (wordsize == 8) 2813119643Ssam tdep->lr_frame_offset = 16; 2814105197Ssam else if (sysv_abi) 2815105197Ssam tdep->lr_frame_offset = 4; 2816105197Ssam else 2817105197Ssam tdep->lr_frame_offset = 8; 2818119643Ssam 2819105197Ssam /* Calculate byte offsets in raw register array. */ 2820105197Ssam tdep->regoff = xmalloc (v->num_tot_regs * sizeof (int)); 2821105197Ssam for (i = off = 0; i < v->num_tot_regs; i++) 2822119643Ssam { 2823105197Ssam tdep->regoff[i] = off; 2824105197Ssam off += regsize (v->regs + i, wordsize); 2825105197Ssam } 2826119643Ssam 2827105197Ssam /* Select instruction printer. */ 2828105197Ssam if (arch == power) 2829105197Ssam set_gdbarch_print_insn (gdbarch, print_insn_rs6000); 2830119643Ssam else 2831105197Ssam set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); 2832105197Ssam 2833105197Ssam set_gdbarch_write_pc (gdbarch, generic_target_write_pc); 2834119643Ssam 2835105197Ssam set_gdbarch_num_regs (gdbarch, v->nregs); 2836105197Ssam set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); 2837119643Ssam set_gdbarch_register_name (gdbarch, rs6000_register_name); 2838105197Ssam set_gdbarch_deprecated_register_size (gdbarch, wordsize); 2839119643Ssam set_gdbarch_deprecated_register_bytes (gdbarch, off); 2840119643Ssam set_gdbarch_deprecated_register_byte (gdbarch, rs6000_register_byte); 2841119643Ssam set_gdbarch_deprecated_register_raw_size (gdbarch, rs6000_register_raw_size); 2842119643Ssam set_gdbarch_deprecated_register_virtual_type (gdbarch, rs6000_register_virtual_type); 2843119643Ssam 2844119643Ssam set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); 2845119643Ssam set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); 2846120585Ssam set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2847120585Ssam set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); 2848105197Ssam set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2849119643Ssam set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); 2850119643Ssam set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2851119643Ssam if (sysv_abi) 2852119643Ssam set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); 2853120585Ssam else 2854119643Ssam set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 2855105197Ssam set_gdbarch_char_signed (gdbarch, 0); 2856105197Ssam 2857105197Ssam set_gdbarch_frame_align (gdbarch, rs6000_frame_align); 2858105197Ssam if (sysv_abi && wordsize == 8) 2859105197Ssam /* PPC64 SYSV. */ 2860105197Ssam set_gdbarch_frame_red_zone_size (gdbarch, 288); 2861105197Ssam else if (!sysv_abi && wordsize == 4) 2862105197Ssam /* PowerOpen / AIX 32 bit. The saved area or red zone consists of 2863105197Ssam 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes. 2864105197Ssam Problem is, 220 isn't frame (16 byte) aligned. Round it up to 2865105197Ssam 224. */ 2866105197Ssam set_gdbarch_frame_red_zone_size (gdbarch, 224); 2867105197Ssam set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); 2868105197Ssam set_gdbarch_believe_pcc_promotion (gdbarch, 1); 2869120585Ssam 2870105197Ssam set_gdbarch_deprecated_register_convertible (gdbarch, rs6000_register_convertible); 2871105197Ssam set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual); 2872105197Ssam set_gdbarch_deprecated_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw); 2873105197Ssam set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); 2874119643Ssam /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments() 2875105197Ssam is correct for the SysV ABI when the wordsize is 8, but I'm also 2876120585Ssam fairly certain that ppc_sysv_abi_push_arguments() will give even 2877105197Ssam worse results since it only works for 32-bit code. So, for the moment, 2878119643Ssam we're better off calling rs6000_push_arguments() since it works for 2879105197Ssam 64-bit code. At some point in the future, this matter needs to be 2880105197Ssam revisited. */ 2881105197Ssam if (sysv_abi && wordsize == 4) 2882105197Ssam set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); 2883105197Ssam else if (sysv_abi && wordsize == 8) 2884105197Ssam set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); 2885105197Ssam else 2886105197Ssam set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call); 2887105197Ssam 2888105197Ssam set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address); 2889105197Ssam set_gdbarch_deprecated_pop_frame (gdbarch, rs6000_pop_frame); 2890105197Ssam 2891105197Ssam set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); 2892105197Ssam set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 2893105197Ssam set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); 2894105197Ssam 2895105197Ssam /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" 2896105197Ssam for the descriptor and ".FN" for the entry-point -- a user 2897105197Ssam specifying "break FN" will unexpectedly end up with a breakpoint 2898120585Ssam on the descriptor and not the function. This architecture method 2899120585Ssam transforms any breakpoints on descriptors into breakpoints on the 2900105197Ssam corresponding entry point. */ 2901105197Ssam if (sysv_abi && wordsize == 8) 2902105197Ssam set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address); 2903119643Ssam 2904105197Ssam /* Not sure on this. FIXMEmgo */ 2905120585Ssam set_gdbarch_frame_args_skip (gdbarch, 8); 2906105197Ssam 2907105197Ssam if (!sysv_abi) 2908105197Ssam set_gdbarch_use_struct_convention (gdbarch, 2909105197Ssam rs6000_use_struct_convention); 2910105197Ssam 2911119643Ssam set_gdbarch_deprecated_frameless_function_invocation (gdbarch, rs6000_frameless_function_invocation); 2912105197Ssam set_gdbarch_deprecated_frame_chain (gdbarch, rs6000_frame_chain); 2913120585Ssam set_gdbarch_deprecated_frame_saved_pc (gdbarch, rs6000_frame_saved_pc); 2914105197Ssam 2915119643Ssam set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, rs6000_frame_init_saved_regs); 2916105197Ssam set_gdbarch_deprecated_init_extra_frame_info (gdbarch, rs6000_init_extra_frame_info); 2917105197Ssam 2918105197Ssam if (!sysv_abi) 2919105197Ssam { 2920105197Ssam /* Handle RS/6000 function pointers (which are really function 2921105197Ssam descriptors). */ 2922105197Ssam set_gdbarch_convert_from_func_ptr_addr (gdbarch, 2923105197Ssam rs6000_convert_from_func_ptr_addr); 2924105197Ssam } 2925105197Ssam set_gdbarch_deprecated_frame_args_address (gdbarch, rs6000_frame_args_address); 2926105197Ssam set_gdbarch_deprecated_frame_locals_address (gdbarch, rs6000_frame_args_address); 2927105197Ssam set_gdbarch_deprecated_saved_pc_after_call (gdbarch, rs6000_saved_pc_after_call); 2928105197Ssam 2929105197Ssam /* Helpers for function argument information. */ 2930105197Ssam set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); 2931105197Ssam 2932119643Ssam /* Hook in ABI-specific overrides, if they have been registered. */ 2933120585Ssam gdbarch_init_osabi (info, gdbarch); 2934105197Ssam 2935105197Ssam if (from_xcoff_exec) 2936105197Ssam { 2937105197Ssam /* NOTE: jimix/2003-06-09: This test should really check for 2938105197Ssam GDB_OSABI_AIX when that is defined and becomes 2939105197Ssam available. (Actually, once things are properly split apart, 2940105197Ssam the test goes away.) */ 2941105197Ssam /* RS6000/AIX does not support PT_STEP. Has to be simulated. */ 2942105197Ssam set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step); 2943105197Ssam } 2944120585Ssam 2945105197Ssam return gdbarch; 2946120585Ssam} 2947105197Ssam 2948105197Ssamstatic void 2949105197Ssamrs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) 2950105197Ssam{ 2951128859Ssam struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2952105197Ssam 2953105197Ssam if (tdep == NULL) 2954105197Ssam return; 2955128859Ssam 2956105197Ssam /* FIXME: Dump gdbarch_tdep. */ 2957105197Ssam} 2958105197Ssam 2959105197Ssamstatic struct cmd_list_element *info_powerpc_cmdlist = NULL; 2960105197Ssam 2961105197Ssamstatic void 2962105197Ssamrs6000_info_powerpc_command (char *args, int from_tty) 2963105197Ssam{ 2964105197Ssam help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout); 2965105197Ssam} 2966105197Ssam 2967105197Ssam/* Initialization code. */ 2968105197Ssam 2969105197Ssamextern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */ 2970105197Ssam 2971105197Ssamvoid 2972105197Ssam_initialize_rs6000_tdep (void) 2973105197Ssam{ 2974120585Ssam gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); 2975120585Ssam gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); 2976120585Ssam 2977105197Ssam /* Add root prefix command for "info powerpc" commands */ 2978105197Ssam add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command, 2979105197Ssam "Various POWERPC info specific commands.", 2980105197Ssam &info_powerpc_cmdlist, "info powerpc ", 0, &infolist); 2981105197Ssam} 2982105197Ssam