reload.c revision 38021
1/* Search an insn for pseudo regs that must be in hard regs and are not. 2 Copyright (C) 1987, 88, 89, 92, 93, 94, 1995 Free Software Foundation, Inc. 3 4This file is part of GNU CC. 5 6GNU CC is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 2, or (at your option) 9any later version. 10 11GNU CC is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16You should have received a copy of the GNU General Public License 17along with GNU CC; see the file COPYING. If not, write to 18the Free Software Foundation, 59 Temple Place - Suite 330, 19Boston, MA 02111-1307, USA. */ 20 21 22/* This file contains subroutines used only from the file reload1.c. 23 It knows how to scan one insn for operands and values 24 that need to be copied into registers to make valid code. 25 It also finds other operands and values which are valid 26 but for which equivalent values in registers exist and 27 ought to be used instead. 28 29 Before processing the first insn of the function, call `init_reload'. 30 31 To scan an insn, call `find_reloads'. This does two things: 32 1. sets up tables describing which values must be reloaded 33 for this insn, and what kind of hard regs they must be reloaded into; 34 2. optionally record the locations where those values appear in 35 the data, so they can be replaced properly later. 36 This is done only if the second arg to `find_reloads' is nonzero. 37 38 The third arg to `find_reloads' specifies the number of levels 39 of indirect addressing supported by the machine. If it is zero, 40 indirect addressing is not valid. If it is one, (MEM (REG n)) 41 is valid even if (REG n) did not get a hard register; if it is two, 42 (MEM (MEM (REG n))) is also valid even if (REG n) did not get a 43 hard register, and similarly for higher values. 44 45 Then you must choose the hard regs to reload those pseudo regs into, 46 and generate appropriate load insns before this insn and perhaps 47 also store insns after this insn. Set up the array `reload_reg_rtx' 48 to contain the REG rtx's for the registers you used. In some 49 cases `find_reloads' will return a nonzero value in `reload_reg_rtx' 50 for certain reloads. Then that tells you which register to use, 51 so you do not need to allocate one. But you still do need to add extra 52 instructions to copy the value into and out of that register. 53 54 Finally you must call `subst_reloads' to substitute the reload reg rtx's 55 into the locations already recorded. 56 57NOTE SIDE EFFECTS: 58 59 find_reloads can alter the operands of the instruction it is called on. 60 61 1. Two operands of any sort may be interchanged, if they are in a 62 commutative instruction. 63 This happens only if find_reloads thinks the instruction will compile 64 better that way. 65 66 2. Pseudo-registers that are equivalent to constants are replaced 67 with those constants if they are not in hard registers. 68 691 happens every time find_reloads is called. 702 happens only when REPLACE is 1, which is only when 71actually doing the reloads, not when just counting them. 72 73 74Using a reload register for several reloads in one insn: 75 76When an insn has reloads, it is considered as having three parts: 77the input reloads, the insn itself after reloading, and the output reloads. 78Reloads of values used in memory addresses are often needed for only one part. 79 80When this is so, reload_when_needed records which part needs the reload. 81Two reloads for different parts of the insn can share the same reload 82register. 83 84When a reload is used for addresses in multiple parts, or when it is 85an ordinary operand, it is classified as RELOAD_OTHER, and cannot share 86a register with any other reload. */ 87 88#define REG_OK_STRICT 89 90#include <stdio.h> 91#include "config.h" 92#include "rtl.h" 93#include "insn-config.h" 94#include "insn-codes.h" 95#include "recog.h" 96#include "reload.h" 97#include "regs.h" 98#include "hard-reg-set.h" 99#include "flags.h" 100#include "real.h" 101#include "output.h" 102 103#ifndef REGISTER_MOVE_COST 104#define REGISTER_MOVE_COST(x, y) 2 105#endif 106 107/* The variables set up by `find_reloads' are: 108 109 n_reloads number of distinct reloads needed; max reload # + 1 110 tables indexed by reload number 111 reload_in rtx for value to reload from 112 reload_out rtx for where to store reload-reg afterward if nec 113 (often the same as reload_in) 114 reload_reg_class enum reg_class, saying what regs to reload into 115 reload_inmode enum machine_mode; mode this operand should have 116 when reloaded, on input. 117 reload_outmode enum machine_mode; mode this operand should have 118 when reloaded, on output. 119 reload_optional char, nonzero for an optional reload. 120 Optional reloads are ignored unless the 121 value is already sitting in a register. 122 reload_inc int, positive amount to increment or decrement by if 123 reload_in is a PRE_DEC, PRE_INC, POST_DEC, POST_INC. 124 Ignored otherwise (don't assume it is zero). 125 reload_in_reg rtx. A reg for which reload_in is the equivalent. 126 If reload_in is a symbol_ref which came from 127 reg_equiv_constant, then this is the pseudo 128 which has that symbol_ref as equivalent. 129 reload_reg_rtx rtx. This is the register to reload into. 130 If it is zero when `find_reloads' returns, 131 you must find a suitable register in the class 132 specified by reload_reg_class, and store here 133 an rtx for that register with mode from 134 reload_inmode or reload_outmode. 135 reload_nocombine char, nonzero if this reload shouldn't be 136 combined with another reload. 137 reload_opnum int, operand number being reloaded. This is 138 used to group related reloads and need not always 139 be equal to the actual operand number in the insn, 140 though it current will be; for in-out operands, it 141 is one of the two operand numbers. 142 reload_when_needed enum, classifies reload as needed either for 143 addressing an input reload, addressing an output, 144 for addressing a non-reloaded mem ref, 145 or for unspecified purposes (i.e., more than one 146 of the above). 147 reload_secondary_p int, 1 if this is a secondary register for one 148 or more reloads. 149 reload_secondary_in_reload 150 reload_secondary_out_reload 151 int, gives the reload number of a secondary 152 reload, when needed; otherwise -1 153 reload_secondary_in_icode 154 reload_secondary_out_icode 155 enum insn_code, if a secondary reload is required, 156 gives the INSN_CODE that uses the secondary 157 reload as a scratch register, or CODE_FOR_nothing 158 if the secondary reload register is to be an 159 intermediate register. */ 160int n_reloads; 161 162rtx reload_in[MAX_RELOADS]; 163rtx reload_out[MAX_RELOADS]; 164enum reg_class reload_reg_class[MAX_RELOADS]; 165enum machine_mode reload_inmode[MAX_RELOADS]; 166enum machine_mode reload_outmode[MAX_RELOADS]; 167rtx reload_reg_rtx[MAX_RELOADS]; 168char reload_optional[MAX_RELOADS]; 169int reload_inc[MAX_RELOADS]; 170rtx reload_in_reg[MAX_RELOADS]; 171char reload_nocombine[MAX_RELOADS]; 172int reload_opnum[MAX_RELOADS]; 173enum reload_type reload_when_needed[MAX_RELOADS]; 174int reload_secondary_p[MAX_RELOADS]; 175int reload_secondary_in_reload[MAX_RELOADS]; 176int reload_secondary_out_reload[MAX_RELOADS]; 177enum insn_code reload_secondary_in_icode[MAX_RELOADS]; 178enum insn_code reload_secondary_out_icode[MAX_RELOADS]; 179 180/* All the "earlyclobber" operands of the current insn 181 are recorded here. */ 182int n_earlyclobbers; 183rtx reload_earlyclobbers[MAX_RECOG_OPERANDS]; 184 185int reload_n_operands; 186 187/* Replacing reloads. 188 189 If `replace_reloads' is nonzero, then as each reload is recorded 190 an entry is made for it in the table `replacements'. 191 Then later `subst_reloads' can look through that table and 192 perform all the replacements needed. */ 193 194/* Nonzero means record the places to replace. */ 195static int replace_reloads; 196 197/* Each replacement is recorded with a structure like this. */ 198struct replacement 199{ 200 rtx *where; /* Location to store in */ 201 rtx *subreg_loc; /* Location of SUBREG if WHERE is inside 202 a SUBREG; 0 otherwise. */ 203 int what; /* which reload this is for */ 204 enum machine_mode mode; /* mode it must have */ 205}; 206 207static struct replacement replacements[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; 208 209/* Number of replacements currently recorded. */ 210static int n_replacements; 211 212/* Used to track what is modified by an operand. */ 213struct decomposition 214{ 215 int reg_flag; /* Nonzero if referencing a register. */ 216 int safe; /* Nonzero if this can't conflict with anything. */ 217 rtx base; /* Base address for MEM. */ 218 HOST_WIDE_INT start; /* Starting offset or register number. */ 219 HOST_WIDE_INT end; /* Ending offset or register number. */ 220}; 221 222/* MEM-rtx's created for pseudo-regs in stack slots not directly addressable; 223 (see reg_equiv_address). */ 224static rtx memlocs[MAX_RECOG_OPERANDS * ((MAX_REGS_PER_ADDRESS * 2) + 1)]; 225static int n_memlocs; 226 227#ifdef SECONDARY_MEMORY_NEEDED 228 229/* Save MEMs needed to copy from one class of registers to another. One MEM 230 is used per mode, but normally only one or two modes are ever used. 231 232 We keep two versions, before and after register elimination. The one 233 after register elimination is record separately for each operand. This 234 is done in case the address is not valid to be sure that we separately 235 reload each. */ 236 237static rtx secondary_memlocs[NUM_MACHINE_MODES]; 238static rtx secondary_memlocs_elim[NUM_MACHINE_MODES][MAX_RECOG_OPERANDS]; 239#endif 240 241/* The instruction we are doing reloads for; 242 so we can test whether a register dies in it. */ 243static rtx this_insn; 244 245/* Nonzero if this instruction is a user-specified asm with operands. */ 246static int this_insn_is_asm; 247 248/* If hard_regs_live_known is nonzero, 249 we can tell which hard regs are currently live, 250 at least enough to succeed in choosing dummy reloads. */ 251static int hard_regs_live_known; 252 253/* Indexed by hard reg number, 254 element is nonegative if hard reg has been spilled. 255 This vector is passed to `find_reloads' as an argument 256 and is not changed here. */ 257static short *static_reload_reg_p; 258 259/* Set to 1 in subst_reg_equivs if it changes anything. */ 260static int subst_reg_equivs_changed; 261 262/* On return from push_reload, holds the reload-number for the OUT 263 operand, which can be different for that from the input operand. */ 264static int output_reloadnum; 265 266 /* Compare two RTX's. */ 267#define MATCHES(x, y) \ 268 (x == y || (x != 0 && (GET_CODE (x) == REG \ 269 ? GET_CODE (y) == REG && REGNO (x) == REGNO (y) \ 270 : rtx_equal_p (x, y) && ! side_effects_p (x)))) 271 272 /* Indicates if two reloads purposes are for similar enough things that we 273 can merge their reloads. */ 274#define MERGABLE_RELOADS(when1, when2, op1, op2) \ 275 ((when1) == RELOAD_OTHER || (when2) == RELOAD_OTHER \ 276 || ((when1) == (when2) && (op1) == (op2)) \ 277 || ((when1) == RELOAD_FOR_INPUT && (when2) == RELOAD_FOR_INPUT) \ 278 || ((when1) == RELOAD_FOR_OPERAND_ADDRESS \ 279 && (when2) == RELOAD_FOR_OPERAND_ADDRESS) \ 280 || ((when1) == RELOAD_FOR_OTHER_ADDRESS \ 281 && (when2) == RELOAD_FOR_OTHER_ADDRESS)) 282 283 /* Nonzero if these two reload purposes produce RELOAD_OTHER when merged. */ 284#define MERGE_TO_OTHER(when1, when2, op1, op2) \ 285 ((when1) != (when2) \ 286 || ! ((op1) == (op2) \ 287 || (when1) == RELOAD_FOR_INPUT \ 288 || (when1) == RELOAD_FOR_OPERAND_ADDRESS \ 289 || (when1) == RELOAD_FOR_OTHER_ADDRESS)) 290 291static int push_secondary_reload PROTO((int, rtx, int, int, enum reg_class, 292 enum machine_mode, enum reload_type, 293 enum insn_code *)); 294static int push_reload PROTO((rtx, rtx, rtx *, rtx *, enum reg_class, 295 enum machine_mode, enum machine_mode, 296 int, int, int, enum reload_type)); 297static void push_replacement PROTO((rtx *, int, enum machine_mode)); 298static void combine_reloads PROTO((void)); 299static rtx find_dummy_reload PROTO((rtx, rtx, rtx *, rtx *, 300 enum machine_mode, enum machine_mode, 301 enum reg_class, int)); 302static int earlyclobber_operand_p PROTO((rtx)); 303static int hard_reg_set_here_p PROTO((int, int, rtx)); 304static struct decomposition decompose PROTO((rtx)); 305static int immune_p PROTO((rtx, rtx, struct decomposition)); 306static int alternative_allows_memconst PROTO((char *, int)); 307static rtx find_reloads_toplev PROTO((rtx, int, enum reload_type, int, int)); 308static rtx make_memloc PROTO((rtx, int)); 309static int find_reloads_address PROTO((enum machine_mode, rtx *, rtx, rtx *, 310 int, enum reload_type, int)); 311static rtx subst_reg_equivs PROTO((rtx)); 312static rtx subst_indexed_address PROTO((rtx)); 313static int find_reloads_address_1 PROTO((rtx, int, rtx *, int, 314 enum reload_type,int)); 315static void find_reloads_address_part PROTO((rtx, rtx *, enum reg_class, 316 enum machine_mode, int, 317 enum reload_type, int)); 318static int find_inc_amount PROTO((rtx, rtx)); 319 320#ifdef HAVE_SECONDARY_RELOADS 321 322/* Determine if any secondary reloads are needed for loading (if IN_P is 323 non-zero) or storing (if IN_P is zero) X to or from a reload register of 324 register class RELOAD_CLASS in mode RELOAD_MODE. If secondary reloads 325 are needed, push them. 326 327 Return the reload number of the secondary reload we made, or -1 if 328 we didn't need one. *PICODE is set to the insn_code to use if we do 329 need a secondary reload. */ 330 331static int 332push_secondary_reload (in_p, x, opnum, optional, reload_class, reload_mode, 333 type, picode) 334 int in_p; 335 rtx x; 336 int opnum; 337 int optional; 338 enum reg_class reload_class; 339 enum machine_mode reload_mode; 340 enum reload_type type; 341 enum insn_code *picode; 342{ 343 enum reg_class class = NO_REGS; 344 enum machine_mode mode = reload_mode; 345 enum insn_code icode = CODE_FOR_nothing; 346 enum reg_class t_class = NO_REGS; 347 enum machine_mode t_mode = VOIDmode; 348 enum insn_code t_icode = CODE_FOR_nothing; 349 enum reload_type secondary_type; 350 int i; 351 int s_reload, t_reload = -1; 352 353 if (type == RELOAD_FOR_INPUT_ADDRESS || type == RELOAD_FOR_OUTPUT_ADDRESS) 354 secondary_type = type; 355 else 356 secondary_type = in_p ? RELOAD_FOR_INPUT_ADDRESS : RELOAD_FOR_OUTPUT_ADDRESS; 357 358 *picode = CODE_FOR_nothing; 359 360 /* If X is a paradoxical SUBREG, use the inner value to determine both the 361 mode and object being reloaded. */ 362 if (GET_CODE (x) == SUBREG 363 && (GET_MODE_SIZE (GET_MODE (x)) 364 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) 365 { 366 x = SUBREG_REG (x); 367 reload_mode = GET_MODE (x); 368 } 369 370 /* If X is a pseudo-register that has an equivalent MEM (actually, if it 371 is still a pseudo-register by now, it *must* have an equivalent MEM 372 but we don't want to assume that), use that equivalent when seeing if 373 a secondary reload is needed since whether or not a reload is needed 374 might be sensitive to the form of the MEM. */ 375 376 if (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER 377 && reg_equiv_mem[REGNO (x)] != 0) 378 x = reg_equiv_mem[REGNO (x)]; 379 380#ifdef SECONDARY_INPUT_RELOAD_CLASS 381 if (in_p) 382 class = SECONDARY_INPUT_RELOAD_CLASS (reload_class, reload_mode, x); 383#endif 384 385#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 386 if (! in_p) 387 class = SECONDARY_OUTPUT_RELOAD_CLASS (reload_class, reload_mode, x); 388#endif 389 390 /* If we don't need any secondary registers, done. */ 391 if (class == NO_REGS) 392 return -1; 393 394 /* Get a possible insn to use. If the predicate doesn't accept X, don't 395 use the insn. */ 396 397 icode = (in_p ? reload_in_optab[(int) reload_mode] 398 : reload_out_optab[(int) reload_mode]); 399 400 if (icode != CODE_FOR_nothing 401 && insn_operand_predicate[(int) icode][in_p] 402 && (! (insn_operand_predicate[(int) icode][in_p]) (x, reload_mode))) 403 icode = CODE_FOR_nothing; 404 405 /* If we will be using an insn, see if it can directly handle the reload 406 register we will be using. If it can, the secondary reload is for a 407 scratch register. If it can't, we will use the secondary reload for 408 an intermediate register and require a tertiary reload for the scratch 409 register. */ 410 411 if (icode != CODE_FOR_nothing) 412 { 413 /* If IN_P is non-zero, the reload register will be the output in 414 operand 0. If IN_P is zero, the reload register will be the input 415 in operand 1. Outputs should have an initial "=", which we must 416 skip. */ 417 418 char insn_letter = insn_operand_constraint[(int) icode][!in_p][in_p]; 419 enum reg_class insn_class 420 = (insn_letter == 'r' ? GENERAL_REGS 421 : REG_CLASS_FROM_LETTER (insn_letter)); 422 423 if (insn_class == NO_REGS 424 || (in_p && insn_operand_constraint[(int) icode][!in_p][0] != '=') 425 /* The scratch register's constraint must start with "=&". */ 426 || insn_operand_constraint[(int) icode][2][0] != '=' 427 || insn_operand_constraint[(int) icode][2][1] != '&') 428 abort (); 429 430 if (reg_class_subset_p (reload_class, insn_class)) 431 mode = insn_operand_mode[(int) icode][2]; 432 else 433 { 434 char t_letter = insn_operand_constraint[(int) icode][2][2]; 435 class = insn_class; 436 t_mode = insn_operand_mode[(int) icode][2]; 437 t_class = (t_letter == 'r' ? GENERAL_REGS 438 : REG_CLASS_FROM_LETTER (t_letter)); 439 t_icode = icode; 440 icode = CODE_FOR_nothing; 441 } 442 } 443 444 /* This case isn't valid, so fail. Reload is allowed to use the same 445 register for RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT reloads, but 446 in the case of a secondary register, we actually need two different 447 registers for correct code. We fail here to prevent the possibility of 448 silently generating incorrect code later. 449 450 The convention is that secondary input reloads are valid only if the 451 secondary_class is different from class. If you have such a case, you 452 can not use secondary reloads, you must work around the problem some 453 other way. 454 455 Allow this when MODE is not reload_mode and assume that the generated 456 code handles this case (it does on the Alpha, which is the only place 457 this currently happens). */ 458 459 if (in_p && class == reload_class && mode == reload_mode) 460 abort (); 461 462 /* If we need a tertiary reload, see if we have one we can reuse or else 463 make a new one. */ 464 465 if (t_class != NO_REGS) 466 { 467 for (t_reload = 0; t_reload < n_reloads; t_reload++) 468 if (reload_secondary_p[t_reload] 469 && (reg_class_subset_p (t_class, reload_reg_class[t_reload]) 470 || reg_class_subset_p (reload_reg_class[t_reload], t_class)) 471 && ((in_p && reload_inmode[t_reload] == t_mode) 472 || (! in_p && reload_outmode[t_reload] == t_mode)) 473 && ((in_p && (reload_secondary_in_icode[t_reload] 474 == CODE_FOR_nothing)) 475 || (! in_p &&(reload_secondary_out_icode[t_reload] 476 == CODE_FOR_nothing))) 477 && (reg_class_size[(int) t_class] == 1 478#ifdef SMALL_REGISTER_CLASSES 479 || 1 480#endif 481 ) 482 && MERGABLE_RELOADS (secondary_type, 483 reload_when_needed[t_reload], 484 opnum, reload_opnum[t_reload])) 485 { 486 if (in_p) 487 reload_inmode[t_reload] = t_mode; 488 if (! in_p) 489 reload_outmode[t_reload] = t_mode; 490 491 if (reg_class_subset_p (t_class, reload_reg_class[t_reload])) 492 reload_reg_class[t_reload] = t_class; 493 494 reload_opnum[t_reload] = MIN (reload_opnum[t_reload], opnum); 495 reload_optional[t_reload] &= optional; 496 reload_secondary_p[t_reload] = 1; 497 if (MERGE_TO_OTHER (secondary_type, reload_when_needed[t_reload], 498 opnum, reload_opnum[t_reload])) 499 reload_when_needed[t_reload] = RELOAD_OTHER; 500 } 501 502 if (t_reload == n_reloads) 503 { 504 /* We need to make a new tertiary reload for this register class. */ 505 reload_in[t_reload] = reload_out[t_reload] = 0; 506 reload_reg_class[t_reload] = t_class; 507 reload_inmode[t_reload] = in_p ? t_mode : VOIDmode; 508 reload_outmode[t_reload] = ! in_p ? t_mode : VOIDmode; 509 reload_reg_rtx[t_reload] = 0; 510 reload_optional[t_reload] = optional; 511 reload_inc[t_reload] = 0; 512 /* Maybe we could combine these, but it seems too tricky. */ 513 reload_nocombine[t_reload] = 1; 514 reload_in_reg[t_reload] = 0; 515 reload_opnum[t_reload] = opnum; 516 reload_when_needed[t_reload] = secondary_type; 517 reload_secondary_in_reload[t_reload] = -1; 518 reload_secondary_out_reload[t_reload] = -1; 519 reload_secondary_in_icode[t_reload] = CODE_FOR_nothing; 520 reload_secondary_out_icode[t_reload] = CODE_FOR_nothing; 521 reload_secondary_p[t_reload] = 1; 522 523 n_reloads++; 524 } 525 } 526 527 /* See if we can reuse an existing secondary reload. */ 528 for (s_reload = 0; s_reload < n_reloads; s_reload++) 529 if (reload_secondary_p[s_reload] 530 && (reg_class_subset_p (class, reload_reg_class[s_reload]) 531 || reg_class_subset_p (reload_reg_class[s_reload], class)) 532 && ((in_p && reload_inmode[s_reload] == mode) 533 || (! in_p && reload_outmode[s_reload] == mode)) 534 && ((in_p && reload_secondary_in_reload[s_reload] == t_reload) 535 || (! in_p && reload_secondary_out_reload[s_reload] == t_reload)) 536 && ((in_p && reload_secondary_in_icode[s_reload] == t_icode) 537 || (! in_p && reload_secondary_out_icode[s_reload] == t_icode)) 538 && (reg_class_size[(int) class] == 1 539#ifdef SMALL_REGISTER_CLASSES 540 || 1 541#endif 542 ) 543 && MERGABLE_RELOADS (secondary_type, reload_when_needed[s_reload], 544 opnum, reload_opnum[s_reload])) 545 { 546 if (in_p) 547 reload_inmode[s_reload] = mode; 548 if (! in_p) 549 reload_outmode[s_reload] = mode; 550 551 if (reg_class_subset_p (class, reload_reg_class[s_reload])) 552 reload_reg_class[s_reload] = class; 553 554 reload_opnum[s_reload] = MIN (reload_opnum[s_reload], opnum); 555 reload_optional[s_reload] &= optional; 556 reload_secondary_p[s_reload] = 1; 557 if (MERGE_TO_OTHER (secondary_type, reload_when_needed[s_reload], 558 opnum, reload_opnum[s_reload])) 559 reload_when_needed[s_reload] = RELOAD_OTHER; 560 } 561 562 if (s_reload == n_reloads) 563 { 564 /* We need to make a new secondary reload for this register class. */ 565 reload_in[s_reload] = reload_out[s_reload] = 0; 566 reload_reg_class[s_reload] = class; 567 568 reload_inmode[s_reload] = in_p ? mode : VOIDmode; 569 reload_outmode[s_reload] = ! in_p ? mode : VOIDmode; 570 reload_reg_rtx[s_reload] = 0; 571 reload_optional[s_reload] = optional; 572 reload_inc[s_reload] = 0; 573 /* Maybe we could combine these, but it seems too tricky. */ 574 reload_nocombine[s_reload] = 1; 575 reload_in_reg[s_reload] = 0; 576 reload_opnum[s_reload] = opnum; 577 reload_when_needed[s_reload] = secondary_type; 578 reload_secondary_in_reload[s_reload] = in_p ? t_reload : -1; 579 reload_secondary_out_reload[s_reload] = ! in_p ? t_reload : -1; 580 reload_secondary_in_icode[s_reload] = in_p ? t_icode : CODE_FOR_nothing; 581 reload_secondary_out_icode[s_reload] 582 = ! in_p ? t_icode : CODE_FOR_nothing; 583 reload_secondary_p[s_reload] = 1; 584 585 n_reloads++; 586 587#ifdef SECONDARY_MEMORY_NEEDED 588 /* If we need a memory location to copy between the two reload regs, 589 set it up now. */ 590 591 if (in_p && icode == CODE_FOR_nothing 592 && SECONDARY_MEMORY_NEEDED (class, reload_class, reload_mode)) 593 get_secondary_mem (x, reload_mode, opnum, type); 594 595 if (! in_p && icode == CODE_FOR_nothing 596 && SECONDARY_MEMORY_NEEDED (reload_class, class, reload_mode)) 597 get_secondary_mem (x, reload_mode, opnum, type); 598#endif 599 } 600 601 *picode = icode; 602 return s_reload; 603} 604#endif /* HAVE_SECONDARY_RELOADS */ 605 606#ifdef SECONDARY_MEMORY_NEEDED 607 608/* Return a memory location that will be used to copy X in mode MODE. 609 If we haven't already made a location for this mode in this insn, 610 call find_reloads_address on the location being returned. */ 611 612rtx 613get_secondary_mem (x, mode, opnum, type) 614 rtx x; 615 enum machine_mode mode; 616 int opnum; 617 enum reload_type type; 618{ 619 rtx loc; 620 int mem_valid; 621 622 /* By default, if MODE is narrower than a word, widen it to a word. 623 This is required because most machines that require these memory 624 locations do not support short load and stores from all registers 625 (e.g., FP registers). */ 626 627#ifdef SECONDARY_MEMORY_NEEDED_MODE 628 mode = SECONDARY_MEMORY_NEEDED_MODE (mode); 629#else 630 if (GET_MODE_BITSIZE (mode) < BITS_PER_WORD) 631 mode = mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0); 632#endif 633 634 /* If we already have made a MEM for this operand in MODE, return it. */ 635 if (secondary_memlocs_elim[(int) mode][opnum] != 0) 636 return secondary_memlocs_elim[(int) mode][opnum]; 637 638 /* If this is the first time we've tried to get a MEM for this mode, 639 allocate a new one. `something_changed' in reload will get set 640 by noticing that the frame size has changed. */ 641 642 if (secondary_memlocs[(int) mode] == 0) 643 { 644#ifdef SECONDARY_MEMORY_NEEDED_RTX 645 secondary_memlocs[(int) mode] = SECONDARY_MEMORY_NEEDED_RTX (mode); 646#else 647 secondary_memlocs[(int) mode] 648 = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); 649#endif 650 } 651 652 /* Get a version of the address doing any eliminations needed. If that 653 didn't give us a new MEM, make a new one if it isn't valid. */ 654 655 loc = eliminate_regs (secondary_memlocs[(int) mode], VOIDmode, NULL_RTX); 656 mem_valid = strict_memory_address_p (mode, XEXP (loc, 0)); 657 658 if (! mem_valid && loc == secondary_memlocs[(int) mode]) 659 loc = copy_rtx (loc); 660 661 /* The only time the call below will do anything is if the stack 662 offset is too large. In that case IND_LEVELS doesn't matter, so we 663 can just pass a zero. Adjust the type to be the address of the 664 corresponding object. If the address was valid, save the eliminated 665 address. If it wasn't valid, we need to make a reload each time, so 666 don't save it. */ 667 668 if (! mem_valid) 669 { 670 type = (type == RELOAD_FOR_INPUT ? RELOAD_FOR_INPUT_ADDRESS 671 : type == RELOAD_FOR_OUTPUT ? RELOAD_FOR_OUTPUT_ADDRESS 672 : RELOAD_OTHER); 673 674 find_reloads_address (mode, NULL_PTR, XEXP (loc, 0), &XEXP (loc, 0), 675 opnum, type, 0); 676 } 677 678 secondary_memlocs_elim[(int) mode][opnum] = loc; 679 return loc; 680} 681 682/* Clear any secondary memory locations we've made. */ 683 684void 685clear_secondary_mem () 686{ 687 bzero ((char *) secondary_memlocs, sizeof secondary_memlocs); 688} 689#endif /* SECONDARY_MEMORY_NEEDED */ 690 691/* Record one reload that needs to be performed. 692 IN is an rtx saying where the data are to be found before this instruction. 693 OUT says where they must be stored after the instruction. 694 (IN is zero for data not read, and OUT is zero for data not written.) 695 INLOC and OUTLOC point to the places in the instructions where 696 IN and OUT were found. 697 If IN and OUT are both non-zero, it means the same register must be used 698 to reload both IN and OUT. 699 700 CLASS is a register class required for the reloaded data. 701 INMODE is the machine mode that the instruction requires 702 for the reg that replaces IN and OUTMODE is likewise for OUT. 703 704 If IN is zero, then OUT's location and mode should be passed as 705 INLOC and INMODE. 706 707 STRICT_LOW is the 1 if there is a containing STRICT_LOW_PART rtx. 708 709 OPTIONAL nonzero means this reload does not need to be performed: 710 it can be discarded if that is more convenient. 711 712 OPNUM and TYPE say what the purpose of this reload is. 713 714 The return value is the reload-number for this reload. 715 716 If both IN and OUT are nonzero, in some rare cases we might 717 want to make two separate reloads. (Actually we never do this now.) 718 Therefore, the reload-number for OUT is stored in 719 output_reloadnum when we return; the return value applies to IN. 720 Usually (presently always), when IN and OUT are nonzero, 721 the two reload-numbers are equal, but the caller should be careful to 722 distinguish them. */ 723 724static int 725push_reload (in, out, inloc, outloc, class, 726 inmode, outmode, strict_low, optional, opnum, type) 727 register rtx in, out; 728 rtx *inloc, *outloc; 729 enum reg_class class; 730 enum machine_mode inmode, outmode; 731 int strict_low; 732 int optional; 733 int opnum; 734 enum reload_type type; 735{ 736 register int i; 737 int dont_share = 0; 738 int dont_remove_subreg = 0; 739 rtx *in_subreg_loc = 0, *out_subreg_loc = 0; 740 int secondary_in_reload = -1, secondary_out_reload = -1; 741 enum insn_code secondary_in_icode = CODE_FOR_nothing; 742 enum insn_code secondary_out_icode = CODE_FOR_nothing; 743 744 /* INMODE and/or OUTMODE could be VOIDmode if no mode 745 has been specified for the operand. In that case, 746 use the operand's mode as the mode to reload. */ 747 if (inmode == VOIDmode && in != 0) 748 inmode = GET_MODE (in); 749 if (outmode == VOIDmode && out != 0) 750 outmode = GET_MODE (out); 751 752 /* If IN is a pseudo register everywhere-equivalent to a constant, and 753 it is not in a hard register, reload straight from the constant, 754 since we want to get rid of such pseudo registers. 755 Often this is done earlier, but not always in find_reloads_address. */ 756 if (in != 0 && GET_CODE (in) == REG) 757 { 758 register int regno = REGNO (in); 759 760 if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 761 && reg_equiv_constant[regno] != 0) 762 in = reg_equiv_constant[regno]; 763 } 764 765 /* Likewise for OUT. Of course, OUT will never be equivalent to 766 an actual constant, but it might be equivalent to a memory location 767 (in the case of a parameter). */ 768 if (out != 0 && GET_CODE (out) == REG) 769 { 770 register int regno = REGNO (out); 771 772 if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 773 && reg_equiv_constant[regno] != 0) 774 out = reg_equiv_constant[regno]; 775 } 776 777 /* If we have a read-write operand with an address side-effect, 778 change either IN or OUT so the side-effect happens only once. */ 779 if (in != 0 && out != 0 && GET_CODE (in) == MEM && rtx_equal_p (in, out)) 780 { 781 if (GET_CODE (XEXP (in, 0)) == POST_INC 782 || GET_CODE (XEXP (in, 0)) == POST_DEC) 783 in = gen_rtx (MEM, GET_MODE (in), XEXP (XEXP (in, 0), 0)); 784 if (GET_CODE (XEXP (in, 0)) == PRE_INC 785 || GET_CODE (XEXP (in, 0)) == PRE_DEC) 786 out = gen_rtx (MEM, GET_MODE (out), XEXP (XEXP (out, 0), 0)); 787 } 788 789 /* If we are reloading a (SUBREG constant ...), really reload just the 790 inside expression in its own mode. Similarly for (SUBREG (PLUS ...)). 791 If we have (SUBREG:M1 (MEM:M2 ...) ...) (or an inner REG that is still 792 a pseudo and hence will become a MEM) with M1 wider than M2 and the 793 register is a pseudo, also reload the inside expression. 794 For machines that extend byte loads, do this for any SUBREG of a pseudo 795 where both M1 and M2 are a word or smaller, M1 is wider than M2, and 796 M2 is an integral mode that gets extended when loaded. 797 Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where 798 either M1 is not valid for R or M2 is wider than a word but we only 799 need one word to store an M2-sized quantity in R. 800 (However, if OUT is nonzero, we need to reload the reg *and* 801 the subreg, so do nothing here, and let following statement handle it.) 802 803 Note that the case of (SUBREG (CONST_INT...)...) is handled elsewhere; 804 we can't handle it here because CONST_INT does not indicate a mode. 805 806 Similarly, we must reload the inside expression if we have a 807 STRICT_LOW_PART (presumably, in == out in the cas). 808 809 Also reload the inner expression if it does not require a secondary 810 reload but the SUBREG does. 811 812 Finally, reload the inner expression if it is a register that is in 813 the class whose registers cannot be referenced in a different size 814 and M1 is not the same size as M2. If SUBREG_WORD is nonzero, we 815 cannot reload just the inside since we might end up with the wrong 816 register class. */ 817 818 if (in != 0 && GET_CODE (in) == SUBREG && SUBREG_WORD (in) == 0 819#ifdef CLASS_CANNOT_CHANGE_SIZE 820 && class != CLASS_CANNOT_CHANGE_SIZE 821#endif 822 && (CONSTANT_P (SUBREG_REG (in)) 823 || GET_CODE (SUBREG_REG (in)) == PLUS 824 || strict_low 825 || (((GET_CODE (SUBREG_REG (in)) == REG 826 && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER) 827 || GET_CODE (SUBREG_REG (in)) == MEM) 828 && ((GET_MODE_SIZE (inmode) 829 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) 830#ifdef LOAD_EXTEND_OP 831 || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD 832 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) 833 <= UNITS_PER_WORD) 834 && (GET_MODE_SIZE (inmode) 835 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) 836 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in))) 837 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != NIL) 838#endif 839 )) 840 || (GET_CODE (SUBREG_REG (in)) == REG 841 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER 842 /* The case where out is nonzero 843 is handled differently in the following statement. */ 844 && (out == 0 || SUBREG_WORD (in) == 0) 845 && ((GET_MODE_SIZE (inmode) <= UNITS_PER_WORD 846 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) 847 > UNITS_PER_WORD) 848 && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) 849 / UNITS_PER_WORD) 850 != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)), 851 GET_MODE (SUBREG_REG (in))))) 852 || ! HARD_REGNO_MODE_OK ((REGNO (SUBREG_REG (in)) 853 + SUBREG_WORD (in)), 854 inmode))) 855#ifdef SECONDARY_INPUT_RELOAD_CLASS 856 || (SECONDARY_INPUT_RELOAD_CLASS (class, inmode, in) != NO_REGS 857 && (SECONDARY_INPUT_RELOAD_CLASS (class, 858 GET_MODE (SUBREG_REG (in)), 859 SUBREG_REG (in)) 860 == NO_REGS)) 861#endif 862#ifdef CLASS_CANNOT_CHANGE_SIZE 863 || (GET_CODE (SUBREG_REG (in)) == REG 864 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER 865 && (TEST_HARD_REG_BIT 866 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], 867 REGNO (SUBREG_REG (in)))) 868 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) 869 != GET_MODE_SIZE (inmode))) 870#endif 871 )) 872 { 873 in_subreg_loc = inloc; 874 inloc = &SUBREG_REG (in); 875 in = *inloc; 876#ifndef LOAD_EXTEND_OP 877 if (GET_CODE (in) == MEM) 878 /* This is supposed to happen only for paradoxical subregs made by 879 combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */ 880 if (GET_MODE_SIZE (GET_MODE (in)) > GET_MODE_SIZE (inmode)) 881 abort (); 882#endif 883 inmode = GET_MODE (in); 884 } 885 886 /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where 887 either M1 is not valid for R or M2 is wider than a word but we only 888 need one word to store an M2-sized quantity in R. 889 890 However, we must reload the inner reg *as well as* the subreg in 891 that case. */ 892 893 if (in != 0 && GET_CODE (in) == SUBREG 894 && GET_CODE (SUBREG_REG (in)) == REG 895 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER 896 && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (in)), inmode) 897 || (GET_MODE_SIZE (inmode) <= UNITS_PER_WORD 898 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) 899 > UNITS_PER_WORD) 900 && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) 901 / UNITS_PER_WORD) 902 != HARD_REGNO_NREGS (REGNO (SUBREG_REG (in)), 903 GET_MODE (SUBREG_REG (in))))))) 904 { 905 /* This relies on the fact that emit_reload_insns outputs the 906 instructions for input reloads of type RELOAD_OTHER in the same 907 order as the reloads. Thus if the outer reload is also of type 908 RELOAD_OTHER, we are guaranteed that this inner reload will be 909 output before the outer reload. */ 910 push_reload (SUBREG_REG (in), NULL_RTX, &SUBREG_REG (in), NULL_PTR, 911 GENERAL_REGS, VOIDmode, VOIDmode, 0, 0, opnum, type); 912 dont_remove_subreg = 1; 913 } 914 915 916 /* Similarly for paradoxical and problematical SUBREGs on the output. 917 Note that there is no reason we need worry about the previous value 918 of SUBREG_REG (out); even if wider than out, 919 storing in a subreg is entitled to clobber it all 920 (except in the case of STRICT_LOW_PART, 921 and in that case the constraint should label it input-output.) */ 922 if (out != 0 && GET_CODE (out) == SUBREG && SUBREG_WORD (out) == 0 923#ifdef CLASS_CANNOT_CHANGE_SIZE 924 && class != CLASS_CANNOT_CHANGE_SIZE 925#endif 926 && (CONSTANT_P (SUBREG_REG (out)) 927 || strict_low 928 || (((GET_CODE (SUBREG_REG (out)) == REG 929 && REGNO (SUBREG_REG (out)) >= FIRST_PSEUDO_REGISTER) 930 || GET_CODE (SUBREG_REG (out)) == MEM) 931 && ((GET_MODE_SIZE (outmode) 932 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))))) 933 || (GET_CODE (SUBREG_REG (out)) == REG 934 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER 935 && ((GET_MODE_SIZE (outmode) <= UNITS_PER_WORD 936 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) 937 > UNITS_PER_WORD) 938 && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) 939 / UNITS_PER_WORD) 940 != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)), 941 GET_MODE (SUBREG_REG (out))))) 942 || ! HARD_REGNO_MODE_OK ((REGNO (SUBREG_REG (out)) 943 + SUBREG_WORD (out)), 944 outmode))) 945#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 946 || (SECONDARY_OUTPUT_RELOAD_CLASS (class, outmode, out) != NO_REGS 947 && (SECONDARY_OUTPUT_RELOAD_CLASS (class, 948 GET_MODE (SUBREG_REG (out)), 949 SUBREG_REG (out)) 950 == NO_REGS)) 951#endif 952#ifdef CLASS_CANNOT_CHANGE_SIZE 953 || (GET_CODE (SUBREG_REG (out)) == REG 954 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER 955 && (TEST_HARD_REG_BIT 956 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE], 957 REGNO (SUBREG_REG (out)))) 958 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) 959 != GET_MODE_SIZE (outmode))) 960#endif 961 )) 962 { 963 out_subreg_loc = outloc; 964 outloc = &SUBREG_REG (out); 965 out = *outloc; 966#ifndef LOAD_EXTEND_OP 967 if (GET_CODE (out) == MEM 968 && GET_MODE_SIZE (GET_MODE (out)) > GET_MODE_SIZE (outmode)) 969 abort (); 970#endif 971 outmode = GET_MODE (out); 972 } 973 974 /* Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where 975 either M1 is not valid for R or M2 is wider than a word but we only 976 need one word to store an M2-sized quantity in R. 977 978 However, we must reload the inner reg *as well as* the subreg in 979 that case. In this case, the inner reg is an in-out reload. */ 980 981 if (out != 0 && GET_CODE (out) == SUBREG 982 && GET_CODE (SUBREG_REG (out)) == REG 983 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER 984 && (! HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (out)), outmode) 985 || (GET_MODE_SIZE (outmode) <= UNITS_PER_WORD 986 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) 987 > UNITS_PER_WORD) 988 && ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))) 989 / UNITS_PER_WORD) 990 != HARD_REGNO_NREGS (REGNO (SUBREG_REG (out)), 991 GET_MODE (SUBREG_REG (out))))))) 992 { 993 /* This relies on the fact that emit_reload_insns outputs the 994 instructions for output reloads of type RELOAD_OTHER in reverse 995 order of the reloads. Thus if the outer reload is also of type 996 RELOAD_OTHER, we are guaranteed that this inner reload will be 997 output after the outer reload. */ 998 dont_remove_subreg = 1; 999 push_reload (SUBREG_REG (out), SUBREG_REG (out), &SUBREG_REG (out), 1000 &SUBREG_REG (out), ALL_REGS, VOIDmode, VOIDmode, 0, 0, 1001 opnum, RELOAD_OTHER); 1002 } 1003 1004 /* If IN appears in OUT, we can't share any input-only reload for IN. */ 1005 if (in != 0 && out != 0 && GET_CODE (out) == MEM 1006 && (GET_CODE (in) == REG || GET_CODE (in) == MEM) 1007 && reg_overlap_mentioned_for_reload_p (in, XEXP (out, 0))) 1008 dont_share = 1; 1009 1010 /* If IN is a SUBREG of a hard register, make a new REG. This 1011 simplifies some of the cases below. */ 1012 1013 if (in != 0 && GET_CODE (in) == SUBREG && GET_CODE (SUBREG_REG (in)) == REG 1014 && REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER 1015 && ! dont_remove_subreg) 1016 in = gen_rtx (REG, GET_MODE (in), 1017 REGNO (SUBREG_REG (in)) + SUBREG_WORD (in)); 1018 1019 /* Similarly for OUT. */ 1020 if (out != 0 && GET_CODE (out) == SUBREG 1021 && GET_CODE (SUBREG_REG (out)) == REG 1022 && REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER 1023 && ! dont_remove_subreg) 1024 out = gen_rtx (REG, GET_MODE (out), 1025 REGNO (SUBREG_REG (out)) + SUBREG_WORD (out)); 1026 1027 /* Narrow down the class of register wanted if that is 1028 desirable on this machine for efficiency. */ 1029 if (in != 0) 1030 class = PREFERRED_RELOAD_CLASS (in, class); 1031 1032 /* Output reloads may need analogous treatment, different in detail. */ 1033#ifdef PREFERRED_OUTPUT_RELOAD_CLASS 1034 if (out != 0) 1035 class = PREFERRED_OUTPUT_RELOAD_CLASS (out, class); 1036#endif 1037 1038 /* Make sure we use a class that can handle the actual pseudo 1039 inside any subreg. For example, on the 386, QImode regs 1040 can appear within SImode subregs. Although GENERAL_REGS 1041 can handle SImode, QImode needs a smaller class. */ 1042#ifdef LIMIT_RELOAD_CLASS 1043 if (in_subreg_loc) 1044 class = LIMIT_RELOAD_CLASS (inmode, class); 1045 else if (in != 0 && GET_CODE (in) == SUBREG) 1046 class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), class); 1047 1048 if (out_subreg_loc) 1049 class = LIMIT_RELOAD_CLASS (outmode, class); 1050 if (out != 0 && GET_CODE (out) == SUBREG) 1051 class = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), class); 1052#endif 1053 1054 /* Verify that this class is at least possible for the mode that 1055 is specified. */ 1056 if (this_insn_is_asm) 1057 { 1058 enum machine_mode mode; 1059 if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) 1060 mode = inmode; 1061 else 1062 mode = outmode; 1063 if (mode == VOIDmode) 1064 { 1065 error_for_asm (this_insn, "cannot reload integer constant operand in `asm'"); 1066 mode = word_mode; 1067 if (in != 0) 1068 inmode = word_mode; 1069 if (out != 0) 1070 outmode = word_mode; 1071 } 1072 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1073 if (HARD_REGNO_MODE_OK (i, mode) 1074 && TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)) 1075 { 1076 int nregs = HARD_REGNO_NREGS (i, mode); 1077 1078 int j; 1079 for (j = 1; j < nregs; j++) 1080 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], i + j)) 1081 break; 1082 if (j == nregs) 1083 break; 1084 } 1085 if (i == FIRST_PSEUDO_REGISTER) 1086 { 1087 error_for_asm (this_insn, "impossible register constraint in `asm'"); 1088 class = ALL_REGS; 1089 } 1090 } 1091 1092 if (class == NO_REGS) 1093 abort (); 1094 1095 /* We can use an existing reload if the class is right 1096 and at least one of IN and OUT is a match 1097 and the other is at worst neutral. 1098 (A zero compared against anything is neutral.) 1099 1100 If SMALL_REGISTER_CLASSES, don't use existing reloads unless they are 1101 for the same thing since that can cause us to need more reload registers 1102 than we otherwise would. */ 1103 1104 for (i = 0; i < n_reloads; i++) 1105 if ((reg_class_subset_p (class, reload_reg_class[i]) 1106 || reg_class_subset_p (reload_reg_class[i], class)) 1107 /* If the existing reload has a register, it must fit our class. */ 1108 && (reload_reg_rtx[i] == 0 1109 || TEST_HARD_REG_BIT (reg_class_contents[(int) class], 1110 true_regnum (reload_reg_rtx[i]))) 1111 && ((in != 0 && MATCHES (reload_in[i], in) && ! dont_share 1112 && (out == 0 || reload_out[i] == 0 || MATCHES (reload_out[i], out))) 1113 || 1114 (out != 0 && MATCHES (reload_out[i], out) 1115 && (in == 0 || reload_in[i] == 0 || MATCHES (reload_in[i], in)))) 1116 && (reg_class_size[(int) class] == 1 1117#ifdef SMALL_REGISTER_CLASSES 1118 || 1 1119#endif 1120 ) 1121 && MERGABLE_RELOADS (type, reload_when_needed[i], 1122 opnum, reload_opnum[i])) 1123 break; 1124 1125 /* Reloading a plain reg for input can match a reload to postincrement 1126 that reg, since the postincrement's value is the right value. 1127 Likewise, it can match a preincrement reload, since we regard 1128 the preincrementation as happening before any ref in this insn 1129 to that register. */ 1130 if (i == n_reloads) 1131 for (i = 0; i < n_reloads; i++) 1132 if ((reg_class_subset_p (class, reload_reg_class[i]) 1133 || reg_class_subset_p (reload_reg_class[i], class)) 1134 /* If the existing reload has a register, it must fit our class. */ 1135 && (reload_reg_rtx[i] == 0 1136 || TEST_HARD_REG_BIT (reg_class_contents[(int) class], 1137 true_regnum (reload_reg_rtx[i]))) 1138 && out == 0 && reload_out[i] == 0 && reload_in[i] != 0 1139 && ((GET_CODE (in) == REG 1140 && (GET_CODE (reload_in[i]) == POST_INC 1141 || GET_CODE (reload_in[i]) == POST_DEC 1142 || GET_CODE (reload_in[i]) == PRE_INC 1143 || GET_CODE (reload_in[i]) == PRE_DEC) 1144 && MATCHES (XEXP (reload_in[i], 0), in)) 1145 || 1146 (GET_CODE (reload_in[i]) == REG 1147 && (GET_CODE (in) == POST_INC 1148 || GET_CODE (in) == POST_DEC 1149 || GET_CODE (in) == PRE_INC 1150 || GET_CODE (in) == PRE_DEC) 1151 && MATCHES (XEXP (in, 0), reload_in[i]))) 1152 && (reg_class_size[(int) class] == 1 1153#ifdef SMALL_REGISTER_CLASSES 1154 || 1 1155#endif 1156 ) 1157 && MERGABLE_RELOADS (type, reload_when_needed[i], 1158 opnum, reload_opnum[i])) 1159 { 1160 /* Make sure reload_in ultimately has the increment, 1161 not the plain register. */ 1162 if (GET_CODE (in) == REG) 1163 in = reload_in[i]; 1164 break; 1165 } 1166 1167 if (i == n_reloads) 1168 { 1169 /* See if we need a secondary reload register to move between CLASS 1170 and IN or CLASS and OUT. Get the icode and push any required reloads 1171 needed for each of them if so. */ 1172 1173#ifdef SECONDARY_INPUT_RELOAD_CLASS 1174 if (in != 0) 1175 secondary_in_reload 1176 = push_secondary_reload (1, in, opnum, optional, class, inmode, type, 1177 &secondary_in_icode); 1178#endif 1179 1180#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1181 if (out != 0 && GET_CODE (out) != SCRATCH) 1182 secondary_out_reload 1183 = push_secondary_reload (0, out, opnum, optional, class, outmode, 1184 type, &secondary_out_icode); 1185#endif 1186 1187 /* We found no existing reload suitable for re-use. 1188 So add an additional reload. */ 1189 1190 i = n_reloads; 1191 reload_in[i] = in; 1192 reload_out[i] = out; 1193 reload_reg_class[i] = class; 1194 reload_inmode[i] = inmode; 1195 reload_outmode[i] = outmode; 1196 reload_reg_rtx[i] = 0; 1197 reload_optional[i] = optional; 1198 reload_inc[i] = 0; 1199 reload_nocombine[i] = 0; 1200 reload_in_reg[i] = inloc ? *inloc : 0; 1201 reload_opnum[i] = opnum; 1202 reload_when_needed[i] = type; 1203 reload_secondary_in_reload[i] = secondary_in_reload; 1204 reload_secondary_out_reload[i] = secondary_out_reload; 1205 reload_secondary_in_icode[i] = secondary_in_icode; 1206 reload_secondary_out_icode[i] = secondary_out_icode; 1207 reload_secondary_p[i] = 0; 1208 1209 n_reloads++; 1210 1211#ifdef SECONDARY_MEMORY_NEEDED 1212 /* If a memory location is needed for the copy, make one. */ 1213 if (in != 0 && GET_CODE (in) == REG 1214 && REGNO (in) < FIRST_PSEUDO_REGISTER 1215 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), 1216 class, inmode)) 1217 get_secondary_mem (in, inmode, opnum, type); 1218 1219 if (out != 0 && GET_CODE (out) == REG 1220 && REGNO (out) < FIRST_PSEUDO_REGISTER 1221 && SECONDARY_MEMORY_NEEDED (class, REGNO_REG_CLASS (REGNO (out)), 1222 outmode)) 1223 get_secondary_mem (out, outmode, opnum, type); 1224#endif 1225 } 1226 else 1227 { 1228 /* We are reusing an existing reload, 1229 but we may have additional information for it. 1230 For example, we may now have both IN and OUT 1231 while the old one may have just one of them. */ 1232 1233 if (inmode != VOIDmode) 1234 reload_inmode[i] = inmode; 1235 if (outmode != VOIDmode) 1236 reload_outmode[i] = outmode; 1237 if (in != 0) 1238 reload_in[i] = in; 1239 if (out != 0) 1240 reload_out[i] = out; 1241 if (reg_class_subset_p (class, reload_reg_class[i])) 1242 reload_reg_class[i] = class; 1243 reload_optional[i] &= optional; 1244 if (MERGE_TO_OTHER (type, reload_when_needed[i], 1245 opnum, reload_opnum[i])) 1246 reload_when_needed[i] = RELOAD_OTHER; 1247 reload_opnum[i] = MIN (reload_opnum[i], opnum); 1248 } 1249 1250 /* If the ostensible rtx being reload differs from the rtx found 1251 in the location to substitute, this reload is not safe to combine 1252 because we cannot reliably tell whether it appears in the insn. */ 1253 1254 if (in != 0 && in != *inloc) 1255 reload_nocombine[i] = 1; 1256 1257#if 0 1258 /* This was replaced by changes in find_reloads_address_1 and the new 1259 function inc_for_reload, which go with a new meaning of reload_inc. */ 1260 1261 /* If this is an IN/OUT reload in an insn that sets the CC, 1262 it must be for an autoincrement. It doesn't work to store 1263 the incremented value after the insn because that would clobber the CC. 1264 So we must do the increment of the value reloaded from, 1265 increment it, store it back, then decrement again. */ 1266 if (out != 0 && sets_cc0_p (PATTERN (this_insn))) 1267 { 1268 out = 0; 1269 reload_out[i] = 0; 1270 reload_inc[i] = find_inc_amount (PATTERN (this_insn), in); 1271 /* If we did not find a nonzero amount-to-increment-by, 1272 that contradicts the belief that IN is being incremented 1273 in an address in this insn. */ 1274 if (reload_inc[i] == 0) 1275 abort (); 1276 } 1277#endif 1278 1279 /* If we will replace IN and OUT with the reload-reg, 1280 record where they are located so that substitution need 1281 not do a tree walk. */ 1282 1283 if (replace_reloads) 1284 { 1285 if (inloc != 0) 1286 { 1287 register struct replacement *r = &replacements[n_replacements++]; 1288 r->what = i; 1289 r->subreg_loc = in_subreg_loc; 1290 r->where = inloc; 1291 r->mode = inmode; 1292 } 1293 if (outloc != 0 && outloc != inloc) 1294 { 1295 register struct replacement *r = &replacements[n_replacements++]; 1296 r->what = i; 1297 r->where = outloc; 1298 r->subreg_loc = out_subreg_loc; 1299 r->mode = outmode; 1300 } 1301 } 1302 1303 /* If this reload is just being introduced and it has both 1304 an incoming quantity and an outgoing quantity that are 1305 supposed to be made to match, see if either one of the two 1306 can serve as the place to reload into. 1307 1308 If one of them is acceptable, set reload_reg_rtx[i] 1309 to that one. */ 1310 1311 if (in != 0 && out != 0 && in != out && reload_reg_rtx[i] == 0) 1312 { 1313 reload_reg_rtx[i] = find_dummy_reload (in, out, inloc, outloc, 1314 inmode, outmode, 1315 reload_reg_class[i], i); 1316 1317 /* If the outgoing register already contains the same value 1318 as the incoming one, we can dispense with loading it. 1319 The easiest way to tell the caller that is to give a phony 1320 value for the incoming operand (same as outgoing one). */ 1321 if (reload_reg_rtx[i] == out 1322 && (GET_CODE (in) == REG || CONSTANT_P (in)) 1323 && 0 != find_equiv_reg (in, this_insn, 0, REGNO (out), 1324 static_reload_reg_p, i, inmode)) 1325 reload_in[i] = out; 1326 } 1327 1328 /* If this is an input reload and the operand contains a register that 1329 dies in this insn and is used nowhere else, see if it is the right class 1330 to be used for this reload. Use it if so. (This occurs most commonly 1331 in the case of paradoxical SUBREGs and in-out reloads). We cannot do 1332 this if it is also an output reload that mentions the register unless 1333 the output is a SUBREG that clobbers an entire register. 1334 1335 Note that the operand might be one of the spill regs, if it is a 1336 pseudo reg and we are in a block where spilling has not taken place. 1337 But if there is no spilling in this block, that is OK. 1338 An explicitly used hard reg cannot be a spill reg. */ 1339 1340 if (reload_reg_rtx[i] == 0 && in != 0) 1341 { 1342 rtx note; 1343 int regno; 1344 1345 for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) 1346 if (REG_NOTE_KIND (note) == REG_DEAD 1347 && GET_CODE (XEXP (note, 0)) == REG 1348 && (regno = REGNO (XEXP (note, 0))) < FIRST_PSEUDO_REGISTER 1349 && reg_mentioned_p (XEXP (note, 0), in) 1350 && ! refers_to_regno_for_reload_p (regno, 1351 (regno 1352 + HARD_REGNO_NREGS (regno, 1353 inmode)), 1354 PATTERN (this_insn), inloc) 1355 /* If this is also an output reload, IN cannot be used as 1356 the reload register if it is set in this insn unless IN 1357 is also OUT. */ 1358 && (out == 0 || in == out 1359 || ! hard_reg_set_here_p (regno, 1360 (regno 1361 + HARD_REGNO_NREGS (regno, 1362 inmode)), 1363 PATTERN (this_insn))) 1364 /* ??? Why is this code so different from the previous? 1365 Is there any simple coherent way to describe the two together? 1366 What's going on here. */ 1367 && (in != out 1368 || (GET_CODE (in) == SUBREG 1369 && (((GET_MODE_SIZE (GET_MODE (in)) + (UNITS_PER_WORD - 1)) 1370 / UNITS_PER_WORD) 1371 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))) 1372 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))) 1373 /* Make sure the operand fits in the reg that dies. */ 1374 && GET_MODE_SIZE (inmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 1375 && HARD_REGNO_MODE_OK (regno, inmode) 1376 && GET_MODE_SIZE (outmode) <= GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) 1377 && HARD_REGNO_MODE_OK (regno, outmode) 1378 && TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno) 1379 && !fixed_regs[regno]) 1380 { 1381 reload_reg_rtx[i] = gen_rtx (REG, inmode, regno); 1382 break; 1383 } 1384 } 1385 1386 if (out) 1387 output_reloadnum = i; 1388 1389 return i; 1390} 1391 1392/* Record an additional place we must replace a value 1393 for which we have already recorded a reload. 1394 RELOADNUM is the value returned by push_reload 1395 when the reload was recorded. 1396 This is used in insn patterns that use match_dup. */ 1397 1398static void 1399push_replacement (loc, reloadnum, mode) 1400 rtx *loc; 1401 int reloadnum; 1402 enum machine_mode mode; 1403{ 1404 if (replace_reloads) 1405 { 1406 register struct replacement *r = &replacements[n_replacements++]; 1407 r->what = reloadnum; 1408 r->where = loc; 1409 r->subreg_loc = 0; 1410 r->mode = mode; 1411 } 1412} 1413 1414/* Transfer all replacements that used to be in reload FROM to be in 1415 reload TO. */ 1416 1417void 1418transfer_replacements (to, from) 1419 int to, from; 1420{ 1421 int i; 1422 1423 for (i = 0; i < n_replacements; i++) 1424 if (replacements[i].what == from) 1425 replacements[i].what = to; 1426} 1427 1428/* If there is only one output reload, and it is not for an earlyclobber 1429 operand, try to combine it with a (logically unrelated) input reload 1430 to reduce the number of reload registers needed. 1431 1432 This is safe if the input reload does not appear in 1433 the value being output-reloaded, because this implies 1434 it is not needed any more once the original insn completes. 1435 1436 If that doesn't work, see we can use any of the registers that 1437 die in this insn as a reload register. We can if it is of the right 1438 class and does not appear in the value being output-reloaded. */ 1439 1440static void 1441combine_reloads () 1442{ 1443 int i; 1444 int output_reload = -1; 1445 int secondary_out = -1; 1446 rtx note; 1447 1448 /* Find the output reload; return unless there is exactly one 1449 and that one is mandatory. */ 1450 1451 for (i = 0; i < n_reloads; i++) 1452 if (reload_out[i] != 0) 1453 { 1454 if (output_reload >= 0) 1455 return; 1456 output_reload = i; 1457 } 1458 1459 if (output_reload < 0 || reload_optional[output_reload]) 1460 return; 1461 1462 /* An input-output reload isn't combinable. */ 1463 1464 if (reload_in[output_reload] != 0) 1465 return; 1466 1467 /* If this reload is for an earlyclobber operand, we can't do anything. */ 1468 if (earlyclobber_operand_p (reload_out[output_reload])) 1469 return; 1470 1471 /* Check each input reload; can we combine it? */ 1472 1473 for (i = 0; i < n_reloads; i++) 1474 if (reload_in[i] && ! reload_optional[i] && ! reload_nocombine[i] 1475 /* Life span of this reload must not extend past main insn. */ 1476 && reload_when_needed[i] != RELOAD_FOR_OUTPUT_ADDRESS 1477 && reload_when_needed[i] != RELOAD_OTHER 1478 && (CLASS_MAX_NREGS (reload_reg_class[i], reload_inmode[i]) 1479 == CLASS_MAX_NREGS (reload_reg_class[output_reload], 1480 reload_outmode[output_reload])) 1481 && reload_inc[i] == 0 1482 && reload_reg_rtx[i] == 0 1483#ifdef SECONDARY_MEMORY_NEEDED 1484 /* Don't combine two reloads with different secondary 1485 memory locations. */ 1486 && (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]] == 0 1487 || secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]] == 0 1488 || rtx_equal_p (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]], 1489 secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]])) 1490#endif 1491#ifdef SMALL_REGISTER_CLASSES 1492 && reload_reg_class[i] == reload_reg_class[output_reload] 1493#else 1494 && (reg_class_subset_p (reload_reg_class[i], 1495 reload_reg_class[output_reload]) 1496 || reg_class_subset_p (reload_reg_class[output_reload], 1497 reload_reg_class[i])) 1498#endif 1499 && (MATCHES (reload_in[i], reload_out[output_reload]) 1500 /* Args reversed because the first arg seems to be 1501 the one that we imagine being modified 1502 while the second is the one that might be affected. */ 1503 || (! reg_overlap_mentioned_for_reload_p (reload_out[output_reload], 1504 reload_in[i]) 1505 /* However, if the input is a register that appears inside 1506 the output, then we also can't share. 1507 Imagine (set (mem (reg 69)) (plus (reg 69) ...)). 1508 If the same reload reg is used for both reg 69 and the 1509 result to be stored in memory, then that result 1510 will clobber the address of the memory ref. */ 1511 && ! (GET_CODE (reload_in[i]) == REG 1512 && reg_overlap_mentioned_for_reload_p (reload_in[i], 1513 reload_out[output_reload])))) 1514 && (reg_class_size[(int) reload_reg_class[i]] 1515#ifdef SMALL_REGISTER_CLASSES 1516 || 1 1517#endif 1518 ) 1519 /* We will allow making things slightly worse by combining an 1520 input and an output, but no worse than that. */ 1521 && (reload_when_needed[i] == RELOAD_FOR_INPUT 1522 || reload_when_needed[i] == RELOAD_FOR_OUTPUT)) 1523 { 1524 int j; 1525 1526 /* We have found a reload to combine with! */ 1527 reload_out[i] = reload_out[output_reload]; 1528 reload_outmode[i] = reload_outmode[output_reload]; 1529 /* Mark the old output reload as inoperative. */ 1530 reload_out[output_reload] = 0; 1531 /* The combined reload is needed for the entire insn. */ 1532 reload_when_needed[i] = RELOAD_OTHER; 1533 /* If the output reload had a secondary reload, copy it. */ 1534 if (reload_secondary_out_reload[output_reload] != -1) 1535 { 1536 reload_secondary_out_reload[i] 1537 = reload_secondary_out_reload[output_reload]; 1538 reload_secondary_out_icode[i] 1539 = reload_secondary_out_icode[output_reload]; 1540 } 1541 1542#ifdef SECONDARY_MEMORY_NEEDED 1543 /* Copy any secondary MEM. */ 1544 if (secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]] != 0) 1545 secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[i]] 1546 = secondary_memlocs_elim[(int) reload_outmode[output_reload]][reload_opnum[output_reload]]; 1547#endif 1548 /* If required, minimize the register class. */ 1549 if (reg_class_subset_p (reload_reg_class[output_reload], 1550 reload_reg_class[i])) 1551 reload_reg_class[i] = reload_reg_class[output_reload]; 1552 1553 /* Transfer all replacements from the old reload to the combined. */ 1554 for (j = 0; j < n_replacements; j++) 1555 if (replacements[j].what == output_reload) 1556 replacements[j].what = i; 1557 1558 return; 1559 } 1560 1561 /* If this insn has only one operand that is modified or written (assumed 1562 to be the first), it must be the one corresponding to this reload. It 1563 is safe to use anything that dies in this insn for that output provided 1564 that it does not occur in the output (we already know it isn't an 1565 earlyclobber. If this is an asm insn, give up. */ 1566 1567 if (INSN_CODE (this_insn) == -1) 1568 return; 1569 1570 for (i = 1; i < insn_n_operands[INSN_CODE (this_insn)]; i++) 1571 if (insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '=' 1572 || insn_operand_constraint[INSN_CODE (this_insn)][i][0] == '+') 1573 return; 1574 1575 /* See if some hard register that dies in this insn and is not used in 1576 the output is the right class. Only works if the register we pick 1577 up can fully hold our output reload. */ 1578 for (note = REG_NOTES (this_insn); note; note = XEXP (note, 1)) 1579 if (REG_NOTE_KIND (note) == REG_DEAD 1580 && GET_CODE (XEXP (note, 0)) == REG 1581 && ! reg_overlap_mentioned_for_reload_p (XEXP (note, 0), 1582 reload_out[output_reload]) 1583 && REGNO (XEXP (note, 0)) < FIRST_PSEUDO_REGISTER 1584 && HARD_REGNO_MODE_OK (REGNO (XEXP (note, 0)), reload_outmode[output_reload]) 1585 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[output_reload]], 1586 REGNO (XEXP (note, 0))) 1587 && (HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), reload_outmode[output_reload]) 1588 <= HARD_REGNO_NREGS (REGNO (XEXP (note, 0)), GET_MODE (XEXP (note, 0)))) 1589 /* Ensure that a secondary or tertiary reload for this output 1590 won't want this register. */ 1591 && ((secondary_out = reload_secondary_out_reload[output_reload]) == -1 1592 || (! (TEST_HARD_REG_BIT 1593 (reg_class_contents[(int) reload_reg_class[secondary_out]], 1594 REGNO (XEXP (note, 0)))) 1595 && ((secondary_out = reload_secondary_out_reload[secondary_out]) == -1 1596 || ! (TEST_HARD_REG_BIT 1597 (reg_class_contents[(int) reload_reg_class[secondary_out]], 1598 REGNO (XEXP (note, 0))))))) 1599 && ! fixed_regs[REGNO (XEXP (note, 0))]) 1600 { 1601 reload_reg_rtx[output_reload] = gen_rtx (REG, 1602 reload_outmode[output_reload], 1603 REGNO (XEXP (note, 0))); 1604 return; 1605 } 1606} 1607 1608/* Try to find a reload register for an in-out reload (expressions IN and OUT). 1609 See if one of IN and OUT is a register that may be used; 1610 this is desirable since a spill-register won't be needed. 1611 If so, return the register rtx that proves acceptable. 1612 1613 INLOC and OUTLOC are locations where IN and OUT appear in the insn. 1614 CLASS is the register class required for the reload. 1615 1616 If FOR_REAL is >= 0, it is the number of the reload, 1617 and in some cases when it can be discovered that OUT doesn't need 1618 to be computed, clear out reload_out[FOR_REAL]. 1619 1620 If FOR_REAL is -1, this should not be done, because this call 1621 is just to see if a register can be found, not to find and install it. */ 1622 1623static rtx 1624find_dummy_reload (real_in, real_out, inloc, outloc, 1625 inmode, outmode, class, for_real) 1626 rtx real_in, real_out; 1627 rtx *inloc, *outloc; 1628 enum machine_mode inmode, outmode; 1629 enum reg_class class; 1630 int for_real; 1631{ 1632 rtx in = real_in; 1633 rtx out = real_out; 1634 int in_offset = 0; 1635 int out_offset = 0; 1636 rtx value = 0; 1637 1638 /* If operands exceed a word, we can't use either of them 1639 unless they have the same size. */ 1640 if (GET_MODE_SIZE (outmode) != GET_MODE_SIZE (inmode) 1641 && (GET_MODE_SIZE (outmode) > UNITS_PER_WORD 1642 || GET_MODE_SIZE (inmode) > UNITS_PER_WORD)) 1643 return 0; 1644 1645 /* Find the inside of any subregs. */ 1646 while (GET_CODE (out) == SUBREG) 1647 { 1648 out_offset = SUBREG_WORD (out); 1649 out = SUBREG_REG (out); 1650 } 1651 while (GET_CODE (in) == SUBREG) 1652 { 1653 in_offset = SUBREG_WORD (in); 1654 in = SUBREG_REG (in); 1655 } 1656 1657 /* Narrow down the reg class, the same way push_reload will; 1658 otherwise we might find a dummy now, but push_reload won't. */ 1659 class = PREFERRED_RELOAD_CLASS (in, class); 1660 1661 /* See if OUT will do. */ 1662 if (GET_CODE (out) == REG 1663 && REGNO (out) < FIRST_PSEUDO_REGISTER) 1664 { 1665 register int regno = REGNO (out) + out_offset; 1666 int nwords = HARD_REGNO_NREGS (regno, outmode); 1667 rtx saved_rtx; 1668 1669 /* When we consider whether the insn uses OUT, 1670 ignore references within IN. They don't prevent us 1671 from copying IN into OUT, because those refs would 1672 move into the insn that reloads IN. 1673 1674 However, we only ignore IN in its role as this reload. 1675 If the insn uses IN elsewhere and it contains OUT, 1676 that counts. We can't be sure it's the "same" operand 1677 so it might not go through this reload. */ 1678 saved_rtx = *inloc; 1679 *inloc = const0_rtx; 1680 1681 if (regno < FIRST_PSEUDO_REGISTER 1682 /* A fixed reg that can overlap other regs better not be used 1683 for reloading in any way. */ 1684#ifdef OVERLAPPING_REGNO_P 1685 && ! (fixed_regs[regno] && OVERLAPPING_REGNO_P (regno)) 1686#endif 1687 && ! refers_to_regno_for_reload_p (regno, regno + nwords, 1688 PATTERN (this_insn), outloc)) 1689 { 1690 int i; 1691 for (i = 0; i < nwords; i++) 1692 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], 1693 regno + i)) 1694 break; 1695 1696 if (i == nwords) 1697 { 1698 if (GET_CODE (real_out) == REG) 1699 value = real_out; 1700 else 1701 value = gen_rtx (REG, outmode, regno); 1702 } 1703 } 1704 1705 *inloc = saved_rtx; 1706 } 1707 1708 /* Consider using IN if OUT was not acceptable 1709 or if OUT dies in this insn (like the quotient in a divmod insn). 1710 We can't use IN unless it is dies in this insn, 1711 which means we must know accurately which hard regs are live. 1712 Also, the result can't go in IN if IN is used within OUT. */ 1713 if (hard_regs_live_known 1714 && GET_CODE (in) == REG 1715 && REGNO (in) < FIRST_PSEUDO_REGISTER 1716 && (value == 0 1717 || find_reg_note (this_insn, REG_UNUSED, real_out)) 1718 && find_reg_note (this_insn, REG_DEAD, real_in) 1719 && !fixed_regs[REGNO (in)] 1720 && HARD_REGNO_MODE_OK (REGNO (in), 1721 /* The only case where out and real_out might 1722 have different modes is where real_out 1723 is a subreg, and in that case, out 1724 has a real mode. */ 1725 (GET_MODE (out) != VOIDmode 1726 ? GET_MODE (out) : outmode))) 1727 { 1728 register int regno = REGNO (in) + in_offset; 1729 int nwords = HARD_REGNO_NREGS (regno, inmode); 1730 1731 if (! refers_to_regno_for_reload_p (regno, regno + nwords, out, NULL_PTR) 1732 && ! hard_reg_set_here_p (regno, regno + nwords, 1733 PATTERN (this_insn))) 1734 { 1735 int i; 1736 for (i = 0; i < nwords; i++) 1737 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class], 1738 regno + i)) 1739 break; 1740 1741 if (i == nwords) 1742 { 1743 /* If we were going to use OUT as the reload reg 1744 and changed our mind, it means OUT is a dummy that 1745 dies here. So don't bother copying value to it. */ 1746 if (for_real >= 0 && value == real_out) 1747 reload_out[for_real] = 0; 1748 if (GET_CODE (real_in) == REG) 1749 value = real_in; 1750 else 1751 value = gen_rtx (REG, inmode, regno); 1752 } 1753 } 1754 } 1755 1756 return value; 1757} 1758 1759/* This page contains subroutines used mainly for determining 1760 whether the IN or an OUT of a reload can serve as the 1761 reload register. */ 1762 1763/* Return 1 if X is an operand of an insn that is being earlyclobbered. */ 1764 1765static int 1766earlyclobber_operand_p (x) 1767 rtx x; 1768{ 1769 int i; 1770 1771 for (i = 0; i < n_earlyclobbers; i++) 1772 if (reload_earlyclobbers[i] == x) 1773 return 1; 1774 1775 return 0; 1776} 1777 1778/* Return 1 if expression X alters a hard reg in the range 1779 from BEG_REGNO (inclusive) to END_REGNO (exclusive), 1780 either explicitly or in the guise of a pseudo-reg allocated to REGNO. 1781 X should be the body of an instruction. */ 1782 1783static int 1784hard_reg_set_here_p (beg_regno, end_regno, x) 1785 register int beg_regno, end_regno; 1786 rtx x; 1787{ 1788 if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) 1789 { 1790 register rtx op0 = SET_DEST (x); 1791 while (GET_CODE (op0) == SUBREG) 1792 op0 = SUBREG_REG (op0); 1793 if (GET_CODE (op0) == REG) 1794 { 1795 register int r = REGNO (op0); 1796 /* See if this reg overlaps range under consideration. */ 1797 if (r < end_regno 1798 && r + HARD_REGNO_NREGS (r, GET_MODE (op0)) > beg_regno) 1799 return 1; 1800 } 1801 } 1802 else if (GET_CODE (x) == PARALLEL) 1803 { 1804 register int i = XVECLEN (x, 0) - 1; 1805 for (; i >= 0; i--) 1806 if (hard_reg_set_here_p (beg_regno, end_regno, XVECEXP (x, 0, i))) 1807 return 1; 1808 } 1809 1810 return 0; 1811} 1812 1813/* Return 1 if ADDR is a valid memory address for mode MODE, 1814 and check that each pseudo reg has the proper kind of 1815 hard reg. */ 1816 1817int 1818strict_memory_address_p (mode, addr) 1819 enum machine_mode mode; 1820 register rtx addr; 1821{ 1822 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); 1823 return 0; 1824 1825 win: 1826 return 1; 1827} 1828 1829/* Like rtx_equal_p except that it allows a REG and a SUBREG to match 1830 if they are the same hard reg, and has special hacks for 1831 autoincrement and autodecrement. 1832 This is specifically intended for find_reloads to use 1833 in determining whether two operands match. 1834 X is the operand whose number is the lower of the two. 1835 1836 The value is 2 if Y contains a pre-increment that matches 1837 a non-incrementing address in X. */ 1838 1839/* ??? To be completely correct, we should arrange to pass 1840 for X the output operand and for Y the input operand. 1841 For now, we assume that the output operand has the lower number 1842 because that is natural in (SET output (... input ...)). */ 1843 1844int 1845operands_match_p (x, y) 1846 register rtx x, y; 1847{ 1848 register int i; 1849 register RTX_CODE code = GET_CODE (x); 1850 register char *fmt; 1851 int success_2; 1852 1853 if (x == y) 1854 return 1; 1855 if ((code == REG || (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG)) 1856 && (GET_CODE (y) == REG || (GET_CODE (y) == SUBREG 1857 && GET_CODE (SUBREG_REG (y)) == REG))) 1858 { 1859 register int j; 1860 1861 if (code == SUBREG) 1862 { 1863 i = REGNO (SUBREG_REG (x)); 1864 if (i >= FIRST_PSEUDO_REGISTER) 1865 goto slow; 1866 i += SUBREG_WORD (x); 1867 } 1868 else 1869 i = REGNO (x); 1870 1871 if (GET_CODE (y) == SUBREG) 1872 { 1873 j = REGNO (SUBREG_REG (y)); 1874 if (j >= FIRST_PSEUDO_REGISTER) 1875 goto slow; 1876 j += SUBREG_WORD (y); 1877 } 1878 else 1879 j = REGNO (y); 1880 1881 /* On a WORDS_BIG_ENDIAN machine, point to the last register of a 1882 multiple hard register group, so that for example (reg:DI 0) and 1883 (reg:SI 1) will be considered the same register. */ 1884 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD 1885 && i < FIRST_PSEUDO_REGISTER) 1886 i += (GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD) - 1; 1887 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (y)) > UNITS_PER_WORD 1888 && j < FIRST_PSEUDO_REGISTER) 1889 j += (GET_MODE_SIZE (GET_MODE (y)) / UNITS_PER_WORD) - 1; 1890 1891 return i == j; 1892 } 1893 /* If two operands must match, because they are really a single 1894 operand of an assembler insn, then two postincrements are invalid 1895 because the assembler insn would increment only once. 1896 On the other hand, an postincrement matches ordinary indexing 1897 if the postincrement is the output operand. */ 1898 if (code == POST_DEC || code == POST_INC) 1899 return operands_match_p (XEXP (x, 0), y); 1900 /* Two preincrements are invalid 1901 because the assembler insn would increment only once. 1902 On the other hand, an preincrement matches ordinary indexing 1903 if the preincrement is the input operand. 1904 In this case, return 2, since some callers need to do special 1905 things when this happens. */ 1906 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC) 1907 return operands_match_p (x, XEXP (y, 0)) ? 2 : 0; 1908 1909 slow: 1910 1911 /* Now we have disposed of all the cases 1912 in which different rtx codes can match. */ 1913 if (code != GET_CODE (y)) 1914 return 0; 1915 if (code == LABEL_REF) 1916 return XEXP (x, 0) == XEXP (y, 0); 1917 if (code == SYMBOL_REF) 1918 return XSTR (x, 0) == XSTR (y, 0); 1919 1920 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ 1921 1922 if (GET_MODE (x) != GET_MODE (y)) 1923 return 0; 1924 1925 /* Compare the elements. If any pair of corresponding elements 1926 fail to match, return 0 for the whole things. */ 1927 1928 success_2 = 0; 1929 fmt = GET_RTX_FORMAT (code); 1930 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1931 { 1932 int val; 1933 switch (fmt[i]) 1934 { 1935 case 'w': 1936 if (XWINT (x, i) != XWINT (y, i)) 1937 return 0; 1938 break; 1939 1940 case 'i': 1941 if (XINT (x, i) != XINT (y, i)) 1942 return 0; 1943 break; 1944 1945 case 'e': 1946 val = operands_match_p (XEXP (x, i), XEXP (y, i)); 1947 if (val == 0) 1948 return 0; 1949 /* If any subexpression returns 2, 1950 we should return 2 if we are successful. */ 1951 if (val == 2) 1952 success_2 = 1; 1953 break; 1954 1955 case '0': 1956 break; 1957 1958 /* It is believed that rtx's at this level will never 1959 contain anything but integers and other rtx's, 1960 except for within LABEL_REFs and SYMBOL_REFs. */ 1961 default: 1962 abort (); 1963 } 1964 } 1965 return 1 + success_2; 1966} 1967 1968/* Return the number of times character C occurs in string S. */ 1969 1970int 1971n_occurrences (c, s) 1972 int c; 1973 char *s; 1974{ 1975 int n = 0; 1976 while (*s) 1977 n += (*s++ == c); 1978 return n; 1979} 1980 1981/* Describe the range of registers or memory referenced by X. 1982 If X is a register, set REG_FLAG and put the first register 1983 number into START and the last plus one into END. 1984 If X is a memory reference, put a base address into BASE 1985 and a range of integer offsets into START and END. 1986 If X is pushing on the stack, we can assume it causes no trouble, 1987 so we set the SAFE field. */ 1988 1989static struct decomposition 1990decompose (x) 1991 rtx x; 1992{ 1993 struct decomposition val; 1994 int all_const = 0; 1995 1996 val.reg_flag = 0; 1997 val.safe = 0; 1998 if (GET_CODE (x) == MEM) 1999 { 2000 rtx base, offset = 0; 2001 rtx addr = XEXP (x, 0); 2002 2003 if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == PRE_INC 2004 || GET_CODE (addr) == POST_DEC || GET_CODE (addr) == POST_INC) 2005 { 2006 val.base = XEXP (addr, 0); 2007 val.start = - GET_MODE_SIZE (GET_MODE (x)); 2008 val.end = GET_MODE_SIZE (GET_MODE (x)); 2009 val.safe = REGNO (val.base) == STACK_POINTER_REGNUM; 2010 return val; 2011 } 2012 2013 if (GET_CODE (addr) == CONST) 2014 { 2015 addr = XEXP (addr, 0); 2016 all_const = 1; 2017 } 2018 if (GET_CODE (addr) == PLUS) 2019 { 2020 if (CONSTANT_P (XEXP (addr, 0))) 2021 { 2022 base = XEXP (addr, 1); 2023 offset = XEXP (addr, 0); 2024 } 2025 else if (CONSTANT_P (XEXP (addr, 1))) 2026 { 2027 base = XEXP (addr, 0); 2028 offset = XEXP (addr, 1); 2029 } 2030 } 2031 2032 if (offset == 0) 2033 { 2034 base = addr; 2035 offset = const0_rtx; 2036 } 2037 if (GET_CODE (offset) == CONST) 2038 offset = XEXP (offset, 0); 2039 if (GET_CODE (offset) == PLUS) 2040 { 2041 if (GET_CODE (XEXP (offset, 0)) == CONST_INT) 2042 { 2043 base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 1)); 2044 offset = XEXP (offset, 0); 2045 } 2046 else if (GET_CODE (XEXP (offset, 1)) == CONST_INT) 2047 { 2048 base = gen_rtx (PLUS, GET_MODE (base), base, XEXP (offset, 0)); 2049 offset = XEXP (offset, 1); 2050 } 2051 else 2052 { 2053 base = gen_rtx (PLUS, GET_MODE (base), base, offset); 2054 offset = const0_rtx; 2055 } 2056 } 2057 else if (GET_CODE (offset) != CONST_INT) 2058 { 2059 base = gen_rtx (PLUS, GET_MODE (base), base, offset); 2060 offset = const0_rtx; 2061 } 2062 2063 if (all_const && GET_CODE (base) == PLUS) 2064 base = gen_rtx (CONST, GET_MODE (base), base); 2065 2066 if (GET_CODE (offset) != CONST_INT) 2067 abort (); 2068 2069 val.start = INTVAL (offset); 2070 val.end = val.start + GET_MODE_SIZE (GET_MODE (x)); 2071 val.base = base; 2072 return val; 2073 } 2074 else if (GET_CODE (x) == REG) 2075 { 2076 val.reg_flag = 1; 2077 val.start = true_regnum (x); 2078 if (val.start < 0) 2079 { 2080 /* A pseudo with no hard reg. */ 2081 val.start = REGNO (x); 2082 val.end = val.start + 1; 2083 } 2084 else 2085 /* A hard reg. */ 2086 val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x)); 2087 } 2088 else if (GET_CODE (x) == SUBREG) 2089 { 2090 if (GET_CODE (SUBREG_REG (x)) != REG) 2091 /* This could be more precise, but it's good enough. */ 2092 return decompose (SUBREG_REG (x)); 2093 val.reg_flag = 1; 2094 val.start = true_regnum (x); 2095 if (val.start < 0) 2096 return decompose (SUBREG_REG (x)); 2097 else 2098 /* A hard reg. */ 2099 val.end = val.start + HARD_REGNO_NREGS (val.start, GET_MODE (x)); 2100 } 2101 else if (CONSTANT_P (x) 2102 /* This hasn't been assigned yet, so it can't conflict yet. */ 2103 || GET_CODE (x) == SCRATCH) 2104 val.safe = 1; 2105 else 2106 abort (); 2107 return val; 2108} 2109 2110/* Return 1 if altering Y will not modify the value of X. 2111 Y is also described by YDATA, which should be decompose (Y). */ 2112 2113static int 2114immune_p (x, y, ydata) 2115 rtx x, y; 2116 struct decomposition ydata; 2117{ 2118 struct decomposition xdata; 2119 2120 if (ydata.reg_flag) 2121 return !refers_to_regno_for_reload_p (ydata.start, ydata.end, x, NULL_PTR); 2122 if (ydata.safe) 2123 return 1; 2124 2125 if (GET_CODE (y) != MEM) 2126 abort (); 2127 /* If Y is memory and X is not, Y can't affect X. */ 2128 if (GET_CODE (x) != MEM) 2129 return 1; 2130 2131 xdata = decompose (x); 2132 2133 if (! rtx_equal_p (xdata.base, ydata.base)) 2134 { 2135 /* If bases are distinct symbolic constants, there is no overlap. */ 2136 if (CONSTANT_P (xdata.base) && CONSTANT_P (ydata.base)) 2137 return 1; 2138 /* Constants and stack slots never overlap. */ 2139 if (CONSTANT_P (xdata.base) 2140 && (ydata.base == frame_pointer_rtx 2141 || ydata.base == hard_frame_pointer_rtx 2142 || ydata.base == stack_pointer_rtx)) 2143 return 1; 2144 if (CONSTANT_P (ydata.base) 2145 && (xdata.base == frame_pointer_rtx 2146 || xdata.base == hard_frame_pointer_rtx 2147 || xdata.base == stack_pointer_rtx)) 2148 return 1; 2149 /* If either base is variable, we don't know anything. */ 2150 return 0; 2151 } 2152 2153 2154 return (xdata.start >= ydata.end || ydata.start >= xdata.end); 2155} 2156 2157/* Similar, but calls decompose. */ 2158 2159int 2160safe_from_earlyclobber (op, clobber) 2161 rtx op, clobber; 2162{ 2163 struct decomposition early_data; 2164 2165 early_data = decompose (clobber); 2166 return immune_p (op, clobber, early_data); 2167} 2168 2169/* Main entry point of this file: search the body of INSN 2170 for values that need reloading and record them with push_reload. 2171 REPLACE nonzero means record also where the values occur 2172 so that subst_reloads can be used. 2173 2174 IND_LEVELS says how many levels of indirection are supported by this 2175 machine; a value of zero means that a memory reference is not a valid 2176 memory address. 2177 2178 LIVE_KNOWN says we have valid information about which hard 2179 regs are live at each point in the program; this is true when 2180 we are called from global_alloc but false when stupid register 2181 allocation has been done. 2182 2183 RELOAD_REG_P if nonzero is a vector indexed by hard reg number 2184 which is nonnegative if the reg has been commandeered for reloading into. 2185 It is copied into STATIC_RELOAD_REG_P and referenced from there 2186 by various subroutines. */ 2187 2188void 2189find_reloads (insn, replace, ind_levels, live_known, reload_reg_p) 2190 rtx insn; 2191 int replace, ind_levels; 2192 int live_known; 2193 short *reload_reg_p; 2194{ 2195#ifdef REGISTER_CONSTRAINTS 2196 2197 register int insn_code_number; 2198 register int i, j; 2199 int noperands; 2200 /* These are the constraints for the insn. We don't change them. */ 2201 char *constraints1[MAX_RECOG_OPERANDS]; 2202 /* These start out as the constraints for the insn 2203 and they are chewed up as we consider alternatives. */ 2204 char *constraints[MAX_RECOG_OPERANDS]; 2205 /* These are the preferred classes for an operand, or NO_REGS if it isn't 2206 a register. */ 2207 enum reg_class preferred_class[MAX_RECOG_OPERANDS]; 2208 char pref_or_nothing[MAX_RECOG_OPERANDS]; 2209 /* Nonzero for a MEM operand whose entire address needs a reload. */ 2210 int address_reloaded[MAX_RECOG_OPERANDS]; 2211 /* Value of enum reload_type to use for operand. */ 2212 enum reload_type operand_type[MAX_RECOG_OPERANDS]; 2213 /* Value of enum reload_type to use within address of operand. */ 2214 enum reload_type address_type[MAX_RECOG_OPERANDS]; 2215 /* Save the usage of each operand. */ 2216 enum reload_usage { RELOAD_READ, RELOAD_READ_WRITE, RELOAD_WRITE } modified[MAX_RECOG_OPERANDS]; 2217 int no_input_reloads = 0, no_output_reloads = 0; 2218 int n_alternatives; 2219 int this_alternative[MAX_RECOG_OPERANDS]; 2220 char this_alternative_win[MAX_RECOG_OPERANDS]; 2221 char this_alternative_offmemok[MAX_RECOG_OPERANDS]; 2222 char this_alternative_earlyclobber[MAX_RECOG_OPERANDS]; 2223 int this_alternative_matches[MAX_RECOG_OPERANDS]; 2224 int swapped; 2225 int goal_alternative[MAX_RECOG_OPERANDS]; 2226 int this_alternative_number; 2227 int goal_alternative_number; 2228 int operand_reloadnum[MAX_RECOG_OPERANDS]; 2229 int goal_alternative_matches[MAX_RECOG_OPERANDS]; 2230 int goal_alternative_matched[MAX_RECOG_OPERANDS]; 2231 char goal_alternative_win[MAX_RECOG_OPERANDS]; 2232 char goal_alternative_offmemok[MAX_RECOG_OPERANDS]; 2233 char goal_alternative_earlyclobber[MAX_RECOG_OPERANDS]; 2234 int goal_alternative_swapped; 2235 int best; 2236 int commutative; 2237 char operands_match[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; 2238 rtx substed_operand[MAX_RECOG_OPERANDS]; 2239 rtx body = PATTERN (insn); 2240 rtx set = single_set (insn); 2241 int goal_earlyclobber, this_earlyclobber; 2242 enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; 2243 2244 this_insn = insn; 2245 this_insn_is_asm = 0; /* Tentative. */ 2246 n_reloads = 0; 2247 n_replacements = 0; 2248 n_memlocs = 0; 2249 n_earlyclobbers = 0; 2250 replace_reloads = replace; 2251 hard_regs_live_known = live_known; 2252 static_reload_reg_p = reload_reg_p; 2253 2254 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads; 2255 neither are insns that SET cc0. Insns that use CC0 are not allowed 2256 to have any input reloads. */ 2257 if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN) 2258 no_output_reloads = 1; 2259 2260#ifdef HAVE_cc0 2261 if (reg_referenced_p (cc0_rtx, PATTERN (insn))) 2262 no_input_reloads = 1; 2263 if (reg_set_p (cc0_rtx, PATTERN (insn))) 2264 no_output_reloads = 1; 2265#endif 2266 2267#ifdef SECONDARY_MEMORY_NEEDED 2268 /* The eliminated forms of any secondary memory locations are per-insn, so 2269 clear them out here. */ 2270 2271 bzero ((char *) secondary_memlocs_elim, sizeof secondary_memlocs_elim); 2272#endif 2273 2274 /* Find what kind of insn this is. NOPERANDS gets number of operands. 2275 Make OPERANDS point to a vector of operand values. 2276 Make OPERAND_LOCS point to a vector of pointers to 2277 where the operands were found. 2278 Fill CONSTRAINTS and CONSTRAINTS1 with pointers to the 2279 constraint-strings for this insn. 2280 Return if the insn needs no reload processing. */ 2281 2282 switch (GET_CODE (body)) 2283 { 2284 case USE: 2285 case CLOBBER: 2286 case ASM_INPUT: 2287 case ADDR_VEC: 2288 case ADDR_DIFF_VEC: 2289 return; 2290 2291 case SET: 2292 /* Dispose quickly of (set (reg..) (reg..)) if both have hard regs and it 2293 is cheap to move between them. If it is not, there may not be an insn 2294 to do the copy, so we may need a reload. */ 2295 if (GET_CODE (SET_DEST (body)) == REG 2296 && REGNO (SET_DEST (body)) < FIRST_PSEUDO_REGISTER 2297 && GET_CODE (SET_SRC (body)) == REG 2298 && REGNO (SET_SRC (body)) < FIRST_PSEUDO_REGISTER 2299 && REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (SET_SRC (body))), 2300 REGNO_REG_CLASS (REGNO (SET_DEST (body)))) == 2) 2301 return; 2302 case PARALLEL: 2303 case ASM_OPERANDS: 2304 reload_n_operands = noperands = asm_noperands (body); 2305 if (noperands >= 0) 2306 { 2307 /* This insn is an `asm' with operands. */ 2308 2309 insn_code_number = -1; 2310 this_insn_is_asm = 1; 2311 2312 /* expand_asm_operands makes sure there aren't too many operands. */ 2313 if (noperands > MAX_RECOG_OPERANDS) 2314 abort (); 2315 2316 /* Now get the operand values and constraints out of the insn. */ 2317 2318 decode_asm_operands (body, recog_operand, recog_operand_loc, 2319 constraints, operand_mode); 2320 if (noperands > 0) 2321 { 2322 bcopy ((char *) constraints, (char *) constraints1, 2323 noperands * sizeof (char *)); 2324 n_alternatives = n_occurrences (',', constraints[0]) + 1; 2325 for (i = 1; i < noperands; i++) 2326 if (n_alternatives != n_occurrences (',', constraints[i]) + 1) 2327 { 2328 error_for_asm (insn, "operand constraints differ in number of alternatives"); 2329 /* Avoid further trouble with this insn. */ 2330 PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx); 2331 n_reloads = 0; 2332 return; 2333 } 2334 } 2335 break; 2336 } 2337 2338 default: 2339 /* Ordinary insn: recognize it, get the operands via insn_extract 2340 and get the constraints. */ 2341 2342 insn_code_number = recog_memoized (insn); 2343 if (insn_code_number < 0) 2344 fatal_insn_not_found (insn); 2345 2346 reload_n_operands = noperands = insn_n_operands[insn_code_number]; 2347 n_alternatives = insn_n_alternatives[insn_code_number]; 2348 /* Just return "no reloads" if insn has no operands with constraints. */ 2349 if (n_alternatives == 0) 2350 return; 2351 insn_extract (insn); 2352 for (i = 0; i < noperands; i++) 2353 { 2354 constraints[i] = constraints1[i] 2355 = insn_operand_constraint[insn_code_number][i]; 2356 operand_mode[i] = insn_operand_mode[insn_code_number][i]; 2357 } 2358 } 2359 2360 if (noperands == 0) 2361 return; 2362 2363 commutative = -1; 2364 2365 /* If we will need to know, later, whether some pair of operands 2366 are the same, we must compare them now and save the result. 2367 Reloading the base and index registers will clobber them 2368 and afterward they will fail to match. */ 2369 2370 for (i = 0; i < noperands; i++) 2371 { 2372 register char *p; 2373 register int c; 2374 2375 substed_operand[i] = recog_operand[i]; 2376 p = constraints[i]; 2377 2378 modified[i] = RELOAD_READ; 2379 2380 /* Scan this operand's constraint to see if it is an output operand, 2381 an in-out operand, is commutative, or should match another. */ 2382 2383 while (c = *p++) 2384 { 2385 if (c == '=') 2386 modified[i] = RELOAD_WRITE; 2387 else if (c == '+') 2388 modified[i] = RELOAD_READ_WRITE; 2389 else if (c == '%') 2390 { 2391 /* The last operand should not be marked commutative. */ 2392 if (i == noperands - 1) 2393 { 2394 if (this_insn_is_asm) 2395 warning_for_asm (this_insn, 2396 "`%%' constraint used with last operand"); 2397 else 2398 abort (); 2399 } 2400 else 2401 commutative = i; 2402 } 2403 else if (c >= '0' && c <= '9') 2404 { 2405 c -= '0'; 2406 operands_match[c][i] 2407 = operands_match_p (recog_operand[c], recog_operand[i]); 2408 2409 /* An operand may not match itself. */ 2410 if (c == i) 2411 { 2412 if (this_insn_is_asm) 2413 warning_for_asm (this_insn, 2414 "operand %d has constraint %d", i, c); 2415 else 2416 abort (); 2417 } 2418 2419 /* If C can be commuted with C+1, and C might need to match I, 2420 then C+1 might also need to match I. */ 2421 if (commutative >= 0) 2422 { 2423 if (c == commutative || c == commutative + 1) 2424 { 2425 int other = c + (c == commutative ? 1 : -1); 2426 operands_match[other][i] 2427 = operands_match_p (recog_operand[other], recog_operand[i]); 2428 } 2429 if (i == commutative || i == commutative + 1) 2430 { 2431 int other = i + (i == commutative ? 1 : -1); 2432 operands_match[c][other] 2433 = operands_match_p (recog_operand[c], recog_operand[other]); 2434 } 2435 /* Note that C is supposed to be less than I. 2436 No need to consider altering both C and I because in 2437 that case we would alter one into the other. */ 2438 } 2439 } 2440 } 2441 } 2442 2443 /* Examine each operand that is a memory reference or memory address 2444 and reload parts of the addresses into index registers. 2445 Also here any references to pseudo regs that didn't get hard regs 2446 but are equivalent to constants get replaced in the insn itself 2447 with those constants. Nobody will ever see them again. 2448 2449 Finally, set up the preferred classes of each operand. */ 2450 2451 for (i = 0; i < noperands; i++) 2452 { 2453 register RTX_CODE code = GET_CODE (recog_operand[i]); 2454 2455 address_reloaded[i] = 0; 2456 operand_type[i] = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT 2457 : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT 2458 : RELOAD_OTHER); 2459 address_type[i] 2460 = (modified[i] == RELOAD_READ ? RELOAD_FOR_INPUT_ADDRESS 2461 : modified[i] == RELOAD_WRITE ? RELOAD_FOR_OUTPUT_ADDRESS 2462 : RELOAD_OTHER); 2463 2464 if (*constraints[i] == 0) 2465 /* Ignore things like match_operator operands. */ 2466 ; 2467 else if (constraints[i][0] == 'p') 2468 { 2469 find_reloads_address (VOIDmode, NULL_PTR, 2470 recog_operand[i], recog_operand_loc[i], 2471 i, operand_type[i], ind_levels); 2472 substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; 2473 } 2474 else if (code == MEM) 2475 { 2476 if (find_reloads_address (GET_MODE (recog_operand[i]), 2477 recog_operand_loc[i], 2478 XEXP (recog_operand[i], 0), 2479 &XEXP (recog_operand[i], 0), 2480 i, address_type[i], ind_levels)) 2481 address_reloaded[i] = 1; 2482 substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; 2483 } 2484 else if (code == SUBREG) 2485 substed_operand[i] = recog_operand[i] = *recog_operand_loc[i] 2486 = find_reloads_toplev (recog_operand[i], i, address_type[i], 2487 ind_levels, 2488 set != 0 2489 && &SET_DEST (set) == recog_operand_loc[i]); 2490 else if (code == PLUS) 2491 /* We can get a PLUS as an "operand" as a result of 2492 register elimination. See eliminate_regs and gen_reload. */ 2493 substed_operand[i] = recog_operand[i] = *recog_operand_loc[i] 2494 = find_reloads_toplev (recog_operand[i], i, address_type[i], 2495 ind_levels, 0); 2496 else if (code == REG) 2497 { 2498 /* This is equivalent to calling find_reloads_toplev. 2499 The code is duplicated for speed. 2500 When we find a pseudo always equivalent to a constant, 2501 we replace it by the constant. We must be sure, however, 2502 that we don't try to replace it in the insn in which it 2503 is being set. */ 2504 register int regno = REGNO (recog_operand[i]); 2505 if (reg_equiv_constant[regno] != 0 2506 && (set == 0 || &SET_DEST (set) != recog_operand_loc[i])) 2507 substed_operand[i] = recog_operand[i] 2508 = reg_equiv_constant[regno]; 2509#if 0 /* This might screw code in reload1.c to delete prior output-reload 2510 that feeds this insn. */ 2511 if (reg_equiv_mem[regno] != 0) 2512 substed_operand[i] = recog_operand[i] 2513 = reg_equiv_mem[regno]; 2514#endif 2515 if (reg_equiv_address[regno] != 0) 2516 { 2517 /* If reg_equiv_address is not a constant address, copy it, 2518 since it may be shared. */ 2519 /* We must rerun eliminate_regs, in case the elimination 2520 offsets have changed. */ 2521 rtx address = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], 2522 0, NULL_RTX), 2523 0); 2524 2525 if (rtx_varies_p (address)) 2526 address = copy_rtx (address); 2527 2528 /* If this is an output operand, we must output a CLOBBER 2529 after INSN so find_equiv_reg knows REGNO is being written. 2530 Mark this insn specially, do we can put our output reloads 2531 after it. */ 2532 2533 if (modified[i] != RELOAD_READ) 2534 PUT_MODE (emit_insn_after (gen_rtx (CLOBBER, VOIDmode, 2535 recog_operand[i]), 2536 insn), 2537 DImode); 2538 2539 *recog_operand_loc[i] = recog_operand[i] 2540 = gen_rtx (MEM, GET_MODE (recog_operand[i]), address); 2541 RTX_UNCHANGING_P (recog_operand[i]) 2542 = RTX_UNCHANGING_P (regno_reg_rtx[regno]); 2543 find_reloads_address (GET_MODE (recog_operand[i]), 2544 recog_operand_loc[i], 2545 XEXP (recog_operand[i], 0), 2546 &XEXP (recog_operand[i], 0), 2547 i, address_type[i], ind_levels); 2548 substed_operand[i] = recog_operand[i] = *recog_operand_loc[i]; 2549 } 2550 } 2551 /* If the operand is still a register (we didn't replace it with an 2552 equivalent), get the preferred class to reload it into. */ 2553 code = GET_CODE (recog_operand[i]); 2554 preferred_class[i] 2555 = ((code == REG && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER) 2556 ? reg_preferred_class (REGNO (recog_operand[i])) : NO_REGS); 2557 pref_or_nothing[i] 2558 = (code == REG && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER 2559 && reg_alternate_class (REGNO (recog_operand[i])) == NO_REGS); 2560 } 2561 2562 /* If this is simply a copy from operand 1 to operand 0, merge the 2563 preferred classes for the operands. */ 2564 if (set != 0 && noperands >= 2 && recog_operand[0] == SET_DEST (set) 2565 && recog_operand[1] == SET_SRC (set)) 2566 { 2567 preferred_class[0] = preferred_class[1] 2568 = reg_class_subunion[(int) preferred_class[0]][(int) preferred_class[1]]; 2569 pref_or_nothing[0] |= pref_or_nothing[1]; 2570 pref_or_nothing[1] |= pref_or_nothing[0]; 2571 } 2572 2573 /* Now see what we need for pseudo-regs that didn't get hard regs 2574 or got the wrong kind of hard reg. For this, we must consider 2575 all the operands together against the register constraints. */ 2576 2577 best = MAX_RECOG_OPERANDS + 300; 2578 2579 swapped = 0; 2580 goal_alternative_swapped = 0; 2581 try_swapped: 2582 2583 /* The constraints are made of several alternatives. 2584 Each operand's constraint looks like foo,bar,... with commas 2585 separating the alternatives. The first alternatives for all 2586 operands go together, the second alternatives go together, etc. 2587 2588 First loop over alternatives. */ 2589 2590 for (this_alternative_number = 0; 2591 this_alternative_number < n_alternatives; 2592 this_alternative_number++) 2593 { 2594 /* Loop over operands for one constraint alternative. */ 2595 /* LOSERS counts those that don't fit this alternative 2596 and would require loading. */ 2597 int losers = 0; 2598 /* BAD is set to 1 if it some operand can't fit this alternative 2599 even after reloading. */ 2600 int bad = 0; 2601 /* REJECT is a count of how undesirable this alternative says it is 2602 if any reloading is required. If the alternative matches exactly 2603 then REJECT is ignored, but otherwise it gets this much 2604 counted against it in addition to the reloading needed. Each 2605 ? counts three times here since we want the disparaging caused by 2606 a bad register class to only count 1/3 as much. */ 2607 int reject = 0; 2608 2609 this_earlyclobber = 0; 2610 2611 for (i = 0; i < noperands; i++) 2612 { 2613 register char *p = constraints[i]; 2614 register int win = 0; 2615 /* 0 => this operand can be reloaded somehow for this alternative */ 2616 int badop = 1; 2617 /* 0 => this operand can be reloaded if the alternative allows regs. */ 2618 int winreg = 0; 2619 int c; 2620 register rtx operand = recog_operand[i]; 2621 int offset = 0; 2622 /* Nonzero means this is a MEM that must be reloaded into a reg 2623 regardless of what the constraint says. */ 2624 int force_reload = 0; 2625 int offmemok = 0; 2626 /* Nonzero if a constant forced into memory would be OK for this 2627 operand. */ 2628 int constmemok = 0; 2629 int earlyclobber = 0; 2630 2631 /* If the operand is a SUBREG, extract 2632 the REG or MEM (or maybe even a constant) within. 2633 (Constants can occur as a result of reg_equiv_constant.) */ 2634 2635 while (GET_CODE (operand) == SUBREG) 2636 { 2637 offset += SUBREG_WORD (operand); 2638 operand = SUBREG_REG (operand); 2639 /* Force reload if this is a constant or PLUS or if there may may 2640 be a problem accessing OPERAND in the outer mode. */ 2641 if (CONSTANT_P (operand) 2642 || GET_CODE (operand) == PLUS 2643 /* We must force a reload of paradoxical SUBREGs 2644 of a MEM because the alignment of the inner value 2645 may not be enough to do the outer reference. On 2646 big-endian machines, it may also reference outside 2647 the object. 2648 2649 On machines that extend byte operations and we have a 2650 SUBREG where both the inner and outer modes are no wider 2651 than a word and the inner mode is narrower, is integral, 2652 and gets extended when loaded from memory, combine.c has 2653 made assumptions about the behavior of the machine in such 2654 register access. If the data is, in fact, in memory we 2655 must always load using the size assumed to be in the 2656 register and let the insn do the different-sized 2657 accesses. */ 2658 || ((GET_CODE (operand) == MEM 2659 || (GET_CODE (operand)== REG 2660 && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) 2661 && (((GET_MODE_BITSIZE (GET_MODE (operand)) 2662 < BIGGEST_ALIGNMENT) 2663 && (GET_MODE_SIZE (operand_mode[i]) 2664 > GET_MODE_SIZE (GET_MODE (operand)))) 2665 || (GET_CODE (operand) == MEM && BYTES_BIG_ENDIAN) 2666#ifdef LOAD_EXTEND_OP 2667 || (GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD 2668 && (GET_MODE_SIZE (GET_MODE (operand)) 2669 <= UNITS_PER_WORD) 2670 && (GET_MODE_SIZE (operand_mode[i]) 2671 > GET_MODE_SIZE (GET_MODE (operand))) 2672 && INTEGRAL_MODE_P (GET_MODE (operand)) 2673 && LOAD_EXTEND_OP (GET_MODE (operand)) != NIL) 2674#endif 2675 )) 2676 /* Subreg of a hard reg which can't handle the subreg's mode 2677 or which would handle that mode in the wrong number of 2678 registers for subregging to work. */ 2679 || (GET_CODE (operand) == REG 2680 && REGNO (operand) < FIRST_PSEUDO_REGISTER 2681 && ((GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD 2682 && (GET_MODE_SIZE (GET_MODE (operand)) 2683 > UNITS_PER_WORD) 2684 && ((GET_MODE_SIZE (GET_MODE (operand)) 2685 / UNITS_PER_WORD) 2686 != HARD_REGNO_NREGS (REGNO (operand), 2687 GET_MODE (operand)))) 2688 || ! HARD_REGNO_MODE_OK (REGNO (operand) + offset, 2689 operand_mode[i])))) 2690 force_reload = 1; 2691 } 2692 2693 this_alternative[i] = (int) NO_REGS; 2694 this_alternative_win[i] = 0; 2695 this_alternative_offmemok[i] = 0; 2696 this_alternative_earlyclobber[i] = 0; 2697 this_alternative_matches[i] = -1; 2698 2699 /* An empty constraint or empty alternative 2700 allows anything which matched the pattern. */ 2701 if (*p == 0 || *p == ',') 2702 win = 1, badop = 0; 2703 2704 /* Scan this alternative's specs for this operand; 2705 set WIN if the operand fits any letter in this alternative. 2706 Otherwise, clear BADOP if this operand could 2707 fit some letter after reloads, 2708 or set WINREG if this operand could fit after reloads 2709 provided the constraint allows some registers. */ 2710 2711 while (*p && (c = *p++) != ',') 2712 switch (c) 2713 { 2714 case '=': 2715 case '+': 2716 case '*': 2717 break; 2718 2719 case '%': 2720 /* The last operand should not be marked commutative. */ 2721 if (i != noperands - 1) 2722 commutative = i; 2723 break; 2724 2725 case '?': 2726 reject += 3; 2727 break; 2728 2729 case '!': 2730 reject = 300; 2731 break; 2732 2733 case '#': 2734 /* Ignore rest of this alternative as far as 2735 reloading is concerned. */ 2736 while (*p && *p != ',') p++; 2737 break; 2738 2739 case '0': 2740 case '1': 2741 case '2': 2742 case '3': 2743 case '4': 2744 c -= '0'; 2745 this_alternative_matches[i] = c; 2746 /* We are supposed to match a previous operand. 2747 If we do, we win if that one did. 2748 If we do not, count both of the operands as losers. 2749 (This is too conservative, since most of the time 2750 only a single reload insn will be needed to make 2751 the two operands win. As a result, this alternative 2752 may be rejected when it is actually desirable.) */ 2753 if ((swapped && (c != commutative || i != commutative + 1)) 2754 /* If we are matching as if two operands were swapped, 2755 also pretend that operands_match had been computed 2756 with swapped. 2757 But if I is the second of those and C is the first, 2758 don't exchange them, because operands_match is valid 2759 only on one side of its diagonal. */ 2760 ? (operands_match 2761 [(c == commutative || c == commutative + 1) 2762 ? 2*commutative + 1 - c : c] 2763 [(i == commutative || i == commutative + 1) 2764 ? 2*commutative + 1 - i : i]) 2765 : operands_match[c][i]) 2766 win = this_alternative_win[c]; 2767 else 2768 { 2769 /* Operands don't match. */ 2770 rtx value; 2771 /* Retroactively mark the operand we had to match 2772 as a loser, if it wasn't already. */ 2773 if (this_alternative_win[c]) 2774 losers++; 2775 this_alternative_win[c] = 0; 2776 if (this_alternative[c] == (int) NO_REGS) 2777 bad = 1; 2778 /* But count the pair only once in the total badness of 2779 this alternative, if the pair can be a dummy reload. */ 2780 value 2781 = find_dummy_reload (recog_operand[i], recog_operand[c], 2782 recog_operand_loc[i], recog_operand_loc[c], 2783 operand_mode[i], operand_mode[c], 2784 this_alternative[c], -1); 2785 2786 if (value != 0) 2787 losers--; 2788 } 2789 /* This can be fixed with reloads if the operand 2790 we are supposed to match can be fixed with reloads. */ 2791 badop = 0; 2792 this_alternative[i] = this_alternative[c]; 2793 2794 /* If we have to reload this operand and some previous 2795 operand also had to match the same thing as this 2796 operand, we don't know how to do that. So reject this 2797 alternative. */ 2798 if (! win || force_reload) 2799 for (j = 0; j < i; j++) 2800 if (this_alternative_matches[j] 2801 == this_alternative_matches[i]) 2802 badop = 1; 2803 2804 break; 2805 2806 case 'p': 2807 /* All necessary reloads for an address_operand 2808 were handled in find_reloads_address. */ 2809 this_alternative[i] = (int) BASE_REG_CLASS; 2810 win = 1; 2811 break; 2812 2813 case 'm': 2814 if (force_reload) 2815 break; 2816 if (GET_CODE (operand) == MEM 2817 || (GET_CODE (operand) == REG 2818 && REGNO (operand) >= FIRST_PSEUDO_REGISTER 2819 && reg_renumber[REGNO (operand)] < 0)) 2820 win = 1; 2821 if (CONSTANT_P (operand)) 2822 badop = 0; 2823 constmemok = 1; 2824 break; 2825 2826 case '<': 2827 if (GET_CODE (operand) == MEM 2828 && ! address_reloaded[i] 2829 && (GET_CODE (XEXP (operand, 0)) == PRE_DEC 2830 || GET_CODE (XEXP (operand, 0)) == POST_DEC)) 2831 win = 1; 2832 break; 2833 2834 case '>': 2835 if (GET_CODE (operand) == MEM 2836 && ! address_reloaded[i] 2837 && (GET_CODE (XEXP (operand, 0)) == PRE_INC 2838 || GET_CODE (XEXP (operand, 0)) == POST_INC)) 2839 win = 1; 2840 break; 2841 2842 /* Memory operand whose address is not offsettable. */ 2843 case 'V': 2844 if (force_reload) 2845 break; 2846 if (GET_CODE (operand) == MEM 2847 && ! (ind_levels ? offsettable_memref_p (operand) 2848 : offsettable_nonstrict_memref_p (operand)) 2849 /* Certain mem addresses will become offsettable 2850 after they themselves are reloaded. This is important; 2851 we don't want our own handling of unoffsettables 2852 to override the handling of reg_equiv_address. */ 2853 && !(GET_CODE (XEXP (operand, 0)) == REG 2854 && (ind_levels == 0 2855 || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0))) 2856 win = 1; 2857 break; 2858 2859 /* Memory operand whose address is offsettable. */ 2860 case 'o': 2861 if (force_reload) 2862 break; 2863 if ((GET_CODE (operand) == MEM 2864 /* If IND_LEVELS, find_reloads_address won't reload a 2865 pseudo that didn't get a hard reg, so we have to 2866 reject that case. */ 2867 && (ind_levels ? offsettable_memref_p (operand) 2868 : offsettable_nonstrict_memref_p (operand))) 2869 /* A reloaded auto-increment address is offsettable, 2870 because it is now just a simple register indirect. */ 2871 || (GET_CODE (operand) == MEM 2872 && address_reloaded[i] 2873 && (GET_CODE (XEXP (operand, 0)) == PRE_INC 2874 || GET_CODE (XEXP (operand, 0)) == PRE_DEC 2875 || GET_CODE (XEXP (operand, 0)) == POST_INC 2876 || GET_CODE (XEXP (operand, 0)) == POST_DEC)) 2877 /* Certain mem addresses will become offsettable 2878 after they themselves are reloaded. This is important; 2879 we don't want our own handling of unoffsettables 2880 to override the handling of reg_equiv_address. */ 2881 || (GET_CODE (operand) == MEM 2882 && GET_CODE (XEXP (operand, 0)) == REG 2883 && (ind_levels == 0 2884 || reg_equiv_address[REGNO (XEXP (operand, 0))] != 0)) 2885 || (GET_CODE (operand) == REG 2886 && REGNO (operand) >= FIRST_PSEUDO_REGISTER 2887 && reg_renumber[REGNO (operand)] < 0 2888 /* If reg_equiv_address is nonzero, we will be 2889 loading it into a register; hence it will be 2890 offsettable, but we cannot say that reg_equiv_mem 2891 is offsettable without checking. */ 2892 && ((reg_equiv_mem[REGNO (operand)] != 0 2893 && offsettable_memref_p (reg_equiv_mem[REGNO (operand)])) 2894 || (reg_equiv_address[REGNO (operand)] != 0)))) 2895 win = 1; 2896 if (CONSTANT_P (operand) || GET_CODE (operand) == MEM) 2897 badop = 0; 2898 constmemok = 1; 2899 offmemok = 1; 2900 break; 2901 2902 case '&': 2903 /* Output operand that is stored before the need for the 2904 input operands (and their index registers) is over. */ 2905 earlyclobber = 1, this_earlyclobber = 1; 2906 break; 2907 2908 case 'E': 2909#ifndef REAL_ARITHMETIC 2910 /* Match any floating double constant, but only if 2911 we can examine the bits of it reliably. */ 2912 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT 2913 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD) 2914 && GET_MODE (operand) != VOIDmode && ! flag_pretend_float) 2915 break; 2916#endif 2917 if (GET_CODE (operand) == CONST_DOUBLE) 2918 win = 1; 2919 break; 2920 2921 case 'F': 2922 if (GET_CODE (operand) == CONST_DOUBLE) 2923 win = 1; 2924 break; 2925 2926 case 'G': 2927 case 'H': 2928 if (GET_CODE (operand) == CONST_DOUBLE 2929 && CONST_DOUBLE_OK_FOR_LETTER_P (operand, c)) 2930 win = 1; 2931 break; 2932 2933 case 's': 2934 if (GET_CODE (operand) == CONST_INT 2935 || (GET_CODE (operand) == CONST_DOUBLE 2936 && GET_MODE (operand) == VOIDmode)) 2937 break; 2938 case 'i': 2939 if (CONSTANT_P (operand) 2940#ifdef LEGITIMATE_PIC_OPERAND_P 2941 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (operand)) 2942#endif 2943 ) 2944 win = 1; 2945 break; 2946 2947 case 'n': 2948 if (GET_CODE (operand) == CONST_INT 2949 || (GET_CODE (operand) == CONST_DOUBLE 2950 && GET_MODE (operand) == VOIDmode)) 2951 win = 1; 2952 break; 2953 2954 case 'I': 2955 case 'J': 2956 case 'K': 2957 case 'L': 2958 case 'M': 2959 case 'N': 2960 case 'O': 2961 case 'P': 2962 if (GET_CODE (operand) == CONST_INT 2963 && CONST_OK_FOR_LETTER_P (INTVAL (operand), c)) 2964 win = 1; 2965 break; 2966 2967 case 'X': 2968 win = 1; 2969 break; 2970 2971 case 'g': 2972 if (! force_reload 2973 /* A PLUS is never a valid operand, but reload can make 2974 it from a register when eliminating registers. */ 2975 && GET_CODE (operand) != PLUS 2976 /* A SCRATCH is not a valid operand. */ 2977 && GET_CODE (operand) != SCRATCH 2978#ifdef LEGITIMATE_PIC_OPERAND_P 2979 && (! CONSTANT_P (operand) 2980 || ! flag_pic 2981 || LEGITIMATE_PIC_OPERAND_P (operand)) 2982#endif 2983 && (GENERAL_REGS == ALL_REGS 2984 || GET_CODE (operand) != REG 2985 || (REGNO (operand) >= FIRST_PSEUDO_REGISTER 2986 && reg_renumber[REGNO (operand)] < 0))) 2987 win = 1; 2988 /* Drop through into 'r' case */ 2989 2990 case 'r': 2991 this_alternative[i] 2992 = (int) reg_class_subunion[this_alternative[i]][(int) GENERAL_REGS]; 2993 goto reg; 2994 2995#ifdef EXTRA_CONSTRAINT 2996 case 'Q': 2997 case 'R': 2998 case 'S': 2999 case 'T': 3000 case 'U': 3001 if (EXTRA_CONSTRAINT (operand, c)) 3002 win = 1; 3003 break; 3004#endif 3005 3006 default: 3007 this_alternative[i] 3008 = (int) reg_class_subunion[this_alternative[i]][(int) REG_CLASS_FROM_LETTER (c)]; 3009 3010 reg: 3011 if (GET_MODE (operand) == BLKmode) 3012 break; 3013 winreg = 1; 3014 if (GET_CODE (operand) == REG 3015 && reg_fits_class_p (operand, this_alternative[i], 3016 offset, GET_MODE (recog_operand[i]))) 3017 win = 1; 3018 break; 3019 } 3020 3021 constraints[i] = p; 3022 3023 /* If this operand could be handled with a reg, 3024 and some reg is allowed, then this operand can be handled. */ 3025 if (winreg && this_alternative[i] != (int) NO_REGS) 3026 badop = 0; 3027 3028 /* Record which operands fit this alternative. */ 3029 this_alternative_earlyclobber[i] = earlyclobber; 3030 if (win && ! force_reload) 3031 this_alternative_win[i] = 1; 3032 else 3033 { 3034 int const_to_mem = 0; 3035 3036 this_alternative_offmemok[i] = offmemok; 3037 losers++; 3038 if (badop) 3039 bad = 1; 3040 /* Alternative loses if it has no regs for a reg operand. */ 3041 if (GET_CODE (operand) == REG 3042 && this_alternative[i] == (int) NO_REGS 3043 && this_alternative_matches[i] < 0) 3044 bad = 1; 3045 3046 /* Alternative loses if it requires a type of reload not 3047 permitted for this insn. We can always reload SCRATCH 3048 and objects with a REG_UNUSED note. */ 3049 if (GET_CODE (operand) != SCRATCH 3050 && modified[i] != RELOAD_READ && no_output_reloads 3051 && ! find_reg_note (insn, REG_UNUSED, operand)) 3052 bad = 1; 3053 else if (modified[i] != RELOAD_WRITE && no_input_reloads) 3054 bad = 1; 3055 3056 /* If this is a constant that is reloaded into the desired 3057 class by copying it to memory first, count that as another 3058 reload. This is consistent with other code and is 3059 required to avoid choosing another alternative when 3060 the constant is moved into memory by this function on 3061 an early reload pass. Note that the test here is 3062 precisely the same as in the code below that calls 3063 force_const_mem. */ 3064 if (CONSTANT_P (operand) 3065 /* force_const_mem does not accept HIGH. */ 3066 && GET_CODE (operand) != HIGH 3067 && (PREFERRED_RELOAD_CLASS (operand, 3068 (enum reg_class) this_alternative[i]) 3069 == NO_REGS) 3070 && operand_mode[i] != VOIDmode) 3071 { 3072 const_to_mem = 1; 3073 if (this_alternative[i] != (int) NO_REGS) 3074 losers++; 3075 } 3076 3077 /* If we can't reload this value at all, reject this 3078 alternative. Note that we could also lose due to 3079 LIMIT_RELOAD_RELOAD_CLASS, but we don't check that 3080 here. */ 3081 3082 if (! CONSTANT_P (operand) 3083 && (enum reg_class) this_alternative[i] != NO_REGS 3084 && (PREFERRED_RELOAD_CLASS (operand, 3085 (enum reg_class) this_alternative[i]) 3086 == NO_REGS)) 3087 bad = 1; 3088 3089 /* We prefer to reload pseudos over reloading other things, 3090 since such reloads may be able to be eliminated later. 3091 If we are reloading a SCRATCH, we won't be generating any 3092 insns, just using a register, so it is also preferred. 3093 So bump REJECT in other cases. Don't do this in the 3094 case where we are forcing a constant into memory and 3095 it will then win since we don't want to have a different 3096 alternative match then. */ 3097 if (! (GET_CODE (operand) == REG 3098 && REGNO (operand) >= FIRST_PSEUDO_REGISTER) 3099 && GET_CODE (operand) != SCRATCH 3100 && ! (const_to_mem && constmemok)) 3101 reject++; 3102 } 3103 3104 /* If this operand is a pseudo register that didn't get a hard 3105 reg and this alternative accepts some register, see if the 3106 class that we want is a subset of the preferred class for this 3107 register. If not, but it intersects that class, use the 3108 preferred class instead. If it does not intersect the preferred 3109 class, show that usage of this alternative should be discouraged; 3110 it will be discouraged more still if the register is `preferred 3111 or nothing'. We do this because it increases the chance of 3112 reusing our spill register in a later insn and avoiding a pair 3113 of memory stores and loads. 3114 3115 Don't bother with this if this alternative will accept this 3116 operand. 3117 3118 Don't do this for a multiword operand, since it is only a 3119 small win and has the risk of requiring more spill registers, 3120 which could cause a large loss. 3121 3122 Don't do this if the preferred class has only one register 3123 because we might otherwise exhaust the class. */ 3124 3125 3126 if (! win && this_alternative[i] != (int) NO_REGS 3127 && GET_MODE_SIZE (operand_mode[i]) <= UNITS_PER_WORD 3128 && reg_class_size[(int) preferred_class[i]] > 1) 3129 { 3130 if (! reg_class_subset_p (this_alternative[i], 3131 preferred_class[i])) 3132 { 3133 /* Since we don't have a way of forming the intersection, 3134 we just do something special if the preferred class 3135 is a subset of the class we have; that's the most 3136 common case anyway. */ 3137 if (reg_class_subset_p (preferred_class[i], 3138 this_alternative[i])) 3139 this_alternative[i] = (int) preferred_class[i]; 3140 else 3141 reject += (1 + pref_or_nothing[i]); 3142 } 3143 } 3144 } 3145 3146 /* Now see if any output operands that are marked "earlyclobber" 3147 in this alternative conflict with any input operands 3148 or any memory addresses. */ 3149 3150 for (i = 0; i < noperands; i++) 3151 if (this_alternative_earlyclobber[i] 3152 && this_alternative_win[i]) 3153 { 3154 struct decomposition early_data; 3155 3156 early_data = decompose (recog_operand[i]); 3157 3158 if (modified[i] == RELOAD_READ) 3159 { 3160 if (this_insn_is_asm) 3161 warning_for_asm (this_insn, 3162 "`&' constraint used with input operand"); 3163 else 3164 abort (); 3165 continue; 3166 } 3167 3168 if (this_alternative[i] == NO_REGS) 3169 { 3170 this_alternative_earlyclobber[i] = 0; 3171 if (this_insn_is_asm) 3172 error_for_asm (this_insn, 3173 "`&' constraint used with no register class"); 3174 else 3175 abort (); 3176 } 3177 3178 for (j = 0; j < noperands; j++) 3179 /* Is this an input operand or a memory ref? */ 3180 if ((GET_CODE (recog_operand[j]) == MEM 3181 || modified[j] != RELOAD_WRITE) 3182 && j != i 3183 /* Ignore things like match_operator operands. */ 3184 && *constraints1[j] != 0 3185 /* Don't count an input operand that is constrained to match 3186 the early clobber operand. */ 3187 && ! (this_alternative_matches[j] == i 3188 && rtx_equal_p (recog_operand[i], recog_operand[j])) 3189 /* Is it altered by storing the earlyclobber operand? */ 3190 && !immune_p (recog_operand[j], recog_operand[i], early_data)) 3191 { 3192 /* If the output is in a single-reg class, 3193 it's costly to reload it, so reload the input instead. */ 3194 if (reg_class_size[this_alternative[i]] == 1 3195 && (GET_CODE (recog_operand[j]) == REG 3196 || GET_CODE (recog_operand[j]) == SUBREG)) 3197 { 3198 losers++; 3199 this_alternative_win[j] = 0; 3200 } 3201 else 3202 break; 3203 } 3204 /* If an earlyclobber operand conflicts with something, 3205 it must be reloaded, so request this and count the cost. */ 3206 if (j != noperands) 3207 { 3208 losers++; 3209 this_alternative_win[i] = 0; 3210 for (j = 0; j < noperands; j++) 3211 if (this_alternative_matches[j] == i 3212 && this_alternative_win[j]) 3213 { 3214 this_alternative_win[j] = 0; 3215 losers++; 3216 } 3217 } 3218 } 3219 3220 /* If one alternative accepts all the operands, no reload required, 3221 choose that alternative; don't consider the remaining ones. */ 3222 if (losers == 0) 3223 { 3224 /* Unswap these so that they are never swapped at `finish'. */ 3225 if (commutative >= 0) 3226 { 3227 recog_operand[commutative] = substed_operand[commutative]; 3228 recog_operand[commutative + 1] 3229 = substed_operand[commutative + 1]; 3230 } 3231 for (i = 0; i < noperands; i++) 3232 { 3233 goal_alternative_win[i] = 1; 3234 goal_alternative[i] = this_alternative[i]; 3235 goal_alternative_offmemok[i] = this_alternative_offmemok[i]; 3236 goal_alternative_matches[i] = this_alternative_matches[i]; 3237 goal_alternative_earlyclobber[i] 3238 = this_alternative_earlyclobber[i]; 3239 } 3240 goal_alternative_number = this_alternative_number; 3241 goal_alternative_swapped = swapped; 3242 goal_earlyclobber = this_earlyclobber; 3243 goto finish; 3244 } 3245 3246 /* REJECT, set by the ! and ? constraint characters and when a register 3247 would be reloaded into a non-preferred class, discourages the use of 3248 this alternative for a reload goal. REJECT is incremented by three 3249 for each ? and one for each non-preferred class. */ 3250 losers = losers * 3 + reject; 3251 3252 /* If this alternative can be made to work by reloading, 3253 and it needs less reloading than the others checked so far, 3254 record it as the chosen goal for reloading. */ 3255 if (! bad && best > losers) 3256 { 3257 for (i = 0; i < noperands; i++) 3258 { 3259 goal_alternative[i] = this_alternative[i]; 3260 goal_alternative_win[i] = this_alternative_win[i]; 3261 goal_alternative_offmemok[i] = this_alternative_offmemok[i]; 3262 goal_alternative_matches[i] = this_alternative_matches[i]; 3263 goal_alternative_earlyclobber[i] 3264 = this_alternative_earlyclobber[i]; 3265 } 3266 goal_alternative_swapped = swapped; 3267 best = losers; 3268 goal_alternative_number = this_alternative_number; 3269 goal_earlyclobber = this_earlyclobber; 3270 } 3271 } 3272 3273 /* If insn is commutative (it's safe to exchange a certain pair of operands) 3274 then we need to try each alternative twice, 3275 the second time matching those two operands 3276 as if we had exchanged them. 3277 To do this, really exchange them in operands. 3278 3279 If we have just tried the alternatives the second time, 3280 return operands to normal and drop through. */ 3281 3282 if (commutative >= 0) 3283 { 3284 swapped = !swapped; 3285 if (swapped) 3286 { 3287 register enum reg_class tclass; 3288 register int t; 3289 3290 recog_operand[commutative] = substed_operand[commutative + 1]; 3291 recog_operand[commutative + 1] = substed_operand[commutative]; 3292 3293 tclass = preferred_class[commutative]; 3294 preferred_class[commutative] = preferred_class[commutative + 1]; 3295 preferred_class[commutative + 1] = tclass; 3296 3297 t = pref_or_nothing[commutative]; 3298 pref_or_nothing[commutative] = pref_or_nothing[commutative + 1]; 3299 pref_or_nothing[commutative + 1] = t; 3300 3301 bcopy ((char *) constraints1, (char *) constraints, 3302 noperands * sizeof (char *)); 3303 goto try_swapped; 3304 } 3305 else 3306 { 3307 recog_operand[commutative] = substed_operand[commutative]; 3308 recog_operand[commutative + 1] = substed_operand[commutative + 1]; 3309 } 3310 } 3311 3312 /* The operands don't meet the constraints. 3313 goal_alternative describes the alternative 3314 that we could reach by reloading the fewest operands. 3315 Reload so as to fit it. */ 3316 3317 if (best == MAX_RECOG_OPERANDS + 300) 3318 { 3319 /* No alternative works with reloads?? */ 3320 if (insn_code_number >= 0) 3321 abort (); 3322 error_for_asm (insn, "inconsistent operand constraints in an `asm'"); 3323 /* Avoid further trouble with this insn. */ 3324 PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx); 3325 n_reloads = 0; 3326 return; 3327 } 3328 3329 /* Jump to `finish' from above if all operands are valid already. 3330 In that case, goal_alternative_win is all 1. */ 3331 finish: 3332 3333 /* Right now, for any pair of operands I and J that are required to match, 3334 with I < J, 3335 goal_alternative_matches[J] is I. 3336 Set up goal_alternative_matched as the inverse function: 3337 goal_alternative_matched[I] = J. */ 3338 3339 for (i = 0; i < noperands; i++) 3340 goal_alternative_matched[i] = -1; 3341 3342 for (i = 0; i < noperands; i++) 3343 if (! goal_alternative_win[i] 3344 && goal_alternative_matches[i] >= 0) 3345 goal_alternative_matched[goal_alternative_matches[i]] = i; 3346 3347 /* If the best alternative is with operands 1 and 2 swapped, 3348 consider them swapped before reporting the reloads. Update the 3349 operand numbers of any reloads already pushed. */ 3350 3351 if (goal_alternative_swapped) 3352 { 3353 register rtx tem; 3354 3355 tem = substed_operand[commutative]; 3356 substed_operand[commutative] = substed_operand[commutative + 1]; 3357 substed_operand[commutative + 1] = tem; 3358 tem = recog_operand[commutative]; 3359 recog_operand[commutative] = recog_operand[commutative + 1]; 3360 recog_operand[commutative + 1] = tem; 3361 3362 for (i = 0; i < n_reloads; i++) 3363 { 3364 if (reload_opnum[i] == commutative) 3365 reload_opnum[i] = commutative + 1; 3366 else if (reload_opnum[i] == commutative + 1) 3367 reload_opnum[i] = commutative; 3368 } 3369 } 3370 3371 /* Perform whatever substitutions on the operands we are supposed 3372 to make due to commutativity or replacement of registers 3373 with equivalent constants or memory slots. */ 3374 3375 for (i = 0; i < noperands; i++) 3376 { 3377 *recog_operand_loc[i] = substed_operand[i]; 3378 /* While we are looping on operands, initialize this. */ 3379 operand_reloadnum[i] = -1; 3380 3381 /* If this is an earlyclobber operand, we need to widen the scope. 3382 The reload must remain valid from the start of the insn being 3383 reloaded until after the operand is stored into its destination. 3384 We approximate this with RELOAD_OTHER even though we know that we 3385 do not conflict with RELOAD_FOR_INPUT_ADDRESS reloads. 3386 3387 One special case that is worth checking is when we have an 3388 output that is earlyclobber but isn't used past the insn (typically 3389 a SCRATCH). In this case, we only need have the reload live 3390 through the insn itself, but not for any of our input or output 3391 reloads. 3392 3393 In any case, anything needed to address this operand can remain 3394 however they were previously categorized. */ 3395 3396 if (goal_alternative_earlyclobber[i]) 3397 operand_type[i] 3398 = (find_reg_note (insn, REG_UNUSED, recog_operand[i]) 3399 ? RELOAD_FOR_INSN : RELOAD_OTHER); 3400 } 3401 3402 /* Any constants that aren't allowed and can't be reloaded 3403 into registers are here changed into memory references. */ 3404 for (i = 0; i < noperands; i++) 3405 if (! goal_alternative_win[i] 3406 && CONSTANT_P (recog_operand[i]) 3407 /* force_const_mem does not accept HIGH. */ 3408 && GET_CODE (recog_operand[i]) != HIGH 3409 && (PREFERRED_RELOAD_CLASS (recog_operand[i], 3410 (enum reg_class) goal_alternative[i]) 3411 == NO_REGS) 3412 && operand_mode[i] != VOIDmode) 3413 { 3414 *recog_operand_loc[i] = recog_operand[i] 3415 = find_reloads_toplev (force_const_mem (operand_mode[i], 3416 recog_operand[i]), 3417 i, address_type[i], ind_levels, 0); 3418 if (alternative_allows_memconst (constraints1[i], 3419 goal_alternative_number)) 3420 goal_alternative_win[i] = 1; 3421 } 3422 3423 /* Record the values of the earlyclobber operands for the caller. */ 3424 if (goal_earlyclobber) 3425 for (i = 0; i < noperands; i++) 3426 if (goal_alternative_earlyclobber[i]) 3427 reload_earlyclobbers[n_earlyclobbers++] = recog_operand[i]; 3428 3429 /* Now record reloads for all the operands that need them. */ 3430 for (i = 0; i < noperands; i++) 3431 if (! goal_alternative_win[i]) 3432 { 3433 /* Operands that match previous ones have already been handled. */ 3434 if (goal_alternative_matches[i] >= 0) 3435 ; 3436 /* Handle an operand with a nonoffsettable address 3437 appearing where an offsettable address will do 3438 by reloading the address into a base register. 3439 3440 ??? We can also do this when the operand is a register and 3441 reg_equiv_mem is not offsettable, but this is a bit tricky, 3442 so we don't bother with it. It may not be worth doing. */ 3443 else if (goal_alternative_matched[i] == -1 3444 && goal_alternative_offmemok[i] 3445 && GET_CODE (recog_operand[i]) == MEM) 3446 { 3447 operand_reloadnum[i] 3448 = push_reload (XEXP (recog_operand[i], 0), NULL_RTX, 3449 &XEXP (recog_operand[i], 0), NULL_PTR, 3450 BASE_REG_CLASS, GET_MODE (XEXP (recog_operand[i], 0)), 3451 VOIDmode, 0, 0, i, RELOAD_FOR_INPUT); 3452 reload_inc[operand_reloadnum[i]] 3453 = GET_MODE_SIZE (GET_MODE (recog_operand[i])); 3454 3455 /* If this operand is an output, we will have made any 3456 reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but 3457 now we are treating part of the operand as an input, so 3458 we must change these to RELOAD_FOR_INPUT_ADDRESS. */ 3459 3460 if (modified[i] == RELOAD_WRITE) 3461 for (j = 0; j < n_reloads; j++) 3462 if (reload_opnum[j] == i 3463 && reload_when_needed[j] == RELOAD_FOR_OUTPUT_ADDRESS) 3464 reload_when_needed[j] = RELOAD_FOR_INPUT_ADDRESS; 3465 } 3466 else if (goal_alternative_matched[i] == -1) 3467 operand_reloadnum[i] = 3468 push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0, 3469 modified[i] != RELOAD_READ ? recog_operand[i] : 0, 3470 (modified[i] != RELOAD_WRITE ? 3471 recog_operand_loc[i] : 0), 3472 modified[i] != RELOAD_READ ? recog_operand_loc[i] : 0, 3473 (enum reg_class) goal_alternative[i], 3474 (modified[i] == RELOAD_WRITE 3475 ? VOIDmode : operand_mode[i]), 3476 (modified[i] == RELOAD_READ 3477 ? VOIDmode : operand_mode[i]), 3478 (insn_code_number < 0 ? 0 3479 : insn_operand_strict_low[insn_code_number][i]), 3480 0, i, operand_type[i]); 3481 /* In a matching pair of operands, one must be input only 3482 and the other must be output only. 3483 Pass the input operand as IN and the other as OUT. */ 3484 else if (modified[i] == RELOAD_READ 3485 && modified[goal_alternative_matched[i]] == RELOAD_WRITE) 3486 { 3487 operand_reloadnum[i] 3488 = push_reload (recog_operand[i], 3489 recog_operand[goal_alternative_matched[i]], 3490 recog_operand_loc[i], 3491 recog_operand_loc[goal_alternative_matched[i]], 3492 (enum reg_class) goal_alternative[i], 3493 operand_mode[i], 3494 operand_mode[goal_alternative_matched[i]], 3495 0, 0, i, RELOAD_OTHER); 3496 operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum; 3497 } 3498 else if (modified[i] == RELOAD_WRITE 3499 && modified[goal_alternative_matched[i]] == RELOAD_READ) 3500 { 3501 operand_reloadnum[goal_alternative_matched[i]] 3502 = push_reload (recog_operand[goal_alternative_matched[i]], 3503 recog_operand[i], 3504 recog_operand_loc[goal_alternative_matched[i]], 3505 recog_operand_loc[i], 3506 (enum reg_class) goal_alternative[i], 3507 operand_mode[goal_alternative_matched[i]], 3508 operand_mode[i], 3509 0, 0, i, RELOAD_OTHER); 3510 operand_reloadnum[i] = output_reloadnum; 3511 } 3512 else if (insn_code_number >= 0) 3513 abort (); 3514 else 3515 { 3516 error_for_asm (insn, "inconsistent operand constraints in an `asm'"); 3517 /* Avoid further trouble with this insn. */ 3518 PATTERN (insn) = gen_rtx (USE, VOIDmode, const0_rtx); 3519 n_reloads = 0; 3520 return; 3521 } 3522 } 3523 else if (goal_alternative_matched[i] < 0 3524 && goal_alternative_matches[i] < 0 3525 && optimize) 3526 { 3527 /* For each non-matching operand that's a MEM or a pseudo-register 3528 that didn't get a hard register, make an optional reload. 3529 This may get done even if the insn needs no reloads otherwise. */ 3530 3531 rtx operand = recog_operand[i]; 3532 3533 while (GET_CODE (operand) == SUBREG) 3534 operand = XEXP (operand, 0); 3535 if ((GET_CODE (operand) == MEM 3536 || (GET_CODE (operand) == REG 3537 && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) 3538 && (enum reg_class) goal_alternative[i] != NO_REGS 3539 && ! no_input_reloads 3540 /* Optional output reloads don't do anything and we mustn't 3541 make in-out reloads on insns that are not permitted output 3542 reloads. */ 3543 && (modified[i] == RELOAD_READ 3544 || (modified[i] == RELOAD_READ_WRITE && ! no_output_reloads))) 3545 operand_reloadnum[i] 3546 = push_reload (modified[i] != RELOAD_WRITE ? recog_operand[i] : 0, 3547 modified[i] != RELOAD_READ ? recog_operand[i] : 0, 3548 (modified[i] != RELOAD_WRITE 3549 ? recog_operand_loc[i] : 0), 3550 (modified[i] != RELOAD_READ 3551 ? recog_operand_loc[i] : 0), 3552 (enum reg_class) goal_alternative[i], 3553 (modified[i] == RELOAD_WRITE 3554 ? VOIDmode : operand_mode[i]), 3555 (modified[i] == RELOAD_READ 3556 ? VOIDmode : operand_mode[i]), 3557 (insn_code_number < 0 ? 0 3558 : insn_operand_strict_low[insn_code_number][i]), 3559 1, i, operand_type[i]); 3560 } 3561 else if (goal_alternative_matches[i] >= 0 3562 && goal_alternative_win[goal_alternative_matches[i]] 3563 && modified[i] == RELOAD_READ 3564 && modified[goal_alternative_matches[i]] == RELOAD_WRITE 3565 && ! no_input_reloads && ! no_output_reloads 3566 && optimize) 3567 { 3568 /* Similarly, make an optional reload for a pair of matching 3569 objects that are in MEM or a pseudo that didn't get a hard reg. */ 3570 3571 rtx operand = recog_operand[i]; 3572 3573 while (GET_CODE (operand) == SUBREG) 3574 operand = XEXP (operand, 0); 3575 if ((GET_CODE (operand) == MEM 3576 || (GET_CODE (operand) == REG 3577 && REGNO (operand) >= FIRST_PSEUDO_REGISTER)) 3578 && ((enum reg_class) goal_alternative[goal_alternative_matches[i]] 3579 != NO_REGS)) 3580 operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]] 3581 = push_reload (recog_operand[goal_alternative_matches[i]], 3582 recog_operand[i], 3583 recog_operand_loc[goal_alternative_matches[i]], 3584 recog_operand_loc[i], 3585 (enum reg_class) goal_alternative[goal_alternative_matches[i]], 3586 operand_mode[goal_alternative_matches[i]], 3587 operand_mode[i], 3588 0, 1, goal_alternative_matches[i], RELOAD_OTHER); 3589 } 3590 3591 /* If this insn pattern contains any MATCH_DUP's, make sure that 3592 they will be substituted if the operands they match are substituted. 3593 Also do now any substitutions we already did on the operands. 3594 3595 Don't do this if we aren't making replacements because we might be 3596 propagating things allocated by frame pointer elimination into places 3597 it doesn't expect. */ 3598 3599 if (insn_code_number >= 0 && replace) 3600 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) 3601 { 3602 int opno = recog_dup_num[i]; 3603 *recog_dup_loc[i] = *recog_operand_loc[opno]; 3604 if (operand_reloadnum[opno] >= 0) 3605 push_replacement (recog_dup_loc[i], operand_reloadnum[opno], 3606 insn_operand_mode[insn_code_number][opno]); 3607 } 3608 3609#if 0 3610 /* This loses because reloading of prior insns can invalidate the equivalence 3611 (or at least find_equiv_reg isn't smart enough to find it any more), 3612 causing this insn to need more reload regs than it needed before. 3613 It may be too late to make the reload regs available. 3614 Now this optimization is done safely in choose_reload_regs. */ 3615 3616 /* For each reload of a reg into some other class of reg, 3617 search for an existing equivalent reg (same value now) in the right class. 3618 We can use it as long as we don't need to change its contents. */ 3619 for (i = 0; i < n_reloads; i++) 3620 if (reload_reg_rtx[i] == 0 3621 && reload_in[i] != 0 3622 && GET_CODE (reload_in[i]) == REG 3623 && reload_out[i] == 0) 3624 { 3625 reload_reg_rtx[i] 3626 = find_equiv_reg (reload_in[i], insn, reload_reg_class[i], -1, 3627 static_reload_reg_p, 0, reload_inmode[i]); 3628 /* Prevent generation of insn to load the value 3629 because the one we found already has the value. */ 3630 if (reload_reg_rtx[i]) 3631 reload_in[i] = reload_reg_rtx[i]; 3632 } 3633#endif 3634 3635 /* Perhaps an output reload can be combined with another 3636 to reduce needs by one. */ 3637 if (!goal_earlyclobber) 3638 combine_reloads (); 3639 3640 /* If we have a pair of reloads for parts of an address, they are reloading 3641 the same object, the operands themselves were not reloaded, and they 3642 are for two operands that are supposed to match, merge the reloads and 3643 change the type of the surviving reload to RELOAD_FOR_OPERAND_ADDRESS. */ 3644 3645 for (i = 0; i < n_reloads; i++) 3646 { 3647 int k; 3648 3649 for (j = i + 1; j < n_reloads; j++) 3650 if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS 3651 || reload_when_needed[i] == RELOAD_FOR_OUTPUT_ADDRESS) 3652 && (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS 3653 || reload_when_needed[j] == RELOAD_FOR_OUTPUT_ADDRESS) 3654 && rtx_equal_p (reload_in[i], reload_in[j]) 3655 && (operand_reloadnum[reload_opnum[i]] < 0 3656 || reload_optional[operand_reloadnum[reload_opnum[i]]]) 3657 && (operand_reloadnum[reload_opnum[j]] < 0 3658 || reload_optional[operand_reloadnum[reload_opnum[j]]]) 3659 && (goal_alternative_matches[reload_opnum[i]] == reload_opnum[j] 3660 || (goal_alternative_matches[reload_opnum[j]] 3661 == reload_opnum[i]))) 3662 { 3663 for (k = 0; k < n_replacements; k++) 3664 if (replacements[k].what == j) 3665 replacements[k].what = i; 3666 3667 reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS; 3668 reload_in[j] = 0; 3669 } 3670 } 3671 3672 /* Scan all the reloads and update their type. 3673 If a reload is for the address of an operand and we didn't reload 3674 that operand, change the type. Similarly, change the operand number 3675 of a reload when two operands match. If a reload is optional, treat it 3676 as though the operand isn't reloaded. 3677 3678 ??? This latter case is somewhat odd because if we do the optional 3679 reload, it means the object is hanging around. Thus we need only 3680 do the address reload if the optional reload was NOT done. 3681 3682 Change secondary reloads to be the address type of their operand, not 3683 the normal type. 3684 3685 If an operand's reload is now RELOAD_OTHER, change any 3686 RELOAD_FOR_INPUT_ADDRESS reloads of that operand to 3687 RELOAD_FOR_OTHER_ADDRESS. */ 3688 3689 for (i = 0; i < n_reloads; i++) 3690 { 3691 if (reload_secondary_p[i] 3692 && reload_when_needed[i] == operand_type[reload_opnum[i]]) 3693 reload_when_needed[i] = address_type[reload_opnum[i]]; 3694 3695 if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS 3696 || reload_when_needed[i] == RELOAD_FOR_OUTPUT_ADDRESS) 3697 && (operand_reloadnum[reload_opnum[i]] < 0 3698 || reload_optional[operand_reloadnum[reload_opnum[i]]])) 3699 { 3700 /* If we have a secondary reload to go along with this reload, 3701 change its type to RELOAD_FOR_OPADDR_ADDR. */ 3702 3703 if (reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS 3704 && reload_secondary_in_reload[i] != -1) 3705 { 3706 int secondary_in_reload = reload_secondary_in_reload[i]; 3707 3708 reload_when_needed[secondary_in_reload] = 3709 RELOAD_FOR_OPADDR_ADDR; 3710 3711 /* If there's a tertiary reload we have to change it also. */ 3712 if (secondary_in_reload > 0 3713 && reload_secondary_in_reload[secondary_in_reload] != -1) 3714 reload_when_needed[reload_secondary_in_reload[secondary_in_reload]] 3715 = RELOAD_FOR_OPADDR_ADDR; 3716 } 3717 3718 if (reload_when_needed[i] == RELOAD_FOR_OUTPUT_ADDRESS 3719 && reload_secondary_out_reload[i] != -1) 3720 { 3721 int secondary_out_reload = reload_secondary_out_reload[i]; 3722 3723 reload_when_needed[secondary_out_reload] = 3724 RELOAD_FOR_OPADDR_ADDR; 3725 3726 /* If there's a tertiary reload we have to change it also. */ 3727 if (secondary_out_reload 3728 && reload_secondary_out_reload[secondary_out_reload] != -1) 3729 reload_when_needed[reload_secondary_out_reload[secondary_out_reload]] 3730 = RELOAD_FOR_OPADDR_ADDR; 3731 } 3732 reload_when_needed[i] = RELOAD_FOR_OPERAND_ADDRESS; 3733 } 3734 3735 if (reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS 3736 && operand_reloadnum[reload_opnum[i]] >= 0 3737 && (reload_when_needed[operand_reloadnum[reload_opnum[i]]] 3738 == RELOAD_OTHER)) 3739 reload_when_needed[i] = RELOAD_FOR_OTHER_ADDRESS; 3740 3741 if (goal_alternative_matches[reload_opnum[i]] >= 0) 3742 reload_opnum[i] = goal_alternative_matches[reload_opnum[i]]; 3743 } 3744 3745 /* See if we have any reloads that are now allowed to be merged 3746 because we've changed when the reload is needed to 3747 RELOAD_FOR_OPERAND_ADDRESS or RELOAD_FOR_OTHER_ADDRESS. Only 3748 check for the most common cases. */ 3749 3750 for (i = 0; i < n_reloads; i++) 3751 if (reload_in[i] != 0 && reload_out[i] == 0 3752 && (reload_when_needed[i] == RELOAD_FOR_OPERAND_ADDRESS 3753 || reload_when_needed[i] == RELOAD_FOR_OTHER_ADDRESS)) 3754 for (j = 0; j < n_reloads; j++) 3755 if (i != j && reload_in[j] != 0 && reload_out[j] == 0 3756 && reload_when_needed[j] == reload_when_needed[i] 3757 && MATCHES (reload_in[i], reload_in[j]) 3758 && reload_reg_class[i] == reload_reg_class[j] 3759 && !reload_nocombine[i] && !reload_nocombine[j] 3760 && reload_reg_rtx[i] == reload_reg_rtx[j]) 3761 { 3762 reload_opnum[i] = MIN (reload_opnum[i], reload_opnum[j]); 3763 transfer_replacements (i, j); 3764 reload_in[j] = 0; 3765 } 3766 3767#else /* no REGISTER_CONSTRAINTS */ 3768 int noperands; 3769 int insn_code_number; 3770 int goal_earlyclobber = 0; /* Always 0, to make combine_reloads happen. */ 3771 register int i; 3772 rtx body = PATTERN (insn); 3773 3774 n_reloads = 0; 3775 n_replacements = 0; 3776 n_earlyclobbers = 0; 3777 replace_reloads = replace; 3778 this_insn = insn; 3779 3780 /* Find what kind of insn this is. NOPERANDS gets number of operands. 3781 Store the operand values in RECOG_OPERAND and the locations 3782 of the words in the insn that point to them in RECOG_OPERAND_LOC. 3783 Return if the insn needs no reload processing. */ 3784 3785 switch (GET_CODE (body)) 3786 { 3787 case USE: 3788 case CLOBBER: 3789 case ASM_INPUT: 3790 case ADDR_VEC: 3791 case ADDR_DIFF_VEC: 3792 return; 3793 3794 case PARALLEL: 3795 case SET: 3796 noperands = asm_noperands (body); 3797 if (noperands >= 0) 3798 { 3799 /* This insn is an `asm' with operands. 3800 First, find out how many operands, and allocate space. */ 3801 3802 insn_code_number = -1; 3803 /* ??? This is a bug! ??? 3804 Give up and delete this insn if it has too many operands. */ 3805 if (noperands > MAX_RECOG_OPERANDS) 3806 abort (); 3807 3808 /* Now get the operand values out of the insn. */ 3809 3810 decode_asm_operands (body, recog_operand, recog_operand_loc, 3811 NULL_PTR, NULL_PTR); 3812 break; 3813 } 3814 3815 default: 3816 /* Ordinary insn: recognize it, allocate space for operands and 3817 constraints, and get them out via insn_extract. */ 3818 3819 insn_code_number = recog_memoized (insn); 3820 noperands = insn_n_operands[insn_code_number]; 3821 insn_extract (insn); 3822 } 3823 3824 if (noperands == 0) 3825 return; 3826 3827 for (i = 0; i < noperands; i++) 3828 { 3829 register RTX_CODE code = GET_CODE (recog_operand[i]); 3830 int is_set_dest = GET_CODE (body) == SET && (i == 0); 3831 3832 if (insn_code_number >= 0) 3833 if (insn_operand_address_p[insn_code_number][i]) 3834 find_reloads_address (VOIDmode, NULL_PTR, 3835 recog_operand[i], recog_operand_loc[i], 3836 i, RELOAD_FOR_INPUT, ind_levels); 3837 3838 /* In these cases, we can't tell if the operand is an input 3839 or an output, so be conservative. In practice it won't be 3840 problem. */ 3841 3842 if (code == MEM) 3843 find_reloads_address (GET_MODE (recog_operand[i]), 3844 recog_operand_loc[i], 3845 XEXP (recog_operand[i], 0), 3846 &XEXP (recog_operand[i], 0), 3847 i, RELOAD_OTHER, ind_levels); 3848 if (code == SUBREG) 3849 recog_operand[i] = *recog_operand_loc[i] 3850 = find_reloads_toplev (recog_operand[i], i, RELOAD_OTHER, 3851 ind_levels, is_set_dest); 3852 if (code == REG) 3853 { 3854 register int regno = REGNO (recog_operand[i]); 3855 if (reg_equiv_constant[regno] != 0 && !is_set_dest) 3856 recog_operand[i] = *recog_operand_loc[i] 3857 = reg_equiv_constant[regno]; 3858#if 0 /* This might screw code in reload1.c to delete prior output-reload 3859 that feeds this insn. */ 3860 if (reg_equiv_mem[regno] != 0) 3861 recog_operand[i] = *recog_operand_loc[i] 3862 = reg_equiv_mem[regno]; 3863#endif 3864 } 3865 } 3866 3867 /* Perhaps an output reload can be combined with another 3868 to reduce needs by one. */ 3869 if (!goal_earlyclobber) 3870 combine_reloads (); 3871#endif /* no REGISTER_CONSTRAINTS */ 3872} 3873 3874/* Return 1 if alternative number ALTNUM in constraint-string CONSTRAINT 3875 accepts a memory operand with constant address. */ 3876 3877static int 3878alternative_allows_memconst (constraint, altnum) 3879 char *constraint; 3880 int altnum; 3881{ 3882 register int c; 3883 /* Skip alternatives before the one requested. */ 3884 while (altnum > 0) 3885 { 3886 while (*constraint++ != ','); 3887 altnum--; 3888 } 3889 /* Scan the requested alternative for 'm' or 'o'. 3890 If one of them is present, this alternative accepts memory constants. */ 3891 while ((c = *constraint++) && c != ',' && c != '#') 3892 if (c == 'm' || c == 'o') 3893 return 1; 3894 return 0; 3895} 3896 3897/* Scan X for memory references and scan the addresses for reloading. 3898 Also checks for references to "constant" regs that we want to eliminate 3899 and replaces them with the values they stand for. 3900 We may alter X destructively if it contains a reference to such. 3901 If X is just a constant reg, we return the equivalent value 3902 instead of X. 3903 3904 IND_LEVELS says how many levels of indirect addressing this machine 3905 supports. 3906 3907 OPNUM and TYPE identify the purpose of the reload. 3908 3909 IS_SET_DEST is true if X is the destination of a SET, which is not 3910 appropriate to be replaced by a constant. */ 3911 3912static rtx 3913find_reloads_toplev (x, opnum, type, ind_levels, is_set_dest) 3914 rtx x; 3915 int opnum; 3916 enum reload_type type; 3917 int ind_levels; 3918 int is_set_dest; 3919{ 3920 register RTX_CODE code = GET_CODE (x); 3921 3922 register char *fmt = GET_RTX_FORMAT (code); 3923 register int i; 3924 3925 if (code == REG) 3926 { 3927 /* This code is duplicated for speed in find_reloads. */ 3928 register int regno = REGNO (x); 3929 if (reg_equiv_constant[regno] != 0 && !is_set_dest) 3930 x = reg_equiv_constant[regno]; 3931#if 0 3932/* This creates (subreg (mem...)) which would cause an unnecessary 3933 reload of the mem. */ 3934 else if (reg_equiv_mem[regno] != 0) 3935 x = reg_equiv_mem[regno]; 3936#endif 3937 else if (reg_equiv_address[regno] != 0) 3938 { 3939 /* If reg_equiv_address varies, it may be shared, so copy it. */ 3940 /* We must rerun eliminate_regs, in case the elimination 3941 offsets have changed. */ 3942 rtx addr = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], 0, 3943 NULL_RTX), 3944 0); 3945 3946 if (rtx_varies_p (addr)) 3947 addr = copy_rtx (addr); 3948 3949 x = gen_rtx (MEM, GET_MODE (x), addr); 3950 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); 3951 find_reloads_address (GET_MODE (x), NULL_PTR, 3952 XEXP (x, 0), 3953 &XEXP (x, 0), opnum, type, ind_levels); 3954 } 3955 return x; 3956 } 3957 if (code == MEM) 3958 { 3959 rtx tem = x; 3960 find_reloads_address (GET_MODE (x), &tem, XEXP (x, 0), &XEXP (x, 0), 3961 opnum, type, ind_levels); 3962 return tem; 3963 } 3964 3965 if (code == SUBREG && GET_CODE (SUBREG_REG (x)) == REG) 3966 { 3967 /* Check for SUBREG containing a REG that's equivalent to a constant. 3968 If the constant has a known value, truncate it right now. 3969 Similarly if we are extracting a single-word of a multi-word 3970 constant. If the constant is symbolic, allow it to be substituted 3971 normally. push_reload will strip the subreg later. If the 3972 constant is VOIDmode, abort because we will lose the mode of 3973 the register (this should never happen because one of the cases 3974 above should handle it). */ 3975 3976 register int regno = REGNO (SUBREG_REG (x)); 3977 rtx tem; 3978 3979 if (subreg_lowpart_p (x) 3980 && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 3981 && reg_equiv_constant[regno] != 0 3982 && (tem = gen_lowpart_common (GET_MODE (x), 3983 reg_equiv_constant[regno])) != 0) 3984 return tem; 3985 3986 if (GET_MODE_BITSIZE (GET_MODE (x)) == BITS_PER_WORD 3987 && regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 3988 && reg_equiv_constant[regno] != 0 3989 && (tem = operand_subword (reg_equiv_constant[regno], 3990 SUBREG_WORD (x), 0, 3991 GET_MODE (SUBREG_REG (x)))) != 0) 3992 return tem; 3993 3994 if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] < 0 3995 && reg_equiv_constant[regno] != 0 3996 && GET_MODE (reg_equiv_constant[regno]) == VOIDmode) 3997 abort (); 3998 3999 /* If the subreg contains a reg that will be converted to a mem, 4000 convert the subreg to a narrower memref now. 4001 Otherwise, we would get (subreg (mem ...) ...), 4002 which would force reload of the mem. 4003 4004 We also need to do this if there is an equivalent MEM that is 4005 not offsettable. In that case, alter_subreg would produce an 4006 invalid address on big-endian machines. 4007 4008 For machines that extend byte loads, we must not reload using 4009 a wider mode if we have a paradoxical SUBREG. find_reloads will 4010 force a reload in that case. So we should not do anything here. */ 4011 4012 else if (regno >= FIRST_PSEUDO_REGISTER 4013#ifdef LOAD_EXTEND_OP 4014 && (GET_MODE_SIZE (GET_MODE (x)) 4015 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 4016#endif 4017 && (reg_equiv_address[regno] != 0 4018 || (reg_equiv_mem[regno] != 0 4019 && (! strict_memory_address_p (GET_MODE (x), 4020 XEXP (reg_equiv_mem[regno], 0)) 4021 || ! offsettable_memref_p (reg_equiv_mem[regno]))))) 4022 { 4023 int offset = SUBREG_WORD (x) * UNITS_PER_WORD; 4024 /* We must rerun eliminate_regs, in case the elimination 4025 offsets have changed. */ 4026 rtx addr = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], 0, 4027 NULL_RTX), 4028 0); 4029 if (BYTES_BIG_ENDIAN) 4030 { 4031 int size; 4032 size = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))); 4033 offset += MIN (size, UNITS_PER_WORD); 4034 size = GET_MODE_SIZE (GET_MODE (x)); 4035 offset -= MIN (size, UNITS_PER_WORD); 4036 } 4037 addr = plus_constant (addr, offset); 4038 x = gen_rtx (MEM, GET_MODE (x), addr); 4039 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); 4040 find_reloads_address (GET_MODE (x), NULL_PTR, 4041 XEXP (x, 0), 4042 &XEXP (x, 0), opnum, type, ind_levels); 4043 } 4044 4045 } 4046 4047 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 4048 { 4049 if (fmt[i] == 'e') 4050 XEXP (x, i) = find_reloads_toplev (XEXP (x, i), opnum, type, 4051 ind_levels, is_set_dest); 4052 } 4053 return x; 4054} 4055 4056/* Return a mem ref for the memory equivalent of reg REGNO. 4057 This mem ref is not shared with anything. */ 4058 4059static rtx 4060make_memloc (ad, regno) 4061 rtx ad; 4062 int regno; 4063{ 4064 register int i; 4065 /* We must rerun eliminate_regs, in case the elimination 4066 offsets have changed. */ 4067 rtx tem = XEXP (eliminate_regs (reg_equiv_memory_loc[regno], 0, NULL_RTX), 4068 0); 4069 4070#if 0 /* We cannot safely reuse a memloc made here; 4071 if the pseudo appears twice, and its mem needs a reload, 4072 it gets two separate reloads assigned, but it only 4073 gets substituted with the second of them; 4074 then it can get used before that reload reg gets loaded up. */ 4075 for (i = 0; i < n_memlocs; i++) 4076 if (rtx_equal_p (tem, XEXP (memlocs[i], 0))) 4077 return memlocs[i]; 4078#endif 4079 4080 /* If TEM might contain a pseudo, we must copy it to avoid 4081 modifying it when we do the substitution for the reload. */ 4082 if (rtx_varies_p (tem)) 4083 tem = copy_rtx (tem); 4084 4085 tem = gen_rtx (MEM, GET_MODE (ad), tem); 4086 RTX_UNCHANGING_P (tem) = RTX_UNCHANGING_P (regno_reg_rtx[regno]); 4087 memlocs[n_memlocs++] = tem; 4088 return tem; 4089} 4090 4091/* Record all reloads needed for handling memory address AD 4092 which appears in *LOC in a memory reference to mode MODE 4093 which itself is found in location *MEMREFLOC. 4094 Note that we take shortcuts assuming that no multi-reg machine mode 4095 occurs as part of an address. 4096 4097 OPNUM and TYPE specify the purpose of this reload. 4098 4099 IND_LEVELS says how many levels of indirect addressing this machine 4100 supports. 4101 4102 Value is nonzero if this address is reloaded or replaced as a whole. 4103 This is interesting to the caller if the address is an autoincrement. 4104 4105 Note that there is no verification that the address will be valid after 4106 this routine does its work. Instead, we rely on the fact that the address 4107 was valid when reload started. So we need only undo things that reload 4108 could have broken. These are wrong register types, pseudos not allocated 4109 to a hard register, and frame pointer elimination. */ 4110 4111static int 4112find_reloads_address (mode, memrefloc, ad, loc, opnum, type, ind_levels) 4113 enum machine_mode mode; 4114 rtx *memrefloc; 4115 rtx ad; 4116 rtx *loc; 4117 int opnum; 4118 enum reload_type type; 4119 int ind_levels; 4120{ 4121 register int regno; 4122 rtx tem; 4123 4124 /* If the address is a register, see if it is a legitimate address and 4125 reload if not. We first handle the cases where we need not reload 4126 or where we must reload in a non-standard way. */ 4127 4128 if (GET_CODE (ad) == REG) 4129 { 4130 regno = REGNO (ad); 4131 4132 if (reg_equiv_constant[regno] != 0 4133 && strict_memory_address_p (mode, reg_equiv_constant[regno])) 4134 { 4135 *loc = ad = reg_equiv_constant[regno]; 4136 return 1; 4137 } 4138 4139 else if (reg_equiv_address[regno] != 0) 4140 { 4141 tem = make_memloc (ad, regno); 4142 find_reloads_address (GET_MODE (tem), NULL_PTR, XEXP (tem, 0), 4143 &XEXP (tem, 0), opnum, type, ind_levels); 4144 push_reload (tem, NULL_RTX, loc, NULL_PTR, BASE_REG_CLASS, 4145 GET_MODE (ad), VOIDmode, 0, 0, 4146 opnum, type); 4147 return 1; 4148 } 4149 4150 /* We can avoid a reload if the register's equivalent memory expression 4151 is valid as an indirect memory address. 4152 But not all addresses are valid in a mem used as an indirect address: 4153 only reg or reg+constant. */ 4154 4155 else if (reg_equiv_mem[regno] != 0 && ind_levels > 0 4156 && strict_memory_address_p (mode, reg_equiv_mem[regno]) 4157 && (GET_CODE (XEXP (reg_equiv_mem[regno], 0)) == REG 4158 || (GET_CODE (XEXP (reg_equiv_mem[regno], 0)) == PLUS 4159 && GET_CODE (XEXP (XEXP (reg_equiv_mem[regno], 0), 0)) == REG 4160 && CONSTANT_P (XEXP (XEXP (reg_equiv_mem[regno], 0), 1))))) 4161 return 0; 4162 4163 /* The only remaining case where we can avoid a reload is if this is a 4164 hard register that is valid as a base register and which is not the 4165 subject of a CLOBBER in this insn. */ 4166 4167 else if (regno < FIRST_PSEUDO_REGISTER && REGNO_OK_FOR_BASE_P (regno) 4168 && ! regno_clobbered_p (regno, this_insn)) 4169 return 0; 4170 4171 /* If we do not have one of the cases above, we must do the reload. */ 4172 push_reload (ad, NULL_RTX, loc, NULL_PTR, BASE_REG_CLASS, 4173 GET_MODE (ad), VOIDmode, 0, 0, opnum, type); 4174 return 1; 4175 } 4176 4177 if (strict_memory_address_p (mode, ad)) 4178 { 4179 /* The address appears valid, so reloads are not needed. 4180 But the address may contain an eliminable register. 4181 This can happen because a machine with indirect addressing 4182 may consider a pseudo register by itself a valid address even when 4183 it has failed to get a hard reg. 4184 So do a tree-walk to find and eliminate all such regs. */ 4185 4186 /* But first quickly dispose of a common case. */ 4187 if (GET_CODE (ad) == PLUS 4188 && GET_CODE (XEXP (ad, 1)) == CONST_INT 4189 && GET_CODE (XEXP (ad, 0)) == REG 4190 && reg_equiv_constant[REGNO (XEXP (ad, 0))] == 0) 4191 return 0; 4192 4193 subst_reg_equivs_changed = 0; 4194 *loc = subst_reg_equivs (ad); 4195 4196 if (! subst_reg_equivs_changed) 4197 return 0; 4198 4199 /* Check result for validity after substitution. */ 4200 if (strict_memory_address_p (mode, ad)) 4201 return 0; 4202 } 4203 4204 /* The address is not valid. We have to figure out why. One possibility 4205 is that it is itself a MEM. This can happen when the frame pointer is 4206 being eliminated, a pseudo is not allocated to a hard register, and the 4207 offset between the frame and stack pointers is not its initial value. 4208 In that case the pseudo will have been replaced by a MEM referring to 4209 the stack pointer. */ 4210 if (GET_CODE (ad) == MEM) 4211 { 4212 /* First ensure that the address in this MEM is valid. Then, unless 4213 indirect addresses are valid, reload the MEM into a register. */ 4214 tem = ad; 4215 find_reloads_address (GET_MODE (ad), &tem, XEXP (ad, 0), &XEXP (ad, 0), 4216 opnum, type, ind_levels == 0 ? 0 : ind_levels - 1); 4217 4218 /* If tem was changed, then we must create a new memory reference to 4219 hold it and store it back into memrefloc. */ 4220 if (tem != ad && memrefloc) 4221 { 4222 *memrefloc = copy_rtx (*memrefloc); 4223 copy_replacements (tem, XEXP (*memrefloc, 0)); 4224 loc = &XEXP (*memrefloc, 0); 4225 } 4226 4227 /* Check similar cases as for indirect addresses as above except 4228 that we can allow pseudos and a MEM since they should have been 4229 taken care of above. */ 4230 4231 if (ind_levels == 0 4232 || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok) 4233 || GET_CODE (XEXP (tem, 0)) == MEM 4234 || ! (GET_CODE (XEXP (tem, 0)) == REG 4235 || (GET_CODE (XEXP (tem, 0)) == PLUS 4236 && GET_CODE (XEXP (XEXP (tem, 0), 0)) == REG 4237 && GET_CODE (XEXP (XEXP (tem, 0), 1)) == CONST_INT))) 4238 { 4239 /* Must use TEM here, not AD, since it is the one that will 4240 have any subexpressions reloaded, if needed. */ 4241 push_reload (tem, NULL_RTX, loc, NULL_PTR, 4242 BASE_REG_CLASS, GET_MODE (tem), VOIDmode, 0, 4243 0, opnum, type); 4244 return 1; 4245 } 4246 else 4247 return 0; 4248 } 4249 4250 /* If we have address of a stack slot but it's not valid because the 4251 displacement is too large, compute the sum in a register. 4252 Handle all base registers here, not just fp/ap/sp, because on some 4253 targets (namely SH) we can also get too large displacements from 4254 big-endian corrections. */ 4255 else if (GET_CODE (ad) == PLUS 4256 && GET_CODE (XEXP (ad, 0)) == REG 4257 && REGNO (XEXP (ad, 0)) < FIRST_PSEUDO_REGISTER 4258 && REG_OK_FOR_BASE_P (XEXP (ad, 0)) 4259 && GET_CODE (XEXP (ad, 1)) == CONST_INT) 4260 { 4261 /* Unshare the MEM rtx so we can safely alter it. */ 4262 if (memrefloc) 4263 { 4264 *memrefloc = copy_rtx (*memrefloc); 4265 loc = &XEXP (*memrefloc, 0); 4266 } 4267 if (double_reg_address_ok) 4268 { 4269 /* Unshare the sum as well. */ 4270 *loc = ad = copy_rtx (ad); 4271 /* Reload the displacement into an index reg. 4272 We assume the frame pointer or arg pointer is a base reg. */ 4273 find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), 4274 INDEX_REG_CLASS, GET_MODE (ad), opnum, 4275 type, ind_levels); 4276 } 4277 else 4278 { 4279 /* If the sum of two regs is not necessarily valid, 4280 reload the sum into a base reg. 4281 That will at least work. */ 4282 find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode, 4283 opnum, type, ind_levels); 4284 } 4285 return 1; 4286 } 4287 4288 /* If we have an indexed stack slot, there are three possible reasons why 4289 it might be invalid: The index might need to be reloaded, the address 4290 might have been made by frame pointer elimination and hence have a 4291 constant out of range, or both reasons might apply. 4292 4293 We can easily check for an index needing reload, but even if that is the 4294 case, we might also have an invalid constant. To avoid making the 4295 conservative assumption and requiring two reloads, we see if this address 4296 is valid when not interpreted strictly. If it is, the only problem is 4297 that the index needs a reload and find_reloads_address_1 will take care 4298 of it. 4299 4300 There is still a case when we might generate an extra reload, 4301 however. In certain cases eliminate_regs will return a MEM for a REG 4302 (see the code there for details). In those cases, memory_address_p 4303 applied to our address will return 0 so we will think that our offset 4304 must be too large. But it might indeed be valid and the only problem 4305 is that a MEM is present where a REG should be. This case should be 4306 very rare and there doesn't seem to be any way to avoid it. 4307 4308 If we decide to do something here, it must be that 4309 `double_reg_address_ok' is true and that this address rtl was made by 4310 eliminate_regs. We generate a reload of the fp/sp/ap + constant and 4311 rework the sum so that the reload register will be added to the index. 4312 This is safe because we know the address isn't shared. 4313 4314 We check for fp/ap/sp as both the first and second operand of the 4315 innermost PLUS. */ 4316 4317 else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT 4318 && GET_CODE (XEXP (ad, 0)) == PLUS 4319 && (XEXP (XEXP (ad, 0), 0) == frame_pointer_rtx 4320#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM 4321 || XEXP (XEXP (ad, 0), 0) == hard_frame_pointer_rtx 4322#endif 4323#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 4324 || XEXP (XEXP (ad, 0), 0) == arg_pointer_rtx 4325#endif 4326 || XEXP (XEXP (ad, 0), 0) == stack_pointer_rtx) 4327 && ! memory_address_p (mode, ad)) 4328 { 4329 *loc = ad = gen_rtx (PLUS, GET_MODE (ad), 4330 plus_constant (XEXP (XEXP (ad, 0), 0), 4331 INTVAL (XEXP (ad, 1))), 4332 XEXP (XEXP (ad, 0), 1)); 4333 find_reloads_address_part (XEXP (ad, 0), &XEXP (ad, 0), BASE_REG_CLASS, 4334 GET_MODE (ad), opnum, type, ind_levels); 4335 find_reloads_address_1 (XEXP (ad, 1), 1, &XEXP (ad, 1), opnum, type, 0); 4336 4337 return 1; 4338 } 4339 4340 else if (GET_CODE (ad) == PLUS && GET_CODE (XEXP (ad, 1)) == CONST_INT 4341 && GET_CODE (XEXP (ad, 0)) == PLUS 4342 && (XEXP (XEXP (ad, 0), 1) == frame_pointer_rtx 4343#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 4344 || XEXP (XEXP (ad, 0), 1) == hard_frame_pointer_rtx 4345#endif 4346#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 4347 || XEXP (XEXP (ad, 0), 1) == arg_pointer_rtx 4348#endif 4349 || XEXP (XEXP (ad, 0), 1) == stack_pointer_rtx) 4350 && ! memory_address_p (mode, ad)) 4351 { 4352 *loc = ad = gen_rtx (PLUS, GET_MODE (ad), 4353 XEXP (XEXP (ad, 0), 0), 4354 plus_constant (XEXP (XEXP (ad, 0), 1), 4355 INTVAL (XEXP (ad, 1)))); 4356 find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1), BASE_REG_CLASS, 4357 GET_MODE (ad), opnum, type, ind_levels); 4358 find_reloads_address_1 (XEXP (ad, 0), 1, &XEXP (ad, 0), opnum, type, 0); 4359 4360 return 1; 4361 } 4362 4363 /* See if address becomes valid when an eliminable register 4364 in a sum is replaced. */ 4365 4366 tem = ad; 4367 if (GET_CODE (ad) == PLUS) 4368 tem = subst_indexed_address (ad); 4369 if (tem != ad && strict_memory_address_p (mode, tem)) 4370 { 4371 /* Ok, we win that way. Replace any additional eliminable 4372 registers. */ 4373 4374 subst_reg_equivs_changed = 0; 4375 tem = subst_reg_equivs (tem); 4376 4377 /* Make sure that didn't make the address invalid again. */ 4378 4379 if (! subst_reg_equivs_changed || strict_memory_address_p (mode, tem)) 4380 { 4381 *loc = tem; 4382 return 0; 4383 } 4384 } 4385 4386 /* If constants aren't valid addresses, reload the constant address 4387 into a register. */ 4388 if (CONSTANT_P (ad) && ! strict_memory_address_p (mode, ad)) 4389 { 4390 /* If AD is in address in the constant pool, the MEM rtx may be shared. 4391 Unshare it so we can safely alter it. */ 4392 if (memrefloc && GET_CODE (ad) == SYMBOL_REF 4393 && CONSTANT_POOL_ADDRESS_P (ad)) 4394 { 4395 *memrefloc = copy_rtx (*memrefloc); 4396 loc = &XEXP (*memrefloc, 0); 4397 } 4398 4399 find_reloads_address_part (ad, loc, BASE_REG_CLASS, Pmode, opnum, type, 4400 ind_levels); 4401 return 1; 4402 } 4403 4404 return find_reloads_address_1 (ad, 0, loc, opnum, type, ind_levels); 4405} 4406 4407/* Find all pseudo regs appearing in AD 4408 that are eliminable in favor of equivalent values 4409 and do not have hard regs; replace them by their equivalents. */ 4410 4411static rtx 4412subst_reg_equivs (ad) 4413 rtx ad; 4414{ 4415 register RTX_CODE code = GET_CODE (ad); 4416 register int i; 4417 register char *fmt; 4418 4419 switch (code) 4420 { 4421 case HIGH: 4422 case CONST_INT: 4423 case CONST: 4424 case CONST_DOUBLE: 4425 case SYMBOL_REF: 4426 case LABEL_REF: 4427 case PC: 4428 case CC0: 4429 return ad; 4430 4431 case REG: 4432 { 4433 register int regno = REGNO (ad); 4434 4435 if (reg_equiv_constant[regno] != 0) 4436 { 4437 subst_reg_equivs_changed = 1; 4438 return reg_equiv_constant[regno]; 4439 } 4440 } 4441 return ad; 4442 4443 case PLUS: 4444 /* Quickly dispose of a common case. */ 4445 if (XEXP (ad, 0) == frame_pointer_rtx 4446 && GET_CODE (XEXP (ad, 1)) == CONST_INT) 4447 return ad; 4448 } 4449 4450 fmt = GET_RTX_FORMAT (code); 4451 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 4452 if (fmt[i] == 'e') 4453 XEXP (ad, i) = subst_reg_equivs (XEXP (ad, i)); 4454 return ad; 4455} 4456 4457/* Compute the sum of X and Y, making canonicalizations assumed in an 4458 address, namely: sum constant integers, surround the sum of two 4459 constants with a CONST, put the constant as the second operand, and 4460 group the constant on the outermost sum. 4461 4462 This routine assumes both inputs are already in canonical form. */ 4463 4464rtx 4465form_sum (x, y) 4466 rtx x, y; 4467{ 4468 rtx tem; 4469 enum machine_mode mode = GET_MODE (x); 4470 4471 if (mode == VOIDmode) 4472 mode = GET_MODE (y); 4473 4474 if (mode == VOIDmode) 4475 mode = Pmode; 4476 4477 if (GET_CODE (x) == CONST_INT) 4478 return plus_constant (y, INTVAL (x)); 4479 else if (GET_CODE (y) == CONST_INT) 4480 return plus_constant (x, INTVAL (y)); 4481 else if (CONSTANT_P (x)) 4482 tem = x, x = y, y = tem; 4483 4484 if (GET_CODE (x) == PLUS && CONSTANT_P (XEXP (x, 1))) 4485 return form_sum (XEXP (x, 0), form_sum (XEXP (x, 1), y)); 4486 4487 /* Note that if the operands of Y are specified in the opposite 4488 order in the recursive calls below, infinite recursion will occur. */ 4489 if (GET_CODE (y) == PLUS && CONSTANT_P (XEXP (y, 1))) 4490 return form_sum (form_sum (x, XEXP (y, 0)), XEXP (y, 1)); 4491 4492 /* If both constant, encapsulate sum. Otherwise, just form sum. A 4493 constant will have been placed second. */ 4494 if (CONSTANT_P (x) && CONSTANT_P (y)) 4495 { 4496 if (GET_CODE (x) == CONST) 4497 x = XEXP (x, 0); 4498 if (GET_CODE (y) == CONST) 4499 y = XEXP (y, 0); 4500 4501 return gen_rtx (CONST, VOIDmode, gen_rtx (PLUS, mode, x, y)); 4502 } 4503 4504 return gen_rtx (PLUS, mode, x, y); 4505} 4506 4507/* If ADDR is a sum containing a pseudo register that should be 4508 replaced with a constant (from reg_equiv_constant), 4509 return the result of doing so, and also apply the associative 4510 law so that the result is more likely to be a valid address. 4511 (But it is not guaranteed to be one.) 4512 4513 Note that at most one register is replaced, even if more are 4514 replaceable. Also, we try to put the result into a canonical form 4515 so it is more likely to be a valid address. 4516 4517 In all other cases, return ADDR. */ 4518 4519static rtx 4520subst_indexed_address (addr) 4521 rtx addr; 4522{ 4523 rtx op0 = 0, op1 = 0, op2 = 0; 4524 rtx tem; 4525 int regno; 4526 4527 if (GET_CODE (addr) == PLUS) 4528 { 4529 /* Try to find a register to replace. */ 4530 op0 = XEXP (addr, 0), op1 = XEXP (addr, 1), op2 = 0; 4531 if (GET_CODE (op0) == REG 4532 && (regno = REGNO (op0)) >= FIRST_PSEUDO_REGISTER 4533 && reg_renumber[regno] < 0 4534 && reg_equiv_constant[regno] != 0) 4535 op0 = reg_equiv_constant[regno]; 4536 else if (GET_CODE (op1) == REG 4537 && (regno = REGNO (op1)) >= FIRST_PSEUDO_REGISTER 4538 && reg_renumber[regno] < 0 4539 && reg_equiv_constant[regno] != 0) 4540 op1 = reg_equiv_constant[regno]; 4541 else if (GET_CODE (op0) == PLUS 4542 && (tem = subst_indexed_address (op0)) != op0) 4543 op0 = tem; 4544 else if (GET_CODE (op1) == PLUS 4545 && (tem = subst_indexed_address (op1)) != op1) 4546 op1 = tem; 4547 else 4548 return addr; 4549 4550 /* Pick out up to three things to add. */ 4551 if (GET_CODE (op1) == PLUS) 4552 op2 = XEXP (op1, 1), op1 = XEXP (op1, 0); 4553 else if (GET_CODE (op0) == PLUS) 4554 op2 = op1, op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); 4555 4556 /* Compute the sum. */ 4557 if (op2 != 0) 4558 op1 = form_sum (op1, op2); 4559 if (op1 != 0) 4560 op0 = form_sum (op0, op1); 4561 4562 return op0; 4563 } 4564 return addr; 4565} 4566 4567/* Record the pseudo registers we must reload into hard registers 4568 in a subexpression of a would-be memory address, X. 4569 (This function is not called if the address we find is strictly valid.) 4570 CONTEXT = 1 means we are considering regs as index regs, 4571 = 0 means we are considering them as base regs. 4572 4573 OPNUM and TYPE specify the purpose of any reloads made. 4574 4575 IND_LEVELS says how many levels of indirect addressing are 4576 supported at this point in the address. 4577 4578 We return nonzero if X, as a whole, is reloaded or replaced. */ 4579 4580/* Note that we take shortcuts assuming that no multi-reg machine mode 4581 occurs as part of an address. 4582 Also, this is not fully machine-customizable; it works for machines 4583 such as vaxes and 68000's and 32000's, but other possible machines 4584 could have addressing modes that this does not handle right. */ 4585 4586static int 4587find_reloads_address_1 (x, context, loc, opnum, type, ind_levels) 4588 rtx x; 4589 int context; 4590 rtx *loc; 4591 int opnum; 4592 enum reload_type type; 4593 int ind_levels; 4594{ 4595 register RTX_CODE code = GET_CODE (x); 4596 4597 switch (code) 4598 { 4599 case PLUS: 4600 { 4601 register rtx orig_op0 = XEXP (x, 0); 4602 register rtx orig_op1 = XEXP (x, 1); 4603 register RTX_CODE code0 = GET_CODE (orig_op0); 4604 register RTX_CODE code1 = GET_CODE (orig_op1); 4605 register rtx op0 = orig_op0; 4606 register rtx op1 = orig_op1; 4607 4608 if (GET_CODE (op0) == SUBREG) 4609 { 4610 op0 = SUBREG_REG (op0); 4611 code0 = GET_CODE (op0); 4612 if (code0 == REG && REGNO (op0) < FIRST_PSEUDO_REGISTER) 4613 op0 = gen_rtx (REG, word_mode, 4614 REGNO (op0) + SUBREG_WORD (orig_op0)); 4615 } 4616 4617 if (GET_CODE (op1) == SUBREG) 4618 { 4619 op1 = SUBREG_REG (op1); 4620 code1 = GET_CODE (op1); 4621 if (code1 == REG && REGNO (op1) < FIRST_PSEUDO_REGISTER) 4622 op1 = gen_rtx (REG, GET_MODE (op1), 4623 REGNO (op1) + SUBREG_WORD (orig_op1)); 4624 } 4625 4626 if (code0 == MULT || code0 == SIGN_EXTEND || code0 == TRUNCATE 4627 || code0 == ZERO_EXTEND || code1 == MEM) 4628 { 4629 find_reloads_address_1 (orig_op0, 1, &XEXP (x, 0), opnum, type, 4630 ind_levels); 4631 find_reloads_address_1 (orig_op1, 0, &XEXP (x, 1), opnum, type, 4632 ind_levels); 4633 } 4634 4635 else if (code1 == MULT || code1 == SIGN_EXTEND || code1 == TRUNCATE 4636 || code1 == ZERO_EXTEND || code0 == MEM) 4637 { 4638 find_reloads_address_1 (orig_op0, 0, &XEXP (x, 0), opnum, type, 4639 ind_levels); 4640 find_reloads_address_1 (orig_op1, 1, &XEXP (x, 1), opnum, type, 4641 ind_levels); 4642 } 4643 4644 else if (code0 == CONST_INT || code0 == CONST 4645 || code0 == SYMBOL_REF || code0 == LABEL_REF) 4646 find_reloads_address_1 (orig_op1, 0, &XEXP (x, 1), opnum, type, 4647 ind_levels); 4648 4649 else if (code1 == CONST_INT || code1 == CONST 4650 || code1 == SYMBOL_REF || code1 == LABEL_REF) 4651 find_reloads_address_1 (orig_op0, 0, &XEXP (x, 0), opnum, type, 4652 ind_levels); 4653 4654 else if (code0 == REG && code1 == REG) 4655 { 4656 if (REG_OK_FOR_INDEX_P (op0) 4657 && REG_OK_FOR_BASE_P (op1)) 4658 return 0; 4659 else if (REG_OK_FOR_INDEX_P (op1) 4660 && REG_OK_FOR_BASE_P (op0)) 4661 return 0; 4662 else if (REG_OK_FOR_BASE_P (op1)) 4663 find_reloads_address_1 (orig_op0, 1, &XEXP (x, 0), opnum, type, 4664 ind_levels); 4665 else if (REG_OK_FOR_BASE_P (op0)) 4666 find_reloads_address_1 (orig_op1, 1, &XEXP (x, 1), opnum, type, 4667 ind_levels); 4668 else if (REG_OK_FOR_INDEX_P (op1)) 4669 find_reloads_address_1 (orig_op0, 0, &XEXP (x, 0), opnum, type, 4670 ind_levels); 4671 else if (REG_OK_FOR_INDEX_P (op0)) 4672 find_reloads_address_1 (orig_op1, 0, &XEXP (x, 1), opnum, type, 4673 ind_levels); 4674 else 4675 { 4676 find_reloads_address_1 (orig_op0, 1, &XEXP (x, 0), opnum, type, 4677 ind_levels); 4678 find_reloads_address_1 (orig_op1, 0, &XEXP (x, 1), opnum, type, 4679 ind_levels); 4680 } 4681 } 4682 4683 else if (code0 == REG) 4684 { 4685 find_reloads_address_1 (orig_op0, 1, &XEXP (x, 0), opnum, type, 4686 ind_levels); 4687 find_reloads_address_1 (orig_op1, 0, &XEXP (x, 1), opnum, type, 4688 ind_levels); 4689 } 4690 4691 else if (code1 == REG) 4692 { 4693 find_reloads_address_1 (orig_op1, 1, &XEXP (x, 1), opnum, type, 4694 ind_levels); 4695 find_reloads_address_1 (orig_op0, 0, &XEXP (x, 0), opnum, type, 4696 ind_levels); 4697 } 4698 } 4699 4700 return 0; 4701 4702 case POST_INC: 4703 case POST_DEC: 4704 case PRE_INC: 4705 case PRE_DEC: 4706 if (GET_CODE (XEXP (x, 0)) == REG) 4707 { 4708 register int regno = REGNO (XEXP (x, 0)); 4709 int value = 0; 4710 rtx x_orig = x; 4711 4712 /* A register that is incremented cannot be constant! */ 4713 if (regno >= FIRST_PSEUDO_REGISTER 4714 && reg_equiv_constant[regno] != 0) 4715 abort (); 4716 4717 /* Handle a register that is equivalent to a memory location 4718 which cannot be addressed directly. */ 4719 if (reg_equiv_address[regno] != 0) 4720 { 4721 rtx tem = make_memloc (XEXP (x, 0), regno); 4722 /* First reload the memory location's address. */ 4723 find_reloads_address (GET_MODE (tem), 0, XEXP (tem, 0), 4724 &XEXP (tem, 0), opnum, type, ind_levels); 4725 /* Put this inside a new increment-expression. */ 4726 x = gen_rtx (GET_CODE (x), GET_MODE (x), tem); 4727 /* Proceed to reload that, as if it contained a register. */ 4728 } 4729 4730 /* If we have a hard register that is ok as an index, 4731 don't make a reload. If an autoincrement of a nice register 4732 isn't "valid", it must be that no autoincrement is "valid". 4733 If that is true and something made an autoincrement anyway, 4734 this must be a special context where one is allowed. 4735 (For example, a "push" instruction.) 4736 We can't improve this address, so leave it alone. */ 4737 4738 /* Otherwise, reload the autoincrement into a suitable hard reg 4739 and record how much to increment by. */ 4740 4741 if (reg_renumber[regno] >= 0) 4742 regno = reg_renumber[regno]; 4743 if ((regno >= FIRST_PSEUDO_REGISTER 4744 || !(context ? REGNO_OK_FOR_INDEX_P (regno) 4745 : REGNO_OK_FOR_BASE_P (regno)))) 4746 { 4747 register rtx link; 4748 4749 int reloadnum 4750 = push_reload (x, NULL_RTX, loc, NULL_PTR, 4751 context ? INDEX_REG_CLASS : BASE_REG_CLASS, 4752 GET_MODE (x), GET_MODE (x), VOIDmode, 0, 4753 opnum, type); 4754 reload_inc[reloadnum] 4755 = find_inc_amount (PATTERN (this_insn), XEXP (x_orig, 0)); 4756 4757 value = 1; 4758 4759#ifdef AUTO_INC_DEC 4760 /* Update the REG_INC notes. */ 4761 4762 for (link = REG_NOTES (this_insn); 4763 link; link = XEXP (link, 1)) 4764 if (REG_NOTE_KIND (link) == REG_INC 4765 && REGNO (XEXP (link, 0)) == REGNO (XEXP (x_orig, 0))) 4766 push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); 4767#endif 4768 } 4769 return value; 4770 } 4771 4772 else if (GET_CODE (XEXP (x, 0)) == MEM) 4773 { 4774 /* This is probably the result of a substitution, by eliminate_regs, 4775 of an equivalent address for a pseudo that was not allocated to a 4776 hard register. Verify that the specified address is valid and 4777 reload it into a register. */ 4778 rtx tem = XEXP (x, 0); 4779 register rtx link; 4780 int reloadnum; 4781 4782 /* Since we know we are going to reload this item, don't decrement 4783 for the indirection level. 4784 4785 Note that this is actually conservative: it would be slightly 4786 more efficient to use the value of SPILL_INDIRECT_LEVELS from 4787 reload1.c here. */ 4788 find_reloads_address (GET_MODE (x), &XEXP (x, 0), 4789 XEXP (XEXP (x, 0), 0), &XEXP (XEXP (x, 0), 0), 4790 opnum, type, ind_levels); 4791 4792 reloadnum = push_reload (x, NULL_RTX, loc, NULL_PTR, 4793 context ? INDEX_REG_CLASS : BASE_REG_CLASS, 4794 GET_MODE (x), VOIDmode, 0, 0, opnum, type); 4795 reload_inc[reloadnum] 4796 = find_inc_amount (PATTERN (this_insn), XEXP (x, 0)); 4797 4798 link = FIND_REG_INC_NOTE (this_insn, tem); 4799 if (link != 0) 4800 push_replacement (&XEXP (link, 0), reloadnum, VOIDmode); 4801 4802 return 1; 4803 } 4804 return 0; 4805 4806 case MEM: 4807 /* This is probably the result of a substitution, by eliminate_regs, of 4808 an equivalent address for a pseudo that was not allocated to a hard 4809 register. Verify that the specified address is valid and reload it 4810 into a register. 4811 4812 Since we know we are going to reload this item, don't decrement for 4813 the indirection level. 4814 4815 Note that this is actually conservative: it would be slightly more 4816 efficient to use the value of SPILL_INDIRECT_LEVELS from 4817 reload1.c here. */ 4818 4819 find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0), 4820 opnum, type, ind_levels); 4821 push_reload (*loc, NULL_RTX, loc, NULL_PTR, 4822 context ? INDEX_REG_CLASS : BASE_REG_CLASS, 4823 GET_MODE (x), VOIDmode, 0, 0, opnum, type); 4824 return 1; 4825 4826 case REG: 4827 { 4828 register int regno = REGNO (x); 4829 4830 if (reg_equiv_constant[regno] != 0) 4831 { 4832 find_reloads_address_part (reg_equiv_constant[regno], loc, 4833 (context ? INDEX_REG_CLASS 4834 : BASE_REG_CLASS), 4835 GET_MODE (x), opnum, type, ind_levels); 4836 return 1; 4837 } 4838 4839#if 0 /* This might screw code in reload1.c to delete prior output-reload 4840 that feeds this insn. */ 4841 if (reg_equiv_mem[regno] != 0) 4842 { 4843 push_reload (reg_equiv_mem[regno], NULL_RTX, loc, NULL_PTR, 4844 context ? INDEX_REG_CLASS : BASE_REG_CLASS, 4845 GET_MODE (x), VOIDmode, 0, 0, opnum, type); 4846 return 1; 4847 } 4848#endif 4849 4850 if (reg_equiv_address[regno] != 0) 4851 { 4852 x = make_memloc (x, regno); 4853 find_reloads_address (GET_MODE (x), 0, XEXP (x, 0), &XEXP (x, 0), 4854 opnum, type, ind_levels); 4855 } 4856 4857 if (reg_renumber[regno] >= 0) 4858 regno = reg_renumber[regno]; 4859 4860 if ((regno >= FIRST_PSEUDO_REGISTER 4861 || !(context ? REGNO_OK_FOR_INDEX_P (regno) 4862 : REGNO_OK_FOR_BASE_P (regno)))) 4863 { 4864 push_reload (x, NULL_RTX, loc, NULL_PTR, 4865 context ? INDEX_REG_CLASS : BASE_REG_CLASS, 4866 GET_MODE (x), VOIDmode, 0, 0, opnum, type); 4867 return 1; 4868 } 4869 4870 /* If a register appearing in an address is the subject of a CLOBBER 4871 in this insn, reload it into some other register to be safe. 4872 The CLOBBER is supposed to make the register unavailable 4873 from before this insn to after it. */ 4874 if (regno_clobbered_p (regno, this_insn)) 4875 { 4876 push_reload (x, NULL_RTX, loc, NULL_PTR, 4877 context ? INDEX_REG_CLASS : BASE_REG_CLASS, 4878 GET_MODE (x), VOIDmode, 0, 0, opnum, type); 4879 return 1; 4880 } 4881 } 4882 return 0; 4883 4884 case SUBREG: 4885 if (GET_CODE (SUBREG_REG (x)) == REG) 4886 { 4887 /* If this is a SUBREG of a hard register and the resulting register 4888 is of the wrong class, reload the whole SUBREG. This avoids 4889 needless copies if SUBREG_REG is multi-word. */ 4890 if (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) 4891 { 4892 int regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x); 4893 4894 if (! (context ? REGNO_OK_FOR_INDEX_P (regno) 4895 : REGNO_OK_FOR_BASE_P (regno))) 4896 { 4897 push_reload (x, NULL_RTX, loc, NULL_PTR, 4898 context ? INDEX_REG_CLASS : BASE_REG_CLASS, 4899 GET_MODE (x), VOIDmode, 0, 0, opnum, type); 4900 return 1; 4901 } 4902 } 4903 /* If this is a SUBREG of a pseudo-register, and the pseudo-register 4904 is larger than the class size, then reload the whole SUBREG. */ 4905 else 4906 { 4907 enum reg_class class = (context 4908 ? INDEX_REG_CLASS : BASE_REG_CLASS); 4909 if (CLASS_MAX_NREGS (class, GET_MODE (SUBREG_REG (x))) 4910 > reg_class_size[class]) 4911 { 4912 push_reload (x, NULL_RTX, loc, NULL_PTR, class, 4913 GET_MODE (x), VOIDmode, 0, 0, opnum, type); 4914 return 1; 4915 } 4916 } 4917 } 4918 break; 4919 } 4920 4921 { 4922 register char *fmt = GET_RTX_FORMAT (code); 4923 register int i; 4924 4925 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 4926 { 4927 if (fmt[i] == 'e') 4928 find_reloads_address_1 (XEXP (x, i), context, &XEXP (x, i), 4929 opnum, type, ind_levels); 4930 } 4931 } 4932 4933 return 0; 4934} 4935 4936/* X, which is found at *LOC, is a part of an address that needs to be 4937 reloaded into a register of class CLASS. If X is a constant, or if 4938 X is a PLUS that contains a constant, check that the constant is a 4939 legitimate operand and that we are supposed to be able to load 4940 it into the register. 4941 4942 If not, force the constant into memory and reload the MEM instead. 4943 4944 MODE is the mode to use, in case X is an integer constant. 4945 4946 OPNUM and TYPE describe the purpose of any reloads made. 4947 4948 IND_LEVELS says how many levels of indirect addressing this machine 4949 supports. */ 4950 4951static void 4952find_reloads_address_part (x, loc, class, mode, opnum, type, ind_levels) 4953 rtx x; 4954 rtx *loc; 4955 enum reg_class class; 4956 enum machine_mode mode; 4957 int opnum; 4958 enum reload_type type; 4959 int ind_levels; 4960{ 4961 if (CONSTANT_P (x) 4962 && (! LEGITIMATE_CONSTANT_P (x) 4963 || PREFERRED_RELOAD_CLASS (x, class) == NO_REGS)) 4964 { 4965 rtx tem = x = force_const_mem (mode, x); 4966 find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), 4967 opnum, type, ind_levels); 4968 } 4969 4970 else if (GET_CODE (x) == PLUS 4971 && CONSTANT_P (XEXP (x, 1)) 4972 && (! LEGITIMATE_CONSTANT_P (XEXP (x, 1)) 4973 || PREFERRED_RELOAD_CLASS (XEXP (x, 1), class) == NO_REGS)) 4974 { 4975 rtx tem = force_const_mem (GET_MODE (x), XEXP (x, 1)); 4976 4977 x = gen_rtx (PLUS, GET_MODE (x), XEXP (x, 0), tem); 4978 find_reloads_address (mode, &tem, XEXP (tem, 0), &XEXP (tem, 0), 4979 opnum, type, ind_levels); 4980 } 4981 4982 push_reload (x, NULL_RTX, loc, NULL_PTR, class, 4983 mode, VOIDmode, 0, 0, opnum, type); 4984} 4985 4986/* Substitute into the current INSN the registers into which we have reloaded 4987 the things that need reloading. The array `replacements' 4988 says contains the locations of all pointers that must be changed 4989 and says what to replace them with. 4990 4991 Return the rtx that X translates into; usually X, but modified. */ 4992 4993void 4994subst_reloads () 4995{ 4996 register int i; 4997 4998 for (i = 0; i < n_replacements; i++) 4999 { 5000 register struct replacement *r = &replacements[i]; 5001 register rtx reloadreg = reload_reg_rtx[r->what]; 5002 if (reloadreg) 5003 { 5004 /* Encapsulate RELOADREG so its machine mode matches what 5005 used to be there. Note that gen_lowpart_common will 5006 do the wrong thing if RELOADREG is multi-word. RELOADREG 5007 will always be a REG here. */ 5008 if (GET_MODE (reloadreg) != r->mode && r->mode != VOIDmode) 5009 reloadreg = gen_rtx (REG, r->mode, REGNO (reloadreg)); 5010 5011 /* If we are putting this into a SUBREG and RELOADREG is a 5012 SUBREG, we would be making nested SUBREGs, so we have to fix 5013 this up. Note that r->where == &SUBREG_REG (*r->subreg_loc). */ 5014 5015 if (r->subreg_loc != 0 && GET_CODE (reloadreg) == SUBREG) 5016 { 5017 if (GET_MODE (*r->subreg_loc) 5018 == GET_MODE (SUBREG_REG (reloadreg))) 5019 *r->subreg_loc = SUBREG_REG (reloadreg); 5020 else 5021 { 5022 *r->where = SUBREG_REG (reloadreg); 5023 SUBREG_WORD (*r->subreg_loc) += SUBREG_WORD (reloadreg); 5024 } 5025 } 5026 else 5027 *r->where = reloadreg; 5028 } 5029 /* If reload got no reg and isn't optional, something's wrong. */ 5030 else if (! reload_optional[r->what]) 5031 abort (); 5032 } 5033} 5034 5035/* Make a copy of any replacements being done into X and move those copies 5036 to locations in Y, a copy of X. We only look at the highest level of 5037 the RTL. */ 5038 5039void 5040copy_replacements (x, y) 5041 rtx x; 5042 rtx y; 5043{ 5044 int i, j; 5045 enum rtx_code code = GET_CODE (x); 5046 char *fmt = GET_RTX_FORMAT (code); 5047 struct replacement *r; 5048 5049 /* We can't support X being a SUBREG because we might then need to know its 5050 location if something inside it was replaced. */ 5051 if (code == SUBREG) 5052 abort (); 5053 5054 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 5055 if (fmt[i] == 'e') 5056 for (j = 0; j < n_replacements; j++) 5057 { 5058 if (replacements[j].subreg_loc == &XEXP (x, i)) 5059 { 5060 r = &replacements[n_replacements++]; 5061 r->where = replacements[j].where; 5062 r->subreg_loc = &XEXP (y, i); 5063 r->what = replacements[j].what; 5064 r->mode = replacements[j].mode; 5065 } 5066 else if (replacements[j].where == &XEXP (x, i)) 5067 { 5068 r = &replacements[n_replacements++]; 5069 r->where = &XEXP (y, i); 5070 r->subreg_loc = 0; 5071 r->what = replacements[j].what; 5072 r->mode = replacements[j].mode; 5073 } 5074 } 5075} 5076 5077/* If LOC was scheduled to be replaced by something, return the replacement. 5078 Otherwise, return *LOC. */ 5079 5080rtx 5081find_replacement (loc) 5082 rtx *loc; 5083{ 5084 struct replacement *r; 5085 5086 for (r = &replacements[0]; r < &replacements[n_replacements]; r++) 5087 { 5088 rtx reloadreg = reload_reg_rtx[r->what]; 5089 5090 if (reloadreg && r->where == loc) 5091 { 5092 if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode) 5093 reloadreg = gen_rtx (REG, r->mode, REGNO (reloadreg)); 5094 5095 return reloadreg; 5096 } 5097 else if (reloadreg && r->subreg_loc == loc) 5098 { 5099 /* RELOADREG must be either a REG or a SUBREG. 5100 5101 ??? Is it actually still ever a SUBREG? If so, why? */ 5102 5103 if (GET_CODE (reloadreg) == REG) 5104 return gen_rtx (REG, GET_MODE (*loc), 5105 REGNO (reloadreg) + SUBREG_WORD (*loc)); 5106 else if (GET_MODE (reloadreg) == GET_MODE (*loc)) 5107 return reloadreg; 5108 else 5109 return gen_rtx (SUBREG, GET_MODE (*loc), SUBREG_REG (reloadreg), 5110 SUBREG_WORD (reloadreg) + SUBREG_WORD (*loc)); 5111 } 5112 } 5113 5114 return *loc; 5115} 5116 5117/* Return nonzero if register in range [REGNO, ENDREGNO) 5118 appears either explicitly or implicitly in X 5119 other than being stored into (except for earlyclobber operands). 5120 5121 References contained within the substructure at LOC do not count. 5122 LOC may be zero, meaning don't ignore anything. 5123 5124 This is similar to refers_to_regno_p in rtlanal.c except that we 5125 look at equivalences for pseudos that didn't get hard registers. */ 5126 5127int 5128refers_to_regno_for_reload_p (regno, endregno, x, loc) 5129 int regno, endregno; 5130 rtx x; 5131 rtx *loc; 5132{ 5133 register int i; 5134 register RTX_CODE code; 5135 register char *fmt; 5136 5137 if (x == 0) 5138 return 0; 5139 5140 repeat: 5141 code = GET_CODE (x); 5142 5143 switch (code) 5144 { 5145 case REG: 5146 i = REGNO (x); 5147 5148 /* If this is a pseudo, a hard register must not have been allocated. 5149 X must therefore either be a constant or be in memory. */ 5150 if (i >= FIRST_PSEUDO_REGISTER) 5151 { 5152 if (reg_equiv_memory_loc[i]) 5153 return refers_to_regno_for_reload_p (regno, endregno, 5154 reg_equiv_memory_loc[i], 5155 NULL_PTR); 5156 5157 if (reg_equiv_constant[i]) 5158 return 0; 5159 5160 abort (); 5161 } 5162 5163 return (endregno > i 5164 && regno < i + (i < FIRST_PSEUDO_REGISTER 5165 ? HARD_REGNO_NREGS (i, GET_MODE (x)) 5166 : 1)); 5167 5168 case SUBREG: 5169 /* If this is a SUBREG of a hard reg, we can see exactly which 5170 registers are being modified. Otherwise, handle normally. */ 5171 if (GET_CODE (SUBREG_REG (x)) == REG 5172 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) 5173 { 5174 int inner_regno = REGNO (SUBREG_REG (x)) + SUBREG_WORD (x); 5175 int inner_endregno 5176 = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER 5177 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 5178 5179 return endregno > inner_regno && regno < inner_endregno; 5180 } 5181 break; 5182 5183 case CLOBBER: 5184 case SET: 5185 if (&SET_DEST (x) != loc 5186 /* Note setting a SUBREG counts as referring to the REG it is in for 5187 a pseudo but not for hard registers since we can 5188 treat each word individually. */ 5189 && ((GET_CODE (SET_DEST (x)) == SUBREG 5190 && loc != &SUBREG_REG (SET_DEST (x)) 5191 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG 5192 && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER 5193 && refers_to_regno_for_reload_p (regno, endregno, 5194 SUBREG_REG (SET_DEST (x)), 5195 loc)) 5196 /* If the output is an earlyclobber operand, this is 5197 a conflict. */ 5198 || ((GET_CODE (SET_DEST (x)) != REG 5199 || earlyclobber_operand_p (SET_DEST (x))) 5200 && refers_to_regno_for_reload_p (regno, endregno, 5201 SET_DEST (x), loc)))) 5202 return 1; 5203 5204 if (code == CLOBBER || loc == &SET_SRC (x)) 5205 return 0; 5206 x = SET_SRC (x); 5207 goto repeat; 5208 } 5209 5210 /* X does not match, so try its subexpressions. */ 5211 5212 fmt = GET_RTX_FORMAT (code); 5213 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 5214 { 5215 if (fmt[i] == 'e' && loc != &XEXP (x, i)) 5216 { 5217 if (i == 0) 5218 { 5219 x = XEXP (x, 0); 5220 goto repeat; 5221 } 5222 else 5223 if (refers_to_regno_for_reload_p (regno, endregno, 5224 XEXP (x, i), loc)) 5225 return 1; 5226 } 5227 else if (fmt[i] == 'E') 5228 { 5229 register int j; 5230 for (j = XVECLEN (x, i) - 1; j >=0; j--) 5231 if (loc != &XVECEXP (x, i, j) 5232 && refers_to_regno_for_reload_p (regno, endregno, 5233 XVECEXP (x, i, j), loc)) 5234 return 1; 5235 } 5236 } 5237 return 0; 5238} 5239 5240/* Nonzero if modifying X will affect IN. If X is a register or a SUBREG, 5241 we check if any register number in X conflicts with the relevant register 5242 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN 5243 contains a MEM (we don't bother checking for memory addresses that can't 5244 conflict because we expect this to be a rare case. 5245 5246 This function is similar to reg_overlap_mention_p in rtlanal.c except 5247 that we look at equivalences for pseudos that didn't get hard registers. */ 5248 5249int 5250reg_overlap_mentioned_for_reload_p (x, in) 5251 rtx x, in; 5252{ 5253 int regno, endregno; 5254 5255 if (GET_CODE (x) == SUBREG) 5256 { 5257 regno = REGNO (SUBREG_REG (x)); 5258 if (regno < FIRST_PSEUDO_REGISTER) 5259 regno += SUBREG_WORD (x); 5260 } 5261 else if (GET_CODE (x) == REG) 5262 { 5263 regno = REGNO (x); 5264 5265 /* If this is a pseudo, it must not have been assigned a hard register. 5266 Therefore, it must either be in memory or be a constant. */ 5267 5268 if (regno >= FIRST_PSEUDO_REGISTER) 5269 { 5270 if (reg_equiv_memory_loc[regno]) 5271 return refers_to_mem_for_reload_p (in); 5272 else if (reg_equiv_constant[regno]) 5273 return 0; 5274 abort (); 5275 } 5276 } 5277 else if (CONSTANT_P (x)) 5278 return 0; 5279 else if (GET_CODE (x) == MEM) 5280 return refers_to_mem_for_reload_p (in); 5281 else if (GET_CODE (x) == SCRATCH || GET_CODE (x) == PC 5282 || GET_CODE (x) == CC0) 5283 return reg_mentioned_p (x, in); 5284 else 5285 abort (); 5286 5287 endregno = regno + (regno < FIRST_PSEUDO_REGISTER 5288 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); 5289 5290 return refers_to_regno_for_reload_p (regno, endregno, in, NULL_PTR); 5291} 5292 5293/* Return nonzero if anything in X contains a MEM. Look also for pseudo 5294 registers. */ 5295 5296int 5297refers_to_mem_for_reload_p (x) 5298 rtx x; 5299{ 5300 char *fmt; 5301 int i; 5302 5303 if (GET_CODE (x) == MEM) 5304 return 1; 5305 5306 if (GET_CODE (x) == REG) 5307 return (REGNO (x) >= FIRST_PSEUDO_REGISTER 5308 && reg_equiv_memory_loc[REGNO (x)]); 5309 5310 fmt = GET_RTX_FORMAT (GET_CODE (x)); 5311 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) 5312 if (fmt[i] == 'e' 5313 && (GET_CODE (XEXP (x, i)) == MEM 5314 || refers_to_mem_for_reload_p (XEXP (x, i)))) 5315 return 1; 5316 5317 return 0; 5318} 5319 5320/* Check the insns before INSN to see if there is a suitable register 5321 containing the same value as GOAL. 5322 If OTHER is -1, look for a register in class CLASS. 5323 Otherwise, just see if register number OTHER shares GOAL's value. 5324 5325 Return an rtx for the register found, or zero if none is found. 5326 5327 If RELOAD_REG_P is (short *)1, 5328 we reject any hard reg that appears in reload_reg_rtx 5329 because such a hard reg is also needed coming into this insn. 5330 5331 If RELOAD_REG_P is any other nonzero value, 5332 it is a vector indexed by hard reg number 5333 and we reject any hard reg whose element in the vector is nonnegative 5334 as well as any that appears in reload_reg_rtx. 5335 5336 If GOAL is zero, then GOALREG is a register number; we look 5337 for an equivalent for that register. 5338 5339 MODE is the machine mode of the value we want an equivalence for. 5340 If GOAL is nonzero and not VOIDmode, then it must have mode MODE. 5341 5342 This function is used by jump.c as well as in the reload pass. 5343 5344 If GOAL is the sum of the stack pointer and a constant, we treat it 5345 as if it were a constant except that sp is required to be unchanging. */ 5346 5347rtx 5348find_equiv_reg (goal, insn, class, other, reload_reg_p, goalreg, mode) 5349 register rtx goal; 5350 rtx insn; 5351 enum reg_class class; 5352 register int other; 5353 short *reload_reg_p; 5354 int goalreg; 5355 enum machine_mode mode; 5356{ 5357 register rtx p = insn; 5358 rtx goaltry, valtry, value, where; 5359 register rtx pat; 5360 register int regno = -1; 5361 int valueno; 5362 int goal_mem = 0; 5363 int goal_const = 0; 5364 int goal_mem_addr_varies = 0; 5365 int need_stable_sp = 0; 5366 int nregs; 5367 int valuenregs; 5368 5369 if (goal == 0) 5370 regno = goalreg; 5371 else if (GET_CODE (goal) == REG) 5372 regno = REGNO (goal); 5373 else if (GET_CODE (goal) == MEM) 5374 { 5375 enum rtx_code code = GET_CODE (XEXP (goal, 0)); 5376 if (MEM_VOLATILE_P (goal)) 5377 return 0; 5378 if (flag_float_store && GET_MODE_CLASS (GET_MODE (goal)) == MODE_FLOAT) 5379 return 0; 5380 /* An address with side effects must be reexecuted. */ 5381 switch (code) 5382 { 5383 case POST_INC: 5384 case PRE_INC: 5385 case POST_DEC: 5386 case PRE_DEC: 5387 return 0; 5388 } 5389 goal_mem = 1; 5390 } 5391 else if (CONSTANT_P (goal)) 5392 goal_const = 1; 5393 else if (GET_CODE (goal) == PLUS 5394 && XEXP (goal, 0) == stack_pointer_rtx 5395 && CONSTANT_P (XEXP (goal, 1))) 5396 goal_const = need_stable_sp = 1; 5397 else 5398 return 0; 5399 5400 /* On some machines, certain regs must always be rejected 5401 because they don't behave the way ordinary registers do. */ 5402 5403#ifdef OVERLAPPING_REGNO_P 5404 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER 5405 && OVERLAPPING_REGNO_P (regno)) 5406 return 0; 5407#endif 5408 5409 /* Scan insns back from INSN, looking for one that copies 5410 a value into or out of GOAL. 5411 Stop and give up if we reach a label. */ 5412 5413 while (1) 5414 { 5415 p = PREV_INSN (p); 5416 if (p == 0 || GET_CODE (p) == CODE_LABEL) 5417 return 0; 5418 if (GET_CODE (p) == INSN 5419 /* If we don't want spill regs ... */ 5420 && (! (reload_reg_p != 0 5421 && reload_reg_p != (short *) (HOST_WIDE_INT) 1) 5422 /* ... then ignore insns introduced by reload; they aren't useful 5423 and can cause results in reload_as_needed to be different 5424 from what they were when calculating the need for spills. 5425 If we notice an input-reload insn here, we will reject it below, 5426 but it might hide a usable equivalent. That makes bad code. 5427 It may even abort: perhaps no reg was spilled for this insn 5428 because it was assumed we would find that equivalent. */ 5429 || INSN_UID (p) < reload_first_uid)) 5430 { 5431 rtx tem; 5432 pat = single_set (p); 5433 /* First check for something that sets some reg equal to GOAL. */ 5434 if (pat != 0 5435 && ((regno >= 0 5436 && true_regnum (SET_SRC (pat)) == regno 5437 && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) 5438 || 5439 (regno >= 0 5440 && true_regnum (SET_DEST (pat)) == regno 5441 && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0) 5442 || 5443 (goal_const && rtx_equal_p (SET_SRC (pat), goal) 5444 && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) 5445 || (goal_mem 5446 && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0 5447 && rtx_renumbered_equal_p (goal, SET_SRC (pat))) 5448 || (goal_mem 5449 && (valueno = true_regnum (valtry = SET_SRC (pat))) >= 0 5450 && rtx_renumbered_equal_p (goal, SET_DEST (pat))) 5451 /* If we are looking for a constant, 5452 and something equivalent to that constant was copied 5453 into a reg, we can use that reg. */ 5454 || (goal_const && (tem = find_reg_note (p, REG_EQUIV, 5455 NULL_RTX)) 5456 && rtx_equal_p (XEXP (tem, 0), goal) 5457 && (valueno = true_regnum (valtry = SET_DEST (pat))) >= 0) 5458 || (goal_const && (tem = find_reg_note (p, REG_EQUIV, 5459 NULL_RTX)) 5460 && GET_CODE (SET_DEST (pat)) == REG 5461 && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE 5462 && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT 5463 && GET_CODE (goal) == CONST_INT 5464 && 0 != (goaltry = operand_subword (XEXP (tem, 0), 0, 0, 5465 VOIDmode)) 5466 && rtx_equal_p (goal, goaltry) 5467 && (valtry = operand_subword (SET_DEST (pat), 0, 0, 5468 VOIDmode)) 5469 && (valueno = true_regnum (valtry)) >= 0) 5470 || (goal_const && (tem = find_reg_note (p, REG_EQUIV, 5471 NULL_RTX)) 5472 && GET_CODE (SET_DEST (pat)) == REG 5473 && GET_CODE (XEXP (tem, 0)) == CONST_DOUBLE 5474 && GET_MODE_CLASS (GET_MODE (XEXP (tem, 0))) == MODE_FLOAT 5475 && GET_CODE (goal) == CONST_INT 5476 && 0 != (goaltry = operand_subword (XEXP (tem, 0), 1, 0, 5477 VOIDmode)) 5478 && rtx_equal_p (goal, goaltry) 5479 && (valtry 5480 = operand_subword (SET_DEST (pat), 1, 0, VOIDmode)) 5481 && (valueno = true_regnum (valtry)) >= 0))) 5482 if (other >= 0 5483 ? valueno == other 5484 : ((unsigned) valueno < FIRST_PSEUDO_REGISTER 5485 && TEST_HARD_REG_BIT (reg_class_contents[(int) class], 5486 valueno))) 5487 { 5488 value = valtry; 5489 where = p; 5490 break; 5491 } 5492 } 5493 } 5494 5495 /* We found a previous insn copying GOAL into a suitable other reg VALUE 5496 (or copying VALUE into GOAL, if GOAL is also a register). 5497 Now verify that VALUE is really valid. */ 5498 5499 /* VALUENO is the register number of VALUE; a hard register. */ 5500 5501 /* Don't try to re-use something that is killed in this insn. We want 5502 to be able to trust REG_UNUSED notes. */ 5503 if (find_reg_note (where, REG_UNUSED, value)) 5504 return 0; 5505 5506 /* If we propose to get the value from the stack pointer or if GOAL is 5507 a MEM based on the stack pointer, we need a stable SP. */ 5508 if (valueno == STACK_POINTER_REGNUM 5509 || (goal_mem && reg_overlap_mentioned_for_reload_p (stack_pointer_rtx, 5510 goal))) 5511 need_stable_sp = 1; 5512 5513 /* Reject VALUE if the copy-insn moved the wrong sort of datum. */ 5514 if (GET_MODE (value) != mode) 5515 return 0; 5516 5517 /* Reject VALUE if it was loaded from GOAL 5518 and is also a register that appears in the address of GOAL. */ 5519 5520 if (goal_mem && value == SET_DEST (PATTERN (where)) 5521 && refers_to_regno_for_reload_p (valueno, 5522 (valueno 5523 + HARD_REGNO_NREGS (valueno, mode)), 5524 goal, NULL_PTR)) 5525 return 0; 5526 5527 /* Reject registers that overlap GOAL. */ 5528 5529 if (!goal_mem && !goal_const 5530 && regno + HARD_REGNO_NREGS (regno, mode) > valueno 5531 && regno < valueno + HARD_REGNO_NREGS (valueno, mode)) 5532 return 0; 5533 5534 /* Reject VALUE if it is one of the regs reserved for reloads. 5535 Reload1 knows how to reuse them anyway, and it would get 5536 confused if we allocated one without its knowledge. 5537 (Now that insns introduced by reload are ignored above, 5538 this case shouldn't happen, but I'm not positive.) */ 5539 5540 if (reload_reg_p != 0 && reload_reg_p != (short *) (HOST_WIDE_INT) 1 5541 && reload_reg_p[valueno] >= 0) 5542 return 0; 5543 5544 /* On some machines, certain regs must always be rejected 5545 because they don't behave the way ordinary registers do. */ 5546 5547#ifdef OVERLAPPING_REGNO_P 5548 if (OVERLAPPING_REGNO_P (valueno)) 5549 return 0; 5550#endif 5551 5552 nregs = HARD_REGNO_NREGS (regno, mode); 5553 valuenregs = HARD_REGNO_NREGS (valueno, mode); 5554 5555 /* Reject VALUE if it is a register being used for an input reload 5556 even if it is not one of those reserved. */ 5557 5558 if (reload_reg_p != 0) 5559 { 5560 int i; 5561 for (i = 0; i < n_reloads; i++) 5562 if (reload_reg_rtx[i] != 0 && reload_in[i]) 5563 { 5564 int regno1 = REGNO (reload_reg_rtx[i]); 5565 int nregs1 = HARD_REGNO_NREGS (regno1, 5566 GET_MODE (reload_reg_rtx[i])); 5567 if (regno1 < valueno + valuenregs 5568 && regno1 + nregs1 > valueno) 5569 return 0; 5570 } 5571 } 5572 5573 if (goal_mem) 5574 /* We must treat frame pointer as varying here, 5575 since it can vary--in a nonlocal goto as generated by expand_goto. */ 5576 goal_mem_addr_varies = !CONSTANT_ADDRESS_P (XEXP (goal, 0)); 5577 5578 /* Now verify that the values of GOAL and VALUE remain unaltered 5579 until INSN is reached. */ 5580 5581 p = insn; 5582 while (1) 5583 { 5584 p = PREV_INSN (p); 5585 if (p == where) 5586 return value; 5587 5588 /* Don't trust the conversion past a function call 5589 if either of the two is in a call-clobbered register, or memory. */ 5590 if (GET_CODE (p) == CALL_INSN 5591 && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER 5592 && call_used_regs[regno]) 5593 || 5594 (valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER 5595 && call_used_regs[valueno]) 5596 || 5597 goal_mem 5598 || need_stable_sp)) 5599 return 0; 5600 5601#ifdef NON_SAVING_SETJMP 5602 if (NON_SAVING_SETJMP && GET_CODE (p) == NOTE 5603 && NOTE_LINE_NUMBER (p) == NOTE_INSN_SETJMP) 5604 return 0; 5605#endif 5606 5607#ifdef INSN_CLOBBERS_REGNO_P 5608 if ((valueno >= 0 && valueno < FIRST_PSEUDO_REGISTER 5609 && INSN_CLOBBERS_REGNO_P (p, valueno)) 5610 || (regno >= 0 && regno < FIRST_PSEUDO_REGISTER 5611 && INSN_CLOBBERS_REGNO_P (p, regno))) 5612 return 0; 5613#endif 5614 5615 if (GET_RTX_CLASS (GET_CODE (p)) == 'i') 5616 { 5617 /* If this insn P stores in either GOAL or VALUE, return 0. 5618 If GOAL is a memory ref and this insn writes memory, return 0. 5619 If GOAL is a memory ref and its address is not constant, 5620 and this insn P changes a register used in GOAL, return 0. */ 5621 5622 pat = PATTERN (p); 5623 if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER) 5624 { 5625 register rtx dest = SET_DEST (pat); 5626 while (GET_CODE (dest) == SUBREG 5627 || GET_CODE (dest) == ZERO_EXTRACT 5628 || GET_CODE (dest) == SIGN_EXTRACT 5629 || GET_CODE (dest) == STRICT_LOW_PART) 5630 dest = XEXP (dest, 0); 5631 if (GET_CODE (dest) == REG) 5632 { 5633 register int xregno = REGNO (dest); 5634 int xnregs; 5635 if (REGNO (dest) < FIRST_PSEUDO_REGISTER) 5636 xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); 5637 else 5638 xnregs = 1; 5639 if (xregno < regno + nregs && xregno + xnregs > regno) 5640 return 0; 5641 if (xregno < valueno + valuenregs 5642 && xregno + xnregs > valueno) 5643 return 0; 5644 if (goal_mem_addr_varies 5645 && reg_overlap_mentioned_for_reload_p (dest, goal)) 5646 return 0; 5647 } 5648 else if (goal_mem && GET_CODE (dest) == MEM 5649 && ! push_operand (dest, GET_MODE (dest))) 5650 return 0; 5651 else if (GET_CODE (dest) == MEM && regno >= FIRST_PSEUDO_REGISTER 5652 && reg_equiv_memory_loc[regno] != 0) 5653 return 0; 5654 else if (need_stable_sp && push_operand (dest, GET_MODE (dest))) 5655 return 0; 5656 } 5657 else if (GET_CODE (pat) == PARALLEL) 5658 { 5659 register int i; 5660 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) 5661 { 5662 register rtx v1 = XVECEXP (pat, 0, i); 5663 if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER) 5664 { 5665 register rtx dest = SET_DEST (v1); 5666 while (GET_CODE (dest) == SUBREG 5667 || GET_CODE (dest) == ZERO_EXTRACT 5668 || GET_CODE (dest) == SIGN_EXTRACT 5669 || GET_CODE (dest) == STRICT_LOW_PART) 5670 dest = XEXP (dest, 0); 5671 if (GET_CODE (dest) == REG) 5672 { 5673 register int xregno = REGNO (dest); 5674 int xnregs; 5675 if (REGNO (dest) < FIRST_PSEUDO_REGISTER) 5676 xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); 5677 else 5678 xnregs = 1; 5679 if (xregno < regno + nregs 5680 && xregno + xnregs > regno) 5681 return 0; 5682 if (xregno < valueno + valuenregs 5683 && xregno + xnregs > valueno) 5684 return 0; 5685 if (goal_mem_addr_varies 5686 && reg_overlap_mentioned_for_reload_p (dest, 5687 goal)) 5688 return 0; 5689 } 5690 else if (goal_mem && GET_CODE (dest) == MEM 5691 && ! push_operand (dest, GET_MODE (dest))) 5692 return 0; 5693 else if (need_stable_sp 5694 && push_operand (dest, GET_MODE (dest))) 5695 return 0; 5696 } 5697 } 5698 } 5699 5700 if (GET_CODE (p) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (p)) 5701 { 5702 rtx link; 5703 5704 for (link = CALL_INSN_FUNCTION_USAGE (p); XEXP (link, 1) != 0; 5705 link = XEXP (link, 1)) 5706 { 5707 pat = XEXP (link, 0); 5708 if (GET_CODE (pat) == CLOBBER) 5709 { 5710 register rtx dest = SET_DEST (pat); 5711 while (GET_CODE (dest) == SUBREG 5712 || GET_CODE (dest) == ZERO_EXTRACT 5713 || GET_CODE (dest) == SIGN_EXTRACT 5714 || GET_CODE (dest) == STRICT_LOW_PART) 5715 dest = XEXP (dest, 0); 5716 if (GET_CODE (dest) == REG) 5717 { 5718 register int xregno = REGNO (dest); 5719 int xnregs; 5720 if (REGNO (dest) < FIRST_PSEUDO_REGISTER) 5721 xnregs = HARD_REGNO_NREGS (xregno, GET_MODE (dest)); 5722 else 5723 xnregs = 1; 5724 if (xregno < regno + nregs 5725 && xregno + xnregs > regno) 5726 return 0; 5727 if (xregno < valueno + valuenregs 5728 && xregno + xnregs > valueno) 5729 return 0; 5730 if (goal_mem_addr_varies 5731 && reg_overlap_mentioned_for_reload_p (dest, 5732 goal)) 5733 return 0; 5734 } 5735 else if (goal_mem && GET_CODE (dest) == MEM 5736 && ! push_operand (dest, GET_MODE (dest))) 5737 return 0; 5738 else if (need_stable_sp 5739 && push_operand (dest, GET_MODE (dest))) 5740 return 0; 5741 } 5742 } 5743 } 5744 5745#ifdef AUTO_INC_DEC 5746 /* If this insn auto-increments or auto-decrements 5747 either regno or valueno, return 0 now. 5748 If GOAL is a memory ref and its address is not constant, 5749 and this insn P increments a register used in GOAL, return 0. */ 5750 { 5751 register rtx link; 5752 5753 for (link = REG_NOTES (p); link; link = XEXP (link, 1)) 5754 if (REG_NOTE_KIND (link) == REG_INC 5755 && GET_CODE (XEXP (link, 0)) == REG) 5756 { 5757 register int incno = REGNO (XEXP (link, 0)); 5758 if (incno < regno + nregs && incno >= regno) 5759 return 0; 5760 if (incno < valueno + valuenregs && incno >= valueno) 5761 return 0; 5762 if (goal_mem_addr_varies 5763 && reg_overlap_mentioned_for_reload_p (XEXP (link, 0), 5764 goal)) 5765 return 0; 5766 } 5767 } 5768#endif 5769 } 5770 } 5771} 5772 5773/* Find a place where INCED appears in an increment or decrement operator 5774 within X, and return the amount INCED is incremented or decremented by. 5775 The value is always positive. */ 5776 5777static int 5778find_inc_amount (x, inced) 5779 rtx x, inced; 5780{ 5781 register enum rtx_code code = GET_CODE (x); 5782 register char *fmt; 5783 register int i; 5784 5785 if (code == MEM) 5786 { 5787 register rtx addr = XEXP (x, 0); 5788 if ((GET_CODE (addr) == PRE_DEC 5789 || GET_CODE (addr) == POST_DEC 5790 || GET_CODE (addr) == PRE_INC 5791 || GET_CODE (addr) == POST_INC) 5792 && XEXP (addr, 0) == inced) 5793 return GET_MODE_SIZE (GET_MODE (x)); 5794 } 5795 5796 fmt = GET_RTX_FORMAT (code); 5797 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 5798 { 5799 if (fmt[i] == 'e') 5800 { 5801 register int tem = find_inc_amount (XEXP (x, i), inced); 5802 if (tem != 0) 5803 return tem; 5804 } 5805 if (fmt[i] == 'E') 5806 { 5807 register int j; 5808 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 5809 { 5810 register int tem = find_inc_amount (XVECEXP (x, i, j), inced); 5811 if (tem != 0) 5812 return tem; 5813 } 5814 } 5815 } 5816 5817 return 0; 5818} 5819 5820/* Return 1 if register REGNO is the subject of a clobber in insn INSN. */ 5821 5822int 5823regno_clobbered_p (regno, insn) 5824 int regno; 5825 rtx insn; 5826{ 5827 if (GET_CODE (PATTERN (insn)) == CLOBBER 5828 && GET_CODE (XEXP (PATTERN (insn), 0)) == REG) 5829 return REGNO (XEXP (PATTERN (insn), 0)) == regno; 5830 5831 if (GET_CODE (PATTERN (insn)) == PARALLEL) 5832 { 5833 int i = XVECLEN (PATTERN (insn), 0) - 1; 5834 5835 for (; i >= 0; i--) 5836 { 5837 rtx elt = XVECEXP (PATTERN (insn), 0, i); 5838 if (GET_CODE (elt) == CLOBBER && GET_CODE (XEXP (elt, 0)) == REG 5839 && REGNO (XEXP (elt, 0)) == regno) 5840 return 1; 5841 } 5842 } 5843 5844 return 0; 5845} 5846 5847static char *reload_when_needed_name[] = 5848{ 5849 "RELOAD_FOR_INPUT", 5850 "RELOAD_FOR_OUTPUT", 5851 "RELOAD_FOR_INSN", 5852 "RELOAD_FOR_INPUT_ADDRESS", 5853 "RELOAD_FOR_OUTPUT_ADDRESS", 5854 "RELOAD_FOR_OPERAND_ADDRESS", 5855 "RELOAD_FOR_OPADDR_ADDR", 5856 "RELOAD_OTHER", 5857 "RELOAD_FOR_OTHER_ADDRESS" 5858}; 5859 5860static char *reg_class_names[] = REG_CLASS_NAMES; 5861 5862/* This function is used to print the variables set by 'find_reloads' */ 5863 5864void 5865debug_reload() 5866{ 5867 int r; 5868 5869 fprintf (stderr, "\nn_reloads = %d\n", n_reloads); 5870 5871 for (r = 0; r < n_reloads; r++) 5872 { 5873 fprintf (stderr, "\nRELOAD %d\n", r); 5874 5875 if (reload_in[r]) 5876 { 5877 fprintf (stderr, "\nreload_in (%s) = ", 5878 GET_MODE_NAME (reload_inmode[r])); 5879 debug_rtx (reload_in[r]); 5880 } 5881 5882 if (reload_out[r]) 5883 { 5884 fprintf (stderr, "\nreload_out (%s) = ", 5885 GET_MODE_NAME (reload_outmode[r])); 5886 debug_rtx (reload_out[r]); 5887 } 5888 5889 fprintf (stderr, "%s, ", reg_class_names[(int) reload_reg_class[r]]); 5890 5891 fprintf (stderr, "%s (opnum = %d)", 5892 reload_when_needed_name[(int)reload_when_needed[r]], 5893 reload_opnum[r]); 5894 5895 if (reload_optional[r]) 5896 fprintf (stderr, ", optional"); 5897 5898 if (reload_in[r]) 5899 fprintf (stderr, ", inc by %d\n", reload_inc[r]); 5900 5901 if (reload_nocombine[r]) 5902 fprintf (stderr, ", can combine"); 5903 5904 if (reload_secondary_p[r]) 5905 fprintf (stderr, ", secondary_reload_p"); 5906 5907 if (reload_in_reg[r]) 5908 { 5909 fprintf (stderr, "\nreload_in_reg:\t\t\t"); 5910 debug_rtx (reload_in_reg[r]); 5911 } 5912 5913 if (reload_reg_rtx[r]) 5914 { 5915 fprintf (stderr, "\nreload_reg_rtx:\t\t\t"); 5916 debug_rtx (reload_reg_rtx[r]); 5917 } 5918 5919 if (reload_secondary_in_reload[r] != -1) 5920 { 5921 fprintf (stderr, "\nsecondary_in_reload = "); 5922 fprintf (stderr, "%d ", reload_secondary_in_reload[r]); 5923 } 5924 5925 if (reload_secondary_out_reload[r] != -1) 5926 { 5927 if (reload_secondary_in_reload[r] != -1) 5928 fprintf (stderr, ", secondary_out_reload = "); 5929 else 5930 fprintf (stderr, "\nsecondary_out_reload = "); 5931 5932 fprintf (stderr, "%d", reload_secondary_out_reload[r]); 5933 } 5934 5935 5936 if (reload_secondary_in_icode[r] != CODE_FOR_nothing) 5937 { 5938 fprintf (stderr, "\nsecondary_in_icode = "); 5939 fprintf (stderr, "%s", insn_name[r]); 5940 } 5941 5942 if (reload_secondary_out_icode[r] != CODE_FOR_nothing) 5943 { 5944 if (reload_secondary_in_icode[r] != CODE_FOR_nothing) 5945 fprintf (stderr, ", secondary_out_icode = "); 5946 else 5947 fprintf (stderr, "\nsecondary_out_icode = "); 5948 5949 fprintf (stderr, "%s ", insn_name[r]); 5950 } 5951 fprintf (stderr, "\n"); 5952 } 5953 5954 fprintf (stderr, "\n"); 5955} 5956