regmove.c revision 52750
1/* Move registers around to reduce number of move instructions needed. 2 Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc. 3 4This file is part of GNU CC. 5 6GNU CC is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 2, or (at your option) 9any later version. 10 11GNU CC is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16You should have received a copy of the GNU General Public License 17along with GNU CC; see the file COPYING. If not, write to 18the Free Software Foundation, 59 Temple Place - Suite 330, 19Boston, MA 02111-1307, USA. */ 20 21 22/* This module looks for cases where matching constraints would force 23 an instruction to need a reload, and this reload would be a register 24 to register move. It then attempts to change the registers used by the 25 instruction to avoid the move instruction. */ 26 27#include "config.h" 28#include "system.h" 29#include "rtl.h" /* stdio.h must precede rtl.h for FFS. */ 30#include "insn-config.h" 31#include "recog.h" 32#include "output.h" 33#include "reload.h" 34#include "regs.h" 35#include "hard-reg-set.h" 36#include "flags.h" 37#include "expr.h" 38#include "insn-flags.h" 39#include "basic-block.h" 40#include "toplev.h" 41 42static int optimize_reg_copy_1 PROTO((rtx, rtx, rtx)); 43static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx)); 44static void optimize_reg_copy_3 PROTO((rtx, rtx, rtx)); 45static rtx gen_add3_insn PROTO((rtx, rtx, rtx)); 46static void copy_src_to_dest PROTO((rtx, rtx, rtx, int, int)); 47static int *regmove_bb_head; 48 49struct match { 50 int with[MAX_RECOG_OPERANDS]; 51 enum { READ, WRITE, READWRITE } use[MAX_RECOG_OPERANDS]; 52 int commutative[MAX_RECOG_OPERANDS]; 53 int early_clobber[MAX_RECOG_OPERANDS]; 54}; 55 56static rtx discover_flags_reg PROTO((void)); 57static void mark_flags_life_zones PROTO((rtx)); 58static void flags_set_1 PROTO((rtx, rtx)); 59 60static int try_auto_increment PROTO((rtx, rtx, rtx, rtx, HOST_WIDE_INT, int)); 61static int find_matches PROTO((rtx, struct match *)); 62static int fixup_match_1 PROTO((rtx, rtx, rtx, rtx, rtx, int, int, int, FILE *)) 63; 64static int reg_is_remote_constant_p PROTO((rtx, rtx, rtx)); 65static int stable_and_no_regs_but_for_p PROTO((rtx, rtx, rtx)); 66static int regclass_compatible_p PROTO((int, int)); 67static int loop_depth; 68 69/* Return non-zero if registers with CLASS1 and CLASS2 can be merged without 70 causing too much register allocation problems. */ 71static int 72regclass_compatible_p (class0, class1) 73 int class0, class1; 74{ 75 return (class0 == class1 76 || (reg_class_subset_p (class0, class1) 77 && ! CLASS_LIKELY_SPILLED_P (class0)) 78 || (reg_class_subset_p (class1, class0) 79 && ! CLASS_LIKELY_SPILLED_P (class1))); 80} 81 82/* Generate and return an insn body to add r1 and c, 83 storing the result in r0. */ 84static rtx 85gen_add3_insn (r0, r1, c) 86 rtx r0, r1, c; 87{ 88 int icode = (int) add_optab->handlers[(int) GET_MODE (r0)].insn_code; 89 90 if (icode == CODE_FOR_nothing 91 || ! (*insn_operand_predicate[icode][0]) (r0, insn_operand_mode[icode][0]) 92 || ! (*insn_operand_predicate[icode][1]) (r1, insn_operand_mode[icode][1]) 93 || ! (*insn_operand_predicate[icode][2]) (c, insn_operand_mode[icode][2])) 94 return NULL_RTX; 95 96 return (GEN_FCN (icode) (r0, r1, c)); 97} 98 99 100/* INC_INSN is an instruction that adds INCREMENT to REG. 101 Try to fold INC_INSN as a post/pre in/decrement into INSN. 102 Iff INC_INSN_SET is nonzero, inc_insn has a destination different from src. 103 Return nonzero for success. */ 104static int 105try_auto_increment (insn, inc_insn, inc_insn_set, reg, increment, pre) 106 rtx reg, insn, inc_insn ,inc_insn_set; 107 HOST_WIDE_INT increment; 108 int pre; 109{ 110 enum rtx_code inc_code; 111 112 rtx pset = single_set (insn); 113 if (pset) 114 { 115 /* Can't use the size of SET_SRC, we might have something like 116 (sign_extend:SI (mem:QI ... */ 117 rtx use = find_use_as_address (pset, reg, 0); 118 if (use != 0 && use != (rtx) 1) 119 { 120 int size = GET_MODE_SIZE (GET_MODE (use)); 121 if (0 122 || (HAVE_POST_INCREMENT 123 && pre == 0 && (inc_code = POST_INC, increment == size)) 124 || (HAVE_PRE_INCREMENT 125 && pre == 1 && (inc_code = PRE_INC, increment == size)) 126 || (HAVE_POST_DECREMENT 127 && pre == 0 && (inc_code = POST_DEC, increment == -size)) 128 || (HAVE_PRE_DECREMENT 129 && pre == 1 && (inc_code = PRE_DEC, increment == -size)) 130 ) 131 { 132 if (inc_insn_set) 133 validate_change 134 (inc_insn, 135 &SET_SRC (inc_insn_set), 136 XEXP (SET_SRC (inc_insn_set), 0), 1); 137 validate_change (insn, &XEXP (use, 0), 138 gen_rtx_fmt_e (inc_code, Pmode, reg), 1); 139 if (apply_change_group ()) 140 { 141 REG_NOTES (insn) 142 = gen_rtx_EXPR_LIST (REG_INC, 143 reg, REG_NOTES (insn)); 144 if (! inc_insn_set) 145 { 146 PUT_CODE (inc_insn, NOTE); 147 NOTE_LINE_NUMBER (inc_insn) = NOTE_INSN_DELETED; 148 NOTE_SOURCE_FILE (inc_insn) = 0; 149 } 150 return 1; 151 } 152 } 153 } 154 } 155 return 0; 156} 157 158/* Determine if the pattern generated by add_optab has a clobber, 159 such as might be issued for a flags hard register. To make the 160 code elsewhere simpler, we handle cc0 in this same framework. 161 162 Return the register if one was discovered. Return NULL_RTX if 163 if no flags were found. Return pc_rtx if we got confused. */ 164 165static rtx 166discover_flags_reg () 167{ 168 rtx tmp; 169 tmp = gen_rtx_REG (word_mode, 10000); 170 tmp = gen_add3_insn (tmp, tmp, GEN_INT (2)); 171 172 /* If we get something that isn't a simple set, or a 173 [(set ..) (clobber ..)], this whole function will go wrong. */ 174 if (GET_CODE (tmp) == SET) 175 return NULL_RTX; 176 else if (GET_CODE (tmp) == PARALLEL) 177 { 178 int found; 179 180 if (XVECLEN (tmp, 0) != 2) 181 return pc_rtx; 182 tmp = XVECEXP (tmp, 0, 1); 183 if (GET_CODE (tmp) != CLOBBER) 184 return pc_rtx; 185 tmp = XEXP (tmp, 0); 186 187 /* Don't do anything foolish if the md wanted to clobber a 188 scratch or something. We only care about hard regs. 189 Moreover we don't like the notion of subregs of hard regs. */ 190 if (GET_CODE (tmp) == SUBREG 191 && GET_CODE (SUBREG_REG (tmp)) == REG 192 && REGNO (SUBREG_REG (tmp)) < FIRST_PSEUDO_REGISTER) 193 return pc_rtx; 194 found = (GET_CODE (tmp) == REG && REGNO (tmp) < FIRST_PSEUDO_REGISTER); 195 196 return (found ? tmp : NULL_RTX); 197 } 198 199 return pc_rtx; 200} 201 202/* It is a tedious task identifying when the flags register is live and 203 when it is safe to optimize. Since we process the instruction stream 204 multiple times, locate and record these live zones by marking the 205 mode of the instructions -- 206 207 QImode is used on the instruction at which the flags becomes live. 208 209 HImode is used within the range (exclusive) that the flags are 210 live. Thus the user of the flags is not marked. 211 212 All other instructions are cleared to VOIDmode. */ 213 214/* Used to communicate with flags_set_1. */ 215static rtx flags_set_1_rtx; 216static int flags_set_1_set; 217 218static void 219mark_flags_life_zones (flags) 220 rtx flags; 221{ 222 int flags_regno; 223 int flags_nregs; 224 int block; 225 226#ifdef HAVE_cc0 227 /* If we found a flags register on a cc0 host, bail. */ 228 if (flags == NULL_RTX) 229 flags = cc0_rtx; 230 else if (flags != cc0_rtx) 231 flags = pc_rtx; 232#endif 233 234 /* Simple cases first: if no flags, clear all modes. If confusing, 235 mark the entire function as being in a flags shadow. */ 236 if (flags == NULL_RTX || flags == pc_rtx) 237 { 238 enum machine_mode mode = (flags ? HImode : VOIDmode); 239 rtx insn; 240 for (insn = get_insns(); insn; insn = NEXT_INSN (insn)) 241 PUT_MODE (insn, mode); 242 return; 243 } 244 245#ifdef HAVE_cc0 246 flags_regno = -1; 247 flags_nregs = 1; 248#else 249 flags_regno = REGNO (flags); 250 flags_nregs = HARD_REGNO_NREGS (flags_regno, GET_MODE (flags)); 251#endif 252 flags_set_1_rtx = flags; 253 254 /* Process each basic block. */ 255 for (block = n_basic_blocks - 1; block >= 0; block--) 256 { 257 rtx insn, end; 258 int live; 259 260 insn = BLOCK_HEAD (block); 261 end = BLOCK_END (block); 262 263 /* Look out for the (unlikely) case of flags being live across 264 basic block boundaries. */ 265 live = 0; 266#ifndef HAVE_cc0 267 { 268 int i; 269 for (i = 0; i < flags_nregs; ++i) 270 live |= REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, 271 flags_regno + i); 272 } 273#endif 274 275 while (1) 276 { 277 /* Process liveness in reverse order of importance -- 278 alive, death, birth. This lets more important info 279 overwrite the mode of lesser info. */ 280 281 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 282 { 283#ifdef HAVE_cc0 284 /* In the cc0 case, death is not marked in reg notes, 285 but is instead the mere use of cc0 when it is alive. */ 286 if (live && reg_mentioned_p (cc0_rtx, PATTERN (insn))) 287 live = 0; 288#else 289 /* In the hard reg case, we watch death notes. */ 290 if (live && find_regno_note (insn, REG_DEAD, flags_regno)) 291 live = 0; 292#endif 293 PUT_MODE (insn, (live ? HImode : VOIDmode)); 294 295 /* In either case, birth is denoted simply by it's presence 296 as the destination of a set. */ 297 flags_set_1_set = 0; 298 note_stores (PATTERN (insn), flags_set_1); 299 if (flags_set_1_set) 300 { 301 live = 1; 302 PUT_MODE (insn, QImode); 303 } 304 } 305 else 306 PUT_MODE (insn, (live ? HImode : VOIDmode)); 307 308 if (insn == end) 309 break; 310 insn = NEXT_INSN (insn); 311 } 312 } 313} 314 315/* A subroutine of mark_flags_life_zones, called through note_stores. */ 316 317static void 318flags_set_1 (x, pat) 319 rtx x, pat; 320{ 321 if (GET_CODE (pat) == SET 322 && reg_overlap_mentioned_p (x, flags_set_1_rtx)) 323 flags_set_1_set = 1; 324} 325 326static int *regno_src_regno; 327 328/* Indicate how good a choice REG (which appears as a source) is to replace 329 a destination register with. The higher the returned value, the better 330 the choice. The main objective is to avoid using a register that is 331 a candidate for tying to a hard register, since the output might in 332 turn be a candidate to be tied to a different hard register. */ 333int 334replacement_quality(reg) 335 rtx reg; 336{ 337 int src_regno; 338 339 /* Bad if this isn't a register at all. */ 340 if (GET_CODE (reg) != REG) 341 return 0; 342 343 /* If this register is not meant to get a hard register, 344 it is a poor choice. */ 345 if (REG_LIVE_LENGTH (REGNO (reg)) < 0) 346 return 0; 347 348 src_regno = regno_src_regno[REGNO (reg)]; 349 350 /* If it was not copied from another register, it is fine. */ 351 if (src_regno < 0) 352 return 3; 353 354 /* Copied from a hard register? */ 355 if (src_regno < FIRST_PSEUDO_REGISTER) 356 return 1; 357 358 /* Copied from a pseudo register - not as bad as from a hard register, 359 yet still cumbersome, since the register live length will be lengthened 360 when the registers get tied. */ 361 return 2; 362} 363 364/* INSN is a copy from SRC to DEST, both registers, and SRC does not die 365 in INSN. 366 367 Search forward to see if SRC dies before either it or DEST is modified, 368 but don't scan past the end of a basic block. If so, we can replace SRC 369 with DEST and let SRC die in INSN. 370 371 This will reduce the number of registers live in that range and may enable 372 DEST to be tied to SRC, thus often saving one register in addition to a 373 register-register copy. */ 374 375static int 376optimize_reg_copy_1 (insn, dest, src) 377 rtx insn; 378 rtx dest; 379 rtx src; 380{ 381 rtx p, q; 382 rtx note; 383 rtx dest_death = 0; 384 int sregno = REGNO (src); 385 int dregno = REGNO (dest); 386 387 /* We don't want to mess with hard regs if register classes are small. */ 388 if (sregno == dregno 389 || (SMALL_REGISTER_CLASSES 390 && (sregno < FIRST_PSEUDO_REGISTER 391 || dregno < FIRST_PSEUDO_REGISTER)) 392 /* We don't see all updates to SP if they are in an auto-inc memory 393 reference, so we must disallow this optimization on them. */ 394 || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM) 395 return 0; 396 397 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) 398 { 399 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN 400 || (GET_CODE (p) == NOTE 401 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG 402 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) 403 break; 404 405 /* ??? We can't scan past the end of a basic block without updating 406 the register lifetime info (REG_DEAD/basic_block_live_at_start). 407 A CALL_INSN might be the last insn of a basic block, if it is inside 408 an EH region. There is no easy way to tell, so we just always break 409 when we see a CALL_INSN if flag_exceptions is nonzero. */ 410 if (flag_exceptions && GET_CODE (p) == CALL_INSN) 411 break; 412 413 if (GET_RTX_CLASS (GET_CODE (p)) != 'i') 414 continue; 415 416 if (reg_set_p (src, p) || reg_set_p (dest, p) 417 /* Don't change a USE of a register. */ 418 || (GET_CODE (PATTERN (p)) == USE 419 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) 420 break; 421 422 /* See if all of SRC dies in P. This test is slightly more 423 conservative than it needs to be. */ 424 if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0 425 && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) 426 { 427 int failed = 0; 428 int d_length = 0; 429 int s_length = 0; 430 int d_n_calls = 0; 431 int s_n_calls = 0; 432 433 /* We can do the optimization. Scan forward from INSN again, 434 replacing regs as we go. Set FAILED if a replacement can't 435 be done. In that case, we can't move the death note for SRC. 436 This should be rare. */ 437 438 /* Set to stop at next insn. */ 439 for (q = next_real_insn (insn); 440 q != next_real_insn (p); 441 q = next_real_insn (q)) 442 { 443 if (reg_overlap_mentioned_p (src, PATTERN (q))) 444 { 445 /* If SRC is a hard register, we might miss some 446 overlapping registers with validate_replace_rtx, 447 so we would have to undo it. We can't if DEST is 448 present in the insn, so fail in that combination 449 of cases. */ 450 if (sregno < FIRST_PSEUDO_REGISTER 451 && reg_mentioned_p (dest, PATTERN (q))) 452 failed = 1; 453 454 /* Replace all uses and make sure that the register 455 isn't still present. */ 456 else if (validate_replace_rtx (src, dest, q) 457 && (sregno >= FIRST_PSEUDO_REGISTER 458 || ! reg_overlap_mentioned_p (src, 459 PATTERN (q)))) 460 { 461 /* We assume that a register is used exactly once per 462 insn in the REG_N_REFS updates below. If this is not 463 correct, no great harm is done. 464 465 Since we do not know if we will change the lifetime of 466 SREGNO or DREGNO, we must not update REG_LIVE_LENGTH 467 or REG_N_CALLS_CROSSED at this time. */ 468 if (sregno >= FIRST_PSEUDO_REGISTER) 469 REG_N_REFS (sregno) -= loop_depth; 470 471 if (dregno >= FIRST_PSEUDO_REGISTER) 472 REG_N_REFS (dregno) += loop_depth; 473 } 474 else 475 { 476 validate_replace_rtx (dest, src, q); 477 failed = 1; 478 } 479 } 480 481 /* For SREGNO, count the total number of insns scanned. 482 For DREGNO, count the total number of insns scanned after 483 passing the death note for DREGNO. */ 484 s_length++; 485 if (dest_death) 486 d_length++; 487 488 /* If the insn in which SRC dies is a CALL_INSN, don't count it 489 as a call that has been crossed. Otherwise, count it. */ 490 if (q != p && GET_CODE (q) == CALL_INSN) 491 { 492 /* Similarly, total calls for SREGNO, total calls beyond 493 the death note for DREGNO. */ 494 s_n_calls++; 495 if (dest_death) 496 d_n_calls++; 497 } 498 499 /* If DEST dies here, remove the death note and save it for 500 later. Make sure ALL of DEST dies here; again, this is 501 overly conservative. */ 502 if (dest_death == 0 503 && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0) 504 { 505 if (GET_MODE (XEXP (dest_death, 0)) != GET_MODE (dest)) 506 failed = 1, dest_death = 0; 507 else 508 remove_note (q, dest_death); 509 } 510 } 511 512 if (! failed) 513 { 514 /* These counters need to be updated if and only if we are 515 going to move the REG_DEAD note. */ 516 if (sregno >= FIRST_PSEUDO_REGISTER) 517 { 518 if (REG_LIVE_LENGTH (sregno) >= 0) 519 { 520 REG_LIVE_LENGTH (sregno) -= s_length; 521 /* REG_LIVE_LENGTH is only an approximation after 522 combine if sched is not run, so make sure that we 523 still have a reasonable value. */ 524 if (REG_LIVE_LENGTH (sregno) < 2) 525 REG_LIVE_LENGTH (sregno) = 2; 526 } 527 528 REG_N_CALLS_CROSSED (sregno) -= s_n_calls; 529 } 530 531 /* Move death note of SRC from P to INSN. */ 532 remove_note (p, note); 533 XEXP (note, 1) = REG_NOTES (insn); 534 REG_NOTES (insn) = note; 535 } 536 537 /* Put death note of DEST on P if we saw it die. */ 538 if (dest_death) 539 { 540 XEXP (dest_death, 1) = REG_NOTES (p); 541 REG_NOTES (p) = dest_death; 542 543 if (dregno >= FIRST_PSEUDO_REGISTER) 544 { 545 /* If and only if we are moving the death note for DREGNO, 546 then we need to update its counters. */ 547 if (REG_LIVE_LENGTH (dregno) >= 0) 548 REG_LIVE_LENGTH (dregno) += d_length; 549 REG_N_CALLS_CROSSED (dregno) += d_n_calls; 550 } 551 } 552 553 return ! failed; 554 } 555 556 /* If SRC is a hard register which is set or killed in some other 557 way, we can't do this optimization. */ 558 else if (sregno < FIRST_PSEUDO_REGISTER 559 && dead_or_set_p (p, src)) 560 break; 561 } 562 return 0; 563} 564 565/* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have 566 a sequence of insns that modify DEST followed by an insn that sets 567 SRC to DEST in which DEST dies, with no prior modification of DEST. 568 (There is no need to check if the insns in between actually modify 569 DEST. We should not have cases where DEST is not modified, but 570 the optimization is safe if no such modification is detected.) 571 In that case, we can replace all uses of DEST, starting with INSN and 572 ending with the set of SRC to DEST, with SRC. We do not do this 573 optimization if a CALL_INSN is crossed unless SRC already crosses a 574 call or if DEST dies before the copy back to SRC. 575 576 It is assumed that DEST and SRC are pseudos; it is too complicated to do 577 this for hard registers since the substitutions we may make might fail. */ 578 579static void 580optimize_reg_copy_2 (insn, dest, src) 581 rtx insn; 582 rtx dest; 583 rtx src; 584{ 585 rtx p, q; 586 rtx set; 587 int sregno = REGNO (src); 588 int dregno = REGNO (dest); 589 590 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) 591 { 592 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN 593 || (GET_CODE (p) == NOTE 594 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG 595 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) 596 break; 597 598 /* ??? We can't scan past the end of a basic block without updating 599 the register lifetime info (REG_DEAD/basic_block_live_at_start). 600 A CALL_INSN might be the last insn of a basic block, if it is inside 601 an EH region. There is no easy way to tell, so we just always break 602 when we see a CALL_INSN if flag_exceptions is nonzero. */ 603 if (flag_exceptions && GET_CODE (p) == CALL_INSN) 604 break; 605 606 if (GET_RTX_CLASS (GET_CODE (p)) != 'i') 607 continue; 608 609 set = single_set (p); 610 if (set && SET_SRC (set) == dest && SET_DEST (set) == src 611 && find_reg_note (p, REG_DEAD, dest)) 612 { 613 /* We can do the optimization. Scan forward from INSN again, 614 replacing regs as we go. */ 615 616 /* Set to stop at next insn. */ 617 for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q)) 618 if (GET_RTX_CLASS (GET_CODE (q)) == 'i') 619 { 620 if (reg_mentioned_p (dest, PATTERN (q))) 621 { 622 PATTERN (q) = replace_rtx (PATTERN (q), dest, src); 623 624 /* We assume that a register is used exactly once per 625 insn in the updates below. If this is not correct, 626 no great harm is done. */ 627 REG_N_REFS (dregno) -= loop_depth; 628 REG_N_REFS (sregno) += loop_depth; 629 } 630 631 632 if (GET_CODE (q) == CALL_INSN) 633 { 634 REG_N_CALLS_CROSSED (dregno)--; 635 REG_N_CALLS_CROSSED (sregno)++; 636 } 637 } 638 639 remove_note (p, find_reg_note (p, REG_DEAD, dest)); 640 REG_N_DEATHS (dregno)--; 641 remove_note (insn, find_reg_note (insn, REG_DEAD, src)); 642 REG_N_DEATHS (sregno)--; 643 return; 644 } 645 646 if (reg_set_p (src, p) 647 || find_reg_note (p, REG_DEAD, dest) 648 || (GET_CODE (p) == CALL_INSN && REG_N_CALLS_CROSSED (sregno) == 0)) 649 break; 650 } 651} 652/* INSN is a ZERO_EXTEND or SIGN_EXTEND of SRC to DEST. 653 Look if SRC dies there, and if it is only set once, by loading 654 it from memory. If so, try to encorporate the zero/sign extension 655 into the memory read, change SRC to the mode of DEST, and alter 656 the remaining accesses to use the appropriate SUBREG. This allows 657 SRC and DEST to be tied later. */ 658static void 659optimize_reg_copy_3 (insn, dest, src) 660 rtx insn; 661 rtx dest; 662 rtx src; 663{ 664 rtx src_reg = XEXP (src, 0); 665 int src_no = REGNO (src_reg); 666 int dst_no = REGNO (dest); 667 rtx p, set, subreg; 668 enum machine_mode old_mode; 669 670 if (src_no < FIRST_PSEUDO_REGISTER 671 || dst_no < FIRST_PSEUDO_REGISTER 672 || ! find_reg_note (insn, REG_DEAD, src_reg) 673 || REG_N_SETS (src_no) != 1) 674 return; 675 for (p = PREV_INSN (insn); ! reg_set_p (src_reg, p); p = PREV_INSN (p)) 676 { 677 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN 678 || (GET_CODE (p) == NOTE 679 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG 680 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) 681 return; 682 683 /* ??? We can't scan past the end of a basic block without updating 684 the register lifetime info (REG_DEAD/basic_block_live_at_start). 685 A CALL_INSN might be the last insn of a basic block, if it is inside 686 an EH region. There is no easy way to tell, so we just always break 687 when we see a CALL_INSN if flag_exceptions is nonzero. */ 688 if (flag_exceptions && GET_CODE (p) == CALL_INSN) 689 return; 690 691 if (GET_RTX_CLASS (GET_CODE (p)) != 'i') 692 continue; 693 } 694 if (! (set = single_set (p)) 695 || GET_CODE (SET_SRC (set)) != MEM 696 || SET_DEST (set) != src_reg) 697 return; 698 699 /* Be conserative: although this optimization is also valid for 700 volatile memory references, that could cause trouble in later passes. */ 701 if (MEM_VOLATILE_P (SET_SRC (set))) 702 return; 703 704 /* Do not use a SUBREG to truncate from one mode to another if truncation 705 is not a nop. */ 706 if (GET_MODE_BITSIZE (GET_MODE (src_reg)) <= GET_MODE_BITSIZE (GET_MODE (src)) 707 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (src)), 708 GET_MODE_BITSIZE (GET_MODE (src_reg)))) 709 return; 710 711 old_mode = GET_MODE (src_reg); 712 PUT_MODE (src_reg, GET_MODE (src)); 713 XEXP (src, 0) = SET_SRC (set); 714 715 /* Include this change in the group so that it's easily undone if 716 one of the changes in the group is invalid. */ 717 validate_change (p, &SET_SRC (set), src, 1); 718 719 /* Now walk forward making additional replacements. We want to be able 720 to undo all the changes if a later substitution fails. */ 721 subreg = gen_rtx_SUBREG (old_mode, src_reg, 0); 722 while (p = NEXT_INSN (p), p != insn) 723 { 724 if (GET_RTX_CLASS (GET_CODE (p)) != 'i') 725 continue; 726 727 /* Make a tenative change. */ 728 validate_replace_rtx_group (src_reg, subreg, p); 729 } 730 731 validate_replace_rtx_group (src, src_reg, insn); 732 733 /* Now see if all the changes are valid. */ 734 if (! apply_change_group ()) 735 { 736 /* One or more changes were no good. Back out everything. */ 737 PUT_MODE (src_reg, old_mode); 738 XEXP (src, 0) = src_reg; 739 } 740} 741 742 743/* If we were not able to update the users of src to use dest directly, try 744 instead moving the value to dest directly before the operation. */ 745 746static void 747copy_src_to_dest (insn, src, dest, loop_depth, old_max_uid) 748 rtx insn; 749 rtx src; 750 rtx dest; 751 int loop_depth; 752 int old_max_uid; 753{ 754 rtx seq; 755 rtx link; 756 rtx next; 757 rtx set; 758 rtx move_insn; 759 rtx *p_insn_notes; 760 rtx *p_move_notes; 761 int src_regno; 762 int dest_regno; 763 int bb; 764 int insn_uid; 765 int move_uid; 766 767 /* A REG_LIVE_LENGTH of -1 indicates the register is equivalent to a constant 768 or memory location and is used infrequently; a REG_LIVE_LENGTH of -2 is 769 parameter when there is no frame pointer that is not allocated a register. 770 For now, we just reject them, rather than incrementing the live length. */ 771 772 if (GET_CODE (src) == REG 773 && REG_LIVE_LENGTH (REGNO (src)) > 0 774 && GET_CODE (dest) == REG 775 && REG_LIVE_LENGTH (REGNO (dest)) > 0 776 && (set = single_set (insn)) != NULL_RTX 777 && !reg_mentioned_p (dest, SET_SRC (set)) 778 && GET_MODE (src) == GET_MODE (dest)) 779 { 780 int old_num_regs = reg_rtx_no; 781 782 /* Generate the src->dest move. */ 783 start_sequence (); 784 emit_move_insn (dest, src); 785 seq = gen_sequence (); 786 end_sequence (); 787 /* If this sequence uses new registers, we may not use it. */ 788 if (old_num_regs != reg_rtx_no 789 || ! validate_replace_rtx (src, dest, insn)) 790 { 791 /* We have to restore reg_rtx_no to its old value, lest 792 recompute_reg_usage will try to compute the usage of the 793 new regs, yet reg_n_info is not valid for them. */ 794 reg_rtx_no = old_num_regs; 795 return; 796 } 797 emit_insn_before (seq, insn); 798 move_insn = PREV_INSN (insn); 799 p_move_notes = ®_NOTES (move_insn); 800 p_insn_notes = ®_NOTES (insn); 801 802 /* Move any notes mentioning src to the move instruction */ 803 for (link = REG_NOTES (insn); link != NULL_RTX; link = next) 804 { 805 next = XEXP (link, 1); 806 if (XEXP (link, 0) == src) 807 { 808 *p_move_notes = link; 809 p_move_notes = &XEXP (link, 1); 810 } 811 else 812 { 813 *p_insn_notes = link; 814 p_insn_notes = &XEXP (link, 1); 815 } 816 } 817 818 *p_move_notes = NULL_RTX; 819 *p_insn_notes = NULL_RTX; 820 821 /* Is the insn the head of a basic block? If so extend it */ 822 insn_uid = INSN_UID (insn); 823 move_uid = INSN_UID (move_insn); 824 if (insn_uid < old_max_uid) 825 { 826 bb = regmove_bb_head[insn_uid]; 827 if (bb >= 0) 828 { 829 BLOCK_HEAD (bb) = move_insn; 830 regmove_bb_head[insn_uid] = -1; 831 } 832 } 833 834 /* Update the various register tables. */ 835 dest_regno = REGNO (dest); 836 REG_N_SETS (dest_regno) += loop_depth; 837 REG_N_REFS (dest_regno) += loop_depth; 838 REG_LIVE_LENGTH (dest_regno)++; 839 if (REGNO_FIRST_UID (dest_regno) == insn_uid) 840 REGNO_FIRST_UID (dest_regno) = move_uid; 841 842 src_regno = REGNO (src); 843 if (! find_reg_note (move_insn, REG_DEAD, src)) 844 REG_LIVE_LENGTH (src_regno)++; 845 846 if (REGNO_FIRST_UID (src_regno) == insn_uid) 847 REGNO_FIRST_UID (src_regno) = move_uid; 848 849 if (REGNO_LAST_UID (src_regno) == insn_uid) 850 REGNO_LAST_UID (src_regno) = move_uid; 851 852 if (REGNO_LAST_NOTE_UID (src_regno) == insn_uid) 853 REGNO_LAST_NOTE_UID (src_regno) = move_uid; 854 } 855} 856 857 858/* Return whether REG is set in only one location, and is set to a 859 constant, but is set in a different basic block from INSN (an 860 instructions which uses REG). In this case REG is equivalent to a 861 constant, and we don't want to break that equivalence, because that 862 may increase register pressure and make reload harder. If REG is 863 set in the same basic block as INSN, we don't worry about it, 864 because we'll probably need a register anyhow (??? but what if REG 865 is used in a different basic block as well as this one?). FIRST is 866 the first insn in the function. */ 867 868static int 869reg_is_remote_constant_p (reg, insn, first) 870 rtx reg; 871 rtx insn; 872 rtx first; 873{ 874 register rtx p; 875 876 if (REG_N_SETS (REGNO (reg)) != 1) 877 return 0; 878 879 /* Look for the set. */ 880 for (p = LOG_LINKS (insn); p; p = XEXP (p, 1)) 881 { 882 rtx s; 883 884 if (REG_NOTE_KIND (p) != 0) 885 continue; 886 s = single_set (XEXP (p, 0)); 887 if (s != 0 888 && GET_CODE (SET_DEST (s)) == REG 889 && REGNO (SET_DEST (s)) == REGNO (reg)) 890 { 891 /* The register is set in the same basic block. */ 892 return 0; 893 } 894 } 895 896 for (p = first; p && p != insn; p = NEXT_INSN (p)) 897 { 898 rtx s; 899 900 if (GET_RTX_CLASS (GET_CODE (p)) != 'i') 901 continue; 902 s = single_set (p); 903 if (s != 0 904 && GET_CODE (SET_DEST (s)) == REG 905 && REGNO (SET_DEST (s)) == REGNO (reg)) 906 { 907 /* This is the instruction which sets REG. If there is a 908 REG_EQUAL note, then REG is equivalent to a constant. */ 909 if (find_reg_note (p, REG_EQUAL, NULL_RTX)) 910 return 1; 911 return 0; 912 } 913 } 914 915 return 0; 916} 917 918/* INSN is adding a CONST_INT to a REG. We search backwards looking for 919 another add immediate instruction with the same source and dest registers, 920 and if we find one, we change INSN to an increment, and return 1. If 921 no changes are made, we return 0. 922 923 This changes 924 (set (reg100) (plus reg1 offset1)) 925 ... 926 (set (reg100) (plus reg1 offset2)) 927 to 928 (set (reg100) (plus reg1 offset1)) 929 ... 930 (set (reg100) (plus reg100 offset2-offset1)) */ 931 932/* ??? What does this comment mean? */ 933/* cse disrupts preincrement / postdecrement squences when it finds a 934 hard register as ultimate source, like the frame pointer. */ 935 936int 937fixup_match_2 (insn, dst, src, offset, regmove_dump_file) 938 rtx insn, dst, src, offset; 939 FILE *regmove_dump_file; 940{ 941 rtx p, dst_death = 0; 942 int length, num_calls = 0; 943 944 /* If SRC dies in INSN, we'd have to move the death note. This is 945 considered to be very unlikely, so we just skip the optimization 946 in this case. */ 947 if (find_regno_note (insn, REG_DEAD, REGNO (src))) 948 return 0; 949 950 /* Scan backward to find the first instruction that sets DST. */ 951 952 for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p)) 953 { 954 rtx pset; 955 956 if (GET_CODE (p) == CODE_LABEL 957 || GET_CODE (p) == JUMP_INSN 958 || (GET_CODE (p) == NOTE 959 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG 960 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) 961 break; 962 963 /* ??? We can't scan past the end of a basic block without updating 964 the register lifetime info (REG_DEAD/basic_block_live_at_start). 965 A CALL_INSN might be the last insn of a basic block, if it is inside 966 an EH region. There is no easy way to tell, so we just always break 967 when we see a CALL_INSN if flag_exceptions is nonzero. */ 968 if (flag_exceptions && GET_CODE (p) == CALL_INSN) 969 break; 970 971 if (GET_RTX_CLASS (GET_CODE (p)) != 'i') 972 continue; 973 974 if (find_regno_note (p, REG_DEAD, REGNO (dst))) 975 dst_death = p; 976 if (! dst_death) 977 length++; 978 979 pset = single_set (p); 980 if (pset && SET_DEST (pset) == dst 981 && GET_CODE (SET_SRC (pset)) == PLUS 982 && XEXP (SET_SRC (pset), 0) == src 983 && GET_CODE (XEXP (SET_SRC (pset), 1)) == CONST_INT) 984 { 985 HOST_WIDE_INT newconst 986 = INTVAL (offset) - INTVAL (XEXP (SET_SRC (pset), 1)); 987 rtx add = gen_add3_insn (dst, dst, GEN_INT (newconst)); 988 989 if (add && validate_change (insn, &PATTERN (insn), add, 0)) 990 { 991 /* Remove the death note for DST from DST_DEATH. */ 992 if (dst_death) 993 { 994 remove_death (REGNO (dst), dst_death); 995 REG_LIVE_LENGTH (REGNO (dst)) += length; 996 REG_N_CALLS_CROSSED (REGNO (dst)) += num_calls; 997 } 998 999 REG_N_REFS (REGNO (dst)) += loop_depth; 1000 REG_N_REFS (REGNO (src)) -= loop_depth; 1001 1002 if (regmove_dump_file) 1003 fprintf (regmove_dump_file, 1004 "Fixed operand of insn %d.\n", 1005 INSN_UID (insn)); 1006 1007#ifdef AUTO_INC_DEC 1008 for (p = PREV_INSN (insn); p; p = PREV_INSN (p)) 1009 { 1010 if (GET_CODE (p) == CODE_LABEL 1011 || GET_CODE (p) == JUMP_INSN 1012 || (GET_CODE (p) == NOTE 1013 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG 1014 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) 1015 break; 1016 if (GET_RTX_CLASS (GET_CODE (p)) != 'i') 1017 continue; 1018 if (reg_overlap_mentioned_p (dst, PATTERN (p))) 1019 { 1020 if (try_auto_increment (p, insn, 0, dst, newconst, 0)) 1021 return 1; 1022 break; 1023 } 1024 } 1025 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) 1026 { 1027 if (GET_CODE (p) == CODE_LABEL 1028 || GET_CODE (p) == JUMP_INSN 1029 || (GET_CODE (p) == NOTE 1030 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG 1031 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) 1032 break; 1033 if (GET_RTX_CLASS (GET_CODE (p)) != 'i') 1034 continue; 1035 if (reg_overlap_mentioned_p (dst, PATTERN (p))) 1036 { 1037 try_auto_increment (p, insn, 0, dst, newconst, 1); 1038 break; 1039 } 1040 } 1041#endif 1042 return 1; 1043 } 1044 } 1045 1046 if (reg_set_p (dst, PATTERN (p))) 1047 break; 1048 1049 /* If we have passed a call instruction, and the 1050 pseudo-reg SRC is not already live across a call, 1051 then don't perform the optimization. */ 1052 /* reg_set_p is overly conservative for CALL_INSNS, thinks that all 1053 hard regs are clobbered. Thus, we only use it for src for 1054 non-call insns. */ 1055 if (GET_CODE (p) == CALL_INSN) 1056 { 1057 if (! dst_death) 1058 num_calls++; 1059 1060 if (REG_N_CALLS_CROSSED (REGNO (src)) == 0) 1061 break; 1062 1063 if (call_used_regs [REGNO (dst)] 1064 || find_reg_fusage (p, CLOBBER, dst)) 1065 break; 1066 } 1067 else if (reg_set_p (src, PATTERN (p))) 1068 break; 1069 } 1070 1071 return 0; 1072} 1073 1074void 1075regmove_optimize (f, nregs, regmove_dump_file) 1076 rtx f; 1077 int nregs; 1078 FILE *regmove_dump_file; 1079{ 1080 int old_max_uid = get_max_uid (); 1081 rtx insn; 1082 struct match match; 1083 int pass; 1084 int i; 1085 rtx copy_src, copy_dst; 1086 1087 /* Find out where a potential flags register is live, and so that we 1088 can supress some optimizations in those zones. */ 1089 mark_flags_life_zones (discover_flags_reg ()); 1090 1091 regno_src_regno = (int *)alloca (sizeof *regno_src_regno * nregs); 1092 for (i = nregs; --i >= 0; ) regno_src_regno[i] = -1; 1093 1094 regmove_bb_head = (int *)alloca (sizeof (int) * (old_max_uid + 1)); 1095 for (i = old_max_uid; i >= 0; i--) regmove_bb_head[i] = -1; 1096 for (i = 0; i < n_basic_blocks; i++) 1097 regmove_bb_head[INSN_UID (BLOCK_HEAD (i))] = i; 1098 1099 /* A forward/backward pass. Replace output operands with input operands. */ 1100 1101 loop_depth = 1; 1102 1103 for (pass = 0; pass <= 2; pass++) 1104 { 1105 if (! flag_regmove && pass >= flag_expensive_optimizations) 1106 return; 1107 1108 if (regmove_dump_file) 1109 fprintf (regmove_dump_file, "Starting %s pass...\n", 1110 pass ? "backward" : "forward"); 1111 1112 for (insn = pass ? get_last_insn () : f; insn; 1113 insn = pass ? PREV_INSN (insn) : NEXT_INSN (insn)) 1114 { 1115 rtx set; 1116 int op_no, match_no; 1117 1118 if (GET_CODE (insn) == NOTE) 1119 { 1120 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) 1121 loop_depth++; 1122 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) 1123 loop_depth--; 1124 } 1125 1126 set = single_set (insn); 1127 if (! set) 1128 continue; 1129 1130 if (flag_expensive_optimizations && ! pass 1131 && (GET_CODE (SET_SRC (set)) == SIGN_EXTEND 1132 || GET_CODE (SET_SRC (set)) == ZERO_EXTEND) 1133 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG 1134 && GET_CODE (SET_DEST(set)) == REG) 1135 optimize_reg_copy_3 (insn, SET_DEST (set), SET_SRC (set)); 1136 1137 if (flag_expensive_optimizations && ! pass 1138 && GET_CODE (SET_SRC (set)) == REG 1139 && GET_CODE (SET_DEST(set)) == REG) 1140 { 1141 /* If this is a register-register copy where SRC is not dead, 1142 see if we can optimize it. If this optimization succeeds, 1143 it will become a copy where SRC is dead. */ 1144 if ((find_reg_note (insn, REG_DEAD, SET_SRC (set)) 1145 || optimize_reg_copy_1 (insn, SET_DEST (set), SET_SRC (set))) 1146 && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER) 1147 { 1148 /* Similarly for a pseudo-pseudo copy when SRC is dead. */ 1149 if (REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) 1150 optimize_reg_copy_2 (insn, SET_DEST (set), SET_SRC (set)); 1151 if (regno_src_regno[REGNO (SET_DEST (set))] < 0 1152 && SET_SRC (set) != SET_DEST (set)) 1153 { 1154 int srcregno = REGNO (SET_SRC(set)); 1155 if (regno_src_regno[srcregno] >= 0) 1156 srcregno = regno_src_regno[srcregno]; 1157 regno_src_regno[REGNO (SET_DEST (set))] = srcregno; 1158 } 1159 } 1160 } 1161 if (! flag_regmove) 1162 continue; 1163 1164#ifdef REGISTER_CONSTRAINTS 1165 if (! find_matches (insn, &match)) 1166 continue; 1167 1168 /* Now scan through the operands looking for a source operand 1169 which is supposed to match the destination operand. 1170 Then scan forward for an instruction which uses the dest 1171 operand. 1172 If it dies there, then replace the dest in both operands with 1173 the source operand. */ 1174 1175 for (op_no = 0; op_no < recog_n_operands; op_no++) 1176 { 1177 rtx src, dst, src_subreg; 1178 enum reg_class src_class, dst_class; 1179 1180 match_no = match.with[op_no]; 1181 1182 /* Nothing to do if the two operands aren't supposed to match. */ 1183 if (match_no < 0) 1184 continue; 1185 1186 src = recog_operand[op_no]; 1187 dst = recog_operand[match_no]; 1188 1189 if (GET_CODE (src) != REG) 1190 continue; 1191 1192 src_subreg = src; 1193 if (GET_CODE (dst) == SUBREG 1194 && GET_MODE_SIZE (GET_MODE (dst)) 1195 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (dst)))) 1196 { 1197 src_subreg 1198 = gen_rtx_SUBREG (GET_MODE (SUBREG_REG (dst)), 1199 src, SUBREG_WORD (dst)); 1200 dst = SUBREG_REG (dst); 1201 } 1202 if (GET_CODE (dst) != REG 1203 || REGNO (dst) < FIRST_PSEUDO_REGISTER) 1204 continue; 1205 1206 if (REGNO (src) < FIRST_PSEUDO_REGISTER) 1207 { 1208 if (match.commutative[op_no] < op_no) 1209 regno_src_regno[REGNO (dst)] = REGNO (src); 1210 continue; 1211 } 1212 1213 if (REG_LIVE_LENGTH (REGNO (src)) < 0) 1214 continue; 1215 1216 /* op_no/src must be a read-only operand, and 1217 match_operand/dst must be a write-only operand. */ 1218 if (match.use[op_no] != READ 1219 || match.use[match_no] != WRITE) 1220 continue; 1221 1222 if (match.early_clobber[match_no] 1223 && count_occurrences (PATTERN (insn), src) > 1) 1224 continue; 1225 1226 /* Make sure match_operand is the destination. */ 1227 if (recog_operand[match_no] != SET_DEST (set)) 1228 continue; 1229 1230 /* If the operands already match, then there is nothing to do. */ 1231 /* But in the commutative case, we might find a better match. */ 1232 if (operands_match_p (src, dst) 1233 || (match.commutative[op_no] >= 0 1234 && operands_match_p (recog_operand[match.commutative 1235 [op_no]], dst) 1236 && (replacement_quality (recog_operand[match.commutative 1237 [op_no]]) 1238 >= replacement_quality (src)))) 1239 continue; 1240 1241 src_class = reg_preferred_class (REGNO (src)); 1242 dst_class = reg_preferred_class (REGNO (dst)); 1243 if (! regclass_compatible_p (src_class, dst_class)) 1244 continue; 1245 1246 if (fixup_match_1 (insn, set, src, src_subreg, dst, pass, 1247 op_no, match_no, 1248 regmove_dump_file)) 1249 break; 1250 } 1251 } 1252 } 1253 1254 /* A backward pass. Replace input operands with output operands. */ 1255 1256 if (regmove_dump_file) 1257 fprintf (regmove_dump_file, "Starting backward pass...\n"); 1258 1259 loop_depth = 1; 1260 1261 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) 1262 { 1263 if (GET_CODE (insn) == NOTE) 1264 { 1265 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END) 1266 loop_depth++; 1267 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG) 1268 loop_depth--; 1269 } 1270 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 1271 { 1272 int op_no, match_no; 1273 int success = 0; 1274 1275 if (! find_matches (insn, &match)) 1276 continue; 1277 1278 /* Now scan through the operands looking for a destination operand 1279 which is supposed to match a source operand. 1280 Then scan backward for an instruction which sets the source 1281 operand. If safe, then replace the source operand with the 1282 dest operand in both instructions. */ 1283 1284 copy_src = NULL_RTX; 1285 copy_dst = NULL_RTX; 1286 for (op_no = 0; op_no < recog_n_operands; op_no++) 1287 { 1288 rtx set, p, src, dst; 1289 rtx src_note, dst_note; 1290 int num_calls = 0; 1291 enum reg_class src_class, dst_class; 1292 int length; 1293 1294 match_no = match.with[op_no]; 1295 1296 /* Nothing to do if the two operands aren't supposed to match. */ 1297 if (match_no < 0) 1298 continue; 1299 1300 dst = recog_operand[match_no]; 1301 src = recog_operand[op_no]; 1302 1303 if (GET_CODE (src) != REG) 1304 continue; 1305 1306 if (GET_CODE (dst) != REG 1307 || REGNO (dst) < FIRST_PSEUDO_REGISTER 1308 || REG_LIVE_LENGTH (REGNO (dst)) < 0) 1309 continue; 1310 1311 /* If the operands already match, then there is nothing to do. */ 1312 if (operands_match_p (src, dst) 1313 || (match.commutative[op_no] >= 0 1314 && operands_match_p (recog_operand[match.commutative[op_no]], dst))) 1315 continue; 1316 1317 set = single_set (insn); 1318 if (! set) 1319 continue; 1320 1321 /* match_no/dst must be a write-only operand, and 1322 operand_operand/src must be a read-only operand. */ 1323 if (match.use[op_no] != READ 1324 || match.use[match_no] != WRITE) 1325 continue; 1326 1327 if (match.early_clobber[match_no] 1328 && count_occurrences (PATTERN (insn), src) > 1) 1329 continue; 1330 1331 /* Make sure match_no is the destination. */ 1332 if (recog_operand[match_no] != SET_DEST (set)) 1333 continue; 1334 1335 if (REGNO (src) < FIRST_PSEUDO_REGISTER) 1336 { 1337 if (GET_CODE (SET_SRC (set)) == PLUS 1338 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT 1339 && XEXP (SET_SRC (set), 0) == src 1340 && fixup_match_2 (insn, dst, src, 1341 XEXP (SET_SRC (set), 1), 1342 regmove_dump_file)) 1343 break; 1344 continue; 1345 } 1346 src_class = reg_preferred_class (REGNO (src)); 1347 dst_class = reg_preferred_class (REGNO (dst)); 1348 if (! regclass_compatible_p (src_class, dst_class)) 1349 { 1350 if (!copy_src) 1351 { 1352 copy_src = src; 1353 copy_dst = dst; 1354 } 1355 continue; 1356 } 1357 1358 /* Can not modify an earlier insn to set dst if this insn 1359 uses an old value in the source. */ 1360 if (reg_overlap_mentioned_p (dst, SET_SRC (set))) 1361 { 1362 if (!copy_src) 1363 { 1364 copy_src = src; 1365 copy_dst = dst; 1366 } 1367 continue; 1368 } 1369 1370 if (! (src_note = find_reg_note (insn, REG_DEAD, src))) 1371 { 1372 if (!copy_src) 1373 { 1374 copy_src = src; 1375 copy_dst = dst; 1376 } 1377 continue; 1378 } 1379 1380 1381 /* If src is set once in a different basic block, 1382 and is set equal to a constant, then do not use 1383 it for this optimization, as this would make it 1384 no longer equivalent to a constant. */ 1385 1386 if (reg_is_remote_constant_p (src, insn, f)) 1387 { 1388 if (!copy_src) 1389 { 1390 copy_src = src; 1391 copy_dst = dst; 1392 } 1393 continue; 1394 } 1395 1396 1397 if (regmove_dump_file) 1398 fprintf (regmove_dump_file, 1399 "Could fix operand %d of insn %d matching operand %d.\n", 1400 op_no, INSN_UID (insn), match_no); 1401 1402 /* Scan backward to find the first instruction that uses 1403 the input operand. If the operand is set here, then 1404 replace it in both instructions with match_no. */ 1405 1406 for (length = 0, p = PREV_INSN (insn); p; p = PREV_INSN (p)) 1407 { 1408 rtx pset; 1409 1410 if (GET_CODE (p) == CODE_LABEL 1411 || GET_CODE (p) == JUMP_INSN 1412 || (GET_CODE (p) == NOTE 1413 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG 1414 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) 1415 break; 1416 1417 /* ??? We can't scan past the end of a basic block without 1418 updating the register lifetime info 1419 (REG_DEAD/basic_block_live_at_start). 1420 A CALL_INSN might be the last insn of a basic block, if 1421 it is inside an EH region. There is no easy way to tell, 1422 so we just always break when we see a CALL_INSN if 1423 flag_exceptions is nonzero. */ 1424 if (flag_exceptions && GET_CODE (p) == CALL_INSN) 1425 break; 1426 1427 if (GET_RTX_CLASS (GET_CODE (p)) != 'i') 1428 continue; 1429 1430 length++; 1431 1432 /* ??? See if all of SRC is set in P. This test is much 1433 more conservative than it needs to be. */ 1434 pset = single_set (p); 1435 if (pset && SET_DEST (pset) == src) 1436 { 1437 /* We use validate_replace_rtx, in case there 1438 are multiple identical source operands. All of 1439 them have to be changed at the same time. */ 1440 if (validate_replace_rtx (src, dst, insn)) 1441 { 1442 if (validate_change (p, &SET_DEST (pset), 1443 dst, 0)) 1444 success = 1; 1445 else 1446 { 1447 /* Change all source operands back. 1448 This modifies the dst as a side-effect. */ 1449 validate_replace_rtx (dst, src, insn); 1450 /* Now make sure the dst is right. */ 1451 validate_change (insn, 1452 recog_operand_loc[match_no], 1453 dst, 0); 1454 } 1455 } 1456 break; 1457 } 1458 1459 if (reg_overlap_mentioned_p (src, PATTERN (p)) 1460 || reg_overlap_mentioned_p (dst, PATTERN (p))) 1461 break; 1462 1463 /* If we have passed a call instruction, and the 1464 pseudo-reg DST is not already live across a call, 1465 then don't perform the optimization. */ 1466 if (GET_CODE (p) == CALL_INSN) 1467 { 1468 num_calls++; 1469 1470 if (REG_N_CALLS_CROSSED (REGNO (dst)) == 0) 1471 break; 1472 } 1473 } 1474 1475 if (success) 1476 { 1477 int dstno, srcno; 1478 1479 /* Remove the death note for SRC from INSN. */ 1480 remove_note (insn, src_note); 1481 /* Move the death note for SRC to P if it is used 1482 there. */ 1483 if (reg_overlap_mentioned_p (src, PATTERN (p))) 1484 { 1485 XEXP (src_note, 1) = REG_NOTES (p); 1486 REG_NOTES (p) = src_note; 1487 } 1488 /* If there is a REG_DEAD note for DST on P, then remove 1489 it, because DST is now set there. */ 1490 if ((dst_note = find_reg_note (p, REG_DEAD, dst))) 1491 remove_note (p, dst_note); 1492 1493 dstno = REGNO (dst); 1494 srcno = REGNO (src); 1495 1496 REG_N_SETS (dstno)++; 1497 REG_N_SETS (srcno)--; 1498 1499 REG_N_CALLS_CROSSED (dstno) += num_calls; 1500 REG_N_CALLS_CROSSED (srcno) -= num_calls; 1501 1502 REG_LIVE_LENGTH (dstno) += length; 1503 if (REG_LIVE_LENGTH (srcno) >= 0) 1504 { 1505 REG_LIVE_LENGTH (srcno) -= length; 1506 /* REG_LIVE_LENGTH is only an approximation after 1507 combine if sched is not run, so make sure that we 1508 still have a reasonable value. */ 1509 if (REG_LIVE_LENGTH (srcno) < 2) 1510 REG_LIVE_LENGTH (srcno) = 2; 1511 } 1512 1513 /* We assume that a register is used exactly once per 1514 insn in the updates above. If this is not correct, 1515 no great harm is done. */ 1516 1517 REG_N_REFS (dstno) += 2 * loop_depth; 1518 REG_N_REFS (srcno) -= 2 * loop_depth; 1519 1520 /* If that was the only time src was set, 1521 and src was not live at the start of the 1522 function, we know that we have no more 1523 references to src; clear REG_N_REFS so it 1524 won't make reload do any work. */ 1525 if (REG_N_SETS (REGNO (src)) == 0 1526 && ! regno_uninitialized (REGNO (src))) 1527 REG_N_REFS (REGNO (src)) = 0; 1528 1529 if (regmove_dump_file) 1530 fprintf (regmove_dump_file, 1531 "Fixed operand %d of insn %d matching operand %d.\n", 1532 op_no, INSN_UID (insn), match_no); 1533 1534 break; 1535 } 1536 } 1537 1538 /* If we weren't able to replace any of the alternatives, try an 1539 alternative appoach of copying the source to the destination. */ 1540 if (!success && copy_src != NULL_RTX) 1541 copy_src_to_dest (insn, copy_src, copy_dst, loop_depth, 1542 old_max_uid); 1543 1544 } 1545 } 1546#endif /* REGISTER_CONSTRAINTS */ 1547 1548 /* In fixup_match_1, some insns may have been inserted after basic block 1549 ends. Fix that here. */ 1550 for (i = 0; i < n_basic_blocks; i++) 1551 { 1552 rtx end = BLOCK_END (i); 1553 rtx new = end; 1554 rtx next = NEXT_INSN (new); 1555 while (next != 0 && INSN_UID (next) >= old_max_uid 1556 && (i == n_basic_blocks - 1 || BLOCK_HEAD (i + 1) != next)) 1557 new = next, next = NEXT_INSN (new); 1558 BLOCK_END (i) = new; 1559 } 1560} 1561 1562/* Returns nonzero if INSN's pattern has matching constraints for any operand. 1563 Returns 0 if INSN can't be recognized, or if the alternative can't be 1564 determined. 1565 1566 Initialize the info in MATCHP based on the constraints. */ 1567 1568static int 1569find_matches (insn, matchp) 1570 rtx insn; 1571 struct match *matchp; 1572{ 1573 int likely_spilled[MAX_RECOG_OPERANDS]; 1574 int op_no; 1575 int any_matches = 0; 1576 1577 extract_insn (insn); 1578 if (! constrain_operands (0)) 1579 return 0; 1580 1581 /* Must initialize this before main loop, because the code for 1582 the commutative case may set matches for operands other than 1583 the current one. */ 1584 for (op_no = recog_n_operands; --op_no >= 0; ) 1585 matchp->with[op_no] = matchp->commutative[op_no] = -1; 1586 1587 for (op_no = 0; op_no < recog_n_operands; op_no++) 1588 { 1589 const char *p; 1590 char c; 1591 int i = 0; 1592 1593 p = recog_constraints[op_no]; 1594 1595 likely_spilled[op_no] = 0; 1596 matchp->use[op_no] = READ; 1597 matchp->early_clobber[op_no] = 0; 1598 if (*p == '=') 1599 matchp->use[op_no] = WRITE; 1600 else if (*p == '+') 1601 matchp->use[op_no] = READWRITE; 1602 1603 for (;*p && i < which_alternative; p++) 1604 if (*p == ',') 1605 i++; 1606 1607 while ((c = *p++) != '\0' && c != ',') 1608 switch (c) 1609 { 1610 case '=': 1611 break; 1612 case '+': 1613 break; 1614 case '&': 1615 matchp->early_clobber[op_no] = 1; 1616 break; 1617 case '%': 1618 matchp->commutative[op_no] = op_no + 1; 1619 matchp->commutative[op_no + 1] = op_no; 1620 break; 1621 case '0': case '1': case '2': case '3': case '4': 1622 case '5': case '6': case '7': case '8': case '9': 1623 c -= '0'; 1624 if (c < op_no && likely_spilled[(unsigned char) c]) 1625 break; 1626 matchp->with[op_no] = c; 1627 any_matches = 1; 1628 if (matchp->commutative[op_no] >= 0) 1629 matchp->with[matchp->commutative[op_no]] = c; 1630 break; 1631 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': case 'h': 1632 case 'j': case 'k': case 'l': case 'p': case 'q': case 't': case 'u': 1633 case 'v': case 'w': case 'x': case 'y': case 'z': case 'A': case 'B': 1634 case 'C': case 'D': case 'W': case 'Y': case 'Z': 1635 if (CLASS_LIKELY_SPILLED_P (REG_CLASS_FROM_LETTER ((unsigned char)c))) 1636 likely_spilled[op_no] = 1; 1637 break; 1638 } 1639 } 1640 return any_matches; 1641} 1642 1643/* Try to replace output operand DST in SET, with input operand SRC. SET is 1644 the only set in INSN. INSN has just been recgnized and constrained. 1645 SRC is operand number OPERAND_NUMBER in INSN. 1646 DST is operand number MATCH_NUMBER in INSN. 1647 If BACKWARD is nonzero, we have been called in a backward pass. 1648 Return nonzero for success. */ 1649static int 1650fixup_match_1 (insn, set, src, src_subreg, dst, backward, operand_number, 1651 match_number, regmove_dump_file) 1652 rtx insn, set, src, src_subreg, dst; 1653 int backward, operand_number, match_number; 1654 FILE *regmove_dump_file; 1655{ 1656 rtx p; 1657 rtx post_inc = 0, post_inc_set = 0, search_end = 0; 1658 int success = 0; 1659 int num_calls = 0, s_num_calls = 0; 1660 enum rtx_code code = NOTE; 1661 HOST_WIDE_INT insn_const, newconst; 1662 rtx overlap = 0; /* need to move insn ? */ 1663 rtx src_note = find_reg_note (insn, REG_DEAD, src), dst_note; 1664 int length, s_length, true_loop_depth; 1665 1666 /* If SRC is marked as unchanging, we may not change it. 1667 ??? Maybe we could get better code by removing the unchanging bit 1668 instead, and changing it back if we don't succeed? */ 1669 if (RTX_UNCHANGING_P (src)) 1670 return 0; 1671 1672 if (! src_note) 1673 { 1674 /* Look for (set (regX) (op regA constX)) 1675 (set (regY) (op regA constY)) 1676 and change that to 1677 (set (regA) (op regA constX)). 1678 (set (regY) (op regA constY-constX)). 1679 This works for add and shift operations, if 1680 regA is dead after or set by the second insn. */ 1681 1682 code = GET_CODE (SET_SRC (set)); 1683 if ((code == PLUS || code == LSHIFTRT 1684 || code == ASHIFT || code == ASHIFTRT) 1685 && XEXP (SET_SRC (set), 0) == src 1686 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) 1687 insn_const = INTVAL (XEXP (SET_SRC (set), 1)); 1688 else if (! stable_and_no_regs_but_for_p (SET_SRC (set), src, dst)) 1689 return 0; 1690 else 1691 /* We might find a src_note while scanning. */ 1692 code = NOTE; 1693 } 1694 1695 if (regmove_dump_file) 1696 fprintf (regmove_dump_file, 1697 "Could fix operand %d of insn %d matching operand %d.\n", 1698 operand_number, INSN_UID (insn), match_number); 1699 1700 /* If SRC is equivalent to a constant set in a different basic block, 1701 then do not use it for this optimization. We want the equivalence 1702 so that if we have to reload this register, we can reload the 1703 constant, rather than extending the lifespan of the register. */ 1704 if (reg_is_remote_constant_p (src, insn, get_insns ())) 1705 return 0; 1706 1707 /* Scan forward to find the next instruction that 1708 uses the output operand. If the operand dies here, 1709 then replace it in both instructions with 1710 operand_number. */ 1711 1712 for (length = s_length = 0, p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) 1713 { 1714 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN 1715 || (GET_CODE (p) == NOTE 1716 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG 1717 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END))) 1718 break; 1719 1720 /* ??? We can't scan past the end of a basic block without updating 1721 the register lifetime info (REG_DEAD/basic_block_live_at_start). 1722 A CALL_INSN might be the last insn of a basic block, if it is 1723 inside an EH region. There is no easy way to tell, so we just 1724 always break when we see a CALL_INSN if flag_exceptions is nonzero. */ 1725 if (flag_exceptions && GET_CODE (p) == CALL_INSN) 1726 break; 1727 1728 if (GET_RTX_CLASS (GET_CODE (p)) != 'i') 1729 continue; 1730 1731 length++; 1732 if (src_note) 1733 s_length++; 1734 1735 if (reg_set_p (src, p) || reg_set_p (dst, p) 1736 || (GET_CODE (PATTERN (p)) == USE 1737 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) 1738 break; 1739 1740 /* See if all of DST dies in P. This test is 1741 slightly more conservative than it needs to be. */ 1742 if ((dst_note = find_regno_note (p, REG_DEAD, REGNO (dst))) 1743 && (GET_MODE (XEXP (dst_note, 0)) == GET_MODE (dst))) 1744 { 1745 if (! src_note) 1746 { 1747 rtx q; 1748 rtx set2; 1749 1750 /* If an optimization is done, the value of SRC while P 1751 is executed will be changed. Check that this is OK. */ 1752 if (reg_overlap_mentioned_p (src, PATTERN (p))) 1753 break; 1754 for (q = p; q; q = NEXT_INSN (q)) 1755 { 1756 if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN 1757 || (GET_CODE (q) == NOTE 1758 && (NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_BEG 1759 || NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_END))) 1760 { 1761 q = 0; 1762 break; 1763 } 1764 1765 /* ??? We can't scan past the end of a basic block without 1766 updating the register lifetime info 1767 (REG_DEAD/basic_block_live_at_start). 1768 A CALL_INSN might be the last insn of a basic block, if 1769 it is inside an EH region. There is no easy way to tell, 1770 so we just always break when we see a CALL_INSN if 1771 flag_exceptions is nonzero. */ 1772 if (flag_exceptions && GET_CODE (q) == CALL_INSN) 1773 { 1774 q = 0; 1775 break; 1776 } 1777 1778 if (GET_RTX_CLASS (GET_CODE (q)) != 'i') 1779 continue; 1780 if (reg_overlap_mentioned_p (src, PATTERN (q)) 1781 || reg_set_p (src, q)) 1782 break; 1783 } 1784 if (q) 1785 set2 = single_set (q); 1786 if (! q || ! set2 || GET_CODE (SET_SRC (set2)) != code 1787 || XEXP (SET_SRC (set2), 0) != src 1788 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT 1789 || (SET_DEST (set2) != src 1790 && ! find_reg_note (q, REG_DEAD, src))) 1791 { 1792 /* If this is a PLUS, we can still save a register by doing 1793 src += insn_const; 1794 P; 1795 src -= insn_const; . 1796 This also gives opportunities for subsequent 1797 optimizations in the backward pass, so do it there. */ 1798 if (code == PLUS && backward 1799 /* Don't do this if we can likely tie DST to SET_DEST 1800 of P later; we can't do this tying here if we got a 1801 hard register. */ 1802 && ! (dst_note && ! REG_N_CALLS_CROSSED (REGNO (dst)) 1803 && single_set (p) 1804 && GET_CODE (SET_DEST (single_set (p))) == REG 1805 && (REGNO (SET_DEST (single_set (p))) 1806 < FIRST_PSEUDO_REGISTER)) 1807 /* We may only emit an insn directly after P if we 1808 are not in the shadow of a live flags register. */ 1809 && GET_MODE (p) == VOIDmode) 1810 { 1811 search_end = q; 1812 q = insn; 1813 set2 = set; 1814 newconst = -insn_const; 1815 code = MINUS; 1816 } 1817 else 1818 break; 1819 } 1820 else 1821 { 1822 newconst = INTVAL (XEXP (SET_SRC (set2), 1)) - insn_const; 1823 /* Reject out of range shifts. */ 1824 if (code != PLUS 1825 && (newconst < 0 1826 || (newconst 1827 >= GET_MODE_BITSIZE (GET_MODE (SET_SRC (set2)))))) 1828 break; 1829 if (code == PLUS) 1830 { 1831 post_inc = q; 1832 if (SET_DEST (set2) != src) 1833 post_inc_set = set2; 1834 } 1835 } 1836 /* We use 1 as last argument to validate_change so that all 1837 changes are accepted or rejected together by apply_change_group 1838 when it is called by validate_replace_rtx . */ 1839 validate_change (q, &XEXP (SET_SRC (set2), 1), 1840 GEN_INT (newconst), 1); 1841 } 1842 validate_change (insn, recog_operand_loc[match_number], src, 1); 1843 if (validate_replace_rtx (dst, src_subreg, p)) 1844 success = 1; 1845 break; 1846 } 1847 1848 if (reg_overlap_mentioned_p (dst, PATTERN (p))) 1849 break; 1850 if (! src_note && reg_overlap_mentioned_p (src, PATTERN (p))) 1851 { 1852 /* INSN was already checked to be movable when 1853 we found no REG_DEAD note for src on it. */ 1854 overlap = p; 1855 src_note = find_reg_note (p, REG_DEAD, src); 1856 } 1857 1858 /* If we have passed a call instruction, and the pseudo-reg SRC is not 1859 already live across a call, then don't perform the optimization. */ 1860 if (GET_CODE (p) == CALL_INSN) 1861 { 1862 if (REG_N_CALLS_CROSSED (REGNO (src)) == 0) 1863 break; 1864 1865 num_calls++; 1866 1867 if (src_note) 1868 s_num_calls++; 1869 1870 } 1871 } 1872 1873 if (! success) 1874 return 0; 1875 1876 true_loop_depth = backward ? 2 - loop_depth : loop_depth; 1877 1878 /* Remove the death note for DST from P. */ 1879 remove_note (p, dst_note); 1880 if (code == MINUS) 1881 { 1882 post_inc = emit_insn_after (copy_rtx (PATTERN (insn)), p); 1883 if ((HAVE_PRE_INCREMENT || HAVE_PRE_DECREMENT) 1884 && search_end 1885 && try_auto_increment (search_end, post_inc, 0, src, newconst, 1)) 1886 post_inc = 0; 1887 validate_change (insn, &XEXP (SET_SRC (set), 1), GEN_INT (insn_const), 0); 1888 REG_N_SETS (REGNO (src))++; 1889 REG_N_REFS (REGNO (src)) += true_loop_depth; 1890 REG_LIVE_LENGTH (REGNO (src))++; 1891 } 1892 if (overlap) 1893 { 1894 /* The lifetime of src and dest overlap, 1895 but we can change this by moving insn. */ 1896 rtx pat = PATTERN (insn); 1897 if (src_note) 1898 remove_note (overlap, src_note); 1899 if ((HAVE_POST_INCREMENT || HAVE_POST_DECREMENT) 1900 && code == PLUS 1901 && try_auto_increment (overlap, insn, 0, src, insn_const, 0)) 1902 insn = overlap; 1903 else 1904 { 1905 rtx notes = REG_NOTES (insn); 1906 1907 emit_insn_after_with_line_notes (pat, PREV_INSN (p), insn); 1908 PUT_CODE (insn, NOTE); 1909 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 1910 NOTE_SOURCE_FILE (insn) = 0; 1911 /* emit_insn_after_with_line_notes has no 1912 return value, so search for the new insn. */ 1913 for (insn = p; PATTERN (insn) != pat; ) 1914 insn = PREV_INSN (insn); 1915 1916 REG_NOTES (insn) = notes; 1917 } 1918 } 1919 /* Sometimes we'd generate src = const; src += n; 1920 if so, replace the instruction that set src 1921 in the first place. */ 1922 1923 if (! overlap && (code == PLUS || code == MINUS)) 1924 { 1925 rtx note = find_reg_note (insn, REG_EQUAL, NULL_RTX); 1926 rtx q, set2; 1927 int num_calls2 = 0, s_length2 = 0; 1928 1929 if (note && CONSTANT_P (XEXP (note, 0))) 1930 { 1931 for (q = PREV_INSN (insn); q; q = PREV_INSN(q)) 1932 { 1933 if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN 1934 || (GET_CODE (q) == NOTE 1935 && (NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_BEG 1936 || NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_END))) 1937 { 1938 q = 0; 1939 break; 1940 } 1941 1942 /* ??? We can't scan past the end of a basic block without 1943 updating the register lifetime info 1944 (REG_DEAD/basic_block_live_at_start). 1945 A CALL_INSN might be the last insn of a basic block, if 1946 it is inside an EH region. There is no easy way to tell, 1947 so we just always break when we see a CALL_INSN if 1948 flag_exceptions is nonzero. */ 1949 if (flag_exceptions && GET_CODE (q) == CALL_INSN) 1950 { 1951 q = 0; 1952 break; 1953 } 1954 1955 if (GET_RTX_CLASS (GET_CODE (q)) != 'i') 1956 continue; 1957 s_length2++; 1958 if (reg_set_p (src, q)) 1959 { 1960 set2 = single_set (q); 1961 break; 1962 } 1963 if (reg_overlap_mentioned_p (src, PATTERN (q))) 1964 { 1965 q = 0; 1966 break; 1967 } 1968 if (GET_CODE (p) == CALL_INSN) 1969 num_calls2++; 1970 } 1971 if (q && set2 && SET_DEST (set2) == src && CONSTANT_P (SET_SRC (set2)) 1972 && validate_change (insn, &SET_SRC (set), XEXP (note, 0), 0)) 1973 { 1974 PUT_CODE (q, NOTE); 1975 NOTE_LINE_NUMBER (q) = NOTE_INSN_DELETED; 1976 NOTE_SOURCE_FILE (q) = 0; 1977 REG_N_SETS (REGNO (src))--; 1978 REG_N_CALLS_CROSSED (REGNO (src)) -= num_calls2; 1979 REG_N_REFS (REGNO (src)) -= true_loop_depth; 1980 REG_LIVE_LENGTH (REGNO (src)) -= s_length2; 1981 insn_const = 0; 1982 } 1983 } 1984 } 1985 1986 if ((HAVE_PRE_INCREMENT || HAVE_PRE_DECREMENT) 1987 && (code == PLUS || code == MINUS) && insn_const 1988 && try_auto_increment (p, insn, 0, src, insn_const, 1)) 1989 insn = p; 1990 else if ((HAVE_POST_INCREMENT || HAVE_POST_DECREMENT) 1991 && post_inc 1992 && try_auto_increment (p, post_inc, post_inc_set, src, newconst, 0)) 1993 post_inc = 0; 1994 /* If post_inc still prevails, try to find an 1995 insn where it can be used as a pre-in/decrement. 1996 If code is MINUS, this was already tried. */ 1997 if (post_inc && code == PLUS 1998 /* Check that newconst is likely to be usable 1999 in a pre-in/decrement before starting the search. */ 2000 && ((HAVE_PRE_INCREMENT && newconst > 0 && newconst <= MOVE_MAX) 2001 || (HAVE_PRE_DECREMENT && newconst < 0 && newconst >= -MOVE_MAX)) 2002 && exact_log2 (newconst)) 2003 { 2004 rtx q, inc_dest; 2005 2006 inc_dest = post_inc_set ? SET_DEST (post_inc_set) : src; 2007 for (q = post_inc; (q = NEXT_INSN (q)); ) 2008 { 2009 if (GET_CODE (q) == CODE_LABEL || GET_CODE (q) == JUMP_INSN 2010 || (GET_CODE (q) == NOTE 2011 && (NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_BEG 2012 || NOTE_LINE_NUMBER (q) == NOTE_INSN_LOOP_END))) 2013 break; 2014 2015 /* ??? We can't scan past the end of a basic block without updating 2016 the register lifetime info (REG_DEAD/basic_block_live_at_start). 2017 A CALL_INSN might be the last insn of a basic block, if it 2018 is inside an EH region. There is no easy way to tell so we 2019 just always break when we see a CALL_INSN if flag_exceptions 2020 is nonzero. */ 2021 if (flag_exceptions && GET_CODE (q) == CALL_INSN) 2022 break; 2023 2024 if (GET_RTX_CLASS (GET_CODE (q)) != 'i') 2025 continue; 2026 if (src != inc_dest && (reg_overlap_mentioned_p (src, PATTERN (q)) 2027 || reg_set_p (src, q))) 2028 break; 2029 if (reg_set_p (inc_dest, q)) 2030 break; 2031 if (reg_overlap_mentioned_p (inc_dest, PATTERN (q))) 2032 { 2033 try_auto_increment (q, post_inc, 2034 post_inc_set, inc_dest, newconst, 1); 2035 break; 2036 } 2037 } 2038 } 2039 /* Move the death note for DST to INSN if it is used 2040 there. */ 2041 if (reg_overlap_mentioned_p (dst, PATTERN (insn))) 2042 { 2043 XEXP (dst_note, 1) = REG_NOTES (insn); 2044 REG_NOTES (insn) = dst_note; 2045 } 2046 2047 if (src_note) 2048 { 2049 /* Move the death note for SRC from INSN to P. */ 2050 if (! overlap) 2051 remove_note (insn, src_note); 2052 XEXP (src_note, 1) = REG_NOTES (p); 2053 REG_NOTES (p) = src_note; 2054 2055 REG_N_CALLS_CROSSED (REGNO (src)) += s_num_calls; 2056 } 2057 2058 REG_N_SETS (REGNO (src))++; 2059 REG_N_SETS (REGNO (dst))--; 2060 2061 REG_N_CALLS_CROSSED (REGNO (dst)) -= num_calls; 2062 2063 REG_LIVE_LENGTH (REGNO (src)) += s_length; 2064 if (REG_LIVE_LENGTH (REGNO (dst)) >= 0) 2065 { 2066 REG_LIVE_LENGTH (REGNO (dst)) -= length; 2067 /* REG_LIVE_LENGTH is only an approximation after 2068 combine if sched is not run, so make sure that we 2069 still have a reasonable value. */ 2070 if (REG_LIVE_LENGTH (REGNO (dst)) < 2) 2071 REG_LIVE_LENGTH (REGNO (dst)) = 2; 2072 } 2073 2074 /* We assume that a register is used exactly once per 2075 insn in the updates above. If this is not correct, 2076 no great harm is done. */ 2077 2078 REG_N_REFS (REGNO (src)) += 2 * true_loop_depth; 2079 REG_N_REFS (REGNO (dst)) -= 2 * true_loop_depth; 2080 2081 /* If that was the only time dst was set, 2082 and dst was not live at the start of the 2083 function, we know that we have no more 2084 references to dst; clear REG_N_REFS so it 2085 won't make reload do any work. */ 2086 if (REG_N_SETS (REGNO (dst)) == 0 2087 && ! regno_uninitialized (REGNO (dst))) 2088 REG_N_REFS (REGNO (dst)) = 0; 2089 2090 if (regmove_dump_file) 2091 fprintf (regmove_dump_file, 2092 "Fixed operand %d of insn %d matching operand %d.\n", 2093 operand_number, INSN_UID (insn), match_number); 2094 return 1; 2095} 2096 2097 2098/* return nonzero if X is stable and mentions no regsiters but for 2099 mentioning SRC or mentioning / changing DST . If in doubt, presume 2100 it is unstable. 2101 The rationale is that we want to check if we can move an insn easily 2102 while just paying attention to SRC and DST. A register is considered 2103 stable if it has the RTX_UNCHANGING_P bit set, but that would still 2104 leave the burden to update REG_DEAD / REG_UNUSED notes, so we don't 2105 want any registers but SRC and DST. */ 2106static int 2107stable_and_no_regs_but_for_p (x, src, dst) 2108 rtx x, src, dst; 2109{ 2110 RTX_CODE code = GET_CODE (x); 2111 switch (GET_RTX_CLASS (code)) 2112 { 2113 case '<': case '1': case 'c': case '2': case 'b': case '3': 2114 { 2115 int i; 2116 char *fmt = GET_RTX_FORMAT (code); 2117 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2118 if (fmt[i] == 'e' 2119 && ! stable_and_no_regs_but_for_p (XEXP (x, i), src, dst)) 2120 return 0; 2121 return 1; 2122 } 2123 case 'o': 2124 if (code == REG) 2125 return x == src || x == dst; 2126 /* If this is a MEM, look inside - there might be a register hidden in 2127 the address of an unchanging MEM. */ 2128 if (code == MEM 2129 && ! stable_and_no_regs_but_for_p (XEXP (x, 0), src, dst)) 2130 return 0; 2131 /* fall through */ 2132 default: 2133 return ! rtx_unstable_p (x); 2134 } 2135} 2136 2137/* Test if regmove seems profitable for this target. Regmove is useful only 2138 if some common patterns are two address, i.e. require matching constraints, 2139 so we check that condition here. */ 2140 2141int 2142regmove_profitable_p () 2143{ 2144#ifdef REGISTER_CONSTRAINTS 2145 struct match match; 2146 enum machine_mode mode; 2147 optab tstoptab = add_optab; 2148 do /* check add_optab and ashl_optab */ 2149 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode; 2150 mode = GET_MODE_WIDER_MODE (mode)) 2151 { 2152 int icode = (int) tstoptab->handlers[(int) mode].insn_code; 2153 rtx reg0, reg1, reg2, pat; 2154 int i; 2155 2156 if (GET_MODE_BITSIZE (mode) < 32 || icode == CODE_FOR_nothing) 2157 continue; 2158 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 2159 if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i)) 2160 break; 2161 if (i + 2 >= FIRST_PSEUDO_REGISTER) 2162 break; 2163 reg0 = gen_rtx_REG (insn_operand_mode[icode][0], i); 2164 reg1 = gen_rtx_REG (insn_operand_mode[icode][1], i + 1); 2165 reg2 = gen_rtx_REG (insn_operand_mode[icode][2], i + 2); 2166 if (! (*insn_operand_predicate[icode][0]) (reg0, VOIDmode) 2167 || ! (*insn_operand_predicate[icode][1]) (reg1, VOIDmode) 2168 || ! (*insn_operand_predicate[icode][2]) (reg2, VOIDmode)) 2169 break; 2170 pat = GEN_FCN (icode) (reg0, reg1, reg2); 2171 if (! pat) 2172 continue; 2173 if (GET_CODE (pat) == SEQUENCE) 2174 pat = XVECEXP (pat, 0, XVECLEN (pat, 0) - 1); 2175 else 2176 pat = make_insn_raw (pat); 2177 if (! single_set (pat) 2178 || GET_CODE (SET_SRC (single_set (pat))) != tstoptab->code) 2179 /* Unexpected complexity; don't need to handle this unless 2180 we find a machine where this occurs and regmove should 2181 be enabled. */ 2182 break; 2183 if (find_matches (pat, &match)) 2184 return 1; 2185 break; 2186 } 2187 while (tstoptab != ashl_optab && (tstoptab = ashl_optab, 1)); 2188#endif /* REGISTER_CONSTRAINTS */ 2189 return 0; 2190} 2191