md.texi revision 119256
1@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001, 2@c 2002, 2003 Free Software Foundation, Inc. 3@c This is part of the GCC manual. 4@c For copying conditions, see the file gcc.texi. 5 6@ifset INTERNALS 7@node Machine Desc 8@chapter Machine Descriptions 9@cindex machine descriptions 10 11A machine description has two parts: a file of instruction patterns 12(@file{.md} file) and a C header file of macro definitions. 13 14The @file{.md} file for a target machine contains a pattern for each 15instruction that the target machine supports (or at least each instruction 16that is worth telling the compiler about). It may also contain comments. 17A semicolon causes the rest of the line to be a comment, unless the semicolon 18is inside a quoted string. 19 20See the next chapter for information on the C header file. 21 22@menu 23* Overview:: How the machine description is used. 24* Patterns:: How to write instruction patterns. 25* Example:: An explained example of a @code{define_insn} pattern. 26* RTL Template:: The RTL template defines what insns match a pattern. 27* Output Template:: The output template says how to make assembler code 28 from such an insn. 29* Output Statement:: For more generality, write C code to output 30 the assembler code. 31* Constraints:: When not all operands are general operands. 32* Standard Names:: Names mark patterns to use for code generation. 33* Pattern Ordering:: When the order of patterns makes a difference. 34* Dependent Patterns:: Having one pattern may make you need another. 35* Jump Patterns:: Special considerations for patterns for jump insns. 36* Looping Patterns:: How to define patterns for special looping insns. 37* Insn Canonicalizations::Canonicalization of Instructions 38* Expander Definitions::Generating a sequence of several RTL insns 39 for a standard operation. 40* Insn Splitting:: Splitting Instructions into Multiple Instructions. 41* Including Patterns:: Including Patterns in Machine Descriptions. 42* Peephole Definitions::Defining machine-specific peephole optimizations. 43* Insn Attributes:: Specifying the value of attributes for generated insns. 44* Conditional Execution::Generating @code{define_insn} patterns for 45 predication. 46* Constant Definitions::Defining symbolic constants that can be used in the 47 md file. 48@end menu 49 50@node Overview 51@section Overview of How the Machine Description is Used 52 53There are three main conversions that happen in the compiler: 54 55@enumerate 56 57@item 58The front end reads the source code and builds a parse tree. 59 60@item 61The parse tree is used to generate an RTL insn list based on named 62instruction patterns. 63 64@item 65The insn list is matched against the RTL templates to produce assembler 66code. 67 68@end enumerate 69 70For the generate pass, only the names of the insns matter, from either a 71named @code{define_insn} or a @code{define_expand}. The compiler will 72choose the pattern with the right name and apply the operands according 73to the documentation later in this chapter, without regard for the RTL 74template or operand constraints. Note that the names the compiler looks 75for are hard-coded in the compiler---it will ignore unnamed patterns and 76patterns with names it doesn't know about, but if you don't provide a 77named pattern it needs, it will abort. 78 79If a @code{define_insn} is used, the template given is inserted into the 80insn list. If a @code{define_expand} is used, one of three things 81happens, based on the condition logic. The condition logic may manually 82create new insns for the insn list, say via @code{emit_insn()}, and 83invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the 84compiler to use an alternate way of performing that task. If it invokes 85neither @code{DONE} nor @code{FAIL}, the template given in the pattern 86is inserted, as if the @code{define_expand} were a @code{define_insn}. 87 88Once the insn list is generated, various optimization passes convert, 89replace, and rearrange the insns in the insn list. This is where the 90@code{define_split} and @code{define_peephole} patterns get used, for 91example. 92 93Finally, the insn list's RTL is matched up with the RTL templates in the 94@code{define_insn} patterns, and those patterns are used to emit the 95final assembly code. For this purpose, each named @code{define_insn} 96acts like it's unnamed, since the names are ignored. 97 98@node Patterns 99@section Everything about Instruction Patterns 100@cindex patterns 101@cindex instruction patterns 102 103@findex define_insn 104Each instruction pattern contains an incomplete RTL expression, with pieces 105to be filled in later, operand constraints that restrict how the pieces can 106be filled in, and an output pattern or C code to generate the assembler 107output, all wrapped up in a @code{define_insn} expression. 108 109A @code{define_insn} is an RTL expression containing four or five operands: 110 111@enumerate 112@item 113An optional name. The presence of a name indicate that this instruction 114pattern can perform a certain standard job for the RTL-generation 115pass of the compiler. This pass knows certain names and will use 116the instruction patterns with those names, if the names are defined 117in the machine description. 118 119The absence of a name is indicated by writing an empty string 120where the name should go. Nameless instruction patterns are never 121used for generating RTL code, but they may permit several simpler insns 122to be combined later on. 123 124Names that are not thus known and used in RTL-generation have no 125effect; they are equivalent to no name at all. 126 127For the purpose of debugging the compiler, you may also specify a 128name beginning with the @samp{*} character. Such a name is used only 129for identifying the instruction in RTL dumps; it is entirely equivalent 130to having a nameless pattern for all other purposes. 131 132@item 133The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete 134RTL expressions which show what the instruction should look like. It is 135incomplete because it may contain @code{match_operand}, 136@code{match_operator}, and @code{match_dup} expressions that stand for 137operands of the instruction. 138 139If the vector has only one element, that element is the template for the 140instruction pattern. If the vector has multiple elements, then the 141instruction pattern is a @code{parallel} expression containing the 142elements described. 143 144@item 145@cindex pattern conditions 146@cindex conditions, in patterns 147A condition. This is a string which contains a C expression that is 148the final test to decide whether an insn body matches this pattern. 149 150@cindex named patterns and conditions 151For a named pattern, the condition (if present) may not depend on 152the data in the insn being matched, but only the target-machine-type 153flags. The compiler needs to test these conditions during 154initialization in order to learn exactly which named instructions are 155available in a particular run. 156 157@findex operands 158For nameless patterns, the condition is applied only when matching an 159individual insn, and only after the insn has matched the pattern's 160recognition template. The insn's operands may be found in the vector 161@code{operands}. For an insn where the condition has once matched, it 162can't be used to control register allocation, for example by excluding 163certain hard registers or hard register combinations. 164 165@item 166The @dfn{output template}: a string that says how to output matching 167insns as assembler code. @samp{%} in this string specifies where 168to substitute the value of an operand. @xref{Output Template}. 169 170When simple substitution isn't general enough, you can specify a piece 171of C code to compute the output. @xref{Output Statement}. 172 173@item 174Optionally, a vector containing the values of attributes for insns matching 175this pattern. @xref{Insn Attributes}. 176@end enumerate 177 178@node Example 179@section Example of @code{define_insn} 180@cindex @code{define_insn} example 181 182Here is an actual example of an instruction pattern, for the 68000/68020. 183 184@example 185(define_insn "tstsi" 186 [(set (cc0) 187 (match_operand:SI 0 "general_operand" "rm"))] 188 "" 189 "* 190@{ 191 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) 192 return \"tstl %0\"; 193 return \"cmpl #0,%0\"; 194@}") 195@end example 196 197@noindent 198This can also be written using braced strings: 199 200@example 201(define_insn "tstsi" 202 [(set (cc0) 203 (match_operand:SI 0 "general_operand" "rm"))] 204 "" 205@{ 206 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) 207 return "tstl %0"; 208 return "cmpl #0,%0"; 209@}) 210@end example 211 212This is an instruction that sets the condition codes based on the value of 213a general operand. It has no condition, so any insn whose RTL description 214has the form shown may be handled according to this pattern. The name 215@samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation 216pass that, when it is necessary to test such a value, an insn to do so 217can be constructed using this pattern. 218 219The output control string is a piece of C code which chooses which 220output template to return based on the kind of operand and the specific 221type of CPU for which code is being generated. 222 223@samp{"rm"} is an operand constraint. Its meaning is explained below. 224 225@node RTL Template 226@section RTL Template 227@cindex RTL insn template 228@cindex generating insns 229@cindex insns, generating 230@cindex recognizing insns 231@cindex insns, recognizing 232 233The RTL template is used to define which insns match the particular pattern 234and how to find their operands. For named patterns, the RTL template also 235says how to construct an insn from specified operands. 236 237Construction involves substituting specified operands into a copy of the 238template. Matching involves determining the values that serve as the 239operands in the insn being matched. Both of these activities are 240controlled by special expression types that direct matching and 241substitution of the operands. 242 243@table @code 244@findex match_operand 245@item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint}) 246This expression is a placeholder for operand number @var{n} of 247the insn. When constructing an insn, operand number @var{n} 248will be substituted at this point. When matching an insn, whatever 249appears at this position in the insn will be taken as operand 250number @var{n}; but it must satisfy @var{predicate} or this instruction 251pattern will not match at all. 252 253Operand numbers must be chosen consecutively counting from zero in 254each instruction pattern. There may be only one @code{match_operand} 255expression in the pattern for each operand number. Usually operands 256are numbered in the order of appearance in @code{match_operand} 257expressions. In the case of a @code{define_expand}, any operand numbers 258used only in @code{match_dup} expressions have higher values than all 259other operand numbers. 260 261@var{predicate} is a string that is the name of a C function that accepts two 262arguments, an expression and a machine mode. During matching, the 263function will be called with the putative operand as the expression and 264@var{m} as the mode argument (if @var{m} is not specified, 265@code{VOIDmode} will be used, which normally causes @var{predicate} to accept 266any mode). If it returns zero, this instruction pattern fails to match. 267@var{predicate} may be an empty string; then it means no test is to be done 268on the operand, so anything which occurs in this position is valid. 269 270Most of the time, @var{predicate} will reject modes other than @var{m}---but 271not always. For example, the predicate @code{address_operand} uses 272@var{m} as the mode of memory ref that the address should be valid for. 273Many predicates accept @code{const_int} nodes even though their mode is 274@code{VOIDmode}. 275 276@var{constraint} controls reloading and the choice of the best register 277class to use for a value, as explained later (@pxref{Constraints}). 278 279People are often unclear on the difference between the constraint and the 280predicate. The predicate helps decide whether a given insn matches the 281pattern. The constraint plays no role in this decision; instead, it 282controls various decisions in the case of an insn which does match. 283 284@findex general_operand 285On CISC machines, the most common @var{predicate} is 286@code{"general_operand"}. This function checks that the putative 287operand is either a constant, a register or a memory reference, and that 288it is valid for mode @var{m}. 289 290@findex register_operand 291For an operand that must be a register, @var{predicate} should be 292@code{"register_operand"}. Using @code{"general_operand"} would be 293valid, since the reload pass would copy any non-register operands 294through registers, but this would make GCC do extra work, it would 295prevent invariant operands (such as constant) from being removed from 296loops, and it would prevent the register allocator from doing the best 297possible job. On RISC machines, it is usually most efficient to allow 298@var{predicate} to accept only objects that the constraints allow. 299 300@findex immediate_operand 301For an operand that must be a constant, you must be sure to either use 302@code{"immediate_operand"} for @var{predicate}, or make the instruction 303pattern's extra condition require a constant, or both. You cannot 304expect the constraints to do this work! If the constraints allow only 305constants, but the predicate allows something else, the compiler will 306crash when that case arises. 307 308@findex match_scratch 309@item (match_scratch:@var{m} @var{n} @var{constraint}) 310This expression is also a placeholder for operand number @var{n} 311and indicates that operand must be a @code{scratch} or @code{reg} 312expression. 313 314When matching patterns, this is equivalent to 315 316@smallexample 317(match_operand:@var{m} @var{n} "scratch_operand" @var{pred}) 318@end smallexample 319 320but, when generating RTL, it produces a (@code{scratch}:@var{m}) 321expression. 322 323If the last few expressions in a @code{parallel} are @code{clobber} 324expressions whose operands are either a hard register or 325@code{match_scratch}, the combiner can add or delete them when 326necessary. @xref{Side Effects}. 327 328@findex match_dup 329@item (match_dup @var{n}) 330This expression is also a placeholder for operand number @var{n}. 331It is used when the operand needs to appear more than once in the 332insn. 333 334In construction, @code{match_dup} acts just like @code{match_operand}: 335the operand is substituted into the insn being constructed. But in 336matching, @code{match_dup} behaves differently. It assumes that operand 337number @var{n} has already been determined by a @code{match_operand} 338appearing earlier in the recognition template, and it matches only an 339identical-looking expression. 340 341Note that @code{match_dup} should not be used to tell the compiler that 342a particular register is being used for two operands (example: 343@code{add} that adds one register to another; the second register is 344both an input operand and the output operand). Use a matching 345constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one 346operand is used in two places in the template, such as an instruction 347that computes both a quotient and a remainder, where the opcode takes 348two input operands but the RTL template has to refer to each of those 349twice; once for the quotient pattern and once for the remainder pattern. 350 351@findex match_operator 352@item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}]) 353This pattern is a kind of placeholder for a variable RTL expression 354code. 355 356When constructing an insn, it stands for an RTL expression whose 357expression code is taken from that of operand @var{n}, and whose 358operands are constructed from the patterns @var{operands}. 359 360When matching an expression, it matches an expression if the function 361@var{predicate} returns nonzero on that expression @emph{and} the 362patterns @var{operands} match the operands of the expression. 363 364Suppose that the function @code{commutative_operator} is defined as 365follows, to match any expression whose operator is one of the 366commutative arithmetic operators of RTL and whose mode is @var{mode}: 367 368@smallexample 369int 370commutative_operator (x, mode) 371 rtx x; 372 enum machine_mode mode; 373@{ 374 enum rtx_code code = GET_CODE (x); 375 if (GET_MODE (x) != mode) 376 return 0; 377 return (GET_RTX_CLASS (code) == 'c' 378 || code == EQ || code == NE); 379@} 380@end smallexample 381 382Then the following pattern will match any RTL expression consisting 383of a commutative operator applied to two general operands: 384 385@smallexample 386(match_operator:SI 3 "commutative_operator" 387 [(match_operand:SI 1 "general_operand" "g") 388 (match_operand:SI 2 "general_operand" "g")]) 389@end smallexample 390 391Here the vector @code{[@var{operands}@dots{}]} contains two patterns 392because the expressions to be matched all contain two operands. 393 394When this pattern does match, the two operands of the commutative 395operator are recorded as operands 1 and 2 of the insn. (This is done 396by the two instances of @code{match_operand}.) Operand 3 of the insn 397will be the entire commutative expression: use @code{GET_CODE 398(operands[3])} to see which commutative operator was used. 399 400The machine mode @var{m} of @code{match_operator} works like that of 401@code{match_operand}: it is passed as the second argument to the 402predicate function, and that function is solely responsible for 403deciding whether the expression to be matched ``has'' that mode. 404 405When constructing an insn, argument 3 of the gen-function will specify 406the operation (i.e.@: the expression code) for the expression to be 407made. It should be an RTL expression, whose expression code is copied 408into a new expression whose operands are arguments 1 and 2 of the 409gen-function. The subexpressions of argument 3 are not used; 410only its expression code matters. 411 412When @code{match_operator} is used in a pattern for matching an insn, 413it usually best if the operand number of the @code{match_operator} 414is higher than that of the actual operands of the insn. This improves 415register allocation because the register allocator often looks at 416operands 1 and 2 of insns to see if it can do register tying. 417 418There is no way to specify constraints in @code{match_operator}. The 419operand of the insn which corresponds to the @code{match_operator} 420never has any constraints because it is never reloaded as a whole. 421However, if parts of its @var{operands} are matched by 422@code{match_operand} patterns, those parts may have constraints of 423their own. 424 425@findex match_op_dup 426@item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}]) 427Like @code{match_dup}, except that it applies to operators instead of 428operands. When constructing an insn, operand number @var{n} will be 429substituted at this point. But in matching, @code{match_op_dup} behaves 430differently. It assumes that operand number @var{n} has already been 431determined by a @code{match_operator} appearing earlier in the 432recognition template, and it matches only an identical-looking 433expression. 434 435@findex match_parallel 436@item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}]) 437This pattern is a placeholder for an insn that consists of a 438@code{parallel} expression with a variable number of elements. This 439expression should only appear at the top level of an insn pattern. 440 441When constructing an insn, operand number @var{n} will be substituted at 442this point. When matching an insn, it matches if the body of the insn 443is a @code{parallel} expression with at least as many elements as the 444vector of @var{subpat} expressions in the @code{match_parallel}, if each 445@var{subpat} matches the corresponding element of the @code{parallel}, 446@emph{and} the function @var{predicate} returns nonzero on the 447@code{parallel} that is the body of the insn. It is the responsibility 448of the predicate to validate elements of the @code{parallel} beyond 449those listed in the @code{match_parallel}. 450 451A typical use of @code{match_parallel} is to match load and store 452multiple expressions, which can contain a variable number of elements 453in a @code{parallel}. For example, 454 455@smallexample 456(define_insn "" 457 [(match_parallel 0 "load_multiple_operation" 458 [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 459 (match_operand:SI 2 "memory_operand" "m")) 460 (use (reg:SI 179)) 461 (clobber (reg:SI 179))])] 462 "" 463 "loadm 0,0,%1,%2") 464@end smallexample 465 466This example comes from @file{a29k.md}. The function 467@code{load_multiple_operation} is defined in @file{a29k.c} and checks 468that subsequent elements in the @code{parallel} are the same as the 469@code{set} in the pattern, except that they are referencing subsequent 470registers and memory locations. 471 472An insn that matches this pattern might look like: 473 474@smallexample 475(parallel 476 [(set (reg:SI 20) (mem:SI (reg:SI 100))) 477 (use (reg:SI 179)) 478 (clobber (reg:SI 179)) 479 (set (reg:SI 21) 480 (mem:SI (plus:SI (reg:SI 100) 481 (const_int 4)))) 482 (set (reg:SI 22) 483 (mem:SI (plus:SI (reg:SI 100) 484 (const_int 8))))]) 485@end smallexample 486 487@findex match_par_dup 488@item (match_par_dup @var{n} [@var{subpat}@dots{}]) 489Like @code{match_op_dup}, but for @code{match_parallel} instead of 490@code{match_operator}. 491 492@findex match_insn 493@item (match_insn @var{predicate}) 494Match a complete insn. Unlike the other @code{match_*} recognizers, 495@code{match_insn} does not take an operand number. 496 497The machine mode @var{m} of @code{match_insn} works like that of 498@code{match_operand}: it is passed as the second argument to the 499predicate function, and that function is solely responsible for 500deciding whether the expression to be matched ``has'' that mode. 501 502@findex match_insn2 503@item (match_insn2 @var{n} @var{predicate}) 504Match a complete insn. 505 506The machine mode @var{m} of @code{match_insn2} works like that of 507@code{match_operand}: it is passed as the second argument to the 508predicate function, and that function is solely responsible for 509deciding whether the expression to be matched ``has'' that mode. 510 511@end table 512 513@node Output Template 514@section Output Templates and Operand Substitution 515@cindex output templates 516@cindex operand substitution 517 518@cindex @samp{%} in template 519@cindex percent sign 520The @dfn{output template} is a string which specifies how to output the 521assembler code for an instruction pattern. Most of the template is a 522fixed string which is output literally. The character @samp{%} is used 523to specify where to substitute an operand; it can also be used to 524identify places where different variants of the assembler require 525different syntax. 526 527In the simplest case, a @samp{%} followed by a digit @var{n} says to output 528operand @var{n} at that point in the string. 529 530@samp{%} followed by a letter and a digit says to output an operand in an 531alternate fashion. Four letters have standard, built-in meanings described 532below. The machine description macro @code{PRINT_OPERAND} can define 533additional letters with nonstandard meanings. 534 535@samp{%c@var{digit}} can be used to substitute an operand that is a 536constant value without the syntax that normally indicates an immediate 537operand. 538 539@samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of 540the constant is negated before printing. 541 542@samp{%a@var{digit}} can be used to substitute an operand as if it were a 543memory reference, with the actual operand treated as the address. This may 544be useful when outputting a ``load address'' instruction, because often the 545assembler syntax for such an instruction requires you to write the operand 546as if it were a memory reference. 547 548@samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump 549instruction. 550 551@samp{%=} outputs a number which is unique to each instruction in the 552entire compilation. This is useful for making local labels to be 553referred to more than once in a single template that generates multiple 554assembler instructions. 555 556@samp{%} followed by a punctuation character specifies a substitution that 557does not use an operand. Only one case is standard: @samp{%%} outputs a 558@samp{%} into the assembler code. Other nonstandard cases can be 559defined in the @code{PRINT_OPERAND} macro. You must also define 560which punctuation characters are valid with the 561@code{PRINT_OPERAND_PUNCT_VALID_P} macro. 562 563@cindex \ 564@cindex backslash 565The template may generate multiple assembler instructions. Write the text 566for the instructions, with @samp{\;} between them. 567 568@cindex matching operands 569When the RTL contains two operands which are required by constraint to match 570each other, the output template must refer only to the lower-numbered operand. 571Matching operands are not always identical, and the rest of the compiler 572arranges to put the proper RTL expression for printing into the lower-numbered 573operand. 574 575One use of nonstandard letters or punctuation following @samp{%} is to 576distinguish between different assembler languages for the same machine; for 577example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax 578requires periods in most opcode names, while MIT syntax does not. For 579example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola 580syntax. The same file of patterns is used for both kinds of output syntax, 581but the character sequence @samp{%.} is used in each place where Motorola 582syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax 583defines the sequence to output a period; the macro for MIT syntax defines 584it to do nothing. 585 586@cindex @code{#} in template 587As a special case, a template consisting of the single character @code{#} 588instructs the compiler to first split the insn, and then output the 589resulting instructions separately. This helps eliminate redundancy in the 590output templates. If you have a @code{define_insn} that needs to emit 591multiple assembler instructions, and there is an matching @code{define_split} 592already defined, then you can simply use @code{#} as the output template 593instead of writing an output template that emits the multiple assembler 594instructions. 595 596If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct 597of the form @samp{@{option0|option1|option2@}} in the templates. These 598describe multiple variants of assembler language syntax. 599@xref{Instruction Output}. 600 601@node Output Statement 602@section C Statements for Assembler Output 603@cindex output statements 604@cindex C statements for assembler output 605@cindex generating assembler output 606 607Often a single fixed template string cannot produce correct and efficient 608assembler code for all the cases that are recognized by a single 609instruction pattern. For example, the opcodes may depend on the kinds of 610operands; or some unfortunate combinations of operands may require extra 611machine instructions. 612 613If the output control string starts with a @samp{@@}, then it is actually 614a series of templates, each on a separate line. (Blank lines and 615leading spaces and tabs are ignored.) The templates correspond to the 616pattern's constraint alternatives (@pxref{Multi-Alternative}). For example, 617if a target machine has a two-address add instruction @samp{addr} to add 618into a register and another @samp{addm} to add a register to memory, you 619might write this pattern: 620 621@smallexample 622(define_insn "addsi3" 623 [(set (match_operand:SI 0 "general_operand" "=r,m") 624 (plus:SI (match_operand:SI 1 "general_operand" "0,0") 625 (match_operand:SI 2 "general_operand" "g,r")))] 626 "" 627 "@@ 628 addr %2,%0 629 addm %2,%0") 630@end smallexample 631 632@cindex @code{*} in template 633@cindex asterisk in template 634If the output control string starts with a @samp{*}, then it is not an 635output template but rather a piece of C program that should compute a 636template. It should execute a @code{return} statement to return the 637template-string you want. Most such templates use C string literals, which 638require doublequote characters to delimit them. To include these 639doublequote characters in the string, prefix each one with @samp{\}. 640 641If the output control string is written as a brace block instead of a 642double-quoted string, it is automatically assumed to be C code. In that 643case, it is not necessary to put in a leading asterisk, or to escape the 644doublequotes surrounding C string literals. 645 646The operands may be found in the array @code{operands}, whose C data type 647is @code{rtx []}. 648 649It is very common to select different ways of generating assembler code 650based on whether an immediate operand is within a certain range. Be 651careful when doing this, because the result of @code{INTVAL} is an 652integer on the host machine. If the host machine has more bits in an 653@code{int} than the target machine has in the mode in which the constant 654will be used, then some of the bits you get from @code{INTVAL} will be 655superfluous. For proper results, you must carefully disregard the 656values of those bits. 657 658@findex output_asm_insn 659It is possible to output an assembler instruction and then go on to output 660or compute more of them, using the subroutine @code{output_asm_insn}. This 661receives two arguments: a template-string and a vector of operands. The 662vector may be @code{operands}, or it may be another array of @code{rtx} 663that you declare locally and initialize yourself. 664 665@findex which_alternative 666When an insn pattern has multiple alternatives in its constraints, often 667the appearance of the assembler code is determined mostly by which alternative 668was matched. When this is so, the C code can test the variable 669@code{which_alternative}, which is the ordinal number of the alternative 670that was actually satisfied (0 for the first, 1 for the second alternative, 671etc.). 672 673For example, suppose there are two opcodes for storing zero, @samp{clrreg} 674for registers and @samp{clrmem} for memory locations. Here is how 675a pattern could use @code{which_alternative} to choose between them: 676 677@smallexample 678(define_insn "" 679 [(set (match_operand:SI 0 "general_operand" "=r,m") 680 (const_int 0))] 681 "" 682 @{ 683 return (which_alternative == 0 684 ? "clrreg %0" : "clrmem %0"); 685 @}) 686@end smallexample 687 688The example above, where the assembler code to generate was 689@emph{solely} determined by the alternative, could also have been specified 690as follows, having the output control string start with a @samp{@@}: 691 692@smallexample 693@group 694(define_insn "" 695 [(set (match_operand:SI 0 "general_operand" "=r,m") 696 (const_int 0))] 697 "" 698 "@@ 699 clrreg %0 700 clrmem %0") 701@end group 702@end smallexample 703@end ifset 704 705@c Most of this node appears by itself (in a different place) even 706@c when the INTERNALS flag is clear. Passages that require the internals 707@c manual's context are conditionalized to appear only in the internals manual. 708@ifset INTERNALS 709@node Constraints 710@section Operand Constraints 711@cindex operand constraints 712@cindex constraints 713 714Each @code{match_operand} in an instruction pattern can specify a 715constraint for the type of operands allowed. 716@end ifset 717@ifclear INTERNALS 718@node Constraints 719@section Constraints for @code{asm} Operands 720@cindex operand constraints, @code{asm} 721@cindex constraints, @code{asm} 722@cindex @code{asm} constraints 723 724Here are specific details on what constraint letters you can use with 725@code{asm} operands. 726@end ifclear 727Constraints can say whether 728an operand may be in a register, and which kinds of register; whether the 729operand can be a memory reference, and which kinds of address; whether the 730operand may be an immediate constant, and which possible values it may 731have. Constraints can also require two operands to match. 732 733@ifset INTERNALS 734@menu 735* Simple Constraints:: Basic use of constraints. 736* Multi-Alternative:: When an insn has two alternative constraint-patterns. 737* Class Preferences:: Constraints guide which hard register to put things in. 738* Modifiers:: More precise control over effects of constraints. 739* Machine Constraints:: Existing constraints for some particular machines. 740@end menu 741@end ifset 742 743@ifclear INTERNALS 744@menu 745* Simple Constraints:: Basic use of constraints. 746* Multi-Alternative:: When an insn has two alternative constraint-patterns. 747* Modifiers:: More precise control over effects of constraints. 748* Machine Constraints:: Special constraints for some particular machines. 749@end menu 750@end ifclear 751 752@node Simple Constraints 753@subsection Simple Constraints 754@cindex simple constraints 755 756The simplest kind of constraint is a string full of letters, each of 757which describes one kind of operand that is permitted. Here are 758the letters that are allowed: 759 760@table @asis 761@item whitespace 762Whitespace characters are ignored and can be inserted at any position 763except the first. This enables each alternative for different operands to 764be visually aligned in the machine description even if they have different 765number of constraints and modifiers. 766 767@cindex @samp{m} in constraint 768@cindex memory references in constraints 769@item @samp{m} 770A memory operand is allowed, with any kind of address that the machine 771supports in general. 772 773@cindex offsettable address 774@cindex @samp{o} in constraint 775@item @samp{o} 776A memory operand is allowed, but only if the address is 777@dfn{offsettable}. This means that adding a small integer (actually, 778the width in bytes of the operand, as determined by its machine mode) 779may be added to the address and the result is also a valid memory 780address. 781 782@cindex autoincrement/decrement addressing 783For example, an address which is constant is offsettable; so is an 784address that is the sum of a register and a constant (as long as a 785slightly larger constant is also within the range of address-offsets 786supported by the machine); but an autoincrement or autodecrement 787address is not offsettable. More complicated indirect/indexed 788addresses may or may not be offsettable depending on the other 789addressing modes that the machine supports. 790 791Note that in an output operand which can be matched by another 792operand, the constraint letter @samp{o} is valid only when accompanied 793by both @samp{<} (if the target machine has predecrement addressing) 794and @samp{>} (if the target machine has preincrement addressing). 795 796@cindex @samp{V} in constraint 797@item @samp{V} 798A memory operand that is not offsettable. In other words, anything that 799would fit the @samp{m} constraint but not the @samp{o} constraint. 800 801@cindex @samp{<} in constraint 802@item @samp{<} 803A memory operand with autodecrement addressing (either predecrement or 804postdecrement) is allowed. 805 806@cindex @samp{>} in constraint 807@item @samp{>} 808A memory operand with autoincrement addressing (either preincrement or 809postincrement) is allowed. 810 811@cindex @samp{r} in constraint 812@cindex registers in constraints 813@item @samp{r} 814A register operand is allowed provided that it is in a general 815register. 816 817@cindex constants in constraints 818@cindex @samp{i} in constraint 819@item @samp{i} 820An immediate integer operand (one with constant value) is allowed. 821This includes symbolic constants whose values will be known only at 822assembly time. 823 824@cindex @samp{n} in constraint 825@item @samp{n} 826An immediate integer operand with a known numeric value is allowed. 827Many systems cannot support assembly-time constants for operands less 828than a word wide. Constraints for these operands should use @samp{n} 829rather than @samp{i}. 830 831@cindex @samp{I} in constraint 832@item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P} 833Other letters in the range @samp{I} through @samp{P} may be defined in 834a machine-dependent fashion to permit immediate integer operands with 835explicit integer values in specified ranges. For example, on the 83668000, @samp{I} is defined to stand for the range of values 1 to 8. 837This is the range permitted as a shift count in the shift 838instructions. 839 840@cindex @samp{E} in constraint 841@item @samp{E} 842An immediate floating operand (expression code @code{const_double}) is 843allowed, but only if the target floating point format is the same as 844that of the host machine (on which the compiler is running). 845 846@cindex @samp{F} in constraint 847@item @samp{F} 848An immediate floating operand (expression code @code{const_double} or 849@code{const_vector}) is allowed. 850 851@cindex @samp{G} in constraint 852@cindex @samp{H} in constraint 853@item @samp{G}, @samp{H} 854@samp{G} and @samp{H} may be defined in a machine-dependent fashion to 855permit immediate floating operands in particular ranges of values. 856 857@cindex @samp{s} in constraint 858@item @samp{s} 859An immediate integer operand whose value is not an explicit integer is 860allowed. 861 862This might appear strange; if an insn allows a constant operand with a 863value not known at compile time, it certainly must allow any known 864value. So why use @samp{s} instead of @samp{i}? Sometimes it allows 865better code to be generated. 866 867For example, on the 68000 in a fullword instruction it is possible to 868use an immediate operand; but if the immediate value is between @minus{}128 869and 127, better code results from loading the value into a register and 870using the register. This is because the load into the register can be 871done with a @samp{moveq} instruction. We arrange for this to happen 872by defining the letter @samp{K} to mean ``any integer outside the 873range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand 874constraints. 875 876@cindex @samp{g} in constraint 877@item @samp{g} 878Any register, memory or immediate integer operand is allowed, except for 879registers that are not general registers. 880 881@cindex @samp{X} in constraint 882@item @samp{X} 883@ifset INTERNALS 884Any operand whatsoever is allowed, even if it does not satisfy 885@code{general_operand}. This is normally used in the constraint of 886a @code{match_scratch} when certain alternatives will not actually 887require a scratch register. 888@end ifset 889@ifclear INTERNALS 890Any operand whatsoever is allowed. 891@end ifclear 892 893@cindex @samp{0} in constraint 894@cindex digits in constraint 895@item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9} 896An operand that matches the specified operand number is allowed. If a 897digit is used together with letters within the same alternative, the 898digit should come last. 899 900This number is allowed to be more than a single digit. If multiple 901digits are encountered consecutively, they are interpreted as a single 902decimal integer. There is scant chance for ambiguity, since to-date 903it has never been desirable that @samp{10} be interpreted as matching 904either operand 1 @emph{or} operand 0. Should this be desired, one 905can use multiple alternatives instead. 906 907@cindex matching constraint 908@cindex constraint, matching 909This is called a @dfn{matching constraint} and what it really means is 910that the assembler has only a single operand that fills two roles 911@ifset INTERNALS 912considered separate in the RTL insn. For example, an add insn has two 913input operands and one output operand in the RTL, but on most CISC 914@end ifset 915@ifclear INTERNALS 916which @code{asm} distinguishes. For example, an add instruction uses 917two input operands and an output operand, but on most CISC 918@end ifclear 919machines an add instruction really has only two operands, one of them an 920input-output operand: 921 922@smallexample 923addl #35,r12 924@end smallexample 925 926Matching constraints are used in these circumstances. 927More precisely, the two operands that match must include one input-only 928operand and one output-only operand. Moreover, the digit must be a 929smaller number than the number of the operand that uses it in the 930constraint. 931 932@ifset INTERNALS 933For operands to match in a particular case usually means that they 934are identical-looking RTL expressions. But in a few special cases 935specific kinds of dissimilarity are allowed. For example, @code{*x} 936as an input operand will match @code{*x++} as an output operand. 937For proper results in such cases, the output template should always 938use the output-operand's number when printing the operand. 939@end ifset 940 941@cindex load address instruction 942@cindex push address instruction 943@cindex address constraints 944@cindex @samp{p} in constraint 945@item @samp{p} 946An operand that is a valid memory address is allowed. This is 947for ``load address'' and ``push address'' instructions. 948 949@findex address_operand 950@samp{p} in the constraint must be accompanied by @code{address_operand} 951as the predicate in the @code{match_operand}. This predicate interprets 952the mode specified in the @code{match_operand} as the mode of the memory 953reference for which the address would be valid. 954 955@cindex other register constraints 956@cindex extensible constraints 957@item @var{other-letters} 958Other letters can be defined in machine-dependent fashion to stand for 959particular classes of registers or other arbitrary operand types. 960@samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand 961for data, address and floating point registers. 962 963@ifset INTERNALS 964The machine description macro @code{REG_CLASS_FROM_LETTER} has first 965cut at the otherwise unused letters. If it evaluates to @code{NO_REGS}, 966then @code{EXTRA_CONSTRAINT} is evaluated. 967 968A typical use for @code{EXTRA_CONSTRAINT} would be to distinguish certain 969types of memory references that affect other insn operands. 970@end ifset 971@end table 972 973@ifset INTERNALS 974In order to have valid assembler code, each operand must satisfy 975its constraint. But a failure to do so does not prevent the pattern 976from applying to an insn. Instead, it directs the compiler to modify 977the code so that the constraint will be satisfied. Usually this is 978done by copying an operand into a register. 979 980Contrast, therefore, the two instruction patterns that follow: 981 982@smallexample 983(define_insn "" 984 [(set (match_operand:SI 0 "general_operand" "=r") 985 (plus:SI (match_dup 0) 986 (match_operand:SI 1 "general_operand" "r")))] 987 "" 988 "@dots{}") 989@end smallexample 990 991@noindent 992which has two operands, one of which must appear in two places, and 993 994@smallexample 995(define_insn "" 996 [(set (match_operand:SI 0 "general_operand" "=r") 997 (plus:SI (match_operand:SI 1 "general_operand" "0") 998 (match_operand:SI 2 "general_operand" "r")))] 999 "" 1000 "@dots{}") 1001@end smallexample 1002 1003@noindent 1004which has three operands, two of which are required by a constraint to be 1005identical. If we are considering an insn of the form 1006 1007@smallexample 1008(insn @var{n} @var{prev} @var{next} 1009 (set (reg:SI 3) 1010 (plus:SI (reg:SI 6) (reg:SI 109))) 1011 @dots{}) 1012@end smallexample 1013 1014@noindent 1015the first pattern would not apply at all, because this insn does not 1016contain two identical subexpressions in the right place. The pattern would 1017say, ``That does not look like an add instruction; try other patterns.'' 1018The second pattern would say, ``Yes, that's an add instruction, but there 1019is something wrong with it.'' It would direct the reload pass of the 1020compiler to generate additional insns to make the constraint true. The 1021results might look like this: 1022 1023@smallexample 1024(insn @var{n2} @var{prev} @var{n} 1025 (set (reg:SI 3) (reg:SI 6)) 1026 @dots{}) 1027 1028(insn @var{n} @var{n2} @var{next} 1029 (set (reg:SI 3) 1030 (plus:SI (reg:SI 3) (reg:SI 109))) 1031 @dots{}) 1032@end smallexample 1033 1034It is up to you to make sure that each operand, in each pattern, has 1035constraints that can handle any RTL expression that could be present for 1036that operand. (When multiple alternatives are in use, each pattern must, 1037for each possible combination of operand expressions, have at least one 1038alternative which can handle that combination of operands.) The 1039constraints don't need to @emph{allow} any possible operand---when this is 1040the case, they do not constrain---but they must at least point the way to 1041reloading any possible operand so that it will fit. 1042 1043@itemize @bullet 1044@item 1045If the constraint accepts whatever operands the predicate permits, 1046there is no problem: reloading is never necessary for this operand. 1047 1048For example, an operand whose constraints permit everything except 1049registers is safe provided its predicate rejects registers. 1050 1051An operand whose predicate accepts only constant values is safe 1052provided its constraints include the letter @samp{i}. If any possible 1053constant value is accepted, then nothing less than @samp{i} will do; 1054if the predicate is more selective, then the constraints may also be 1055more selective. 1056 1057@item 1058Any operand expression can be reloaded by copying it into a register. 1059So if an operand's constraints allow some kind of register, it is 1060certain to be safe. It need not permit all classes of registers; the 1061compiler knows how to copy a register into another register of the 1062proper class in order to make an instruction valid. 1063 1064@cindex nonoffsettable memory reference 1065@cindex memory reference, nonoffsettable 1066@item 1067A nonoffsettable memory reference can be reloaded by copying the 1068address into a register. So if the constraint uses the letter 1069@samp{o}, all memory references are taken care of. 1070 1071@item 1072A constant operand can be reloaded by allocating space in memory to 1073hold it as preinitialized data. Then the memory reference can be used 1074in place of the constant. So if the constraint uses the letters 1075@samp{o} or @samp{m}, constant operands are not a problem. 1076 1077@item 1078If the constraint permits a constant and a pseudo register used in an insn 1079was not allocated to a hard register and is equivalent to a constant, 1080the register will be replaced with the constant. If the predicate does 1081not permit a constant and the insn is re-recognized for some reason, the 1082compiler will crash. Thus the predicate must always recognize any 1083objects allowed by the constraint. 1084@end itemize 1085 1086If the operand's predicate can recognize registers, but the constraint does 1087not permit them, it can make the compiler crash. When this operand happens 1088to be a register, the reload pass will be stymied, because it does not know 1089how to copy a register temporarily into memory. 1090 1091If the predicate accepts a unary operator, the constraint applies to the 1092operand. For example, the MIPS processor at ISA level 3 supports an 1093instruction which adds two registers in @code{SImode} to produce a 1094@code{DImode} result, but only if the registers are correctly sign 1095extended. This predicate for the input operands accepts a 1096@code{sign_extend} of an @code{SImode} register. Write the constraint 1097to indicate the type of register that is required for the operand of the 1098@code{sign_extend}. 1099@end ifset 1100 1101@node Multi-Alternative 1102@subsection Multiple Alternative Constraints 1103@cindex multiple alternative constraints 1104 1105Sometimes a single instruction has multiple alternative sets of possible 1106operands. For example, on the 68000, a logical-or instruction can combine 1107register or an immediate value into memory, or it can combine any kind of 1108operand into a register; but it cannot combine one memory location into 1109another. 1110 1111These constraints are represented as multiple alternatives. An alternative 1112can be described by a series of letters for each operand. The overall 1113constraint for an operand is made from the letters for this operand 1114from the first alternative, a comma, the letters for this operand from 1115the second alternative, a comma, and so on until the last alternative. 1116@ifset INTERNALS 1117Here is how it is done for fullword logical-or on the 68000: 1118 1119@smallexample 1120(define_insn "iorsi3" 1121 [(set (match_operand:SI 0 "general_operand" "=m,d") 1122 (ior:SI (match_operand:SI 1 "general_operand" "%0,0") 1123 (match_operand:SI 2 "general_operand" "dKs,dmKs")))] 1124 @dots{}) 1125@end smallexample 1126 1127The first alternative has @samp{m} (memory) for operand 0, @samp{0} for 1128operand 1 (meaning it must match operand 0), and @samp{dKs} for operand 11292. The second alternative has @samp{d} (data register) for operand 0, 1130@samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and 1131@samp{%} in the constraints apply to all the alternatives; their 1132meaning is explained in the next section (@pxref{Class Preferences}). 1133@end ifset 1134 1135@c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL 1136If all the operands fit any one alternative, the instruction is valid. 1137Otherwise, for each alternative, the compiler counts how many instructions 1138must be added to copy the operands so that that alternative applies. 1139The alternative requiring the least copying is chosen. If two alternatives 1140need the same amount of copying, the one that comes first is chosen. 1141These choices can be altered with the @samp{?} and @samp{!} characters: 1142 1143@table @code 1144@cindex @samp{?} in constraint 1145@cindex question mark 1146@item ? 1147Disparage slightly the alternative that the @samp{?} appears in, 1148as a choice when no alternative applies exactly. The compiler regards 1149this alternative as one unit more costly for each @samp{?} that appears 1150in it. 1151 1152@cindex @samp{!} in constraint 1153@cindex exclamation point 1154@item ! 1155Disparage severely the alternative that the @samp{!} appears in. 1156This alternative can still be used if it fits without reloading, 1157but if reloading is needed, some other alternative will be used. 1158@end table 1159 1160@ifset INTERNALS 1161When an insn pattern has multiple alternatives in its constraints, often 1162the appearance of the assembler code is determined mostly by which 1163alternative was matched. When this is so, the C code for writing the 1164assembler code can use the variable @code{which_alternative}, which is 1165the ordinal number of the alternative that was actually satisfied (0 for 1166the first, 1 for the second alternative, etc.). @xref{Output Statement}. 1167@end ifset 1168 1169@ifset INTERNALS 1170@node Class Preferences 1171@subsection Register Class Preferences 1172@cindex class preference constraints 1173@cindex register class preference constraints 1174 1175@cindex voting between constraint alternatives 1176The operand constraints have another function: they enable the compiler 1177to decide which kind of hardware register a pseudo register is best 1178allocated to. The compiler examines the constraints that apply to the 1179insns that use the pseudo register, looking for the machine-dependent 1180letters such as @samp{d} and @samp{a} that specify classes of registers. 1181The pseudo register is put in whichever class gets the most ``votes''. 1182The constraint letters @samp{g} and @samp{r} also vote: they vote in 1183favor of a general register. The machine description says which registers 1184are considered general. 1185 1186Of course, on some machines all registers are equivalent, and no register 1187classes are defined. Then none of this complexity is relevant. 1188@end ifset 1189 1190@node Modifiers 1191@subsection Constraint Modifier Characters 1192@cindex modifiers in constraints 1193@cindex constraint modifier characters 1194 1195@c prevent bad page break with this line 1196Here are constraint modifier characters. 1197 1198@table @samp 1199@cindex @samp{=} in constraint 1200@item = 1201Means that this operand is write-only for this instruction: the previous 1202value is discarded and replaced by output data. 1203 1204@cindex @samp{+} in constraint 1205@item + 1206Means that this operand is both read and written by the instruction. 1207 1208When the compiler fixes up the operands to satisfy the constraints, 1209it needs to know which operands are inputs to the instruction and 1210which are outputs from it. @samp{=} identifies an output; @samp{+} 1211identifies an operand that is both input and output; all other operands 1212are assumed to be input only. 1213 1214If you specify @samp{=} or @samp{+} in a constraint, you put it in the 1215first character of the constraint string. 1216 1217@cindex @samp{&} in constraint 1218@cindex earlyclobber operand 1219@item & 1220Means (in a particular alternative) that this operand is an 1221@dfn{earlyclobber} operand, which is modified before the instruction is 1222finished using the input operands. Therefore, this operand may not lie 1223in a register that is used as an input operand or as part of any memory 1224address. 1225 1226@samp{&} applies only to the alternative in which it is written. In 1227constraints with multiple alternatives, sometimes one alternative 1228requires @samp{&} while others do not. See, for example, the 1229@samp{movdf} insn of the 68000. 1230 1231An input operand can be tied to an earlyclobber operand if its only 1232use as an input occurs before the early result is written. Adding 1233alternatives of this form often allows GCC to produce better code 1234when only some of the inputs can be affected by the earlyclobber. 1235See, for example, the @samp{mulsi3} insn of the ARM@. 1236 1237@samp{&} does not obviate the need to write @samp{=}. 1238 1239@cindex @samp{%} in constraint 1240@item % 1241Declares the instruction to be commutative for this operand and the 1242following operand. This means that the compiler may interchange the 1243two operands if that is the cheapest way to make all operands fit the 1244constraints. 1245@ifset INTERNALS 1246This is often used in patterns for addition instructions 1247that really have only two operands: the result must go in one of the 1248arguments. Here for example, is how the 68000 halfword-add 1249instruction is defined: 1250 1251@smallexample 1252(define_insn "addhi3" 1253 [(set (match_operand:HI 0 "general_operand" "=m,r") 1254 (plus:HI (match_operand:HI 1 "general_operand" "%0,0") 1255 (match_operand:HI 2 "general_operand" "di,g")))] 1256 @dots{}) 1257@end smallexample 1258@end ifset 1259GCC can only handle one commutative pair in an asm; if you use more, 1260the compiler may fail. 1261 1262@cindex @samp{#} in constraint 1263@item # 1264Says that all following characters, up to the next comma, are to be 1265ignored as a constraint. They are significant only for choosing 1266register preferences. 1267 1268@cindex @samp{*} in constraint 1269@item * 1270Says that the following character should be ignored when choosing 1271register preferences. @samp{*} has no effect on the meaning of the 1272constraint as a constraint, and no effect on reloading. 1273 1274@ifset INTERNALS 1275Here is an example: the 68000 has an instruction to sign-extend a 1276halfword in a data register, and can also sign-extend a value by 1277copying it into an address register. While either kind of register is 1278acceptable, the constraints on an address-register destination are 1279less strict, so it is best if register allocation makes an address 1280register its goal. Therefore, @samp{*} is used so that the @samp{d} 1281constraint letter (for data register) is ignored when computing 1282register preferences. 1283 1284@smallexample 1285(define_insn "extendhisi2" 1286 [(set (match_operand:SI 0 "general_operand" "=*d,a") 1287 (sign_extend:SI 1288 (match_operand:HI 1 "general_operand" "0,g")))] 1289 @dots{}) 1290@end smallexample 1291@end ifset 1292@end table 1293 1294@node Machine Constraints 1295@subsection Constraints for Particular Machines 1296@cindex machine specific constraints 1297@cindex constraints, machine specific 1298 1299Whenever possible, you should use the general-purpose constraint letters 1300in @code{asm} arguments, since they will convey meaning more readily to 1301people reading your code. Failing that, use the constraint letters 1302that usually have very similar meanings across architectures. The most 1303commonly used constraints are @samp{m} and @samp{r} (for memory and 1304general-purpose registers respectively; @pxref{Simple Constraints}), and 1305@samp{I}, usually the letter indicating the most common 1306immediate-constant format. 1307 1308For each machine architecture, the 1309@file{config/@var{machine}/@var{machine}.h} file defines additional 1310constraints. These constraints are used by the compiler itself for 1311instruction generation, as well as for @code{asm} statements; therefore, 1312some of the constraints are not particularly interesting for @code{asm}. 1313The constraints are defined through these macros: 1314 1315@table @code 1316@item REG_CLASS_FROM_LETTER 1317Register class constraints (usually lower case). 1318 1319@item CONST_OK_FOR_LETTER_P 1320Immediate constant constraints, for non-floating point constants of 1321word size or smaller precision (usually upper case). 1322 1323@item CONST_DOUBLE_OK_FOR_LETTER_P 1324Immediate constant constraints, for all floating point constants and for 1325constants of greater than word size precision (usually upper case). 1326 1327@item EXTRA_CONSTRAINT 1328Special cases of registers or memory. This macro is not required, and 1329is only defined for some machines. 1330@end table 1331 1332Inspecting these macro definitions in the compiler source for your 1333machine is the best way to be certain you have the right constraints. 1334However, here is a summary of the machine-dependent constraints 1335available on some particular machines. 1336 1337@table @emph 1338@item ARM family---@file{arm.h} 1339@table @code 1340@item f 1341Floating-point register 1342 1343@item F 1344One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0 1345or 10.0 1346 1347@item G 1348Floating-point constant that would satisfy the constraint @samp{F} if it 1349were negated 1350 1351@item I 1352Integer that is valid as an immediate operand in a data processing 1353instruction. That is, an integer in the range 0 to 255 rotated by a 1354multiple of 2 1355 1356@item J 1357Integer in the range @minus{}4095 to 4095 1358 1359@item K 1360Integer that satisfies constraint @samp{I} when inverted (ones complement) 1361 1362@item L 1363Integer that satisfies constraint @samp{I} when negated (twos complement) 1364 1365@item M 1366Integer in the range 0 to 32 1367 1368@item Q 1369A memory reference where the exact address is in a single register 1370(`@samp{m}' is preferable for @code{asm} statements) 1371 1372@item R 1373An item in the constant pool 1374 1375@item S 1376A symbol in the text segment of the current file 1377@end table 1378 1379@item AVR family---@file{avr.h} 1380@table @code 1381@item l 1382Registers from r0 to r15 1383 1384@item a 1385Registers from r16 to r23 1386 1387@item d 1388Registers from r16 to r31 1389 1390@item w 1391Registers from r24 to r31. These registers can be used in @samp{adiw} command 1392 1393@item e 1394Pointer register (r26--r31) 1395 1396@item b 1397Base pointer register (r28--r31) 1398 1399@item q 1400Stack pointer register (SPH:SPL) 1401 1402@item t 1403Temporary register r0 1404 1405@item x 1406Register pair X (r27:r26) 1407 1408@item y 1409Register pair Y (r29:r28) 1410 1411@item z 1412Register pair Z (r31:r30) 1413 1414@item I 1415Constant greater than @minus{}1, less than 64 1416 1417@item J 1418Constant greater than @minus{}64, less than 1 1419 1420@item K 1421Constant integer 2 1422 1423@item L 1424Constant integer 0 1425 1426@item M 1427Constant that fits in 8 bits 1428 1429@item N 1430Constant integer @minus{}1 1431 1432@item O 1433Constant integer 8, 16, or 24 1434 1435@item P 1436Constant integer 1 1437 1438@item G 1439A floating point constant 0.0 1440@end table 1441 1442@item IBM RS6000---@file{rs6000.h} 1443@table @code 1444@item b 1445Address base register 1446 1447@item f 1448Floating point register 1449 1450@item h 1451@samp{MQ}, @samp{CTR}, or @samp{LINK} register 1452 1453@item q 1454@samp{MQ} register 1455 1456@item c 1457@samp{CTR} register 1458 1459@item l 1460@samp{LINK} register 1461 1462@item x 1463@samp{CR} register (condition register) number 0 1464 1465@item y 1466@samp{CR} register (condition register) 1467 1468@item z 1469@samp{FPMEM} stack memory for FPR-GPR transfers 1470 1471@item I 1472Signed 16-bit constant 1473 1474@item J 1475Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for 1476@code{SImode} constants) 1477 1478@item K 1479Unsigned 16-bit constant 1480 1481@item L 1482Signed 16-bit constant shifted left 16 bits 1483 1484@item M 1485Constant larger than 31 1486 1487@item N 1488Exact power of 2 1489 1490@item O 1491Zero 1492 1493@item P 1494Constant whose negation is a signed 16-bit constant 1495 1496@item G 1497Floating point constant that can be loaded into a register with one 1498instruction per word 1499 1500@item Q 1501Memory operand that is an offset from a register (@samp{m} is preferable 1502for @code{asm} statements) 1503 1504@item R 1505AIX TOC entry 1506 1507@item S 1508Constant suitable as a 64-bit mask operand 1509 1510@item T 1511Constant suitable as a 32-bit mask operand 1512 1513@item U 1514System V Release 4 small data area reference 1515@end table 1516 1517@item Intel 386---@file{i386.h} 1518@table @code 1519@item q 1520@samp{a}, @code{b}, @code{c}, or @code{d} register for the i386. 1521For x86-64 it is equivalent to @samp{r} class. (for 8-bit instructions that 1522do not use upper halves) 1523 1524@item Q 1525@samp{a}, @code{b}, @code{c}, or @code{d} register. (for 8-bit instructions, 1526that do use upper halves) 1527 1528@item R 1529Legacy register---equivalent to @code{r} class in i386 mode. 1530(for non-8-bit registers used together with 8-bit upper halves in a single 1531instruction) 1532 1533@item A 1534Specifies the @samp{a} or @samp{d} registers. This is primarily useful 1535for 64-bit integer values (when in 32-bit mode) intended to be returned 1536with the @samp{d} register holding the most significant bits and the 1537@samp{a} register holding the least significant bits. 1538 1539@item f 1540Floating point register 1541 1542@item t 1543First (top of stack) floating point register 1544 1545@item u 1546Second floating point register 1547 1548@item a 1549@samp{a} register 1550 1551@item b 1552@samp{b} register 1553 1554@item c 1555@samp{c} register 1556 1557@item C 1558Specifies constant that can be easily constructed in SSE register without 1559loading it from memory. 1560 1561@item d 1562@samp{d} register 1563 1564@item D 1565@samp{di} register 1566 1567@item S 1568@samp{si} register 1569 1570@item x 1571@samp{xmm} SSE register 1572 1573@item y 1574MMX register 1575 1576@item I 1577Constant in range 0 to 31 (for 32-bit shifts) 1578 1579@item J 1580Constant in range 0 to 63 (for 64-bit shifts) 1581 1582@item K 1583@samp{0xff} 1584 1585@item L 1586@samp{0xffff} 1587 1588@item M 15890, 1, 2, or 3 (shifts for @code{lea} instruction) 1590 1591@item N 1592Constant in range 0 to 255 (for @code{out} instruction) 1593 1594@item Z 1595Constant in range 0 to @code{0xffffffff} or symbolic reference known to fit specified range. 1596(for using immediates in zero extending 32-bit to 64-bit x86-64 instructions) 1597 1598@item e 1599Constant in range @minus{}2147483648 to 2147483647 or symbolic reference known to fit specified range. 1600(for using immediates in 64-bit x86-64 instructions) 1601 1602@item G 1603Standard 80387 floating point constant 1604@end table 1605 1606@item Intel 960---@file{i960.h} 1607@table @code 1608@item f 1609Floating point register (@code{fp0} to @code{fp3}) 1610 1611@item l 1612Local register (@code{r0} to @code{r15}) 1613 1614@item b 1615Global register (@code{g0} to @code{g15}) 1616 1617@item d 1618Any local or global register 1619 1620@item I 1621Integers from 0 to 31 1622 1623@item J 16240 1625 1626@item K 1627Integers from @minus{}31 to 0 1628 1629@item G 1630Floating point 0 1631 1632@item H 1633Floating point 1 1634@end table 1635 1636@item Intel IA-64---@file{ia64.h} 1637@table @code 1638@item a 1639General register @code{r0} to @code{r3} for @code{addl} instruction 1640 1641@item b 1642Branch register 1643 1644@item c 1645Predicate register (@samp{c} as in ``conditional'') 1646 1647@item d 1648Application register residing in M-unit 1649 1650@item e 1651Application register residing in I-unit 1652 1653@item f 1654Floating-point register 1655 1656@item m 1657Memory operand. 1658Remember that @samp{m} allows postincrement and postdecrement which 1659require printing with @samp{%Pn} on IA-64. 1660Use @samp{S} to disallow postincrement and postdecrement. 1661 1662@item G 1663Floating-point constant 0.0 or 1.0 1664 1665@item I 166614-bit signed integer constant 1667 1668@item J 166922-bit signed integer constant 1670 1671@item K 16728-bit signed integer constant for logical instructions 1673 1674@item L 16758-bit adjusted signed integer constant for compare pseudo-ops 1676 1677@item M 16786-bit unsigned integer constant for shift counts 1679 1680@item N 16819-bit signed integer constant for load and store postincrements 1682 1683@item O 1684The constant zero 1685 1686@item P 16870 or -1 for @code{dep} instruction 1688 1689@item Q 1690Non-volatile memory for floating-point loads and stores 1691 1692@item R 1693Integer constant in the range 1 to 4 for @code{shladd} instruction 1694 1695@item S 1696Memory operand except postincrement and postdecrement 1697@end table 1698 1699@item FRV---@file{frv.h} 1700@table @code 1701@item a 1702Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}). 1703 1704@item b 1705Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}). 1706 1707@item c 1708Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and 1709@code{icc0} to @code{icc3}). 1710 1711@item d 1712Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}). 1713 1714@item e 1715Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}). 1716Odd registers are excluded not in the class but through the use of a machine 1717mode larger than 4 bytes. 1718 1719@item f 1720Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}). 1721 1722@item h 1723Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}). 1724Odd registers are excluded not in the class but through the use of a machine 1725mode larger than 4 bytes. 1726 1727@item l 1728Register in the class @code{LR_REG} (the @code{lr} register). 1729 1730@item q 1731Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}). 1732Register numbers not divisible by 4 are excluded not in the class but through 1733the use of a machine mode larger than 8 bytes. 1734 1735@item t 1736Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}). 1737 1738@item u 1739Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}). 1740 1741@item v 1742Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}). 1743 1744@item w 1745Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}). 1746 1747@item x 1748Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}). 1749Register numbers not divisible by 4 are excluded not in the class but through 1750the use of a machine mode larger than 8 bytes. 1751 1752@item z 1753Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}). 1754 1755@item A 1756Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}). 1757 1758@item B 1759Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}). 1760 1761@item C 1762Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}). 1763 1764@item G 1765Floating point constant zero 1766 1767@item I 17686-bit signed integer constant 1769 1770@item J 177110-bit signed integer constant 1772 1773@item L 177416-bit signed integer constant 1775 1776@item M 177716-bit unsigned integer constant 1778 1779@item N 178012-bit signed integer constant that is negative---i.e.@: in the 1781range of @minus{}2048 to @minus{}1 1782 1783@item O 1784Constant zero 1785 1786@item P 178712-bit signed integer constant that is greater than zero---i.e.@: in the 1788range of 1 to 2047. 1789 1790@end table 1791 1792@item IP2K---@file{ip2k.h} 1793@table @code 1794@item a 1795@samp{DP} or @samp{IP} registers (general address) 1796 1797@item f 1798@samp{IP} register 1799 1800@item j 1801@samp{IPL} register 1802 1803@item k 1804@samp{IPH} register 1805 1806@item b 1807@samp{DP} register 1808 1809@item y 1810@samp{DPH} register 1811 1812@item z 1813@samp{DPL} register 1814 1815@item q 1816@samp{SP} register 1817 1818@item c 1819@samp{DP} or @samp{SP} registers (offsettable address) 1820 1821@item d 1822Non-pointer registers (not @samp{SP}, @samp{DP}, @samp{IP}) 1823 1824@item u 1825Non-SP registers (everything except @samp{SP}) 1826 1827@item R 1828Indirect thru @samp{IP} - Avoid this except for @code{QImode}, since we 1829can't access extra bytes 1830 1831@item S 1832Indirect thru @samp{SP} or @samp{DP} with short displacement (0..127) 1833 1834@item T 1835Data-section immediate value 1836 1837@item I 1838Integers from @minus{}255 to @minus{}1 1839 1840@item J 1841Integers from 0 to 7---valid bit number in a register 1842 1843@item K 1844Integers from 0 to 127---valid displacement for addressing mode 1845 1846@item L 1847Integers from 1 to 127 1848 1849@item M 1850Integer @minus{}1 1851 1852@item N 1853Integer 1 1854 1855@item O 1856Zero 1857 1858@item P 1859Integers from 0 to 255 1860@end table 1861 1862@item MIPS---@file{mips.h} 1863@table @code 1864@item d 1865General-purpose integer register 1866 1867@item f 1868Floating-point register (if available) 1869 1870@item h 1871@samp{Hi} register 1872 1873@item l 1874@samp{Lo} register 1875 1876@item x 1877@samp{Hi} or @samp{Lo} register 1878 1879@item y 1880General-purpose integer register 1881 1882@item z 1883Floating-point status register 1884 1885@item I 1886Signed 16-bit constant (for arithmetic instructions) 1887 1888@item J 1889Zero 1890 1891@item K 1892Zero-extended 16-bit constant (for logic instructions) 1893 1894@item L 1895Constant with low 16 bits zero (can be loaded with @code{lui}) 1896 1897@item M 189832-bit constant which requires two instructions to load (a constant 1899which is not @samp{I}, @samp{K}, or @samp{L}) 1900 1901@item N 1902Negative 16-bit constant 1903 1904@item O 1905Exact power of two 1906 1907@item P 1908Positive 16-bit constant 1909 1910@item G 1911Floating point zero 1912 1913@item Q 1914Memory reference that can be loaded with more than one instruction 1915(@samp{m} is preferable for @code{asm} statements) 1916 1917@item R 1918Memory reference that can be loaded with one instruction 1919(@samp{m} is preferable for @code{asm} statements) 1920 1921@item S 1922Memory reference in external OSF/rose PIC format 1923(@samp{m} is preferable for @code{asm} statements) 1924@end table 1925 1926@item Motorola 680x0---@file{m68k.h} 1927@table @code 1928@item a 1929Address register 1930 1931@item d 1932Data register 1933 1934@item f 193568881 floating-point register, if available 1936 1937@item x 1938Sun FPA (floating-point) register, if available 1939 1940@item y 1941First 16 Sun FPA registers, if available 1942 1943@item I 1944Integer in the range 1 to 8 1945 1946@item J 194716-bit signed number 1948 1949@item K 1950Signed number whose magnitude is greater than 0x80 1951 1952@item L 1953Integer in the range @minus{}8 to @minus{}1 1954 1955@item M 1956Signed number whose magnitude is greater than 0x100 1957 1958@item G 1959Floating point constant that is not a 68881 constant 1960 1961@item H 1962Floating point constant that can be used by Sun FPA 1963@end table 1964 1965@item Motorola 68HC11 & 68HC12 families---@file{m68hc11.h} 1966@table @code 1967@item a 1968Register 'a' 1969 1970@item b 1971Register 'b' 1972 1973@item d 1974Register 'd' 1975 1976@item q 1977An 8-bit register 1978 1979@item t 1980Temporary soft register _.tmp 1981 1982@item u 1983A soft register _.d1 to _.d31 1984 1985@item w 1986Stack pointer register 1987 1988@item x 1989Register 'x' 1990 1991@item y 1992Register 'y' 1993 1994@item z 1995Pseudo register 'z' (replaced by 'x' or 'y' at the end) 1996 1997@item A 1998An address register: x, y or z 1999 2000@item B 2001An address register: x or y 2002 2003@item D 2004Register pair (x:d) to form a 32-bit value 2005 2006@item L 2007Constants in the range @minus{}65536 to 65535 2008 2009@item M 2010Constants whose 16-bit low part is zero 2011 2012@item N 2013Constant integer 1 or @minus{}1 2014 2015@item O 2016Constant integer 16 2017 2018@item P 2019Constants in the range @minus{}8 to 2 2020 2021@end table 2022 2023@need 1000 2024@item SPARC---@file{sparc.h} 2025@table @code 2026@item f 2027Floating-point register on the SPARC-V8 architecture and 2028lower floating-point register on the SPARC-V9 architecture. 2029 2030@item e 2031Floating-point register. It is equivalent to @samp{f} on the 2032SPARC-V8 architecture and contains both lower and upper 2033floating-point registers on the SPARC-V9 architecture. 2034 2035@item c 2036Floating-point condition code register. 2037 2038@item d 2039Lower floating-point register. It is only valid on the SPARC-V9 2040architecture when the Visual Instruction Set is available. 2041 2042@item b 2043Floating-point register. It is only valid on the SPARC-V9 architecture 2044when the Visual Instruction Set is available. 2045 2046@item h 204764-bit global or out register for the SPARC-V8+ architecture. 2048 2049@item I 2050Signed 13-bit constant 2051 2052@item J 2053Zero 2054 2055@item K 205632-bit constant with the low 12 bits clear (a constant that can be 2057loaded with the @code{sethi} instruction) 2058 2059@item L 2060A constant in the range supported by @code{movcc} instructions 2061 2062@item M 2063A constant in the range supported by @code{movrcc} instructions 2064 2065@item N 2066Same as @samp{K}, except that it verifies that bits that are not in the 2067lower 32-bit range are all zero. Must be used instead of @samp{K} for 2068modes wider than @code{SImode} 2069 2070@item O 2071The constant 4096 2072 2073@item G 2074Floating-point zero 2075 2076@item H 2077Signed 13-bit constant, sign-extended to 32 or 64 bits 2078 2079@item Q 2080Floating-point constant whose integral representation can 2081be moved into an integer register using a single sethi 2082instruction 2083 2084@item R 2085Floating-point constant whose integral representation can 2086be moved into an integer register using a single mov 2087instruction 2088 2089@item S 2090Floating-point constant whose integral representation can 2091be moved into an integer register using a high/lo_sum 2092instruction sequence 2093 2094@item T 2095Memory address aligned to an 8-byte boundary 2096 2097@item U 2098Even register 2099 2100@item W 2101Memory address for @samp{e} constraint registers. 2102 2103@end table 2104 2105@item TMS320C3x/C4x---@file{c4x.h} 2106@table @code 2107@item a 2108Auxiliary (address) register (ar0-ar7) 2109 2110@item b 2111Stack pointer register (sp) 2112 2113@item c 2114Standard (32-bit) precision integer register 2115 2116@item f 2117Extended (40-bit) precision register (r0-r11) 2118 2119@item k 2120Block count register (bk) 2121 2122@item q 2123Extended (40-bit) precision low register (r0-r7) 2124 2125@item t 2126Extended (40-bit) precision register (r0-r1) 2127 2128@item u 2129Extended (40-bit) precision register (r2-r3) 2130 2131@item v 2132Repeat count register (rc) 2133 2134@item x 2135Index register (ir0-ir1) 2136 2137@item y 2138Status (condition code) register (st) 2139 2140@item z 2141Data page register (dp) 2142 2143@item G 2144Floating-point zero 2145 2146@item H 2147Immediate 16-bit floating-point constant 2148 2149@item I 2150Signed 16-bit constant 2151 2152@item J 2153Signed 8-bit constant 2154 2155@item K 2156Signed 5-bit constant 2157 2158@item L 2159Unsigned 16-bit constant 2160 2161@item M 2162Unsigned 8-bit constant 2163 2164@item N 2165Ones complement of unsigned 16-bit constant 2166 2167@item O 2168High 16-bit constant (32-bit constant with 16 LSBs zero) 2169 2170@item Q 2171Indirect memory reference with signed 8-bit or index register displacement 2172 2173@item R 2174Indirect memory reference with unsigned 5-bit displacement 2175 2176@item S 2177Indirect memory reference with 1 bit or index register displacement 2178 2179@item T 2180Direct memory reference 2181 2182@item U 2183Symbolic address 2184 2185@end table 2186 2187@item S/390 and zSeries---@file{s390.h} 2188@table @code 2189@item a 2190Address register (general purpose register except r0) 2191 2192@item d 2193Data register (arbitrary general purpose register) 2194 2195@item f 2196Floating-point register 2197 2198@item I 2199Unsigned 8-bit constant (0--255) 2200 2201@item J 2202Unsigned 12-bit constant (0--4095) 2203 2204@item K 2205Signed 16-bit constant (@minus{}32768--32767) 2206 2207@item L 2208Unsigned 16-bit constant (0--65535) 2209 2210@item Q 2211Memory reference without index register 2212 2213@item S 2214Symbolic constant suitable for use with the @code{larl} instruction 2215 2216@end table 2217 2218@item Xstormy16---@file{stormy16.h} 2219@table @code 2220@item a 2221Register r0. 2222 2223@item b 2224Register r1. 2225 2226@item c 2227Register r2. 2228 2229@item d 2230Register r8. 2231 2232@item e 2233Registers r0 through r7. 2234 2235@item t 2236Registers r0 and r1. 2237 2238@item y 2239The carry register. 2240 2241@item z 2242Registers r8 and r9. 2243 2244@item I 2245A constant between 0 and 3 inclusive. 2246 2247@item J 2248A constant that has exactly one bit set. 2249 2250@item K 2251A constant that has exactly one bit clear. 2252 2253@item L 2254A constant between 0 and 255 inclusive. 2255 2256@item M 2257A constant between @minus{}255 and 0 inclusive. 2258 2259@item N 2260A constant between @minus{}3 and 0 inclusive. 2261 2262@item O 2263A constant between 1 and 4 inclusive. 2264 2265@item P 2266A constant between @minus{}4 and @minus{}1 inclusive. 2267 2268@item Q 2269A memory reference that is a stack push. 2270 2271@item R 2272A memory reference that is a stack pop. 2273 2274@item S 2275A memory reference that refers to a constant address of known value. 2276 2277@item T 2278The register indicated by Rx (not implemented yet). 2279 2280@item U 2281A constant that is not between 2 and 15 inclusive. 2282 2283@end table 2284 2285@item Xtensa---@file{xtensa.h} 2286@table @code 2287@item a 2288General-purpose 32-bit register 2289 2290@item b 2291One-bit boolean register 2292 2293@item A 2294MAC16 40-bit accumulator register 2295 2296@item I 2297Signed 12-bit integer constant, for use in MOVI instructions 2298 2299@item J 2300Signed 8-bit integer constant, for use in ADDI instructions 2301 2302@item K 2303Integer constant valid for BccI instructions 2304 2305@item L 2306Unsigned constant valid for BccUI instructions 2307 2308@end table 2309 2310@end table 2311 2312@ifset INTERNALS 2313@node Standard Names 2314@section Standard Pattern Names For Generation 2315@cindex standard pattern names 2316@cindex pattern names 2317@cindex names, pattern 2318 2319Here is a table of the instruction names that are meaningful in the RTL 2320generation pass of the compiler. Giving one of these names to an 2321instruction pattern tells the RTL generation pass that it can use the 2322pattern to accomplish a certain task. 2323 2324@table @asis 2325@cindex @code{mov@var{m}} instruction pattern 2326@item @samp{mov@var{m}} 2327Here @var{m} stands for a two-letter machine mode name, in lower case. 2328This instruction pattern moves data with that machine mode from operand 23291 to operand 0. For example, @samp{movsi} moves full-word data. 2330 2331If operand 0 is a @code{subreg} with mode @var{m} of a register whose 2332own mode is wider than @var{m}, the effect of this instruction is 2333to store the specified value in the part of the register that corresponds 2334to mode @var{m}. Bits outside of @var{m}, but which are within the 2335same target word as the @code{subreg} are undefined. Bits which are 2336outside the target word are left unchanged. 2337 2338This class of patterns is special in several ways. First of all, each 2339of these names up to and including full word size @emph{must} be defined, 2340because there is no other way to copy a datum from one place to another. 2341If there are patterns accepting operands in larger modes, 2342@samp{mov@var{m}} must be defined for integer modes of those sizes. 2343 2344Second, these patterns are not used solely in the RTL generation pass. 2345Even the reload pass can generate move insns to copy values from stack 2346slots into temporary registers. When it does so, one of the operands is 2347a hard register and the other is an operand that can need to be reloaded 2348into a register. 2349 2350@findex force_reg 2351Therefore, when given such a pair of operands, the pattern must generate 2352RTL which needs no reloading and needs no temporary registers---no 2353registers other than the operands. For example, if you support the 2354pattern with a @code{define_expand}, then in such a case the 2355@code{define_expand} mustn't call @code{force_reg} or any other such 2356function which might generate new pseudo registers. 2357 2358This requirement exists even for subword modes on a RISC machine where 2359fetching those modes from memory normally requires several insns and 2360some temporary registers. 2361 2362@findex change_address 2363During reload a memory reference with an invalid address may be passed 2364as an operand. Such an address will be replaced with a valid address 2365later in the reload pass. In this case, nothing may be done with the 2366address except to use it as it stands. If it is copied, it will not be 2367replaced with a valid address. No attempt should be made to make such 2368an address into a valid address and no routine (such as 2369@code{change_address}) that will do so may be called. Note that 2370@code{general_operand} will fail when applied to such an address. 2371 2372@findex reload_in_progress 2373The global variable @code{reload_in_progress} (which must be explicitly 2374declared if required) can be used to determine whether such special 2375handling is required. 2376 2377The variety of operands that have reloads depends on the rest of the 2378machine description, but typically on a RISC machine these can only be 2379pseudo registers that did not get hard registers, while on other 2380machines explicit memory references will get optional reloads. 2381 2382If a scratch register is required to move an object to or from memory, 2383it can be allocated using @code{gen_reg_rtx} prior to life analysis. 2384 2385If there are cases which need scratch registers during or after reload, 2386you must define @code{SECONDARY_INPUT_RELOAD_CLASS} and/or 2387@code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide 2388patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle 2389them. @xref{Register Classes}. 2390 2391@findex no_new_pseudos 2392The global variable @code{no_new_pseudos} can be used to determine if it 2393is unsafe to create new pseudo registers. If this variable is nonzero, then 2394it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo. 2395 2396The constraints on a @samp{mov@var{m}} must permit moving any hard 2397register to any other hard register provided that 2398@code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and 2399@code{REGISTER_MOVE_COST} applied to their classes returns a value of 2. 2400 2401It is obligatory to support floating point @samp{mov@var{m}} 2402instructions into and out of any registers that can hold fixed point 2403values, because unions and structures (which have modes @code{SImode} or 2404@code{DImode}) can be in those registers and they may have floating 2405point members. 2406 2407There may also be a need to support fixed point @samp{mov@var{m}} 2408instructions in and out of floating point registers. Unfortunately, I 2409have forgotten why this was so, and I don't know whether it is still 2410true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in 2411floating point registers, then the constraints of the fixed point 2412@samp{mov@var{m}} instructions must be designed to avoid ever trying to 2413reload into a floating point register. 2414 2415@cindex @code{reload_in} instruction pattern 2416@cindex @code{reload_out} instruction pattern 2417@item @samp{reload_in@var{m}} 2418@itemx @samp{reload_out@var{m}} 2419Like @samp{mov@var{m}}, but used when a scratch register is required to 2420move between operand 0 and operand 1. Operand 2 describes the scratch 2421register. See the discussion of the @code{SECONDARY_RELOAD_CLASS} 2422macro in @pxref{Register Classes}. 2423 2424There are special restrictions on the form of the @code{match_operand}s 2425used in these patterns. First, only the predicate for the reload 2426operand is examined, i.e., @code{reload_in} examines operand 1, but not 2427the predicates for operand 0 or 2. Second, there may be only one 2428alternative in the constraints. Third, only a single register class 2429letter may be used for the constraint; subsequent constraint letters 2430are ignored. As a special exception, an empty constraint string 2431matches the @code{ALL_REGS} register class. This may relieve ports 2432of the burden of defining an @code{ALL_REGS} constraint letter just 2433for these patterns. 2434 2435@cindex @code{movstrict@var{m}} instruction pattern 2436@item @samp{movstrict@var{m}} 2437Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg} 2438with mode @var{m} of a register whose natural mode is wider, 2439the @samp{movstrict@var{m}} instruction is guaranteed not to alter 2440any of the register except the part which belongs to mode @var{m}. 2441 2442@cindex @code{load_multiple} instruction pattern 2443@item @samp{load_multiple} 2444Load several consecutive memory locations into consecutive registers. 2445Operand 0 is the first of the consecutive registers, operand 1 2446is the first memory location, and operand 2 is a constant: the 2447number of consecutive registers. 2448 2449Define this only if the target machine really has such an instruction; 2450do not define this if the most efficient way of loading consecutive 2451registers from memory is to do them one at a time. 2452 2453On some machines, there are restrictions as to which consecutive 2454registers can be stored into memory, such as particular starting or 2455ending register numbers or only a range of valid counts. For those 2456machines, use a @code{define_expand} (@pxref{Expander Definitions}) 2457and make the pattern fail if the restrictions are not met. 2458 2459Write the generated insn as a @code{parallel} with elements being a 2460@code{set} of one register from the appropriate memory location (you may 2461also need @code{use} or @code{clobber} elements). Use a 2462@code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See 2463@file{rs6000.md} for examples of the use of this insn pattern. 2464 2465@cindex @samp{store_multiple} instruction pattern 2466@item @samp{store_multiple} 2467Similar to @samp{load_multiple}, but store several consecutive registers 2468into consecutive memory locations. Operand 0 is the first of the 2469consecutive memory locations, operand 1 is the first register, and 2470operand 2 is a constant: the number of consecutive registers. 2471 2472@cindex @code{push@var{m}} instruction pattern 2473@item @samp{push@var{m}} 2474Output a push instruction. Operand 0 is value to push. Used only when 2475@code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be 2476missing and in such case an @code{mov} expander is used instead, with a 2477@code{MEM} expression forming the push operation. The @code{mov} expander 2478method is deprecated. 2479 2480@cindex @code{add@var{m}3} instruction pattern 2481@item @samp{add@var{m}3} 2482Add operand 2 and operand 1, storing the result in operand 0. All operands 2483must have mode @var{m}. This can be used even on two-address machines, by 2484means of constraints requiring operands 1 and 0 to be the same location. 2485 2486@cindex @code{sub@var{m}3} instruction pattern 2487@cindex @code{mul@var{m}3} instruction pattern 2488@cindex @code{div@var{m}3} instruction pattern 2489@cindex @code{udiv@var{m}3} instruction pattern 2490@cindex @code{mod@var{m}3} instruction pattern 2491@cindex @code{umod@var{m}3} instruction pattern 2492@cindex @code{smin@var{m}3} instruction pattern 2493@cindex @code{smax@var{m}3} instruction pattern 2494@cindex @code{umin@var{m}3} instruction pattern 2495@cindex @code{umax@var{m}3} instruction pattern 2496@cindex @code{and@var{m}3} instruction pattern 2497@cindex @code{ior@var{m}3} instruction pattern 2498@cindex @code{xor@var{m}3} instruction pattern 2499@item @samp{sub@var{m}3}, @samp{mul@var{m}3} 2500@itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3} 2501@itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3} 2502@itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} 2503Similar, for other arithmetic operations. 2504@cindex @code{min@var{m}3} instruction pattern 2505@cindex @code{max@var{m}3} instruction pattern 2506@itemx @samp{min@var{m}3}, @samp{max@var{m}3} 2507Floating point min and max operations. If both operands are zeros, 2508or if either operand is NaN, then it is unspecified which of the two 2509operands is returned as the result. 2510 2511 2512@cindex @code{mulhisi3} instruction pattern 2513@item @samp{mulhisi3} 2514Multiply operands 1 and 2, which have mode @code{HImode}, and store 2515a @code{SImode} product in operand 0. 2516 2517@cindex @code{mulqihi3} instruction pattern 2518@cindex @code{mulsidi3} instruction pattern 2519@item @samp{mulqihi3}, @samp{mulsidi3} 2520Similar widening-multiplication instructions of other widths. 2521 2522@cindex @code{umulqihi3} instruction pattern 2523@cindex @code{umulhisi3} instruction pattern 2524@cindex @code{umulsidi3} instruction pattern 2525@item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3} 2526Similar widening-multiplication instructions that do unsigned 2527multiplication. 2528 2529@cindex @code{smul@var{m}3_highpart} instruction pattern 2530@item @samp{smul@var{m}3_highpart} 2531Perform a signed multiplication of operands 1 and 2, which have mode 2532@var{m}, and store the most significant half of the product in operand 0. 2533The least significant half of the product is discarded. 2534 2535@cindex @code{umul@var{m}3_highpart} instruction pattern 2536@item @samp{umul@var{m}3_highpart} 2537Similar, but the multiplication is unsigned. 2538 2539@cindex @code{divmod@var{m}4} instruction pattern 2540@item @samp{divmod@var{m}4} 2541Signed division that produces both a quotient and a remainder. 2542Operand 1 is divided by operand 2 to produce a quotient stored 2543in operand 0 and a remainder stored in operand 3. 2544 2545For machines with an instruction that produces both a quotient and a 2546remainder, provide a pattern for @samp{divmod@var{m}4} but do not 2547provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This 2548allows optimization in the relatively common case when both the quotient 2549and remainder are computed. 2550 2551If an instruction that just produces a quotient or just a remainder 2552exists and is more efficient than the instruction that produces both, 2553write the output routine of @samp{divmod@var{m}4} to call 2554@code{find_reg_note} and look for a @code{REG_UNUSED} note on the 2555quotient or remainder and generate the appropriate instruction. 2556 2557@cindex @code{udivmod@var{m}4} instruction pattern 2558@item @samp{udivmod@var{m}4} 2559Similar, but does unsigned division. 2560 2561@cindex @code{ashl@var{m}3} instruction pattern 2562@item @samp{ashl@var{m}3} 2563Arithmetic-shift operand 1 left by a number of bits specified by operand 25642, and store the result in operand 0. Here @var{m} is the mode of 2565operand 0 and operand 1; operand 2's mode is specified by the 2566instruction pattern, and the compiler will convert the operand to that 2567mode before generating the instruction. 2568 2569@cindex @code{ashr@var{m}3} instruction pattern 2570@cindex @code{lshr@var{m}3} instruction pattern 2571@cindex @code{rotl@var{m}3} instruction pattern 2572@cindex @code{rotr@var{m}3} instruction pattern 2573@item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3} 2574Other shift and rotate instructions, analogous to the 2575@code{ashl@var{m}3} instructions. 2576 2577@cindex @code{neg@var{m}2} instruction pattern 2578@item @samp{neg@var{m}2} 2579Negate operand 1 and store the result in operand 0. 2580 2581@cindex @code{abs@var{m}2} instruction pattern 2582@item @samp{abs@var{m}2} 2583Store the absolute value of operand 1 into operand 0. 2584 2585@cindex @code{sqrt@var{m}2} instruction pattern 2586@item @samp{sqrt@var{m}2} 2587Store the square root of operand 1 into operand 0. 2588 2589The @code{sqrt} built-in function of C always uses the mode which 2590corresponds to the C data type @code{double} and the @code{sqrtf} 2591built-in function uses the mode which corresponds to the C data 2592type @code{float}. 2593 2594@cindex @code{cos@var{m}2} instruction pattern 2595@item @samp{cos@var{m}2} 2596Store the cosine of operand 1 into operand 0. 2597 2598The @code{cos} built-in function of C always uses the mode which 2599corresponds to the C data type @code{double} and the @code{cosf} 2600built-in function uses the mode which corresponds to the C data 2601type @code{float}. 2602 2603@cindex @code{sin@var{m}2} instruction pattern 2604@item @samp{sin@var{m}2} 2605Store the sine of operand 1 into operand 0. 2606 2607The @code{sin} built-in function of C always uses the mode which 2608corresponds to the C data type @code{double} and the @code{sinf} 2609built-in function uses the mode which corresponds to the C data 2610type @code{float}. 2611 2612@cindex @code{exp@var{m}2} instruction pattern 2613@item @samp{exp@var{m}2} 2614Store the exponential of operand 1 into operand 0. 2615 2616The @code{exp} built-in function of C always uses the mode which 2617corresponds to the C data type @code{double} and the @code{expf} 2618built-in function uses the mode which corresponds to the C data 2619type @code{float}. 2620 2621@cindex @code{log@var{m}2} instruction pattern 2622@item @samp{log@var{m}2} 2623Store the natural logarithm of operand 1 into operand 0. 2624 2625The @code{log} built-in function of C always uses the mode which 2626corresponds to the C data type @code{double} and the @code{logf} 2627built-in function uses the mode which corresponds to the C data 2628type @code{float}. 2629 2630@cindex @code{ffs@var{m}2} instruction pattern 2631@item @samp{ffs@var{m}2} 2632Store into operand 0 one plus the index of the least significant 1-bit 2633of operand 1. If operand 1 is zero, store zero. @var{m} is the mode 2634of operand 0; operand 1's mode is specified by the instruction 2635pattern, and the compiler will convert the operand to that mode before 2636generating the instruction. 2637 2638The @code{ffs} built-in function of C always uses the mode which 2639corresponds to the C data type @code{int}. 2640 2641@cindex @code{one_cmpl@var{m}2} instruction pattern 2642@item @samp{one_cmpl@var{m}2} 2643Store the bitwise-complement of operand 1 into operand 0. 2644 2645@cindex @code{cmp@var{m}} instruction pattern 2646@item @samp{cmp@var{m}} 2647Compare operand 0 and operand 1, and set the condition codes. 2648The RTL pattern should look like this: 2649 2650@smallexample 2651(set (cc0) (compare (match_operand:@var{m} 0 @dots{}) 2652 (match_operand:@var{m} 1 @dots{}))) 2653@end smallexample 2654 2655@cindex @code{tst@var{m}} instruction pattern 2656@item @samp{tst@var{m}} 2657Compare operand 0 against zero, and set the condition codes. 2658The RTL pattern should look like this: 2659 2660@smallexample 2661(set (cc0) (match_operand:@var{m} 0 @dots{})) 2662@end smallexample 2663 2664@samp{tst@var{m}} patterns should not be defined for machines that do 2665not use @code{(cc0)}. Doing so would confuse the optimizer since it 2666would no longer be clear which @code{set} operations were comparisons. 2667The @samp{cmp@var{m}} patterns should be used instead. 2668 2669@cindex @code{movstr@var{m}} instruction pattern 2670@item @samp{movstr@var{m}} 2671Block move instruction. The addresses of the destination and source 2672strings are the first two operands, and both are in mode @code{Pmode}. 2673 2674The number of bytes to move is the third operand, in mode @var{m}. 2675Usually, you specify @code{word_mode} for @var{m}. However, if you can 2676generate better code knowing the range of valid lengths is smaller than 2677those representable in a full word, you should provide a pattern with a 2678mode corresponding to the range of values you can handle efficiently 2679(e.g., @code{QImode} for values in the range 0--127; note we avoid numbers 2680that appear negative) and also a pattern with @code{word_mode}. 2681 2682The fourth operand is the known shared alignment of the source and 2683destination, in the form of a @code{const_int} rtx. Thus, if the 2684compiler knows that both source and destination are word-aligned, 2685it may provide the value 4 for this operand. 2686 2687Descriptions of multiple @code{movstr@var{m}} patterns can only be 2688beneficial if the patterns for smaller modes have fewer restrictions 2689on their first, second and fourth operands. Note that the mode @var{m} 2690in @code{movstr@var{m}} does not impose any restriction on the mode of 2691individually moved data units in the block. 2692 2693These patterns need not give special consideration to the possibility 2694that the source and destination strings might overlap. 2695 2696@cindex @code{clrstr@var{m}} instruction pattern 2697@item @samp{clrstr@var{m}} 2698Block clear instruction. The addresses of the destination string is the 2699first operand, in mode @code{Pmode}. The number of bytes to clear is 2700the second operand, in mode @var{m}. See @samp{movstr@var{m}} for 2701a discussion of the choice of mode. 2702 2703The third operand is the known alignment of the destination, in the form 2704of a @code{const_int} rtx. Thus, if the compiler knows that the 2705destination is word-aligned, it may provide the value 4 for this 2706operand. 2707 2708The use for multiple @code{clrstr@var{m}} is as for @code{movstr@var{m}}. 2709 2710@cindex @code{cmpstr@var{m}} instruction pattern 2711@item @samp{cmpstr@var{m}} 2712Block compare instruction, with five operands. Operand 0 is the output; 2713it has mode @var{m}. The remaining four operands are like the operands 2714of @samp{movstr@var{m}}. The two memory blocks specified are compared 2715byte by byte in lexicographic order. The effect of the instruction is 2716to store a value in operand 0 whose sign indicates the result of the 2717comparison. 2718 2719@cindex @code{strlen@var{m}} instruction pattern 2720@item @samp{strlen@var{m}} 2721Compute the length of a string, with three operands. 2722Operand 0 is the result (of mode @var{m}), operand 1 is 2723a @code{mem} referring to the first character of the string, 2724operand 2 is the character to search for (normally zero), 2725and operand 3 is a constant describing the known alignment 2726of the beginning of the string. 2727 2728@cindex @code{float@var{mn}2} instruction pattern 2729@item @samp{float@var{m}@var{n}2} 2730Convert signed integer operand 1 (valid for fixed point mode @var{m}) to 2731floating point mode @var{n} and store in operand 0 (which has mode 2732@var{n}). 2733 2734@cindex @code{floatuns@var{mn}2} instruction pattern 2735@item @samp{floatuns@var{m}@var{n}2} 2736Convert unsigned integer operand 1 (valid for fixed point mode @var{m}) 2737to floating point mode @var{n} and store in operand 0 (which has mode 2738@var{n}). 2739 2740@cindex @code{fix@var{mn}2} instruction pattern 2741@item @samp{fix@var{m}@var{n}2} 2742Convert operand 1 (valid for floating point mode @var{m}) to fixed 2743point mode @var{n} as a signed number and store in operand 0 (which 2744has mode @var{n}). This instruction's result is defined only when 2745the value of operand 1 is an integer. 2746 2747@cindex @code{fixuns@var{mn}2} instruction pattern 2748@item @samp{fixuns@var{m}@var{n}2} 2749Convert operand 1 (valid for floating point mode @var{m}) to fixed 2750point mode @var{n} as an unsigned number and store in operand 0 (which 2751has mode @var{n}). This instruction's result is defined only when the 2752value of operand 1 is an integer. 2753 2754@cindex @code{ftrunc@var{m}2} instruction pattern 2755@item @samp{ftrunc@var{m}2} 2756Convert operand 1 (valid for floating point mode @var{m}) to an 2757integer value, still represented in floating point mode @var{m}, and 2758store it in operand 0 (valid for floating point mode @var{m}). 2759 2760@cindex @code{fix_trunc@var{mn}2} instruction pattern 2761@item @samp{fix_trunc@var{m}@var{n}2} 2762Like @samp{fix@var{m}@var{n}2} but works for any floating point value 2763of mode @var{m} by converting the value to an integer. 2764 2765@cindex @code{fixuns_trunc@var{mn}2} instruction pattern 2766@item @samp{fixuns_trunc@var{m}@var{n}2} 2767Like @samp{fixuns@var{m}@var{n}2} but works for any floating point 2768value of mode @var{m} by converting the value to an integer. 2769 2770@cindex @code{trunc@var{mn}2} instruction pattern 2771@item @samp{trunc@var{m}@var{n}2} 2772Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and 2773store in operand 0 (which has mode @var{n}). Both modes must be fixed 2774point or both floating point. 2775 2776@cindex @code{extend@var{mn}2} instruction pattern 2777@item @samp{extend@var{m}@var{n}2} 2778Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and 2779store in operand 0 (which has mode @var{n}). Both modes must be fixed 2780point or both floating point. 2781 2782@cindex @code{zero_extend@var{mn}2} instruction pattern 2783@item @samp{zero_extend@var{m}@var{n}2} 2784Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and 2785store in operand 0 (which has mode @var{n}). Both modes must be fixed 2786point. 2787 2788@cindex @code{extv} instruction pattern 2789@item @samp{extv} 2790Extract a bit-field from operand 1 (a register or memory operand), where 2791operand 2 specifies the width in bits and operand 3 the starting bit, 2792and store it in operand 0. Operand 0 must have mode @code{word_mode}. 2793Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often 2794@code{word_mode} is allowed only for registers. Operands 2 and 3 must 2795be valid for @code{word_mode}. 2796 2797The RTL generation pass generates this instruction only with constants 2798for operands 2 and 3. 2799 2800The bit-field value is sign-extended to a full word integer 2801before it is stored in operand 0. 2802 2803@cindex @code{extzv} instruction pattern 2804@item @samp{extzv} 2805Like @samp{extv} except that the bit-field value is zero-extended. 2806 2807@cindex @code{insv} instruction pattern 2808@item @samp{insv} 2809Store operand 3 (which must be valid for @code{word_mode}) into a 2810bit-field in operand 0, where operand 1 specifies the width in bits and 2811operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or 2812@code{word_mode}; often @code{word_mode} is allowed only for registers. 2813Operands 1 and 2 must be valid for @code{word_mode}. 2814 2815The RTL generation pass generates this instruction only with constants 2816for operands 1 and 2. 2817 2818@cindex @code{mov@var{mode}cc} instruction pattern 2819@item @samp{mov@var{mode}cc} 2820Conditionally move operand 2 or operand 3 into operand 0 according to the 2821comparison in operand 1. If the comparison is true, operand 2 is moved 2822into operand 0, otherwise operand 3 is moved. 2823 2824The mode of the operands being compared need not be the same as the operands 2825being moved. Some machines, sparc64 for example, have instructions that 2826conditionally move an integer value based on the floating point condition 2827codes and vice versa. 2828 2829If the machine does not have conditional move instructions, do not 2830define these patterns. 2831 2832@cindex @code{s@var{cond}} instruction pattern 2833@item @samp{s@var{cond}} 2834Store zero or nonzero in the operand according to the condition codes. 2835Value stored is nonzero iff the condition @var{cond} is true. 2836@var{cond} is the name of a comparison operation expression code, such 2837as @code{eq}, @code{lt} or @code{leu}. 2838 2839You specify the mode that the operand must have when you write the 2840@code{match_operand} expression. The compiler automatically sees 2841which mode you have used and supplies an operand of that mode. 2842 2843The value stored for a true condition must have 1 as its low bit, or 2844else must be negative. Otherwise the instruction is not suitable and 2845you should omit it from the machine description. You describe to the 2846compiler exactly which value is stored by defining the macro 2847@code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be 2848found that can be used for all the @samp{s@var{cond}} patterns, you 2849should omit those operations from the machine description. 2850 2851These operations may fail, but should do so only in relatively 2852uncommon cases; if they would fail for common cases involving 2853integer comparisons, it is best to omit these patterns. 2854 2855If these operations are omitted, the compiler will usually generate code 2856that copies the constant one to the target and branches around an 2857assignment of zero to the target. If this code is more efficient than 2858the potential instructions used for the @samp{s@var{cond}} pattern 2859followed by those required to convert the result into a 1 or a zero in 2860@code{SImode}, you should omit the @samp{s@var{cond}} operations from 2861the machine description. 2862 2863@cindex @code{b@var{cond}} instruction pattern 2864@item @samp{b@var{cond}} 2865Conditional branch instruction. Operand 0 is a @code{label_ref} that 2866refers to the label to jump to. Jump if the condition codes meet 2867condition @var{cond}. 2868 2869Some machines do not follow the model assumed here where a comparison 2870instruction is followed by a conditional branch instruction. In that 2871case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should 2872simply store the operands away and generate all the required insns in a 2873@code{define_expand} (@pxref{Expander Definitions}) for the conditional 2874branch operations. All calls to expand @samp{b@var{cond}} patterns are 2875immediately preceded by calls to expand either a @samp{cmp@var{m}} 2876pattern or a @samp{tst@var{m}} pattern. 2877 2878Machines that use a pseudo register for the condition code value, or 2879where the mode used for the comparison depends on the condition being 2880tested, should also use the above mechanism. @xref{Jump Patterns}. 2881 2882The above discussion also applies to the @samp{mov@var{mode}cc} and 2883@samp{s@var{cond}} patterns. 2884 2885@cindex @code{jump} instruction pattern 2886@item @samp{jump} 2887A jump inside a function; an unconditional branch. Operand 0 is the 2888@code{label_ref} of the label to jump to. This pattern name is mandatory 2889on all machines. 2890 2891@cindex @code{call} instruction pattern 2892@item @samp{call} 2893Subroutine call instruction returning no value. Operand 0 is the 2894function to call; operand 1 is the number of bytes of arguments pushed 2895as a @code{const_int}; operand 2 is the number of registers used as 2896operands. 2897 2898On most machines, operand 2 is not actually stored into the RTL 2899pattern. It is supplied for the sake of some RISC machines which need 2900to put this information into the assembler code; they can put it in 2901the RTL instead of operand 1. 2902 2903Operand 0 should be a @code{mem} RTX whose address is the address of the 2904function. Note, however, that this address can be a @code{symbol_ref} 2905expression even if it would not be a legitimate memory address on the 2906target machine. If it is also not a valid argument for a call 2907instruction, the pattern for this operation should be a 2908@code{define_expand} (@pxref{Expander Definitions}) that places the 2909address into a register and uses that register in the call instruction. 2910 2911@cindex @code{call_value} instruction pattern 2912@item @samp{call_value} 2913Subroutine call instruction returning a value. Operand 0 is the hard 2914register in which the value is returned. There are three more 2915operands, the same as the three operands of the @samp{call} 2916instruction (but with numbers increased by one). 2917 2918Subroutines that return @code{BLKmode} objects use the @samp{call} 2919insn. 2920 2921@cindex @code{call_pop} instruction pattern 2922@cindex @code{call_value_pop} instruction pattern 2923@item @samp{call_pop}, @samp{call_value_pop} 2924Similar to @samp{call} and @samp{call_value}, except used if defined and 2925if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel} 2926that contains both the function call and a @code{set} to indicate the 2927adjustment made to the frame pointer. 2928 2929For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these 2930patterns increases the number of functions for which the frame pointer 2931can be eliminated, if desired. 2932 2933@cindex @code{untyped_call} instruction pattern 2934@item @samp{untyped_call} 2935Subroutine call instruction returning a value of any type. Operand 0 is 2936the function to call; operand 1 is a memory location where the result of 2937calling the function is to be stored; operand 2 is a @code{parallel} 2938expression where each element is a @code{set} expression that indicates 2939the saving of a function return value into the result block. 2940 2941This instruction pattern should be defined to support 2942@code{__builtin_apply} on machines where special instructions are needed 2943to call a subroutine with arbitrary arguments or to save the value 2944returned. This instruction pattern is required on machines that have 2945multiple registers that can hold a return value 2946(i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register). 2947 2948@cindex @code{return} instruction pattern 2949@item @samp{return} 2950Subroutine return instruction. This instruction pattern name should be 2951defined only if a single instruction can do all the work of returning 2952from a function. 2953 2954Like the @samp{mov@var{m}} patterns, this pattern is also used after the 2955RTL generation phase. In this case it is to support machines where 2956multiple instructions are usually needed to return from a function, but 2957some class of functions only requires one instruction to implement a 2958return. Normally, the applicable functions are those which do not need 2959to save any registers or allocate stack space. 2960 2961@findex reload_completed 2962@findex leaf_function_p 2963For such machines, the condition specified in this pattern should only 2964be true when @code{reload_completed} is nonzero and the function's 2965epilogue would only be a single instruction. For machines with register 2966windows, the routine @code{leaf_function_p} may be used to determine if 2967a register window push is required. 2968 2969Machines that have conditional return instructions should define patterns 2970such as 2971 2972@smallexample 2973(define_insn "" 2974 [(set (pc) 2975 (if_then_else (match_operator 2976 0 "comparison_operator" 2977 [(cc0) (const_int 0)]) 2978 (return) 2979 (pc)))] 2980 "@var{condition}" 2981 "@dots{}") 2982@end smallexample 2983 2984where @var{condition} would normally be the same condition specified on the 2985named @samp{return} pattern. 2986 2987@cindex @code{untyped_return} instruction pattern 2988@item @samp{untyped_return} 2989Untyped subroutine return instruction. This instruction pattern should 2990be defined to support @code{__builtin_return} on machines where special 2991instructions are needed to return a value of any type. 2992 2993Operand 0 is a memory location where the result of calling a function 2994with @code{__builtin_apply} is stored; operand 1 is a @code{parallel} 2995expression where each element is a @code{set} expression that indicates 2996the restoring of a function return value from the result block. 2997 2998@cindex @code{nop} instruction pattern 2999@item @samp{nop} 3000No-op instruction. This instruction pattern name should always be defined 3001to output a no-op in assembler code. @code{(const_int 0)} will do as an 3002RTL pattern. 3003 3004@cindex @code{indirect_jump} instruction pattern 3005@item @samp{indirect_jump} 3006An instruction to jump to an address which is operand zero. 3007This pattern name is mandatory on all machines. 3008 3009@cindex @code{casesi} instruction pattern 3010@item @samp{casesi} 3011Instruction to jump through a dispatch table, including bounds checking. 3012This instruction takes five operands: 3013 3014@enumerate 3015@item 3016The index to dispatch on, which has mode @code{SImode}. 3017 3018@item 3019The lower bound for indices in the table, an integer constant. 3020 3021@item 3022The total range of indices in the table---the largest index 3023minus the smallest one (both inclusive). 3024 3025@item 3026A label that precedes the table itself. 3027 3028@item 3029A label to jump to if the index has a value outside the bounds. 3030(If the machine-description macro @code{CASE_DROPS_THROUGH} is defined, 3031then an out-of-bounds index drops through to the code following 3032the jump table instead of jumping to this label. In that case, 3033this label is not actually used by the @samp{casesi} instruction, 3034but it is always provided as an operand.) 3035@end enumerate 3036 3037The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a 3038@code{jump_insn}. The number of elements in the table is one plus the 3039difference between the upper bound and the lower bound. 3040 3041@cindex @code{tablejump} instruction pattern 3042@item @samp{tablejump} 3043Instruction to jump to a variable address. This is a low-level 3044capability which can be used to implement a dispatch table when there 3045is no @samp{casesi} pattern. 3046 3047This pattern requires two operands: the address or offset, and a label 3048which should immediately precede the jump table. If the macro 3049@code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first 3050operand is an offset which counts from the address of the table; otherwise, 3051it is an absolute address to jump to. In either case, the first operand has 3052mode @code{Pmode}. 3053 3054The @samp{tablejump} insn is always the last insn before the jump 3055table it uses. Its assembler code normally has no need to use the 3056second operand, but you should incorporate it in the RTL pattern so 3057that the jump optimizer will not delete the table as unreachable code. 3058 3059 3060@cindex @code{decrement_and_branch_until_zero} instruction pattern 3061@item @samp{decrement_and_branch_until_zero} 3062Conditional branch instruction that decrements a register and 3063jumps if the register is nonzero. Operand 0 is the register to 3064decrement and test; operand 1 is the label to jump to if the 3065register is nonzero. @xref{Looping Patterns}. 3066 3067This optional instruction pattern is only used by the combiner, 3068typically for loops reversed by the loop optimizer when strength 3069reduction is enabled. 3070 3071@cindex @code{doloop_end} instruction pattern 3072@item @samp{doloop_end} 3073Conditional branch instruction that decrements a register and jumps if 3074the register is nonzero. This instruction takes five operands: Operand 30750 is the register to decrement and test; operand 1 is the number of loop 3076iterations as a @code{const_int} or @code{const0_rtx} if this cannot be 3077determined until run-time; operand 2 is the actual or estimated maximum 3078number of iterations as a @code{const_int}; operand 3 is the number of 3079enclosed loops as a @code{const_int} (an innermost loop has a value of 30801); operand 4 is the label to jump to if the register is nonzero. 3081@xref{Looping Patterns}. 3082 3083This optional instruction pattern should be defined for machines with 3084low-overhead looping instructions as the loop optimizer will try to 3085modify suitable loops to utilize it. If nested low-overhead looping is 3086not supported, use a @code{define_expand} (@pxref{Expander Definitions}) 3087and make the pattern fail if operand 3 is not @code{const1_rtx}. 3088Similarly, if the actual or estimated maximum number of iterations is 3089too large for this instruction, make it fail. 3090 3091@cindex @code{doloop_begin} instruction pattern 3092@item @samp{doloop_begin} 3093Companion instruction to @code{doloop_end} required for machines that 3094need to perform some initialization, such as loading special registers 3095used by a low-overhead looping instruction. If initialization insns do 3096not always need to be emitted, use a @code{define_expand} 3097(@pxref{Expander Definitions}) and make it fail. 3098 3099 3100@cindex @code{canonicalize_funcptr_for_compare} instruction pattern 3101@item @samp{canonicalize_funcptr_for_compare} 3102Canonicalize the function pointer in operand 1 and store the result 3103into operand 0. 3104 3105Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1 3106may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc 3107and also has mode @code{Pmode}. 3108 3109Canonicalization of a function pointer usually involves computing 3110the address of the function which would be called if the function 3111pointer were used in an indirect call. 3112 3113Only define this pattern if function pointers on the target machine 3114can have different values but still call the same function when 3115used in an indirect call. 3116 3117@cindex @code{save_stack_block} instruction pattern 3118@cindex @code{save_stack_function} instruction pattern 3119@cindex @code{save_stack_nonlocal} instruction pattern 3120@cindex @code{restore_stack_block} instruction pattern 3121@cindex @code{restore_stack_function} instruction pattern 3122@cindex @code{restore_stack_nonlocal} instruction pattern 3123@item @samp{save_stack_block} 3124@itemx @samp{save_stack_function} 3125@itemx @samp{save_stack_nonlocal} 3126@itemx @samp{restore_stack_block} 3127@itemx @samp{restore_stack_function} 3128@itemx @samp{restore_stack_nonlocal} 3129Most machines save and restore the stack pointer by copying it to or 3130from an object of mode @code{Pmode}. Do not define these patterns on 3131such machines. 3132 3133Some machines require special handling for stack pointer saves and 3134restores. On those machines, define the patterns corresponding to the 3135non-standard cases by using a @code{define_expand} (@pxref{Expander 3136Definitions}) that produces the required insns. The three types of 3137saves and restores are: 3138 3139@enumerate 3140@item 3141@samp{save_stack_block} saves the stack pointer at the start of a block 3142that allocates a variable-sized object, and @samp{restore_stack_block} 3143restores the stack pointer when the block is exited. 3144 3145@item 3146@samp{save_stack_function} and @samp{restore_stack_function} do a 3147similar job for the outermost block of a function and are used when the 3148function allocates variable-sized objects or calls @code{alloca}. Only 3149the epilogue uses the restored stack pointer, allowing a simpler save or 3150restore sequence on some machines. 3151 3152@item 3153@samp{save_stack_nonlocal} is used in functions that contain labels 3154branched to by nested functions. It saves the stack pointer in such a 3155way that the inner function can use @samp{restore_stack_nonlocal} to 3156restore the stack pointer. The compiler generates code to restore the 3157frame and argument pointer registers, but some machines require saving 3158and restoring additional data such as register window information or 3159stack backchains. Place insns in these patterns to save and restore any 3160such required data. 3161@end enumerate 3162 3163When saving the stack pointer, operand 0 is the save area and operand 1 3164is the stack pointer. The mode used to allocate the save area defaults 3165to @code{Pmode} but you can override that choice by defining the 3166@code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must 3167specify an integral mode, or @code{VOIDmode} if no save area is needed 3168for a particular type of save (either because no save is needed or 3169because a machine-specific save area can be used). Operand 0 is the 3170stack pointer and operand 1 is the save area for restore operations. If 3171@samp{save_stack_block} is defined, operand 0 must not be 3172@code{VOIDmode} since these saves can be arbitrarily nested. 3173 3174A save area is a @code{mem} that is at a constant offset from 3175@code{virtual_stack_vars_rtx} when the stack pointer is saved for use by 3176nonlocal gotos and a @code{reg} in the other two cases. 3177 3178@cindex @code{allocate_stack} instruction pattern 3179@item @samp{allocate_stack} 3180Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from 3181the stack pointer to create space for dynamically allocated data. 3182 3183Store the resultant pointer to this space into operand 0. If you 3184are allocating space from the main stack, do this by emitting a 3185move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0. 3186If you are allocating the space elsewhere, generate code to copy the 3187location of the space to operand 0. In the latter case, you must 3188ensure this space gets freed when the corresponding space on the main 3189stack is free. 3190 3191Do not define this pattern if all that must be done is the subtraction. 3192Some machines require other operations such as stack probes or 3193maintaining the back chain. Define this pattern to emit those 3194operations in addition to updating the stack pointer. 3195 3196@cindex @code{probe} instruction pattern 3197@item @samp{probe} 3198Some machines require instructions to be executed after space is 3199allocated from the stack, for example to generate a reference at 3200the bottom of the stack. 3201 3202If you need to emit instructions before the stack has been adjusted, 3203put them into the @samp{allocate_stack} pattern. Otherwise, define 3204this pattern to emit the required instructions. 3205 3206No operands are provided. 3207 3208@cindex @code{check_stack} instruction pattern 3209@item @samp{check_stack} 3210If stack checking cannot be done on your system by probing the stack with 3211a load or store instruction (@pxref{Stack Checking}), define this pattern 3212to perform the needed check and signaling an error if the stack 3213has overflowed. The single operand is the location in the stack furthest 3214from the current stack pointer that you need to validate. Normally, 3215on machines where this pattern is needed, you would obtain the stack 3216limit from a global or thread-specific variable or register. 3217 3218@cindex @code{nonlocal_goto} instruction pattern 3219@item @samp{nonlocal_goto} 3220Emit code to generate a non-local goto, e.g., a jump from one function 3221to a label in an outer function. This pattern has four arguments, 3222each representing a value to be used in the jump. The first 3223argument is to be loaded into the frame pointer, the second is 3224the address to branch to (code to dispatch to the actual label), 3225the third is the address of a location where the stack is saved, 3226and the last is the address of the label, to be placed in the 3227location for the incoming static chain. 3228 3229On most machines you need not define this pattern, since GCC will 3230already generate the correct code, which is to load the frame pointer 3231and static chain, restore the stack (using the 3232@samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly 3233to the dispatcher. You need only define this pattern if this code will 3234not work on your machine. 3235 3236@cindex @code{nonlocal_goto_receiver} instruction pattern 3237@item @samp{nonlocal_goto_receiver} 3238This pattern, if defined, contains code needed at the target of a 3239nonlocal goto after the code already generated by GCC@. You will not 3240normally need to define this pattern. A typical reason why you might 3241need this pattern is if some value, such as a pointer to a global table, 3242must be restored when the frame pointer is restored. Note that a nonlocal 3243goto only occurs within a unit-of-translation, so a global table pointer 3244that is shared by all functions of a given module need not be restored. 3245There are no arguments. 3246 3247@cindex @code{exception_receiver} instruction pattern 3248@item @samp{exception_receiver} 3249This pattern, if defined, contains code needed at the site of an 3250exception handler that isn't needed at the site of a nonlocal goto. You 3251will not normally need to define this pattern. A typical reason why you 3252might need this pattern is if some value, such as a pointer to a global 3253table, must be restored after control flow is branched to the handler of 3254an exception. There are no arguments. 3255 3256@cindex @code{builtin_setjmp_setup} instruction pattern 3257@item @samp{builtin_setjmp_setup} 3258This pattern, if defined, contains additional code needed to initialize 3259the @code{jmp_buf}. You will not normally need to define this pattern. 3260A typical reason why you might need this pattern is if some value, such 3261as a pointer to a global table, must be restored. Though it is 3262preferred that the pointer value be recalculated if possible (given the 3263address of a label for instance). The single argument is a pointer to 3264the @code{jmp_buf}. Note that the buffer is five words long and that 3265the first three are normally used by the generic mechanism. 3266 3267@cindex @code{builtin_setjmp_receiver} instruction pattern 3268@item @samp{builtin_setjmp_receiver} 3269This pattern, if defined, contains code needed at the site of an 3270built-in setjmp that isn't needed at the site of a nonlocal goto. You 3271will not normally need to define this pattern. A typical reason why you 3272might need this pattern is if some value, such as a pointer to a global 3273table, must be restored. It takes one argument, which is the label 3274to which builtin_longjmp transfered control; this pattern may be emitted 3275at a small offset from that label. 3276 3277@cindex @code{builtin_longjmp} instruction pattern 3278@item @samp{builtin_longjmp} 3279This pattern, if defined, performs the entire action of the longjmp. 3280You will not normally need to define this pattern unless you also define 3281@code{builtin_setjmp_setup}. The single argument is a pointer to the 3282@code{jmp_buf}. 3283 3284@cindex @code{eh_return} instruction pattern 3285@item @samp{eh_return} 3286This pattern, if defined, affects the way @code{__builtin_eh_return}, 3287and thence the call frame exception handling library routines, are 3288built. It is intended to handle non-trivial actions needed along 3289the abnormal return path. 3290 3291The pattern takes two arguments. The first is an offset to be applied 3292to the stack pointer. It will have been copied to some appropriate 3293location (typically @code{EH_RETURN_STACKADJ_RTX}) which will survive 3294until after reload to when the normal epilogue is generated. 3295The second argument is the address of the exception handler to which 3296the function should return. This will normally need to copied by the 3297pattern to some special register or memory location. 3298 3299This pattern only needs to be defined if call frame exception handling 3300is to be used, and simple moves involving @code{EH_RETURN_STACKADJ_RTX} 3301and @code{EH_RETURN_HANDLER_RTX} are not sufficient. 3302 3303@cindex @code{prologue} instruction pattern 3304@anchor{prologue instruction pattern} 3305@item @samp{prologue} 3306This pattern, if defined, emits RTL for entry to a function. The function 3307entry is responsible for setting up the stack frame, initializing the frame 3308pointer register, saving callee saved registers, etc. 3309 3310Using a prologue pattern is generally preferred over defining 3311@code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue. 3312 3313The @code{prologue} pattern is particularly useful for targets which perform 3314instruction scheduling. 3315 3316@cindex @code{epilogue} instruction pattern 3317@anchor{epilogue instruction pattern} 3318@item @samp{epilogue} 3319This pattern emits RTL for exit from a function. The function 3320exit is responsible for deallocating the stack frame, restoring callee saved 3321registers and emitting the return instruction. 3322 3323Using an epilogue pattern is generally preferred over defining 3324@code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue. 3325 3326The @code{epilogue} pattern is particularly useful for targets which perform 3327instruction scheduling or which have delay slots for their return instruction. 3328 3329@cindex @code{sibcall_epilogue} instruction pattern 3330@item @samp{sibcall_epilogue} 3331This pattern, if defined, emits RTL for exit from a function without the final 3332branch back to the calling function. This pattern will be emitted before any 3333sibling call (aka tail call) sites. 3334 3335The @code{sibcall_epilogue} pattern must not clobber any arguments used for 3336parameter passing or any stack slots for arguments passed to the current 3337function. 3338 3339@cindex @code{trap} instruction pattern 3340@item @samp{trap} 3341This pattern, if defined, signals an error, typically by causing some 3342kind of signal to be raised. Among other places, it is used by the Java 3343front end to signal `invalid array index' exceptions. 3344 3345@cindex @code{conditional_trap} instruction pattern 3346@item @samp{conditional_trap} 3347Conditional trap instruction. Operand 0 is a piece of RTL which 3348performs a comparison. Operand 1 is the trap code, an integer. 3349 3350A typical @code{conditional_trap} pattern looks like 3351 3352@smallexample 3353(define_insn "conditional_trap" 3354 [(trap_if (match_operator 0 "trap_operator" 3355 [(cc0) (const_int 0)]) 3356 (match_operand 1 "const_int_operand" "i"))] 3357 "" 3358 "@dots{}") 3359@end smallexample 3360 3361@cindex @code{prefetch} instruction pattern 3362@item @samp{prefetch} 3363 3364This pattern, if defined, emits code for a non-faulting data prefetch 3365instruction. Operand 0 is the address of the memory to prefetch. Operand 1 3366is a constant 1 if the prefetch is preparing for a write to the memory 3367address, or a constant 0 otherwise. Operand 2 is the expected degree of 3368temporal locality of the data and is a value between 0 and 3, inclusive; 0 3369means that the data has no temporal locality, so it need not be left in the 3370cache after the access; 3 means that the data has a high degree of temporal 3371locality and should be left in all levels of cache possible; 1 and 2 mean, 3372respectively, a low or moderate degree of temporal locality. 3373 3374Targets that do not support write prefetches or locality hints can ignore 3375the values of operands 1 and 2. 3376 3377@end table 3378 3379@node Pattern Ordering 3380@section When the Order of Patterns Matters 3381@cindex Pattern Ordering 3382@cindex Ordering of Patterns 3383 3384Sometimes an insn can match more than one instruction pattern. Then the 3385pattern that appears first in the machine description is the one used. 3386Therefore, more specific patterns (patterns that will match fewer things) 3387and faster instructions (those that will produce better code when they 3388do match) should usually go first in the description. 3389 3390In some cases the effect of ordering the patterns can be used to hide 3391a pattern when it is not valid. For example, the 68000 has an 3392instruction for converting a fullword to floating point and another 3393for converting a byte to floating point. An instruction converting 3394an integer to floating point could match either one. We put the 3395pattern to convert the fullword first to make sure that one will 3396be used rather than the other. (Otherwise a large integer might 3397be generated as a single-byte immediate quantity, which would not work.) 3398Instead of using this pattern ordering it would be possible to make the 3399pattern for convert-a-byte smart enough to deal properly with any 3400constant value. 3401 3402@node Dependent Patterns 3403@section Interdependence of Patterns 3404@cindex Dependent Patterns 3405@cindex Interdependence of Patterns 3406 3407Every machine description must have a named pattern for each of the 3408conditional branch names @samp{b@var{cond}}. The recognition template 3409must always have the form 3410 3411@example 3412(set (pc) 3413 (if_then_else (@var{cond} (cc0) (const_int 0)) 3414 (label_ref (match_operand 0 "" "")) 3415 (pc))) 3416@end example 3417 3418@noindent 3419In addition, every machine description must have an anonymous pattern 3420for each of the possible reverse-conditional branches. Their templates 3421look like 3422 3423@example 3424(set (pc) 3425 (if_then_else (@var{cond} (cc0) (const_int 0)) 3426 (pc) 3427 (label_ref (match_operand 0 "" "")))) 3428@end example 3429 3430@noindent 3431They are necessary because jump optimization can turn direct-conditional 3432branches into reverse-conditional branches. 3433 3434It is often convenient to use the @code{match_operator} construct to 3435reduce the number of patterns that must be specified for branches. For 3436example, 3437 3438@example 3439(define_insn "" 3440 [(set (pc) 3441 (if_then_else (match_operator 0 "comparison_operator" 3442 [(cc0) (const_int 0)]) 3443 (pc) 3444 (label_ref (match_operand 1 "" ""))))] 3445 "@var{condition}" 3446 "@dots{}") 3447@end example 3448 3449In some cases machines support instructions identical except for the 3450machine mode of one or more operands. For example, there may be 3451``sign-extend halfword'' and ``sign-extend byte'' instructions whose 3452patterns are 3453 3454@example 3455(set (match_operand:SI 0 @dots{}) 3456 (extend:SI (match_operand:HI 1 @dots{}))) 3457 3458(set (match_operand:SI 0 @dots{}) 3459 (extend:SI (match_operand:QI 1 @dots{}))) 3460@end example 3461 3462@noindent 3463Constant integers do not specify a machine mode, so an instruction to 3464extend a constant value could match either pattern. The pattern it 3465actually will match is the one that appears first in the file. For correct 3466results, this must be the one for the widest possible mode (@code{HImode}, 3467here). If the pattern matches the @code{QImode} instruction, the results 3468will be incorrect if the constant value does not actually fit that mode. 3469 3470Such instructions to extend constants are rarely generated because they are 3471optimized away, but they do occasionally happen in nonoptimized 3472compilations. 3473 3474If a constraint in a pattern allows a constant, the reload pass may 3475replace a register with a constant permitted by the constraint in some 3476cases. Similarly for memory references. Because of this substitution, 3477you should not provide separate patterns for increment and decrement 3478instructions. Instead, they should be generated from the same pattern 3479that supports register-register add insns by examining the operands and 3480generating the appropriate machine instruction. 3481 3482@node Jump Patterns 3483@section Defining Jump Instruction Patterns 3484@cindex jump instruction patterns 3485@cindex defining jump instruction patterns 3486 3487For most machines, GCC assumes that the machine has a condition code. 3488A comparison insn sets the condition code, recording the results of both 3489signed and unsigned comparison of the given operands. A separate branch 3490insn tests the condition code and branches or not according its value. 3491The branch insns come in distinct signed and unsigned flavors. Many 3492common machines, such as the VAX, the 68000 and the 32000, work this 3493way. 3494 3495Some machines have distinct signed and unsigned compare instructions, and 3496only one set of conditional branch instructions. The easiest way to handle 3497these machines is to treat them just like the others until the final stage 3498where assembly code is written. At this time, when outputting code for the 3499compare instruction, peek ahead at the following branch using 3500@code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn 3501being output, in the output-writing code in an instruction pattern.) If 3502the RTL says that is an unsigned branch, output an unsigned compare; 3503otherwise output a signed compare. When the branch itself is output, you 3504can treat signed and unsigned branches identically. 3505 3506The reason you can do this is that GCC always generates a pair of 3507consecutive RTL insns, possibly separated by @code{note} insns, one to 3508set the condition code and one to test it, and keeps the pair inviolate 3509until the end. 3510 3511To go with this technique, you must define the machine-description macro 3512@code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no 3513compare instruction is superfluous. 3514 3515Some machines have compare-and-branch instructions and no condition code. 3516A similar technique works for them. When it is time to ``output'' a 3517compare instruction, record its operands in two static variables. When 3518outputting the branch-on-condition-code instruction that follows, actually 3519output a compare-and-branch instruction that uses the remembered operands. 3520 3521It also works to define patterns for compare-and-branch instructions. 3522In optimizing compilation, the pair of compare and branch instructions 3523will be combined according to these patterns. But this does not happen 3524if optimization is not requested. So you must use one of the solutions 3525above in addition to any special patterns you define. 3526 3527In many RISC machines, most instructions do not affect the condition 3528code and there may not even be a separate condition code register. On 3529these machines, the restriction that the definition and use of the 3530condition code be adjacent insns is not necessary and can prevent 3531important optimizations. For example, on the IBM RS/6000, there is a 3532delay for taken branches unless the condition code register is set three 3533instructions earlier than the conditional branch. The instruction 3534scheduler cannot perform this optimization if it is not permitted to 3535separate the definition and use of the condition code register. 3536 3537On these machines, do not use @code{(cc0)}, but instead use a register 3538to represent the condition code. If there is a specific condition code 3539register in the machine, use a hard register. If the condition code or 3540comparison result can be placed in any general register, or if there are 3541multiple condition registers, use a pseudo register. 3542 3543@findex prev_cc0_setter 3544@findex next_cc0_user 3545On some machines, the type of branch instruction generated may depend on 3546the way the condition code was produced; for example, on the 68k and 3547SPARC, setting the condition code directly from an add or subtract 3548instruction does not clear the overflow bit the way that a test 3549instruction does, so a different branch instruction must be used for 3550some conditional branches. For machines that use @code{(cc0)}, the set 3551and use of the condition code must be adjacent (separated only by 3552@code{note} insns) allowing flags in @code{cc_status} to be used. 3553(@xref{Condition Code}.) Also, the comparison and branch insns can be 3554located from each other by using the functions @code{prev_cc0_setter} 3555and @code{next_cc0_user}. 3556 3557However, this is not true on machines that do not use @code{(cc0)}. On 3558those machines, no assumptions can be made about the adjacency of the 3559compare and branch insns and the above methods cannot be used. Instead, 3560we use the machine mode of the condition code register to record 3561different formats of the condition code register. 3562 3563Registers used to store the condition code value should have a mode that 3564is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If 3565additional modes are required (as for the add example mentioned above in 3566the SPARC), define the macro @code{EXTRA_CC_MODES} to list the 3567additional modes required (@pxref{Condition Code}). Also define 3568@code{SELECT_CC_MODE} to choose a mode given an operand of a compare. 3569 3570If it is known during RTL generation that a different mode will be 3571required (for example, if the machine has separate compare instructions 3572for signed and unsigned quantities, like most IBM processors), they can 3573be specified at that time. 3574 3575If the cases that require different modes would be made by instruction 3576combination, the macro @code{SELECT_CC_MODE} determines which machine 3577mode should be used for the comparison result. The patterns should be 3578written using that mode. To support the case of the add on the SPARC 3579discussed above, we have the pattern 3580 3581@smallexample 3582(define_insn "" 3583 [(set (reg:CC_NOOV 0) 3584 (compare:CC_NOOV 3585 (plus:SI (match_operand:SI 0 "register_operand" "%r") 3586 (match_operand:SI 1 "arith_operand" "rI")) 3587 (const_int 0)))] 3588 "" 3589 "@dots{}") 3590@end smallexample 3591 3592The @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode} 3593for comparisons whose argument is a @code{plus}. 3594 3595@node Looping Patterns 3596@section Defining Looping Instruction Patterns 3597@cindex looping instruction patterns 3598@cindex defining looping instruction patterns 3599 3600Some machines have special jump instructions that can be utilized to 3601make loops more efficient. A common example is the 68000 @samp{dbra} 3602instruction which performs a decrement of a register and a branch if the 3603result was greater than zero. Other machines, in particular digital 3604signal processors (DSPs), have special block repeat instructions to 3605provide low-overhead loop support. For example, the TI TMS320C3x/C4x 3606DSPs have a block repeat instruction that loads special registers to 3607mark the top and end of a loop and to count the number of loop 3608iterations. This avoids the need for fetching and executing a 3609@samp{dbra}-like instruction and avoids pipeline stalls associated with 3610the jump. 3611 3612GCC has three special named patterns to support low overhead looping. 3613They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin}, 3614and @samp{doloop_end}. The first pattern, 3615@samp{decrement_and_branch_until_zero}, is not emitted during RTL 3616generation but may be emitted during the instruction combination phase. 3617This requires the assistance of the loop optimizer, using information 3618collected during strength reduction, to reverse a loop to count down to 3619zero. Some targets also require the loop optimizer to add a 3620@code{REG_NONNEG} note to indicate that the iteration count is always 3621positive. This is needed if the target performs a signed loop 3622termination test. For example, the 68000 uses a pattern similar to the 3623following for its @code{dbra} instruction: 3624 3625@smallexample 3626@group 3627(define_insn "decrement_and_branch_until_zero" 3628 [(set (pc) 3629 (if_then_else 3630 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am") 3631 (const_int -1)) 3632 (const_int 0)) 3633 (label_ref (match_operand 1 "" "")) 3634 (pc))) 3635 (set (match_dup 0) 3636 (plus:SI (match_dup 0) 3637 (const_int -1)))] 3638 "find_reg_note (insn, REG_NONNEG, 0)" 3639 "@dots{}") 3640@end group 3641@end smallexample 3642 3643Note that since the insn is both a jump insn and has an output, it must 3644deal with its own reloads, hence the `m' constraints. Also note that 3645since this insn is generated by the instruction combination phase 3646combining two sequential insns together into an implicit parallel insn, 3647the iteration counter needs to be biased by the same amount as the 3648decrement operation, in this case @minus{}1. Note that the following similar 3649pattern will not be matched by the combiner. 3650 3651@smallexample 3652@group 3653(define_insn "decrement_and_branch_until_zero" 3654 [(set (pc) 3655 (if_then_else 3656 (ge (match_operand:SI 0 "general_operand" "+d*am") 3657 (const_int 1)) 3658 (label_ref (match_operand 1 "" "")) 3659 (pc))) 3660 (set (match_dup 0) 3661 (plus:SI (match_dup 0) 3662 (const_int -1)))] 3663 "find_reg_note (insn, REG_NONNEG, 0)" 3664 "@dots{}") 3665@end group 3666@end smallexample 3667 3668The other two special looping patterns, @samp{doloop_begin} and 3669@samp{doloop_end}, are emitted by the loop optimizer for certain 3670well-behaved loops with a finite number of loop iterations using 3671information collected during strength reduction. 3672 3673The @samp{doloop_end} pattern describes the actual looping instruction 3674(or the implicit looping operation) and the @samp{doloop_begin} pattern 3675is an optional companion pattern that can be used for initialization 3676needed for some low-overhead looping instructions. 3677 3678Note that some machines require the actual looping instruction to be 3679emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting 3680the true RTL for a looping instruction at the top of the loop can cause 3681problems with flow analysis. So instead, a dummy @code{doloop} insn is 3682emitted at the end of the loop. The machine dependent reorg pass checks 3683for the presence of this @code{doloop} insn and then searches back to 3684the top of the loop, where it inserts the true looping insn (provided 3685there are no instructions in the loop which would cause problems). Any 3686additional labels can be emitted at this point. In addition, if the 3687desired special iteration counter register was not allocated, this 3688machine dependent reorg pass could emit a traditional compare and jump 3689instruction pair. 3690 3691The essential difference between the 3692@samp{decrement_and_branch_until_zero} and the @samp{doloop_end} 3693patterns is that the loop optimizer allocates an additional pseudo 3694register for the latter as an iteration counter. This pseudo register 3695cannot be used within the loop (i.e., general induction variables cannot 3696be derived from it), however, in many cases the loop induction variable 3697may become redundant and removed by the flow pass. 3698 3699 3700@node Insn Canonicalizations 3701@section Canonicalization of Instructions 3702@cindex canonicalization of instructions 3703@cindex insn canonicalization 3704 3705There are often cases where multiple RTL expressions could represent an 3706operation performed by a single machine instruction. This situation is 3707most commonly encountered with logical, branch, and multiply-accumulate 3708instructions. In such cases, the compiler attempts to convert these 3709multiple RTL expressions into a single canonical form to reduce the 3710number of insn patterns required. 3711 3712In addition to algebraic simplifications, following canonicalizations 3713are performed: 3714 3715@itemize @bullet 3716@item 3717For commutative and comparison operators, a constant is always made the 3718second operand. If a machine only supports a constant as the second 3719operand, only patterns that match a constant in the second operand need 3720be supplied. 3721 3722@cindex @code{neg}, canonicalization of 3723@cindex @code{not}, canonicalization of 3724@cindex @code{mult}, canonicalization of 3725@cindex @code{plus}, canonicalization of 3726@cindex @code{minus}, canonicalization of 3727For these operators, if only one operand is a @code{neg}, @code{not}, 3728@code{mult}, @code{plus}, or @code{minus} expression, it will be the 3729first operand. 3730 3731@item 3732In combinations of @code{neg}, @code{mult}, @code{plus}, and 3733@code{minus}, the @code{neg} operations (if any) will be moved inside 3734the operations as far as possible. For instance, 3735@code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but 3736@code{(plus (mult (neg A) B) C)} is canonicalized as 3737@code{(minus A (mult B C))}. 3738 3739@cindex @code{compare}, canonicalization of 3740@item 3741For the @code{compare} operator, a constant is always the second operand 3742on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other 3743machines, there are rare cases where the compiler might want to construct 3744a @code{compare} with a constant as the first operand. However, these 3745cases are not common enough for it to be worthwhile to provide a pattern 3746matching a constant as the first operand unless the machine actually has 3747such an instruction. 3748 3749An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or 3750@code{minus} is made the first operand under the same conditions as 3751above. 3752 3753@item 3754@code{(minus @var{x} (const_int @var{n}))} is converted to 3755@code{(plus @var{x} (const_int @var{-n}))}. 3756 3757@item 3758Within address computations (i.e., inside @code{mem}), a left shift is 3759converted into the appropriate multiplication by a power of two. 3760 3761@cindex @code{ior}, canonicalization of 3762@cindex @code{and}, canonicalization of 3763@cindex De Morgan's law 3764@item 3765De`Morgan's Law is used to move bitwise negation inside a bitwise 3766logical-and or logical-or operation. If this results in only one 3767operand being a @code{not} expression, it will be the first one. 3768 3769A machine that has an instruction that performs a bitwise logical-and of one 3770operand with the bitwise negation of the other should specify the pattern 3771for that instruction as 3772 3773@example 3774(define_insn "" 3775 [(set (match_operand:@var{m} 0 @dots{}) 3776 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) 3777 (match_operand:@var{m} 2 @dots{})))] 3778 "@dots{}" 3779 "@dots{}") 3780@end example 3781 3782@noindent 3783Similarly, a pattern for a ``NAND'' instruction should be written 3784 3785@example 3786(define_insn "" 3787 [(set (match_operand:@var{m} 0 @dots{}) 3788 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) 3789 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))] 3790 "@dots{}" 3791 "@dots{}") 3792@end example 3793 3794In both cases, it is not necessary to include patterns for the many 3795logically equivalent RTL expressions. 3796 3797@cindex @code{xor}, canonicalization of 3798@item 3799The only possible RTL expressions involving both bitwise exclusive-or 3800and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})} 3801and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}. 3802 3803@item 3804The sum of three items, one of which is a constant, will only appear in 3805the form 3806 3807@example 3808(plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant}) 3809@end example 3810 3811@item 3812On machines that do not use @code{cc0}, 3813@code{(compare @var{x} (const_int 0))} will be converted to 3814@var{x}. 3815 3816@cindex @code{zero_extract}, canonicalization of 3817@cindex @code{sign_extract}, canonicalization of 3818@item 3819Equality comparisons of a group of bits (usually a single bit) with zero 3820will be written using @code{zero_extract} rather than the equivalent 3821@code{and} or @code{sign_extract} operations. 3822 3823@end itemize 3824 3825@node Expander Definitions 3826@section Defining RTL Sequences for Code Generation 3827@cindex expander definitions 3828@cindex code generation RTL sequences 3829@cindex defining RTL sequences for code generation 3830 3831On some target machines, some standard pattern names for RTL generation 3832cannot be handled with single insn, but a sequence of RTL insns can 3833represent them. For these target machines, you can write a 3834@code{define_expand} to specify how to generate the sequence of RTL@. 3835 3836@findex define_expand 3837A @code{define_expand} is an RTL expression that looks almost like a 3838@code{define_insn}; but, unlike the latter, a @code{define_expand} is used 3839only for RTL generation and it can produce more than one RTL insn. 3840 3841A @code{define_expand} RTX has four operands: 3842 3843@itemize @bullet 3844@item 3845The name. Each @code{define_expand} must have a name, since the only 3846use for it is to refer to it by name. 3847 3848@item 3849The RTL template. This is a vector of RTL expressions representing 3850a sequence of separate instructions. Unlike @code{define_insn}, there 3851is no implicit surrounding @code{PARALLEL}. 3852 3853@item 3854The condition, a string containing a C expression. This expression is 3855used to express how the availability of this pattern depends on 3856subclasses of target machine, selected by command-line options when GCC 3857is run. This is just like the condition of a @code{define_insn} that 3858has a standard name. Therefore, the condition (if present) may not 3859depend on the data in the insn being matched, but only the 3860target-machine-type flags. The compiler needs to test these conditions 3861during initialization in order to learn exactly which named instructions 3862are available in a particular run. 3863 3864@item 3865The preparation statements, a string containing zero or more C 3866statements which are to be executed before RTL code is generated from 3867the RTL template. 3868 3869Usually these statements prepare temporary registers for use as 3870internal operands in the RTL template, but they can also generate RTL 3871insns directly by calling routines such as @code{emit_insn}, etc. 3872Any such insns precede the ones that come from the RTL template. 3873@end itemize 3874 3875Every RTL insn emitted by a @code{define_expand} must match some 3876@code{define_insn} in the machine description. Otherwise, the compiler 3877will crash when trying to generate code for the insn or trying to optimize 3878it. 3879 3880The RTL template, in addition to controlling generation of RTL insns, 3881also describes the operands that need to be specified when this pattern 3882is used. In particular, it gives a predicate for each operand. 3883 3884A true operand, which needs to be specified in order to generate RTL from 3885the pattern, should be described with a @code{match_operand} in its first 3886occurrence in the RTL template. This enters information on the operand's 3887predicate into the tables that record such things. GCC uses the 3888information to preload the operand into a register if that is required for 3889valid RTL code. If the operand is referred to more than once, subsequent 3890references should use @code{match_dup}. 3891 3892The RTL template may also refer to internal ``operands'' which are 3893temporary registers or labels used only within the sequence made by the 3894@code{define_expand}. Internal operands are substituted into the RTL 3895template with @code{match_dup}, never with @code{match_operand}. The 3896values of the internal operands are not passed in as arguments by the 3897compiler when it requests use of this pattern. Instead, they are computed 3898within the pattern, in the preparation statements. These statements 3899compute the values and store them into the appropriate elements of 3900@code{operands} so that @code{match_dup} can find them. 3901 3902There are two special macros defined for use in the preparation statements: 3903@code{DONE} and @code{FAIL}. Use them with a following semicolon, 3904as a statement. 3905 3906@table @code 3907 3908@findex DONE 3909@item DONE 3910Use the @code{DONE} macro to end RTL generation for the pattern. The 3911only RTL insns resulting from the pattern on this occasion will be 3912those already emitted by explicit calls to @code{emit_insn} within the 3913preparation statements; the RTL template will not be generated. 3914 3915@findex FAIL 3916@item FAIL 3917Make the pattern fail on this occasion. When a pattern fails, it means 3918that the pattern was not truly available. The calling routines in the 3919compiler will try other strategies for code generation using other patterns. 3920 3921Failure is currently supported only for binary (addition, multiplication, 3922shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv}) 3923operations. 3924@end table 3925 3926If the preparation falls through (invokes neither @code{DONE} nor 3927@code{FAIL}), then the @code{define_expand} acts like a 3928@code{define_insn} in that the RTL template is used to generate the 3929insn. 3930 3931The RTL template is not used for matching, only for generating the 3932initial insn list. If the preparation statement always invokes 3933@code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple 3934list of operands, such as this example: 3935 3936@smallexample 3937@group 3938(define_expand "addsi3" 3939 [(match_operand:SI 0 "register_operand" "") 3940 (match_operand:SI 1 "register_operand" "") 3941 (match_operand:SI 2 "register_operand" "")] 3942@end group 3943@group 3944 "" 3945 " 3946@{ 3947 handle_add (operands[0], operands[1], operands[2]); 3948 DONE; 3949@}") 3950@end group 3951@end smallexample 3952 3953Here is an example, the definition of left-shift for the SPUR chip: 3954 3955@smallexample 3956@group 3957(define_expand "ashlsi3" 3958 [(set (match_operand:SI 0 "register_operand" "") 3959 (ashift:SI 3960@end group 3961@group 3962 (match_operand:SI 1 "register_operand" "") 3963 (match_operand:SI 2 "nonmemory_operand" "")))] 3964 "" 3965 " 3966@end group 3967@end smallexample 3968 3969@smallexample 3970@group 3971@{ 3972 if (GET_CODE (operands[2]) != CONST_INT 3973 || (unsigned) INTVAL (operands[2]) > 3) 3974 FAIL; 3975@}") 3976@end group 3977@end smallexample 3978 3979@noindent 3980This example uses @code{define_expand} so that it can generate an RTL insn 3981for shifting when the shift-count is in the supported range of 0 to 3 but 3982fail in other cases where machine insns aren't available. When it fails, 3983the compiler tries another strategy using different patterns (such as, a 3984library call). 3985 3986If the compiler were able to handle nontrivial condition-strings in 3987patterns with names, then it would be possible to use a 3988@code{define_insn} in that case. Here is another case (zero-extension 3989on the 68000) which makes more use of the power of @code{define_expand}: 3990 3991@smallexample 3992(define_expand "zero_extendhisi2" 3993 [(set (match_operand:SI 0 "general_operand" "") 3994 (const_int 0)) 3995 (set (strict_low_part 3996 (subreg:HI 3997 (match_dup 0) 3998 0)) 3999 (match_operand:HI 1 "general_operand" ""))] 4000 "" 4001 "operands[1] = make_safe_from (operands[1], operands[0]);") 4002@end smallexample 4003 4004@noindent 4005@findex make_safe_from 4006Here two RTL insns are generated, one to clear the entire output operand 4007and the other to copy the input operand into its low half. This sequence 4008is incorrect if the input operand refers to [the old value of] the output 4009operand, so the preparation statement makes sure this isn't so. The 4010function @code{make_safe_from} copies the @code{operands[1]} into a 4011temporary register if it refers to @code{operands[0]}. It does this 4012by emitting another RTL insn. 4013 4014Finally, a third example shows the use of an internal operand. 4015Zero-extension on the SPUR chip is done by @code{and}-ing the result 4016against a halfword mask. But this mask cannot be represented by a 4017@code{const_int} because the constant value is too large to be legitimate 4018on this machine. So it must be copied into a register with 4019@code{force_reg} and then the register used in the @code{and}. 4020 4021@smallexample 4022(define_expand "zero_extendhisi2" 4023 [(set (match_operand:SI 0 "register_operand" "") 4024 (and:SI (subreg:SI 4025 (match_operand:HI 1 "register_operand" "") 4026 0) 4027 (match_dup 2)))] 4028 "" 4029 "operands[2] 4030 = force_reg (SImode, GEN_INT (65535)); ") 4031@end smallexample 4032 4033@strong{Note:} If the @code{define_expand} is used to serve a 4034standard binary or unary arithmetic operation or a bit-field operation, 4035then the last insn it generates must not be a @code{code_label}, 4036@code{barrier} or @code{note}. It must be an @code{insn}, 4037@code{jump_insn} or @code{call_insn}. If you don't need a real insn 4038at the end, emit an insn to copy the result of the operation into 4039itself. Such an insn will generate no code, but it can avoid problems 4040in the compiler. 4041 4042@node Insn Splitting 4043@section Defining How to Split Instructions 4044@cindex insn splitting 4045@cindex instruction splitting 4046@cindex splitting instructions 4047 4048There are two cases where you should specify how to split a pattern 4049into multiple insns. On machines that have instructions requiring 4050delay slots (@pxref{Delay Slots}) or that have instructions whose 4051output is not available for multiple cycles (@pxref{Processor pipeline 4052description}), the compiler phases that optimize these cases need to 4053be able to move insns into one-instruction delay slots. However, some 4054insns may generate more than one machine instruction. These insns 4055cannot be placed into a delay slot. 4056 4057Often you can rewrite the single insn as a list of individual insns, 4058each corresponding to one machine instruction. The disadvantage of 4059doing so is that it will cause the compilation to be slower and require 4060more space. If the resulting insns are too complex, it may also 4061suppress some optimizations. The compiler splits the insn if there is a 4062reason to believe that it might improve instruction or delay slot 4063scheduling. 4064 4065The insn combiner phase also splits putative insns. If three insns are 4066merged into one insn with a complex expression that cannot be matched by 4067some @code{define_insn} pattern, the combiner phase attempts to split 4068the complex pattern into two insns that are recognized. Usually it can 4069break the complex pattern into two patterns by splitting out some 4070subexpression. However, in some other cases, such as performing an 4071addition of a large constant in two insns on a RISC machine, the way to 4072split the addition into two insns is machine-dependent. 4073 4074@findex define_split 4075The @code{define_split} definition tells the compiler how to split a 4076complex insn into several simpler insns. It looks like this: 4077 4078@smallexample 4079(define_split 4080 [@var{insn-pattern}] 4081 "@var{condition}" 4082 [@var{new-insn-pattern-1} 4083 @var{new-insn-pattern-2} 4084 @dots{}] 4085 "@var{preparation-statements}") 4086@end smallexample 4087 4088@var{insn-pattern} is a pattern that needs to be split and 4089@var{condition} is the final condition to be tested, as in a 4090@code{define_insn}. When an insn matching @var{insn-pattern} and 4091satisfying @var{condition} is found, it is replaced in the insn list 4092with the insns given by @var{new-insn-pattern-1}, 4093@var{new-insn-pattern-2}, etc. 4094 4095The @var{preparation-statements} are similar to those statements that 4096are specified for @code{define_expand} (@pxref{Expander Definitions}) 4097and are executed before the new RTL is generated to prepare for the 4098generated code or emit some insns whose pattern is not fixed. Unlike 4099those in @code{define_expand}, however, these statements must not 4100generate any new pseudo-registers. Once reload has completed, they also 4101must not allocate any space in the stack frame. 4102 4103Patterns are matched against @var{insn-pattern} in two different 4104circumstances. If an insn needs to be split for delay slot scheduling 4105or insn scheduling, the insn is already known to be valid, which means 4106that it must have been matched by some @code{define_insn} and, if 4107@code{reload_completed} is nonzero, is known to satisfy the constraints 4108of that @code{define_insn}. In that case, the new insn patterns must 4109also be insns that are matched by some @code{define_insn} and, if 4110@code{reload_completed} is nonzero, must also satisfy the constraints 4111of those definitions. 4112 4113As an example of this usage of @code{define_split}, consider the following 4114example from @file{a29k.md}, which splits a @code{sign_extend} from 4115@code{HImode} to @code{SImode} into a pair of shift insns: 4116 4117@smallexample 4118(define_split 4119 [(set (match_operand:SI 0 "gen_reg_operand" "") 4120 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] 4121 "" 4122 [(set (match_dup 0) 4123 (ashift:SI (match_dup 1) 4124 (const_int 16))) 4125 (set (match_dup 0) 4126 (ashiftrt:SI (match_dup 0) 4127 (const_int 16)))] 4128 " 4129@{ operands[1] = gen_lowpart (SImode, operands[1]); @}") 4130@end smallexample 4131 4132When the combiner phase tries to split an insn pattern, it is always the 4133case that the pattern is @emph{not} matched by any @code{define_insn}. 4134The combiner pass first tries to split a single @code{set} expression 4135and then the same @code{set} expression inside a @code{parallel}, but 4136followed by a @code{clobber} of a pseudo-reg to use as a scratch 4137register. In these cases, the combiner expects exactly two new insn 4138patterns to be generated. It will verify that these patterns match some 4139@code{define_insn} definitions, so you need not do this test in the 4140@code{define_split} (of course, there is no point in writing a 4141@code{define_split} that will never produce insns that match). 4142 4143Here is an example of this use of @code{define_split}, taken from 4144@file{rs6000.md}: 4145 4146@smallexample 4147(define_split 4148 [(set (match_operand:SI 0 "gen_reg_operand" "") 4149 (plus:SI (match_operand:SI 1 "gen_reg_operand" "") 4150 (match_operand:SI 2 "non_add_cint_operand" "")))] 4151 "" 4152 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 4153 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 4154" 4155@{ 4156 int low = INTVAL (operands[2]) & 0xffff; 4157 int high = (unsigned) INTVAL (operands[2]) >> 16; 4158 4159 if (low & 0x8000) 4160 high++, low |= 0xffff0000; 4161 4162 operands[3] = GEN_INT (high << 16); 4163 operands[4] = GEN_INT (low); 4164@}") 4165@end smallexample 4166 4167Here the predicate @code{non_add_cint_operand} matches any 4168@code{const_int} that is @emph{not} a valid operand of a single add 4169insn. The add with the smaller displacement is written so that it 4170can be substituted into the address of a subsequent operation. 4171 4172An example that uses a scratch register, from the same file, generates 4173an equality comparison of a register and a large constant: 4174 4175@smallexample 4176(define_split 4177 [(set (match_operand:CC 0 "cc_reg_operand" "") 4178 (compare:CC (match_operand:SI 1 "gen_reg_operand" "") 4179 (match_operand:SI 2 "non_short_cint_operand" ""))) 4180 (clobber (match_operand:SI 3 "gen_reg_operand" ""))] 4181 "find_single_use (operands[0], insn, 0) 4182 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ 4183 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" 4184 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) 4185 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] 4186 " 4187@{ 4188 /* Get the constant we are comparing against, C, and see what it 4189 looks like sign-extended to 16 bits. Then see what constant 4190 could be XOR'ed with C to get the sign-extended value. */ 4191 4192 int c = INTVAL (operands[2]); 4193 int sextc = (c << 16) >> 16; 4194 int xorv = c ^ sextc; 4195 4196 operands[4] = GEN_INT (xorv); 4197 operands[5] = GEN_INT (sextc); 4198@}") 4199@end smallexample 4200 4201To avoid confusion, don't write a single @code{define_split} that 4202accepts some insns that match some @code{define_insn} as well as some 4203insns that don't. Instead, write two separate @code{define_split} 4204definitions, one for the insns that are valid and one for the insns that 4205are not valid. 4206 4207The splitter is allowed to split jump instructions into sequence of 4208jumps or create new jumps in while splitting non-jump instructions. As 4209the central flowgraph and branch prediction information needs to be updated, 4210several restriction apply. 4211 4212Splitting of jump instruction into sequence that over by another jump 4213instruction is always valid, as compiler expect identical behavior of new 4214jump. When new sequence contains multiple jump instructions or new labels, 4215more assistance is needed. Splitter is required to create only unconditional 4216jumps, or simple conditional jump instructions. Additionally it must attach a 4217@code{REG_BR_PROB} note to each conditional jump. A global variable 4218@code{split_branch_probability} hold the probability of original branch in case 4219it was an simple conditional jump, @minus{}1 otherwise. To simplify 4220recomputing of edge frequencies, new sequence is required to have only 4221forward jumps to the newly created labels. 4222 4223@findex define_insn_and_split 4224For the common case where the pattern of a define_split exactly matches the 4225pattern of a define_insn, use @code{define_insn_and_split}. It looks like 4226this: 4227 4228@smallexample 4229(define_insn_and_split 4230 [@var{insn-pattern}] 4231 "@var{condition}" 4232 "@var{output-template}" 4233 "@var{split-condition}" 4234 [@var{new-insn-pattern-1} 4235 @var{new-insn-pattern-2} 4236 @dots{}] 4237 "@var{preparation-statements}" 4238 [@var{insn-attributes}]) 4239 4240@end smallexample 4241 4242@var{insn-pattern}, @var{condition}, @var{output-template}, and 4243@var{insn-attributes} are used as in @code{define_insn}. The 4244@var{new-insn-pattern} vector and the @var{preparation-statements} are used as 4245in a @code{define_split}. The @var{split-condition} is also used as in 4246@code{define_split}, with the additional behavior that if the condition starts 4247with @samp{&&}, the condition used for the split will be the constructed as a 4248logical ``and'' of the split condition with the insn condition. For example, 4249from i386.md: 4250 4251@smallexample 4252(define_insn_and_split "zero_extendhisi2_and" 4253 [(set (match_operand:SI 0 "register_operand" "=r") 4254 (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))) 4255 (clobber (reg:CC 17))] 4256 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" 4257 "#" 4258 "&& reload_completed" 4259 [(parallel [(set (match_dup 0) 4260 (and:SI (match_dup 0) (const_int 65535))) 4261 (clobber (reg:CC 17))])] 4262 "" 4263 [(set_attr "type" "alu1")]) 4264 4265@end smallexample 4266 4267In this case, the actual split condition will be 4268@samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}. 4269 4270The @code{define_insn_and_split} construction provides exactly the same 4271functionality as two separate @code{define_insn} and @code{define_split} 4272patterns. It exists for compactness, and as a maintenance tool to prevent 4273having to ensure the two patterns' templates match. 4274 4275@node Including Patterns 4276@section Including Patterns in Machine Descriptions. 4277@cindex insn includes 4278 4279@findex include 4280The @code{include} pattern tells the compiler tools where to 4281look for patterns that are in files other than in the file 4282@file{.md}. This is used only at build time and there is no preprocessing allowed. 4283 4284It looks like: 4285 4286@smallexample 4287 4288(include 4289 @var{pathname}) 4290@end smallexample 4291 4292For example: 4293 4294@smallexample 4295 4296(include "filestuff") 4297 4298@end smallexample 4299 4300Where @var{pathname} is a string that specifies the location of the file, 4301specifies the include file to be in @file{gcc/config/target/filestuff}. The 4302directory @file{gcc/config/target} is regarded as the default directory. 4303 4304 4305Machine descriptions may be split up into smaller more manageable subsections 4306and placed into subdirectories. 4307 4308By specifying: 4309 4310@smallexample 4311 4312(include "BOGUS/filestuff") 4313 4314@end smallexample 4315 4316the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}. 4317 4318Specifying an absolute path for the include file such as; 4319@smallexample 4320 4321(include "/u2/BOGUS/filestuff") 4322 4323@end smallexample 4324is permitted but is not encouraged. 4325 4326@subsection RTL Generation Tool Options for Directory Search 4327@cindex directory options .md 4328@cindex options, directory search 4329@cindex search options 4330 4331The @option{-I@var{dir}} option specifies directories to search for machine descriptions. 4332For example: 4333 4334@smallexample 4335 4336genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md 4337 4338@end smallexample 4339 4340 4341Add the directory @var{dir} to the head of the list of directories to be 4342searched for header files. This can be used to override a system machine definition 4343file, substituting your own version, since these directories are 4344searched before the default machine description file directories. If you use more than 4345one @option{-I} option, the directories are scanned in left-to-right 4346order; the standard default directory come after. 4347 4348 4349@node Peephole Definitions 4350@section Machine-Specific Peephole Optimizers 4351@cindex peephole optimizer definitions 4352@cindex defining peephole optimizers 4353 4354In addition to instruction patterns the @file{md} file may contain 4355definitions of machine-specific peephole optimizations. 4356 4357The combiner does not notice certain peephole optimizations when the data 4358flow in the program does not suggest that it should try them. For example, 4359sometimes two consecutive insns related in purpose can be combined even 4360though the second one does not appear to use a register computed in the 4361first one. A machine-specific peephole optimizer can detect such 4362opportunities. 4363 4364There are two forms of peephole definitions that may be used. The 4365original @code{define_peephole} is run at assembly output time to 4366match insns and substitute assembly text. Use of @code{define_peephole} 4367is deprecated. 4368 4369A newer @code{define_peephole2} matches insns and substitutes new 4370insns. The @code{peephole2} pass is run after register allocation 4371but before scheduling, which may result in much better code for 4372targets that do scheduling. 4373 4374@menu 4375* define_peephole:: RTL to Text Peephole Optimizers 4376* define_peephole2:: RTL to RTL Peephole Optimizers 4377@end menu 4378 4379@node define_peephole 4380@subsection RTL to Text Peephole Optimizers 4381@findex define_peephole 4382 4383@need 1000 4384A definition looks like this: 4385 4386@smallexample 4387(define_peephole 4388 [@var{insn-pattern-1} 4389 @var{insn-pattern-2} 4390 @dots{}] 4391 "@var{condition}" 4392 "@var{template}" 4393 "@var{optional-insn-attributes}") 4394@end smallexample 4395 4396@noindent 4397The last string operand may be omitted if you are not using any 4398machine-specific information in this machine description. If present, 4399it must obey the same rules as in a @code{define_insn}. 4400 4401In this skeleton, @var{insn-pattern-1} and so on are patterns to match 4402consecutive insns. The optimization applies to a sequence of insns when 4403@var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches 4404the next, and so on. 4405 4406Each of the insns matched by a peephole must also match a 4407@code{define_insn}. Peepholes are checked only at the last stage just 4408before code generation, and only optionally. Therefore, any insn which 4409would match a peephole but no @code{define_insn} will cause a crash in code 4410generation in an unoptimized compilation, or at various optimization 4411stages. 4412 4413The operands of the insns are matched with @code{match_operands}, 4414@code{match_operator}, and @code{match_dup}, as usual. What is not 4415usual is that the operand numbers apply to all the insn patterns in the 4416definition. So, you can check for identical operands in two insns by 4417using @code{match_operand} in one insn and @code{match_dup} in the 4418other. 4419 4420The operand constraints used in @code{match_operand} patterns do not have 4421any direct effect on the applicability of the peephole, but they will 4422be validated afterward, so make sure your constraints are general enough 4423to apply whenever the peephole matches. If the peephole matches 4424but the constraints are not satisfied, the compiler will crash. 4425 4426It is safe to omit constraints in all the operands of the peephole; or 4427you can write constraints which serve as a double-check on the criteria 4428previously tested. 4429 4430Once a sequence of insns matches the patterns, the @var{condition} is 4431checked. This is a C expression which makes the final decision whether to 4432perform the optimization (we do so if the expression is nonzero). If 4433@var{condition} is omitted (in other words, the string is empty) then the 4434optimization is applied to every sequence of insns that matches the 4435patterns. 4436 4437The defined peephole optimizations are applied after register allocation 4438is complete. Therefore, the peephole definition can check which 4439operands have ended up in which kinds of registers, just by looking at 4440the operands. 4441 4442@findex prev_active_insn 4443The way to refer to the operands in @var{condition} is to write 4444@code{operands[@var{i}]} for operand number @var{i} (as matched by 4445@code{(match_operand @var{i} @dots{})}). Use the variable @code{insn} 4446to refer to the last of the insns being matched; use 4447@code{prev_active_insn} to find the preceding insns. 4448 4449@findex dead_or_set_p 4450When optimizing computations with intermediate results, you can use 4451@var{condition} to match only when the intermediate results are not used 4452elsewhere. Use the C expression @code{dead_or_set_p (@var{insn}, 4453@var{op})}, where @var{insn} is the insn in which you expect the value 4454to be used for the last time (from the value of @code{insn}, together 4455with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate 4456value (from @code{operands[@var{i}]}). 4457 4458Applying the optimization means replacing the sequence of insns with one 4459new insn. The @var{template} controls ultimate output of assembler code 4460for this combined insn. It works exactly like the template of a 4461@code{define_insn}. Operand numbers in this template are the same ones 4462used in matching the original sequence of insns. 4463 4464The result of a defined peephole optimizer does not need to match any of 4465the insn patterns in the machine description; it does not even have an 4466opportunity to match them. The peephole optimizer definition itself serves 4467as the insn pattern to control how the insn is output. 4468 4469Defined peephole optimizers are run as assembler code is being output, 4470so the insns they produce are never combined or rearranged in any way. 4471 4472Here is an example, taken from the 68000 machine description: 4473 4474@smallexample 4475(define_peephole 4476 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) 4477 (set (match_operand:DF 0 "register_operand" "=f") 4478 (match_operand:DF 1 "register_operand" "ad"))] 4479 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" 4480@{ 4481 rtx xoperands[2]; 4482 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 4483#ifdef MOTOROLA 4484 output_asm_insn ("move.l %1,(sp)", xoperands); 4485 output_asm_insn ("move.l %1,-(sp)", operands); 4486 return "fmove.d (sp)+,%0"; 4487#else 4488 output_asm_insn ("movel %1,sp@@", xoperands); 4489 output_asm_insn ("movel %1,sp@@-", operands); 4490 return "fmoved sp@@+,%0"; 4491#endif 4492@}) 4493@end smallexample 4494 4495@need 1000 4496The effect of this optimization is to change 4497 4498@smallexample 4499@group 4500jbsr _foobar 4501addql #4,sp 4502movel d1,sp@@- 4503movel d0,sp@@- 4504fmoved sp@@+,fp0 4505@end group 4506@end smallexample 4507 4508@noindent 4509into 4510 4511@smallexample 4512@group 4513jbsr _foobar 4514movel d1,sp@@ 4515movel d0,sp@@- 4516fmoved sp@@+,fp0 4517@end group 4518@end smallexample 4519 4520@ignore 4521@findex CC_REVERSED 4522If a peephole matches a sequence including one or more jump insns, you must 4523take account of the flags such as @code{CC_REVERSED} which specify that the 4524condition codes are represented in an unusual manner. The compiler 4525automatically alters any ordinary conditional jumps which occur in such 4526situations, but the compiler cannot alter jumps which have been replaced by 4527peephole optimizations. So it is up to you to alter the assembler code 4528that the peephole produces. Supply C code to write the assembler output, 4529and in this C code check the condition code status flags and change the 4530assembler code as appropriate. 4531@end ignore 4532 4533@var{insn-pattern-1} and so on look @emph{almost} like the second 4534operand of @code{define_insn}. There is one important difference: the 4535second operand of @code{define_insn} consists of one or more RTX's 4536enclosed in square brackets. Usually, there is only one: then the same 4537action can be written as an element of a @code{define_peephole}. But 4538when there are multiple actions in a @code{define_insn}, they are 4539implicitly enclosed in a @code{parallel}. Then you must explicitly 4540write the @code{parallel}, and the square brackets within it, in the 4541@code{define_peephole}. Thus, if an insn pattern looks like this, 4542 4543@smallexample 4544(define_insn "divmodsi4" 4545 [(set (match_operand:SI 0 "general_operand" "=d") 4546 (div:SI (match_operand:SI 1 "general_operand" "0") 4547 (match_operand:SI 2 "general_operand" "dmsK"))) 4548 (set (match_operand:SI 3 "general_operand" "=d") 4549 (mod:SI (match_dup 1) (match_dup 2)))] 4550 "TARGET_68020" 4551 "divsl%.l %2,%3:%0") 4552@end smallexample 4553 4554@noindent 4555then the way to mention this insn in a peephole is as follows: 4556 4557@smallexample 4558(define_peephole 4559 [@dots{} 4560 (parallel 4561 [(set (match_operand:SI 0 "general_operand" "=d") 4562 (div:SI (match_operand:SI 1 "general_operand" "0") 4563 (match_operand:SI 2 "general_operand" "dmsK"))) 4564 (set (match_operand:SI 3 "general_operand" "=d") 4565 (mod:SI (match_dup 1) (match_dup 2)))]) 4566 @dots{}] 4567 @dots{}) 4568@end smallexample 4569 4570@node define_peephole2 4571@subsection RTL to RTL Peephole Optimizers 4572@findex define_peephole2 4573 4574The @code{define_peephole2} definition tells the compiler how to 4575substitute one sequence of instructions for another sequence, 4576what additional scratch registers may be needed and what their 4577lifetimes must be. 4578 4579@smallexample 4580(define_peephole2 4581 [@var{insn-pattern-1} 4582 @var{insn-pattern-2} 4583 @dots{}] 4584 "@var{condition}" 4585 [@var{new-insn-pattern-1} 4586 @var{new-insn-pattern-2} 4587 @dots{}] 4588 "@var{preparation-statements}") 4589@end smallexample 4590 4591The definition is almost identical to @code{define_split} 4592(@pxref{Insn Splitting}) except that the pattern to match is not a 4593single instruction, but a sequence of instructions. 4594 4595It is possible to request additional scratch registers for use in the 4596output template. If appropriate registers are not free, the pattern 4597will simply not match. 4598 4599@findex match_scratch 4600@findex match_dup 4601Scratch registers are requested with a @code{match_scratch} pattern at 4602the top level of the input pattern. The allocated register (initially) will 4603be dead at the point requested within the original sequence. If the scratch 4604is used at more than a single point, a @code{match_dup} pattern at the 4605top level of the input pattern marks the last position in the input sequence 4606at which the register must be available. 4607 4608Here is an example from the IA-32 machine description: 4609 4610@smallexample 4611(define_peephole2 4612 [(match_scratch:SI 2 "r") 4613 (parallel [(set (match_operand:SI 0 "register_operand" "") 4614 (match_operator:SI 3 "arith_or_logical_operator" 4615 [(match_dup 0) 4616 (match_operand:SI 1 "memory_operand" "")])) 4617 (clobber (reg:CC 17))])] 4618 "! optimize_size && ! TARGET_READ_MODIFY" 4619 [(set (match_dup 2) (match_dup 1)) 4620 (parallel [(set (match_dup 0) 4621 (match_op_dup 3 [(match_dup 0) (match_dup 2)])) 4622 (clobber (reg:CC 17))])] 4623 "") 4624@end smallexample 4625 4626@noindent 4627This pattern tries to split a load from its use in the hopes that we'll be 4628able to schedule around the memory load latency. It allocates a single 4629@code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs 4630to be live only at the point just before the arithmetic. 4631 4632A real example requiring extended scratch lifetimes is harder to come by, 4633so here's a silly made-up example: 4634 4635@smallexample 4636(define_peephole2 4637 [(match_scratch:SI 4 "r") 4638 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" "")) 4639 (set (match_operand:SI 2 "" "") (match_dup 1)) 4640 (match_dup 4) 4641 (set (match_operand:SI 3 "" "") (match_dup 1))] 4642 "/* @r{determine 1 does not overlap 0 and 2} */" 4643 [(set (match_dup 4) (match_dup 1)) 4644 (set (match_dup 0) (match_dup 4)) 4645 (set (match_dup 2) (match_dup 4))] 4646 (set (match_dup 3) (match_dup 4))] 4647 "") 4648@end smallexample 4649 4650@noindent 4651If we had not added the @code{(match_dup 4)} in the middle of the input 4652sequence, it might have been the case that the register we chose at the 4653beginning of the sequence is killed by the first or second @code{set}. 4654 4655@node Insn Attributes 4656@section Instruction Attributes 4657@cindex insn attributes 4658@cindex instruction attributes 4659 4660In addition to describing the instruction supported by the target machine, 4661the @file{md} file also defines a group of @dfn{attributes} and a set of 4662values for each. Every generated insn is assigned a value for each attribute. 4663One possible attribute would be the effect that the insn has on the machine's 4664condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC} 4665to track the condition codes. 4666 4667@menu 4668* Defining Attributes:: Specifying attributes and their values. 4669* Expressions:: Valid expressions for attribute values. 4670* Tagging Insns:: Assigning attribute values to insns. 4671* Attr Example:: An example of assigning attributes. 4672* Insn Lengths:: Computing the length of insns. 4673* Constant Attributes:: Defining attributes that are constant. 4674* Delay Slots:: Defining delay slots required for a machine. 4675* Processor pipeline description:: Specifying information for insn scheduling. 4676@end menu 4677 4678@node Defining Attributes 4679@subsection Defining Attributes and their Values 4680@cindex defining attributes and their values 4681@cindex attributes, defining 4682 4683@findex define_attr 4684The @code{define_attr} expression is used to define each attribute required 4685by the target machine. It looks like: 4686 4687@smallexample 4688(define_attr @var{name} @var{list-of-values} @var{default}) 4689@end smallexample 4690 4691@var{name} is a string specifying the name of the attribute being defined. 4692 4693@var{list-of-values} is either a string that specifies a comma-separated 4694list of values that can be assigned to the attribute, or a null string to 4695indicate that the attribute takes numeric values. 4696 4697@var{default} is an attribute expression that gives the value of this 4698attribute for insns that match patterns whose definition does not include 4699an explicit value for this attribute. @xref{Attr Example}, for more 4700information on the handling of defaults. @xref{Constant Attributes}, 4701for information on attributes that do not depend on any particular insn. 4702 4703@findex insn-attr.h 4704For each defined attribute, a number of definitions are written to the 4705@file{insn-attr.h} file. For cases where an explicit set of values is 4706specified for an attribute, the following are defined: 4707 4708@itemize @bullet 4709@item 4710A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}. 4711 4712@item 4713An enumeral class is defined for @samp{attr_@var{name}} with 4714elements of the form @samp{@var{upper-name}_@var{upper-value}} where 4715the attribute name and value are first converted to upper case. 4716 4717@item 4718A function @samp{get_attr_@var{name}} is defined that is passed an insn and 4719returns the attribute value for that insn. 4720@end itemize 4721 4722For example, if the following is present in the @file{md} file: 4723 4724@smallexample 4725(define_attr "type" "branch,fp,load,store,arith" @dots{}) 4726@end smallexample 4727 4728@noindent 4729the following lines will be written to the file @file{insn-attr.h}. 4730 4731@smallexample 4732#define HAVE_ATTR_type 4733enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD, 4734 TYPE_STORE, TYPE_ARITH@}; 4735extern enum attr_type get_attr_type (); 4736@end smallexample 4737 4738If the attribute takes numeric values, no @code{enum} type will be 4739defined and the function to obtain the attribute's value will return 4740@code{int}. 4741 4742@node Expressions 4743@subsection Attribute Expressions 4744@cindex attribute expressions 4745 4746RTL expressions used to define attributes use the codes described above 4747plus a few specific to attribute definitions, to be discussed below. 4748Attribute value expressions must have one of the following forms: 4749 4750@table @code 4751@cindex @code{const_int} and attributes 4752@item (const_int @var{i}) 4753The integer @var{i} specifies the value of a numeric attribute. @var{i} 4754must be non-negative. 4755 4756The value of a numeric attribute can be specified either with a 4757@code{const_int}, or as an integer represented as a string in 4758@code{const_string}, @code{eq_attr} (see below), @code{attr}, 4759@code{symbol_ref}, simple arithmetic expressions, and @code{set_attr} 4760overrides on specific instructions (@pxref{Tagging Insns}). 4761 4762@cindex @code{const_string} and attributes 4763@item (const_string @var{value}) 4764The string @var{value} specifies a constant attribute value. 4765If @var{value} is specified as @samp{"*"}, it means that the default value of 4766the attribute is to be used for the insn containing this expression. 4767@samp{"*"} obviously cannot be used in the @var{default} expression 4768of a @code{define_attr}. 4769 4770If the attribute whose value is being specified is numeric, @var{value} 4771must be a string containing a non-negative integer (normally 4772@code{const_int} would be used in this case). Otherwise, it must 4773contain one of the valid values for the attribute. 4774 4775@cindex @code{if_then_else} and attributes 4776@item (if_then_else @var{test} @var{true-value} @var{false-value}) 4777@var{test} specifies an attribute test, whose format is defined below. 4778The value of this expression is @var{true-value} if @var{test} is true, 4779otherwise it is @var{false-value}. 4780 4781@cindex @code{cond} and attributes 4782@item (cond [@var{test1} @var{value1} @dots{}] @var{default}) 4783The first operand of this expression is a vector containing an even 4784number of expressions and consisting of pairs of @var{test} and @var{value} 4785expressions. The value of the @code{cond} expression is that of the 4786@var{value} corresponding to the first true @var{test} expression. If 4787none of the @var{test} expressions are true, the value of the @code{cond} 4788expression is that of the @var{default} expression. 4789@end table 4790 4791@var{test} expressions can have one of the following forms: 4792 4793@table @code 4794@cindex @code{const_int} and attribute tests 4795@item (const_int @var{i}) 4796This test is true if @var{i} is nonzero and false otherwise. 4797 4798@cindex @code{not} and attributes 4799@cindex @code{ior} and attributes 4800@cindex @code{and} and attributes 4801@item (not @var{test}) 4802@itemx (ior @var{test1} @var{test2}) 4803@itemx (and @var{test1} @var{test2}) 4804These tests are true if the indicated logical function is true. 4805 4806@cindex @code{match_operand} and attributes 4807@item (match_operand:@var{m} @var{n} @var{pred} @var{constraints}) 4808This test is true if operand @var{n} of the insn whose attribute value 4809is being determined has mode @var{m} (this part of the test is ignored 4810if @var{m} is @code{VOIDmode}) and the function specified by the string 4811@var{pred} returns a nonzero value when passed operand @var{n} and mode 4812@var{m} (this part of the test is ignored if @var{pred} is the null 4813string). 4814 4815The @var{constraints} operand is ignored and should be the null string. 4816 4817@cindex @code{le} and attributes 4818@cindex @code{leu} and attributes 4819@cindex @code{lt} and attributes 4820@cindex @code{gt} and attributes 4821@cindex @code{gtu} and attributes 4822@cindex @code{ge} and attributes 4823@cindex @code{geu} and attributes 4824@cindex @code{ne} and attributes 4825@cindex @code{eq} and attributes 4826@cindex @code{plus} and attributes 4827@cindex @code{minus} and attributes 4828@cindex @code{mult} and attributes 4829@cindex @code{div} and attributes 4830@cindex @code{mod} and attributes 4831@cindex @code{abs} and attributes 4832@cindex @code{neg} and attributes 4833@cindex @code{ashift} and attributes 4834@cindex @code{lshiftrt} and attributes 4835@cindex @code{ashiftrt} and attributes 4836@item (le @var{arith1} @var{arith2}) 4837@itemx (leu @var{arith1} @var{arith2}) 4838@itemx (lt @var{arith1} @var{arith2}) 4839@itemx (ltu @var{arith1} @var{arith2}) 4840@itemx (gt @var{arith1} @var{arith2}) 4841@itemx (gtu @var{arith1} @var{arith2}) 4842@itemx (ge @var{arith1} @var{arith2}) 4843@itemx (geu @var{arith1} @var{arith2}) 4844@itemx (ne @var{arith1} @var{arith2}) 4845@itemx (eq @var{arith1} @var{arith2}) 4846These tests are true if the indicated comparison of the two arithmetic 4847expressions is true. Arithmetic expressions are formed with 4848@code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod}, 4849@code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not}, 4850@code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions. 4851 4852@findex get_attr 4853@code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn 4854Lengths},for additional forms). @code{symbol_ref} is a string 4855denoting a C expression that yields an @code{int} when evaluated by the 4856@samp{get_attr_@dots{}} routine. It should normally be a global 4857variable. 4858 4859@findex eq_attr 4860@item (eq_attr @var{name} @var{value}) 4861@var{name} is a string specifying the name of an attribute. 4862 4863@var{value} is a string that is either a valid value for attribute 4864@var{name}, a comma-separated list of values, or @samp{!} followed by a 4865value or list. If @var{value} does not begin with a @samp{!}, this 4866test is true if the value of the @var{name} attribute of the current 4867insn is in the list specified by @var{value}. If @var{value} begins 4868with a @samp{!}, this test is true if the attribute's value is 4869@emph{not} in the specified list. 4870 4871For example, 4872 4873@smallexample 4874(eq_attr "type" "load,store") 4875@end smallexample 4876 4877@noindent 4878is equivalent to 4879 4880@smallexample 4881(ior (eq_attr "type" "load") (eq_attr "type" "store")) 4882@end smallexample 4883 4884If @var{name} specifies an attribute of @samp{alternative}, it refers to the 4885value of the compiler variable @code{which_alternative} 4886(@pxref{Output Statement}) and the values must be small integers. For 4887example, 4888 4889@smallexample 4890(eq_attr "alternative" "2,3") 4891@end smallexample 4892 4893@noindent 4894is equivalent to 4895 4896@smallexample 4897(ior (eq (symbol_ref "which_alternative") (const_int 2)) 4898 (eq (symbol_ref "which_alternative") (const_int 3))) 4899@end smallexample 4900 4901Note that, for most attributes, an @code{eq_attr} test is simplified in cases 4902where the value of the attribute being tested is known for all insns matching 4903a particular pattern. This is by far the most common case. 4904 4905@findex attr_flag 4906@item (attr_flag @var{name}) 4907The value of an @code{attr_flag} expression is true if the flag 4908specified by @var{name} is true for the @code{insn} currently being 4909scheduled. 4910 4911@var{name} is a string specifying one of a fixed set of flags to test. 4912Test the flags @code{forward} and @code{backward} to determine the 4913direction of a conditional branch. Test the flags @code{very_likely}, 4914@code{likely}, @code{very_unlikely}, and @code{unlikely} to determine 4915if a conditional branch is expected to be taken. 4916 4917If the @code{very_likely} flag is true, then the @code{likely} flag is also 4918true. Likewise for the @code{very_unlikely} and @code{unlikely} flags. 4919 4920This example describes a conditional branch delay slot which 4921can be nullified for forward branches that are taken (annul-true) or 4922for backward branches which are not taken (annul-false). 4923 4924@smallexample 4925(define_delay (eq_attr "type" "cbranch") 4926 [(eq_attr "in_branch_delay" "true") 4927 (and (eq_attr "in_branch_delay" "true") 4928 (attr_flag "forward")) 4929 (and (eq_attr "in_branch_delay" "true") 4930 (attr_flag "backward"))]) 4931@end smallexample 4932 4933The @code{forward} and @code{backward} flags are false if the current 4934@code{insn} being scheduled is not a conditional branch. 4935 4936The @code{very_likely} and @code{likely} flags are true if the 4937@code{insn} being scheduled is not a conditional branch. 4938The @code{very_unlikely} and @code{unlikely} flags are false if the 4939@code{insn} being scheduled is not a conditional branch. 4940 4941@code{attr_flag} is only used during delay slot scheduling and has no 4942meaning to other passes of the compiler. 4943 4944@findex attr 4945@item (attr @var{name}) 4946The value of another attribute is returned. This is most useful 4947for numeric attributes, as @code{eq_attr} and @code{attr_flag} 4948produce more efficient code for non-numeric attributes. 4949@end table 4950 4951@node Tagging Insns 4952@subsection Assigning Attribute Values to Insns 4953@cindex tagging insns 4954@cindex assigning attribute values to insns 4955 4956The value assigned to an attribute of an insn is primarily determined by 4957which pattern is matched by that insn (or which @code{define_peephole} 4958generated it). Every @code{define_insn} and @code{define_peephole} can 4959have an optional last argument to specify the values of attributes for 4960matching insns. The value of any attribute not specified in a particular 4961insn is set to the default value for that attribute, as specified in its 4962@code{define_attr}. Extensive use of default values for attributes 4963permits the specification of the values for only one or two attributes 4964in the definition of most insn patterns, as seen in the example in the 4965next section. 4966 4967The optional last argument of @code{define_insn} and 4968@code{define_peephole} is a vector of expressions, each of which defines 4969the value for a single attribute. The most general way of assigning an 4970attribute's value is to use a @code{set} expression whose first operand is an 4971@code{attr} expression giving the name of the attribute being set. The 4972second operand of the @code{set} is an attribute expression 4973(@pxref{Expressions}) giving the value of the attribute. 4974 4975When the attribute value depends on the @samp{alternative} attribute 4976(i.e., which is the applicable alternative in the constraint of the 4977insn), the @code{set_attr_alternative} expression can be used. It 4978allows the specification of a vector of attribute expressions, one for 4979each alternative. 4980 4981@findex set_attr 4982When the generality of arbitrary attribute expressions is not required, 4983the simpler @code{set_attr} expression can be used, which allows 4984specifying a string giving either a single attribute value or a list 4985of attribute values, one for each alternative. 4986 4987The form of each of the above specifications is shown below. In each case, 4988@var{name} is a string specifying the attribute to be set. 4989 4990@table @code 4991@item (set_attr @var{name} @var{value-string}) 4992@var{value-string} is either a string giving the desired attribute value, 4993or a string containing a comma-separated list giving the values for 4994succeeding alternatives. The number of elements must match the number 4995of alternatives in the constraint of the insn pattern. 4996 4997Note that it may be useful to specify @samp{*} for some alternative, in 4998which case the attribute will assume its default value for insns matching 4999that alternative. 5000 5001@findex set_attr_alternative 5002@item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}]) 5003Depending on the alternative of the insn, the value will be one of the 5004specified values. This is a shorthand for using a @code{cond} with 5005tests on the @samp{alternative} attribute. 5006 5007@findex attr 5008@item (set (attr @var{name}) @var{value}) 5009The first operand of this @code{set} must be the special RTL expression 5010@code{attr}, whose sole operand is a string giving the name of the 5011attribute being set. @var{value} is the value of the attribute. 5012@end table 5013 5014The following shows three different ways of representing the same 5015attribute value specification: 5016 5017@smallexample 5018(set_attr "type" "load,store,arith") 5019 5020(set_attr_alternative "type" 5021 [(const_string "load") (const_string "store") 5022 (const_string "arith")]) 5023 5024(set (attr "type") 5025 (cond [(eq_attr "alternative" "1") (const_string "load") 5026 (eq_attr "alternative" "2") (const_string "store")] 5027 (const_string "arith"))) 5028@end smallexample 5029 5030@need 1000 5031@findex define_asm_attributes 5032The @code{define_asm_attributes} expression provides a mechanism to 5033specify the attributes assigned to insns produced from an @code{asm} 5034statement. It has the form: 5035 5036@smallexample 5037(define_asm_attributes [@var{attr-sets}]) 5038@end smallexample 5039 5040@noindent 5041where @var{attr-sets} is specified the same as for both the 5042@code{define_insn} and the @code{define_peephole} expressions. 5043 5044These values will typically be the ``worst case'' attribute values. For 5045example, they might indicate that the condition code will be clobbered. 5046 5047A specification for a @code{length} attribute is handled specially. The 5048way to compute the length of an @code{asm} insn is to multiply the 5049length specified in the expression @code{define_asm_attributes} by the 5050number of machine instructions specified in the @code{asm} statement, 5051determined by counting the number of semicolons and newlines in the 5052string. Therefore, the value of the @code{length} attribute specified 5053in a @code{define_asm_attributes} should be the maximum possible length 5054of a single machine instruction. 5055 5056@node Attr Example 5057@subsection Example of Attribute Specifications 5058@cindex attribute specifications example 5059@cindex attribute specifications 5060 5061The judicious use of defaulting is important in the efficient use of 5062insn attributes. Typically, insns are divided into @dfn{types} and an 5063attribute, customarily called @code{type}, is used to represent this 5064value. This attribute is normally used only to define the default value 5065for other attributes. An example will clarify this usage. 5066 5067Assume we have a RISC machine with a condition code and in which only 5068full-word operations are performed in registers. Let us assume that we 5069can divide all insns into loads, stores, (integer) arithmetic 5070operations, floating point operations, and branches. 5071 5072Here we will concern ourselves with determining the effect of an insn on 5073the condition code and will limit ourselves to the following possible 5074effects: The condition code can be set unpredictably (clobbered), not 5075be changed, be set to agree with the results of the operation, or only 5076changed if the item previously set into the condition code has been 5077modified. 5078 5079Here is part of a sample @file{md} file for such a machine: 5080 5081@smallexample 5082(define_attr "type" "load,store,arith,fp,branch" (const_string "arith")) 5083 5084(define_attr "cc" "clobber,unchanged,set,change0" 5085 (cond [(eq_attr "type" "load") 5086 (const_string "change0") 5087 (eq_attr "type" "store,branch") 5088 (const_string "unchanged") 5089 (eq_attr "type" "arith") 5090 (if_then_else (match_operand:SI 0 "" "") 5091 (const_string "set") 5092 (const_string "clobber"))] 5093 (const_string "clobber"))) 5094 5095(define_insn "" 5096 [(set (match_operand:SI 0 "general_operand" "=r,r,m") 5097 (match_operand:SI 1 "general_operand" "r,m,r"))] 5098 "" 5099 "@@ 5100 move %0,%1 5101 load %0,%1 5102 store %0,%1" 5103 [(set_attr "type" "arith,load,store")]) 5104@end smallexample 5105 5106Note that we assume in the above example that arithmetic operations 5107performed on quantities smaller than a machine word clobber the condition 5108code since they will set the condition code to a value corresponding to the 5109full-word result. 5110 5111@node Insn Lengths 5112@subsection Computing the Length of an Insn 5113@cindex insn lengths, computing 5114@cindex computing the length of an insn 5115 5116For many machines, multiple types of branch instructions are provided, each 5117for different length branch displacements. In most cases, the assembler 5118will choose the correct instruction to use. However, when the assembler 5119cannot do so, GCC can when a special attribute, the @samp{length} 5120attribute, is defined. This attribute must be defined to have numeric 5121values by specifying a null string in its @code{define_attr}. 5122 5123In the case of the @samp{length} attribute, two additional forms of 5124arithmetic terms are allowed in test expressions: 5125 5126@table @code 5127@cindex @code{match_dup} and attributes 5128@item (match_dup @var{n}) 5129This refers to the address of operand @var{n} of the current insn, which 5130must be a @code{label_ref}. 5131 5132@cindex @code{pc} and attributes 5133@item (pc) 5134This refers to the address of the @emph{current} insn. It might have 5135been more consistent with other usage to make this the address of the 5136@emph{next} insn but this would be confusing because the length of the 5137current insn is to be computed. 5138@end table 5139 5140@cindex @code{addr_vec}, length of 5141@cindex @code{addr_diff_vec}, length of 5142For normal insns, the length will be determined by value of the 5143@samp{length} attribute. In the case of @code{addr_vec} and 5144@code{addr_diff_vec} insn patterns, the length is computed as 5145the number of vectors multiplied by the size of each vector. 5146 5147Lengths are measured in addressable storage units (bytes). 5148 5149The following macros can be used to refine the length computation: 5150 5151@table @code 5152@findex FIRST_INSN_ADDRESS 5153@item FIRST_INSN_ADDRESS 5154When the @code{length} insn attribute is used, this macro specifies the 5155value to be assigned to the address of the first insn in a function. If 5156not specified, 0 is used. 5157 5158@findex ADJUST_INSN_LENGTH 5159@item ADJUST_INSN_LENGTH (@var{insn}, @var{length}) 5160If defined, modifies the length assigned to instruction @var{insn} as a 5161function of the context in which it is used. @var{length} is an lvalue 5162that contains the initially computed length of the insn and should be 5163updated with the correct length of the insn. 5164 5165This macro will normally not be required. A case in which it is 5166required is the ROMP@. On this machine, the size of an @code{addr_vec} 5167insn must be increased by two to compensate for the fact that alignment 5168may be required. 5169@end table 5170 5171@findex get_attr_length 5172The routine that returns @code{get_attr_length} (the value of the 5173@code{length} attribute) can be used by the output routine to 5174determine the form of the branch instruction to be written, as the 5175example below illustrates. 5176 5177As an example of the specification of variable-length branches, consider 5178the IBM 360. If we adopt the convention that a register will be set to 5179the starting address of a function, we can jump to labels within 4k of 5180the start using a four-byte instruction. Otherwise, we need a six-byte 5181sequence to load the address from memory and then branch to it. 5182 5183On such a machine, a pattern for a branch instruction might be specified 5184as follows: 5185 5186@smallexample 5187(define_insn "jump" 5188 [(set (pc) 5189 (label_ref (match_operand 0 "" "")))] 5190 "" 5191@{ 5192 return (get_attr_length (insn) == 4 5193 ? "b %l0" : "l r15,=a(%l0); br r15"); 5194@} 5195 [(set (attr "length") 5196 (if_then_else (lt (match_dup 0) (const_int 4096)) 5197 (const_int 4) 5198 (const_int 6)))]) 5199@end smallexample 5200 5201@node Constant Attributes 5202@subsection Constant Attributes 5203@cindex constant attributes 5204 5205A special form of @code{define_attr}, where the expression for the 5206default value is a @code{const} expression, indicates an attribute that 5207is constant for a given run of the compiler. Constant attributes may be 5208used to specify which variety of processor is used. For example, 5209 5210@smallexample 5211(define_attr "cpu" "m88100,m88110,m88000" 5212 (const 5213 (cond [(symbol_ref "TARGET_88100") (const_string "m88100") 5214 (symbol_ref "TARGET_88110") (const_string "m88110")] 5215 (const_string "m88000")))) 5216 5217(define_attr "memory" "fast,slow" 5218 (const 5219 (if_then_else (symbol_ref "TARGET_FAST_MEM") 5220 (const_string "fast") 5221 (const_string "slow")))) 5222@end smallexample 5223 5224The routine generated for constant attributes has no parameters as it 5225does not depend on any particular insn. RTL expressions used to define 5226the value of a constant attribute may use the @code{symbol_ref} form, 5227but may not use either the @code{match_operand} form or @code{eq_attr} 5228forms involving insn attributes. 5229 5230@node Delay Slots 5231@subsection Delay Slot Scheduling 5232@cindex delay slots, defining 5233 5234The insn attribute mechanism can be used to specify the requirements for 5235delay slots, if any, on a target machine. An instruction is said to 5236require a @dfn{delay slot} if some instructions that are physically 5237after the instruction are executed as if they were located before it. 5238Classic examples are branch and call instructions, which often execute 5239the following instruction before the branch or call is performed. 5240 5241On some machines, conditional branch instructions can optionally 5242@dfn{annul} instructions in the delay slot. This means that the 5243instruction will not be executed for certain branch outcomes. Both 5244instructions that annul if the branch is true and instructions that 5245annul if the branch is false are supported. 5246 5247Delay slot scheduling differs from instruction scheduling in that 5248determining whether an instruction needs a delay slot is dependent only 5249on the type of instruction being generated, not on data flow between the 5250instructions. See the next section for a discussion of data-dependent 5251instruction scheduling. 5252 5253@findex define_delay 5254The requirement of an insn needing one or more delay slots is indicated 5255via the @code{define_delay} expression. It has the following form: 5256 5257@smallexample 5258(define_delay @var{test} 5259 [@var{delay-1} @var{annul-true-1} @var{annul-false-1} 5260 @var{delay-2} @var{annul-true-2} @var{annul-false-2} 5261 @dots{}]) 5262@end smallexample 5263 5264@var{test} is an attribute test that indicates whether this 5265@code{define_delay} applies to a particular insn. If so, the number of 5266required delay slots is determined by the length of the vector specified 5267as the second argument. An insn placed in delay slot @var{n} must 5268satisfy attribute test @var{delay-n}. @var{annul-true-n} is an 5269attribute test that specifies which insns may be annulled if the branch 5270is true. Similarly, @var{annul-false-n} specifies which insns in the 5271delay slot may be annulled if the branch is false. If annulling is not 5272supported for that delay slot, @code{(nil)} should be coded. 5273 5274For example, in the common case where branch and call insns require 5275a single delay slot, which may contain any insn other than a branch or 5276call, the following would be placed in the @file{md} file: 5277 5278@smallexample 5279(define_delay (eq_attr "type" "branch,call") 5280 [(eq_attr "type" "!branch,call") (nil) (nil)]) 5281@end smallexample 5282 5283Multiple @code{define_delay} expressions may be specified. In this 5284case, each such expression specifies different delay slot requirements 5285and there must be no insn for which tests in two @code{define_delay} 5286expressions are both true. 5287 5288For example, if we have a machine that requires one delay slot for branches 5289but two for calls, no delay slot can contain a branch or call insn, 5290and any valid insn in the delay slot for the branch can be annulled if the 5291branch is true, we might represent this as follows: 5292 5293@smallexample 5294(define_delay (eq_attr "type" "branch") 5295 [(eq_attr "type" "!branch,call") 5296 (eq_attr "type" "!branch,call") 5297 (nil)]) 5298 5299(define_delay (eq_attr "type" "call") 5300 [(eq_attr "type" "!branch,call") (nil) (nil) 5301 (eq_attr "type" "!branch,call") (nil) (nil)]) 5302@end smallexample 5303@c the above is *still* too long. --mew 4feb93 5304 5305@node Processor pipeline description 5306@subsection Specifying processor pipeline description 5307@cindex processor pipeline description 5308@cindex processor functional units 5309@cindex instruction latency time 5310@cindex interlock delays 5311@cindex data dependence delays 5312@cindex reservation delays 5313@cindex pipeline hazard recognizer 5314@cindex automaton based pipeline description 5315@cindex regular expressions 5316@cindex deterministic finite state automaton 5317@cindex automaton based scheduler 5318@cindex RISC 5319@cindex VLIW 5320 5321To achieve better performance, most modern processors 5322(super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW} 5323processors) have many @dfn{functional units} on which several 5324instructions can be executed simultaneously. An instruction starts 5325execution if its issue conditions are satisfied. If not, the 5326instruction is stalled until its conditions are satisfied. Such 5327@dfn{interlock (pipeline) delay} causes interruption of the fetching 5328of successor instructions (or demands nop instructions, e.g. for some 5329MIPS processors). 5330 5331There are two major kinds of interlock delays in modern processors. 5332The first one is a data dependence delay determining @dfn{instruction 5333latency time}. The instruction execution is not started until all 5334source data have been evaluated by prior instructions (there are more 5335complex cases when the instruction execution starts even when the data 5336are not available but will be ready in given time after the 5337instruction execution start). Taking the data dependence delays into 5338account is simple. The data dependence (true, output, and 5339anti-dependence) delay between two instructions is given by a 5340constant. In most cases this approach is adequate. The second kind 5341of interlock delays is a reservation delay. The reservation delay 5342means that two instructions under execution will be in need of shared 5343processors resources, i.e. buses, internal registers, and/or 5344functional units, which are reserved for some time. Taking this kind 5345of delay into account is complex especially for modern @acronym{RISC} 5346processors. 5347 5348The task of exploiting more processor parallelism is solved by an 5349instruction scheduler. For a better solution to this problem, the 5350instruction scheduler has to have an adequate description of the 5351processor parallelism (or @dfn{pipeline description}). Currently GCC 5352provides two alternative ways to describe processor parallelism, 5353both described below. The first method is outlined in the next section; 5354it was once the only method provided by GCC, and thus is used in a number 5355of exiting ports. The second, and preferred method, specifies functional 5356unit reservations for groups of instructions with the aid of @dfn{regular 5357expressions}. This is called the @dfn{automaton based description}. 5358 5359The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to 5360figure out the possibility of the instruction issue by the processor 5361on a given simulated processor cycle. The pipeline hazard recognizer is 5362automatically generated from the processor pipeline description. The 5363pipeline hazard recognizer generated from the automaton based 5364description is more sophisticated and based on a deterministic finite 5365state automaton (@acronym{DFA}) and therefore faster than one 5366generated from the old description. Furthermore, its speed is not dependent 5367on processor complexity. The instruction issue is possible if there is 5368a transition from one automaton state to another one. 5369 5370You can use any model to describe processor pipeline characteristics 5371or even a mix of them. You could use the old description for some 5372processor submodels and the @acronym{DFA}-based one for the rest 5373processor submodels. 5374 5375In general, the usage of the automaton based description is more 5376preferable. Its model is more rich. It permits to describe more 5377accurately pipeline characteristics of processors which results in 5378improving code quality (although sometimes only on several percent 5379fractions). It will be also used as an infrastructure to implement 5380sophisticated and practical insn scheduling which will try many 5381instruction sequences to choose the best one. 5382 5383 5384@menu 5385* Old pipeline description:: Specifying information for insn scheduling. 5386* Automaton pipeline description:: Describing insn pipeline characteristics. 5387* Comparison of the two descriptions:: Drawbacks of the old pipeline description 5388@end menu 5389 5390@node Old pipeline description 5391@subsubsection Specifying Function Units 5392@cindex old pipeline description 5393@cindex function units, for scheduling 5394 5395On most @acronym{RISC} machines, there are instructions whose results 5396are not available for a specific number of cycles. Common cases are 5397instructions that load data from memory. On many machines, a pipeline 5398stall will result if the data is referenced too soon after the load 5399instruction. 5400 5401In addition, many newer microprocessors have multiple function units, usually 5402one for integer and one for floating point, and often will incur pipeline 5403stalls when a result that is needed is not yet ready. 5404 5405The descriptions in this section allow the specification of how much 5406time must elapse between the execution of an instruction and the time 5407when its result is used. It also allows specification of when the 5408execution of an instruction will delay execution of similar instructions 5409due to function unit conflicts. 5410 5411For the purposes of the specifications in this section, a machine is 5412divided into @dfn{function units}, each of which execute a specific 5413class of instructions in first-in-first-out order. Function units 5414that accept one instruction each cycle and allow a result to be used 5415in the succeeding instruction (usually via forwarding) need not be 5416specified. Classic @acronym{RISC} microprocessors will normally have 5417a single function unit, which we can call @samp{memory}. The newer 5418``superscalar'' processors will often have function units for floating 5419point operations, usually at least a floating point adder and 5420multiplier. 5421 5422@findex define_function_unit 5423Each usage of a function units by a class of insns is specified with a 5424@code{define_function_unit} expression, which looks like this: 5425 5426@smallexample 5427(define_function_unit @var{name} @var{multiplicity} @var{simultaneity} 5428 @var{test} @var{ready-delay} @var{issue-delay} 5429 [@var{conflict-list}]) 5430@end smallexample 5431 5432@var{name} is a string giving the name of the function unit. 5433 5434@var{multiplicity} is an integer specifying the number of identical 5435units in the processor. If more than one unit is specified, they will 5436be scheduled independently. Only truly independent units should be 5437counted; a pipelined unit should be specified as a single unit. (The 5438only common example of a machine that has multiple function units for a 5439single instruction class that are truly independent and not pipelined 5440are the two multiply and two increment units of the CDC 6600.) 5441 5442@var{simultaneity} specifies the maximum number of insns that can be 5443executing in each instance of the function unit simultaneously or zero 5444if the unit is pipelined and has no limit. 5445 5446All @code{define_function_unit} definitions referring to function unit 5447@var{name} must have the same name and values for @var{multiplicity} and 5448@var{simultaneity}. 5449 5450@var{test} is an attribute test that selects the insns we are describing 5451in this definition. Note that an insn may use more than one function 5452unit and a function unit may be specified in more than one 5453@code{define_function_unit}. 5454 5455@var{ready-delay} is an integer that specifies the number of cycles 5456after which the result of the instruction can be used without 5457introducing any stalls. 5458 5459@var{issue-delay} is an integer that specifies the number of cycles 5460after the instruction matching the @var{test} expression begins using 5461this unit until a subsequent instruction can begin. A cost of @var{N} 5462indicates an @var{N-1} cycle delay. A subsequent instruction may also 5463be delayed if an earlier instruction has a longer @var{ready-delay} 5464value. This blocking effect is computed using the @var{simultaneity}, 5465@var{ready-delay}, @var{issue-delay}, and @var{conflict-list} terms. 5466For a normal non-pipelined function unit, @var{simultaneity} is one, the 5467unit is taken to block for the @var{ready-delay} cycles of the executing 5468insn, and smaller values of @var{issue-delay} are ignored. 5469 5470@var{conflict-list} is an optional list giving detailed conflict costs 5471for this unit. If specified, it is a list of condition test expressions 5472to be applied to insns chosen to execute in @var{name} following the 5473particular insn matching @var{test} that is already executing in 5474@var{name}. For each insn in the list, @var{issue-delay} specifies the 5475conflict cost; for insns not in the list, the cost is zero. If not 5476specified, @var{conflict-list} defaults to all instructions that use the 5477function unit. 5478 5479Typical uses of this vector are where a floating point function unit can 5480pipeline either single- or double-precision operations, but not both, or 5481where a memory unit can pipeline loads, but not stores, etc. 5482 5483As an example, consider a classic @acronym{RISC} machine where the 5484result of a load instruction is not available for two cycles (a single 5485``delay'' instruction is required) and where only one load instruction 5486can be executed simultaneously. This would be specified as: 5487 5488@smallexample 5489(define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0) 5490@end smallexample 5491 5492For the case of a floating point function unit that can pipeline either 5493single or double precision, but not both, the following could be specified: 5494 5495@smallexample 5496(define_function_unit 5497 "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")]) 5498(define_function_unit 5499 "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")]) 5500@end smallexample 5501 5502@strong{Note:} The scheduler attempts to avoid function unit conflicts 5503and uses all the specifications in the @code{define_function_unit} 5504expression. It has recently come to our attention that these 5505specifications may not allow modeling of some of the newer 5506``superscalar'' processors that have insns using multiple pipelined 5507units. These insns will cause a potential conflict for the second unit 5508used during their execution and there is no way of representing that 5509conflict. We welcome any examples of how function unit conflicts work 5510in such processors and suggestions for their representation. 5511 5512@node Automaton pipeline description 5513@subsubsection Describing instruction pipeline characteristics 5514@cindex automaton based pipeline description 5515 5516This section describes constructions of the automaton based processor 5517pipeline description. The order of constructions within the machine 5518description file is not important. 5519 5520@findex define_automaton 5521@cindex pipeline hazard recognizer 5522The following optional construction describes names of automata 5523generated and used for the pipeline hazards recognition. Sometimes 5524the generated finite state automaton used by the pipeline hazard 5525recognizer is large. If we use more than one automaton and bind functional 5526units to the automata, the total size of the automata is usually 5527less than the size of the single automaton. If there is no one such 5528construction, only one finite state automaton is generated. 5529 5530@smallexample 5531(define_automaton @var{automata-names}) 5532@end smallexample 5533 5534@var{automata-names} is a string giving names of the automata. The 5535names are separated by commas. All the automata should have unique names. 5536The automaton name is used in the constructions @code{define_cpu_unit} and 5537@code{define_query_cpu_unit}. 5538 5539@findex define_cpu_unit 5540@cindex processor functional units 5541Each processor functional unit used in the description of instruction 5542reservations should be described by the following construction. 5543 5544@smallexample 5545(define_cpu_unit @var{unit-names} [@var{automaton-name}]) 5546@end smallexample 5547 5548@var{unit-names} is a string giving the names of the functional units 5549separated by commas. Don't use name @samp{nothing}, it is reserved 5550for other goals. 5551 5552@var{automaton-name} is a string giving the name of the automaton with 5553which the unit is bound. The automaton should be described in 5554construction @code{define_automaton}. You should give 5555@dfn{automaton-name}, if there is a defined automaton. 5556 5557@findex define_query_cpu_unit 5558@cindex querying function unit reservations 5559The following construction describes CPU functional units analogously 5560to @code{define_cpu_unit}. If we use automata without their 5561minimization, the reservation of such units can be queried for an 5562automaton state. The instruction scheduler never queries reservation 5563of functional units for given automaton state. So as a rule, you 5564don't need this construction. This construction could be used for 5565future code generation goals (e.g. to generate @acronym{VLIW} insn 5566templates). 5567 5568@smallexample 5569(define_query_cpu_unit @var{unit-names} [@var{automaton-name}]) 5570@end smallexample 5571 5572@var{unit-names} is a string giving names of the functional units 5573separated by commas. 5574 5575@var{automaton-name} is a string giving the name of the automaton with 5576which the unit is bound. 5577 5578@findex define_insn_reservation 5579@cindex instruction latency time 5580@cindex regular expressions 5581@cindex data bypass 5582The following construction is the major one to describe pipeline 5583characteristics of an instruction. 5584 5585@smallexample 5586(define_insn_reservation @var{insn-name} @var{default_latency} 5587 @var{condition} @var{regexp}) 5588@end smallexample 5589 5590@var{default_latency} is a number giving latency time of the 5591instruction. There is an important difference between the old 5592description and the automaton based pipeline description. The latency 5593time is used for all dependencies when we use the old description. In 5594the automaton based pipeline description, the given latency time is only 5595used for true dependencies. The cost of anti-dependencies is always 5596zero and the cost of output dependencies is the difference between 5597latency times of the producing and consuming insns (if the difference 5598is negative, the cost is considered to be zero). You can always 5599change the default costs for any description by using the target hook 5600@code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}). 5601 5602@var{insn-name} is a string giving the internal name of the insn. The 5603internal names are used in constructions @code{define_bypass} and in 5604the automaton description file generated for debugging. The internal 5605name has nothing in common with the names in @code{define_insn}. It is a 5606good practice to use insn classes described in the processor manual. 5607 5608@var{condition} defines what RTL insns are described by this 5609construction. You should remember that you will be in trouble if 5610@var{condition} for two or more different 5611@code{define_insn_reservation} constructions is TRUE for an insn. In 5612this case what reservation will be used for the insn is not defined. 5613Such cases are not checked during generation of the pipeline hazards 5614recognizer because in general recognizing that two conditions may have 5615the same value is quite difficult (especially if the conditions 5616contain @code{symbol_ref}). It is also not checked during the 5617pipeline hazard recognizer work because it would slow down the 5618recognizer considerably. 5619 5620@var{regexp} is a string describing the reservation of the cpu's functional 5621units by the instruction. The reservations are described by a regular 5622expression according to the following syntax: 5623 5624@smallexample 5625 regexp = regexp "," oneof 5626 | oneof 5627 5628 oneof = oneof "|" allof 5629 | allof 5630 5631 allof = allof "+" repeat 5632 | repeat 5633 5634 repeat = element "*" number 5635 | element 5636 5637 element = cpu_function_unit_name 5638 | reservation_name 5639 | result_name 5640 | "nothing" 5641 | "(" regexp ")" 5642@end smallexample 5643 5644@itemize @bullet 5645@item 5646@samp{,} is used for describing the start of the next cycle in 5647the reservation. 5648 5649@item 5650@samp{|} is used for describing a reservation described by the first 5651regular expression @strong{or} a reservation described by the second 5652regular expression @strong{or} etc. 5653 5654@item 5655@samp{+} is used for describing a reservation described by the first 5656regular expression @strong{and} a reservation described by the 5657second regular expression @strong{and} etc. 5658 5659@item 5660@samp{*} is used for convenience and simply means a sequence in which 5661the regular expression are repeated @var{number} times with cycle 5662advancing (see @samp{,}). 5663 5664@item 5665@samp{cpu_function_unit_name} denotes reservation of the named 5666functional unit. 5667 5668@item 5669@samp{reservation_name} --- see description of construction 5670@samp{define_reservation}. 5671 5672@item 5673@samp{nothing} denotes no unit reservations. 5674@end itemize 5675 5676@findex define_reservation 5677Sometimes unit reservations for different insns contain common parts. 5678In such case, you can simplify the pipeline description by describing 5679the common part by the following construction 5680 5681@smallexample 5682(define_reservation @var{reservation-name} @var{regexp}) 5683@end smallexample 5684 5685@var{reservation-name} is a string giving name of @var{regexp}. 5686Functional unit names and reservation names are in the same name 5687space. So the reservation names should be different from the 5688functional unit names and can not be the reserved name @samp{nothing}. 5689 5690@findex define_bypass 5691@cindex instruction latency time 5692@cindex data bypass 5693The following construction is used to describe exceptions in the 5694latency time for given instruction pair. This is so called bypasses. 5695 5696@smallexample 5697(define_bypass @var{number} @var{out_insn_names} @var{in_insn_names} 5698 [@var{guard}]) 5699@end smallexample 5700 5701@var{number} defines when the result generated by the instructions 5702given in string @var{out_insn_names} will be ready for the 5703instructions given in string @var{in_insn_names}. The instructions in 5704the string are separated by commas. 5705 5706@var{guard} is an optional string giving the name of a C function which 5707defines an additional guard for the bypass. The function will get the 5708two insns as parameters. If the function returns zero the bypass will 5709be ignored for this case. The additional guard is necessary to 5710recognize complicated bypasses, e.g. when the consumer is only an address 5711of insn @samp{store} (not a stored value). 5712 5713@findex exclusion_set 5714@findex presence_set 5715@findex absence_set 5716@cindex VLIW 5717@cindex RISC 5718Usually the following three constructions are used to describe 5719@acronym{VLIW} processors (more correctly to describe a placement of 5720small insns into @acronym{VLIW} insn slots). Although they can be 5721used for @acronym{RISC} processors too. 5722 5723@smallexample 5724(exclusion_set @var{unit-names} @var{unit-names}) 5725(presence_set @var{unit-names} @var{unit-names}) 5726(absence_set @var{unit-names} @var{unit-names}) 5727@end smallexample 5728 5729@var{unit-names} is a string giving names of functional units 5730separated by commas. 5731 5732The first construction (@samp{exclusion_set}) means that each 5733functional unit in the first string can not be reserved simultaneously 5734with a unit whose name is in the second string and vice versa. For 5735example, the construction is useful for describing processors 5736(e.g. some SPARC processors) with a fully pipelined floating point 5737functional unit which can execute simultaneously only single floating 5738point insns or only double floating point insns. 5739 5740The second construction (@samp{presence_set}) means that each 5741functional unit in the first string can not be reserved unless at 5742least one of units whose names are in the second string is reserved. 5743This is an asymmetric relation. For example, it is useful for 5744description that @acronym{VLIW} @samp{slot1} is reserved after 5745@samp{slot0} reservation. 5746 5747The third construction (@samp{absence_set}) means that each functional 5748unit in the first string can be reserved only if each unit whose name 5749is in the second string is not reserved. This is an asymmetric 5750relation (actually @samp{exclusion_set} is analogous to this one but 5751it is symmetric). For example, it is useful for description that 5752@acronym{VLIW} @samp{slot0} can not be reserved after @samp{slot1} or 5753@samp{slot2} reservation. 5754 5755All functional units mentioned in a set should belong to the same 5756automaton. 5757 5758@findex automata_option 5759@cindex deterministic finite state automaton 5760@cindex nondeterministic finite state automaton 5761@cindex finite state automaton minimization 5762You can control the generator of the pipeline hazard recognizer with 5763the following construction. 5764 5765@smallexample 5766(automata_option @var{options}) 5767@end smallexample 5768 5769@var{options} is a string giving options which affect the generated 5770code. Currently there are the following options: 5771 5772@itemize @bullet 5773@item 5774@dfn{no-minimization} makes no minimization of the automaton. This is 5775only worth to do when we are debugging the description and need to 5776look more accurately at reservations of states. 5777 5778@item 5779@dfn{time} means printing additional time statistics about 5780generation of automata. 5781 5782@item 5783@dfn{v} means a generation of the file describing the result automata. 5784The file has suffix @samp{.dfa} and can be used for the description 5785verification and debugging. 5786 5787@item 5788@dfn{w} means a generation of warning instead of error for 5789non-critical errors. 5790 5791@item 5792@dfn{ndfa} makes nondeterministic finite state automata. This affects 5793the treatment of operator @samp{|} in the regular expressions. The 5794usual treatment of the operator is to try the first alternative and, 5795if the reservation is not possible, the second alternative. The 5796nondeterministic treatment means trying all alternatives, some of them 5797may be rejected by reservations in the subsequent insns. You can not 5798query functional unit reservations in nondeterministic automaton 5799states. 5800@end itemize 5801 5802As an example, consider a superscalar @acronym{RISC} machine which can 5803issue three insns (two integer insns and one floating point insn) on 5804the cycle but can finish only two insns. To describe this, we define 5805the following functional units. 5806 5807@smallexample 5808(define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline") 5809(define_cpu_unit "port0, port1") 5810@end smallexample 5811 5812All simple integer insns can be executed in any integer pipeline and 5813their result is ready in two cycles. The simple integer insns are 5814issued into the first pipeline unless it is reserved, otherwise they 5815are issued into the second pipeline. Integer division and 5816multiplication insns can be executed only in the second integer 5817pipeline and their results are ready correspondingly in 8 and 4 5818cycles. The integer division is not pipelined, i.e. the subsequent 5819integer division insn can not be issued until the current division 5820insn finished. Floating point insns are fully pipelined and their 5821results are ready in 3 cycles. Where the result of a floating point 5822insn is used by an integer insn, an additional delay of one cycle is 5823incurred. To describe all of this we could specify 5824 5825@smallexample 5826(define_cpu_unit "div") 5827 5828(define_insn_reservation "simple" 2 (eq_attr "type" "int") 5829 "(i0_pipeline | i1_pipeline), (port0 | port1)") 5830 5831(define_insn_reservation "mult" 4 (eq_attr "type" "mult") 5832 "i1_pipeline, nothing*2, (port0 | port1)") 5833 5834(define_insn_reservation "div" 8 (eq_attr "type" "div") 5835 "i1_pipeline, div*7, div + (port0 | port1)") 5836 5837(define_insn_reservation "float" 3 (eq_attr "type" "float") 5838 "f_pipeline, nothing, (port0 | port1)) 5839 5840(define_bypass 4 "float" "simple,mult,div") 5841@end smallexample 5842 5843To simplify the description we could describe the following reservation 5844 5845@smallexample 5846(define_reservation "finish" "port0|port1") 5847@end smallexample 5848 5849and use it in all @code{define_insn_reservation} as in the following 5850construction 5851 5852@smallexample 5853(define_insn_reservation "simple" 2 (eq_attr "type" "int") 5854 "(i0_pipeline | i1_pipeline), finish") 5855@end smallexample 5856 5857 5858@node Comparison of the two descriptions 5859@subsubsection Drawbacks of the old pipeline description 5860@cindex old pipeline description 5861@cindex automaton based pipeline description 5862@cindex processor functional units 5863@cindex interlock delays 5864@cindex instruction latency time 5865@cindex pipeline hazard recognizer 5866@cindex data bypass 5867 5868The old instruction level parallelism description and the pipeline 5869hazards recognizer based on it have the following drawbacks in 5870comparison with the @acronym{DFA}-based ones: 5871 5872@itemize @bullet 5873@item 5874Each functional unit is believed to be reserved at the instruction 5875execution start. This is a very inaccurate model for modern 5876processors. 5877 5878@item 5879An inadequate description of instruction latency times. The latency 5880time is bound with a functional unit reserved by an instruction not 5881with the instruction itself. In other words, the description is 5882oriented to describe at most one unit reservation by each instruction. 5883It also does not permit to describe special bypasses between 5884instruction pairs. 5885 5886@item 5887The implementation of the pipeline hazard recognizer interface has 5888constraints on number of functional units. This is a number of bits 5889in integer on the host machine. 5890 5891@item 5892The interface to the pipeline hazard recognizer is more complex than 5893one to the automaton based pipeline recognizer. 5894 5895@item 5896An unnatural description when you write a unit and a condition which 5897selects instructions using the unit. Writing all unit reservations 5898for an instruction (an instruction class) is more natural. 5899 5900@item 5901The recognition of the interlock delays has a slow implementation. The GCC 5902scheduler supports structures which describe the unit reservations. 5903The more functional units a processor has, the slower its pipeline hazard 5904recognizer will be. Such an implementation would become even slower when we 5905allowed to 5906reserve functional units not only at the instruction execution start. 5907In an automaton based pipeline hazard recognizer, speed is not dependent 5908on processor complexity. 5909@end itemize 5910 5911@node Conditional Execution 5912@section Conditional Execution 5913@cindex conditional execution 5914@cindex predication 5915 5916A number of architectures provide for some form of conditional 5917execution, or predication. The hallmark of this feature is the 5918ability to nullify most of the instructions in the instruction set. 5919When the instruction set is large and not entirely symmetric, it 5920can be quite tedious to describe these forms directly in the 5921@file{.md} file. An alternative is the @code{define_cond_exec} template. 5922 5923@findex define_cond_exec 5924@smallexample 5925(define_cond_exec 5926 [@var{predicate-pattern}] 5927 "@var{condition}" 5928 "@var{output-template}") 5929@end smallexample 5930 5931@var{predicate-pattern} is the condition that must be true for the 5932insn to be executed at runtime and should match a relational operator. 5933One can use @code{match_operator} to match several relational operators 5934at once. Any @code{match_operand} operands must have no more than one 5935alternative. 5936 5937@var{condition} is a C expression that must be true for the generated 5938pattern to match. 5939 5940@findex current_insn_predicate 5941@var{output-template} is a string similar to the @code{define_insn} 5942output template (@pxref{Output Template}), except that the @samp{*} 5943and @samp{@@} special cases do not apply. This is only useful if the 5944assembly text for the predicate is a simple prefix to the main insn. 5945In order to handle the general case, there is a global variable 5946@code{current_insn_predicate} that will contain the entire predicate 5947if the current insn is predicated, and will otherwise be @code{NULL}. 5948 5949When @code{define_cond_exec} is used, an implicit reference to 5950the @code{predicable} instruction attribute is made. 5951@xref{Insn Attributes}. This attribute must be boolean (i.e.@: have 5952exactly two elements in its @var{list-of-values}). Further, it must 5953not be used with complex expressions. That is, the default and all 5954uses in the insns must be a simple constant, not dependent on the 5955alternative or anything else. 5956 5957For each @code{define_insn} for which the @code{predicable} 5958attribute is true, a new @code{define_insn} pattern will be 5959generated that matches a predicated version of the instruction. 5960For example, 5961 5962@smallexample 5963(define_insn "addsi" 5964 [(set (match_operand:SI 0 "register_operand" "r") 5965 (plus:SI (match_operand:SI 1 "register_operand" "r") 5966 (match_operand:SI 2 "register_operand" "r")))] 5967 "@var{test1}" 5968 "add %2,%1,%0") 5969 5970(define_cond_exec 5971 [(ne (match_operand:CC 0 "register_operand" "c") 5972 (const_int 0))] 5973 "@var{test2}" 5974 "(%0)") 5975@end smallexample 5976 5977@noindent 5978generates a new pattern 5979 5980@smallexample 5981(define_insn "" 5982 [(cond_exec 5983 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0)) 5984 (set (match_operand:SI 0 "register_operand" "r") 5985 (plus:SI (match_operand:SI 1 "register_operand" "r") 5986 (match_operand:SI 2 "register_operand" "r"))))] 5987 "(@var{test2}) && (@var{test1})" 5988 "(%3) add %2,%1,%0") 5989@end smallexample 5990 5991@node Constant Definitions 5992@section Constant Definitions 5993@cindex constant definitions 5994@findex define_constants 5995 5996Using literal constants inside instruction patterns reduces legibility and 5997can be a maintenance problem. 5998 5999To overcome this problem, you may use the @code{define_constants} 6000expression. It contains a vector of name-value pairs. From that 6001point on, wherever any of the names appears in the MD file, it is as 6002if the corresponding value had been written instead. You may use 6003@code{define_constants} multiple times; each appearance adds more 6004constants to the table. It is an error to redefine a constant with 6005a different value. 6006 6007To come back to the a29k load multiple example, instead of 6008 6009@smallexample 6010(define_insn "" 6011 [(match_parallel 0 "load_multiple_operation" 6012 [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 6013 (match_operand:SI 2 "memory_operand" "m")) 6014 (use (reg:SI 179)) 6015 (clobber (reg:SI 179))])] 6016 "" 6017 "loadm 0,0,%1,%2") 6018@end smallexample 6019 6020You could write: 6021 6022@smallexample 6023(define_constants [ 6024 (R_BP 177) 6025 (R_FC 178) 6026 (R_CR 179) 6027 (R_Q 180) 6028]) 6029 6030(define_insn "" 6031 [(match_parallel 0 "load_multiple_operation" 6032 [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 6033 (match_operand:SI 2 "memory_operand" "m")) 6034 (use (reg:SI R_CR)) 6035 (clobber (reg:SI R_CR))])] 6036 "" 6037 "loadm 0,0,%1,%2") 6038@end smallexample 6039 6040The constants that are defined with a define_constant are also output 6041in the insn-codes.h header file as #defines. 6042@end ifset 6043