1119256Skan@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001, 2169689Skan@c 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 390075Sobrien@c This is part of the GCC manual. 490075Sobrien@c For copying conditions, see the file gcc.texi. 590075Sobrien 690075Sobrien@ifset INTERNALS 790075Sobrien@node Machine Desc 890075Sobrien@chapter Machine Descriptions 990075Sobrien@cindex machine descriptions 1090075Sobrien 1190075SobrienA machine description has two parts: a file of instruction patterns 1290075Sobrien(@file{.md} file) and a C header file of macro definitions. 1390075Sobrien 1490075SobrienThe @file{.md} file for a target machine contains a pattern for each 1590075Sobrieninstruction that the target machine supports (or at least each instruction 1690075Sobrienthat is worth telling the compiler about). It may also contain comments. 1790075SobrienA semicolon causes the rest of the line to be a comment, unless the semicolon 1890075Sobrienis inside a quoted string. 1990075Sobrien 2090075SobrienSee the next chapter for information on the C header file. 2190075Sobrien 2290075Sobrien@menu 2390075Sobrien* Overview:: How the machine description is used. 2490075Sobrien* Patterns:: How to write instruction patterns. 2590075Sobrien* Example:: An explained example of a @code{define_insn} pattern. 2690075Sobrien* RTL Template:: The RTL template defines what insns match a pattern. 2790075Sobrien* Output Template:: The output template says how to make assembler code 2890075Sobrien from such an insn. 2990075Sobrien* Output Statement:: For more generality, write C code to output 3090075Sobrien the assembler code. 31169689Skan* Predicates:: Controlling what kinds of operands can be used 32169689Skan for an insn. 33169689Skan* Constraints:: Fine-tuning operand selection. 3490075Sobrien* Standard Names:: Names mark patterns to use for code generation. 3590075Sobrien* Pattern Ordering:: When the order of patterns makes a difference. 3690075Sobrien* Dependent Patterns:: Having one pattern may make you need another. 3790075Sobrien* Jump Patterns:: Special considerations for patterns for jump insns. 3890075Sobrien* Looping Patterns:: How to define patterns for special looping insns. 3990075Sobrien* Insn Canonicalizations::Canonicalization of Instructions 4090075Sobrien* Expander Definitions::Generating a sequence of several RTL insns 4190075Sobrien for a standard operation. 4290075Sobrien* Insn Splitting:: Splitting Instructions into Multiple Instructions. 4390075Sobrien* Including Patterns:: Including Patterns in Machine Descriptions. 4490075Sobrien* Peephole Definitions::Defining machine-specific peephole optimizations. 4590075Sobrien* Insn Attributes:: Specifying the value of attributes for generated insns. 4690075Sobrien* Conditional Execution::Generating @code{define_insn} patterns for 4790075Sobrien predication. 4890075Sobrien* Constant Definitions::Defining symbolic constants that can be used in the 4990075Sobrien md file. 50169689Skan* Macros:: Using macros to generate patterns from a template. 5190075Sobrien@end menu 5290075Sobrien 5390075Sobrien@node Overview 5490075Sobrien@section Overview of How the Machine Description is Used 5590075Sobrien 5690075SobrienThere are three main conversions that happen in the compiler: 5790075Sobrien 5890075Sobrien@enumerate 5990075Sobrien 6090075Sobrien@item 6190075SobrienThe front end reads the source code and builds a parse tree. 6290075Sobrien 6390075Sobrien@item 6490075SobrienThe parse tree is used to generate an RTL insn list based on named 6590075Sobrieninstruction patterns. 6690075Sobrien 6790075Sobrien@item 6890075SobrienThe insn list is matched against the RTL templates to produce assembler 6990075Sobriencode. 7090075Sobrien 7190075Sobrien@end enumerate 7290075Sobrien 7390075SobrienFor the generate pass, only the names of the insns matter, from either a 7490075Sobriennamed @code{define_insn} or a @code{define_expand}. The compiler will 7590075Sobrienchoose the pattern with the right name and apply the operands according 7690075Sobriento the documentation later in this chapter, without regard for the RTL 7790075Sobrientemplate or operand constraints. Note that the names the compiler looks 7890075Sobrienfor are hard-coded in the compiler---it will ignore unnamed patterns and 7990075Sobrienpatterns with names it doesn't know about, but if you don't provide a 8090075Sobriennamed pattern it needs, it will abort. 8190075Sobrien 8290075SobrienIf a @code{define_insn} is used, the template given is inserted into the 8390075Sobrieninsn list. If a @code{define_expand} is used, one of three things 8490075Sobrienhappens, based on the condition logic. The condition logic may manually 8590075Sobriencreate new insns for the insn list, say via @code{emit_insn()}, and 8690075Sobrieninvoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the 8790075Sobriencompiler to use an alternate way of performing that task. If it invokes 8890075Sobrienneither @code{DONE} nor @code{FAIL}, the template given in the pattern 8990075Sobrienis inserted, as if the @code{define_expand} were a @code{define_insn}. 9090075Sobrien 9190075SobrienOnce the insn list is generated, various optimization passes convert, 9290075Sobrienreplace, and rearrange the insns in the insn list. This is where the 9390075Sobrien@code{define_split} and @code{define_peephole} patterns get used, for 9490075Sobrienexample. 9590075Sobrien 9690075SobrienFinally, the insn list's RTL is matched up with the RTL templates in the 9790075Sobrien@code{define_insn} patterns, and those patterns are used to emit the 9890075Sobrienfinal assembly code. For this purpose, each named @code{define_insn} 9990075Sobrienacts like it's unnamed, since the names are ignored. 10090075Sobrien 10190075Sobrien@node Patterns 10290075Sobrien@section Everything about Instruction Patterns 10390075Sobrien@cindex patterns 10490075Sobrien@cindex instruction patterns 10590075Sobrien 10690075Sobrien@findex define_insn 10790075SobrienEach instruction pattern contains an incomplete RTL expression, with pieces 10890075Sobriento be filled in later, operand constraints that restrict how the pieces can 10990075Sobrienbe filled in, and an output pattern or C code to generate the assembler 11090075Sobrienoutput, all wrapped up in a @code{define_insn} expression. 11190075Sobrien 11290075SobrienA @code{define_insn} is an RTL expression containing four or five operands: 11390075Sobrien 11490075Sobrien@enumerate 11590075Sobrien@item 11690075SobrienAn optional name. The presence of a name indicate that this instruction 11790075Sobrienpattern can perform a certain standard job for the RTL-generation 11890075Sobrienpass of the compiler. This pass knows certain names and will use 11990075Sobrienthe instruction patterns with those names, if the names are defined 12090075Sobrienin the machine description. 12190075Sobrien 12290075SobrienThe absence of a name is indicated by writing an empty string 12390075Sobrienwhere the name should go. Nameless instruction patterns are never 12490075Sobrienused for generating RTL code, but they may permit several simpler insns 12590075Sobriento be combined later on. 12690075Sobrien 12790075SobrienNames that are not thus known and used in RTL-generation have no 12890075Sobrieneffect; they are equivalent to no name at all. 12990075Sobrien 13090075SobrienFor the purpose of debugging the compiler, you may also specify a 13190075Sobrienname beginning with the @samp{*} character. Such a name is used only 13290075Sobrienfor identifying the instruction in RTL dumps; it is entirely equivalent 13390075Sobriento having a nameless pattern for all other purposes. 13490075Sobrien 13590075Sobrien@item 13690075SobrienThe @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete 13790075SobrienRTL expressions which show what the instruction should look like. It is 13890075Sobrienincomplete because it may contain @code{match_operand}, 13990075Sobrien@code{match_operator}, and @code{match_dup} expressions that stand for 14090075Sobrienoperands of the instruction. 14190075Sobrien 14290075SobrienIf the vector has only one element, that element is the template for the 14390075Sobrieninstruction pattern. If the vector has multiple elements, then the 14490075Sobrieninstruction pattern is a @code{parallel} expression containing the 14590075Sobrienelements described. 14690075Sobrien 14790075Sobrien@item 14890075Sobrien@cindex pattern conditions 14990075Sobrien@cindex conditions, in patterns 15090075SobrienA condition. This is a string which contains a C expression that is 15190075Sobrienthe final test to decide whether an insn body matches this pattern. 15290075Sobrien 15390075Sobrien@cindex named patterns and conditions 15490075SobrienFor a named pattern, the condition (if present) may not depend on 15590075Sobrienthe data in the insn being matched, but only the target-machine-type 15690075Sobrienflags. The compiler needs to test these conditions during 15790075Sobrieninitialization in order to learn exactly which named instructions are 15890075Sobrienavailable in a particular run. 15990075Sobrien 16090075Sobrien@findex operands 16190075SobrienFor nameless patterns, the condition is applied only when matching an 16290075Sobrienindividual insn, and only after the insn has matched the pattern's 16390075Sobrienrecognition template. The insn's operands may be found in the vector 164102780Skan@code{operands}. For an insn where the condition has once matched, it 165102780Skancan't be used to control register allocation, for example by excluding 166102780Skancertain hard registers or hard register combinations. 16790075Sobrien 16890075Sobrien@item 16990075SobrienThe @dfn{output template}: a string that says how to output matching 17090075Sobrieninsns as assembler code. @samp{%} in this string specifies where 17190075Sobriento substitute the value of an operand. @xref{Output Template}. 17290075Sobrien 17390075SobrienWhen simple substitution isn't general enough, you can specify a piece 17490075Sobrienof C code to compute the output. @xref{Output Statement}. 17590075Sobrien 17690075Sobrien@item 17790075SobrienOptionally, a vector containing the values of attributes for insns matching 17890075Sobrienthis pattern. @xref{Insn Attributes}. 17990075Sobrien@end enumerate 18090075Sobrien 18190075Sobrien@node Example 18290075Sobrien@section Example of @code{define_insn} 18390075Sobrien@cindex @code{define_insn} example 18490075Sobrien 18590075SobrienHere is an actual example of an instruction pattern, for the 68000/68020. 18690075Sobrien 187132718Skan@smallexample 18890075Sobrien(define_insn "tstsi" 18990075Sobrien [(set (cc0) 19090075Sobrien (match_operand:SI 0 "general_operand" "rm"))] 19190075Sobrien "" 19290075Sobrien "* 19396263Sobrien@{ 19490075Sobrien if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) 19590075Sobrien return \"tstl %0\"; 19696263Sobrien return \"cmpl #0,%0\"; 19790075Sobrien@}") 198132718Skan@end smallexample 19990075Sobrien 20090075Sobrien@noindent 20190075SobrienThis can also be written using braced strings: 20290075Sobrien 203132718Skan@smallexample 20490075Sobrien(define_insn "tstsi" 20590075Sobrien [(set (cc0) 20690075Sobrien (match_operand:SI 0 "general_operand" "rm"))] 20790075Sobrien "" 20896263Sobrien@{ 20990075Sobrien if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) 21090075Sobrien return "tstl %0"; 21196263Sobrien return "cmpl #0,%0"; 21290075Sobrien@}) 213132718Skan@end smallexample 21490075Sobrien 21590075SobrienThis is an instruction that sets the condition codes based on the value of 21690075Sobriena general operand. It has no condition, so any insn whose RTL description 21790075Sobrienhas the form shown may be handled according to this pattern. The name 21890075Sobrien@samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation 21990075Sobrienpass that, when it is necessary to test such a value, an insn to do so 22090075Sobriencan be constructed using this pattern. 22190075Sobrien 22290075SobrienThe output control string is a piece of C code which chooses which 22390075Sobrienoutput template to return based on the kind of operand and the specific 22490075Sobrientype of CPU for which code is being generated. 22590075Sobrien 22690075Sobrien@samp{"rm"} is an operand constraint. Its meaning is explained below. 22790075Sobrien 22890075Sobrien@node RTL Template 22990075Sobrien@section RTL Template 23090075Sobrien@cindex RTL insn template 23190075Sobrien@cindex generating insns 23290075Sobrien@cindex insns, generating 23390075Sobrien@cindex recognizing insns 23490075Sobrien@cindex insns, recognizing 23590075Sobrien 23690075SobrienThe RTL template is used to define which insns match the particular pattern 23790075Sobrienand how to find their operands. For named patterns, the RTL template also 23890075Sobriensays how to construct an insn from specified operands. 23990075Sobrien 24090075SobrienConstruction involves substituting specified operands into a copy of the 24190075Sobrientemplate. Matching involves determining the values that serve as the 24290075Sobrienoperands in the insn being matched. Both of these activities are 24390075Sobriencontrolled by special expression types that direct matching and 24490075Sobriensubstitution of the operands. 24590075Sobrien 24690075Sobrien@table @code 24790075Sobrien@findex match_operand 24890075Sobrien@item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint}) 24990075SobrienThis expression is a placeholder for operand number @var{n} of 25090075Sobrienthe insn. When constructing an insn, operand number @var{n} 25190075Sobrienwill be substituted at this point. When matching an insn, whatever 25290075Sobrienappears at this position in the insn will be taken as operand 25390075Sobriennumber @var{n}; but it must satisfy @var{predicate} or this instruction 25490075Sobrienpattern will not match at all. 25590075Sobrien 25690075SobrienOperand numbers must be chosen consecutively counting from zero in 25790075Sobrieneach instruction pattern. There may be only one @code{match_operand} 25890075Sobrienexpression in the pattern for each operand number. Usually operands 25990075Sobrienare numbered in the order of appearance in @code{match_operand} 26090075Sobrienexpressions. In the case of a @code{define_expand}, any operand numbers 26190075Sobrienused only in @code{match_dup} expressions have higher values than all 26290075Sobrienother operand numbers. 26390075Sobrien 264169689Skan@var{predicate} is a string that is the name of a function that 265169689Skanaccepts two arguments, an expression and a machine mode. 266169689Skan@xref{Predicates}. During matching, the function will be called with 267169689Skanthe putative operand as the expression and @var{m} as the mode 268169689Skanargument (if @var{m} is not specified, @code{VOIDmode} will be used, 269169689Skanwhich normally causes @var{predicate} to accept any mode). If it 270169689Skanreturns zero, this instruction pattern fails to match. 271169689Skan@var{predicate} may be an empty string; then it means no test is to be 272169689Skandone on the operand, so anything which occurs in this position is 273169689Skanvalid. 27490075Sobrien 27590075SobrienMost of the time, @var{predicate} will reject modes other than @var{m}---but 27690075Sobriennot always. For example, the predicate @code{address_operand} uses 27790075Sobrien@var{m} as the mode of memory ref that the address should be valid for. 27890075SobrienMany predicates accept @code{const_int} nodes even though their mode is 27990075Sobrien@code{VOIDmode}. 28090075Sobrien 28190075Sobrien@var{constraint} controls reloading and the choice of the best register 28290075Sobrienclass to use for a value, as explained later (@pxref{Constraints}). 283169689SkanIf the constraint would be an empty string, it can be omitted. 28490075Sobrien 28590075SobrienPeople are often unclear on the difference between the constraint and the 28690075Sobrienpredicate. The predicate helps decide whether a given insn matches the 28790075Sobrienpattern. The constraint plays no role in this decision; instead, it 28890075Sobriencontrols various decisions in the case of an insn which does match. 28990075Sobrien 29090075Sobrien@findex match_scratch 29190075Sobrien@item (match_scratch:@var{m} @var{n} @var{constraint}) 29290075SobrienThis expression is also a placeholder for operand number @var{n} 29390075Sobrienand indicates that operand must be a @code{scratch} or @code{reg} 29490075Sobrienexpression. 29590075Sobrien 29690075SobrienWhen matching patterns, this is equivalent to 29790075Sobrien 29890075Sobrien@smallexample 29990075Sobrien(match_operand:@var{m} @var{n} "scratch_operand" @var{pred}) 30090075Sobrien@end smallexample 30190075Sobrien 30290075Sobrienbut, when generating RTL, it produces a (@code{scratch}:@var{m}) 30390075Sobrienexpression. 30490075Sobrien 30590075SobrienIf the last few expressions in a @code{parallel} are @code{clobber} 30690075Sobrienexpressions whose operands are either a hard register or 30790075Sobrien@code{match_scratch}, the combiner can add or delete them when 30890075Sobriennecessary. @xref{Side Effects}. 30990075Sobrien 31090075Sobrien@findex match_dup 31190075Sobrien@item (match_dup @var{n}) 31290075SobrienThis expression is also a placeholder for operand number @var{n}. 31390075SobrienIt is used when the operand needs to appear more than once in the 31490075Sobrieninsn. 31590075Sobrien 31690075SobrienIn construction, @code{match_dup} acts just like @code{match_operand}: 31790075Sobrienthe operand is substituted into the insn being constructed. But in 31890075Sobrienmatching, @code{match_dup} behaves differently. It assumes that operand 31990075Sobriennumber @var{n} has already been determined by a @code{match_operand} 32090075Sobrienappearing earlier in the recognition template, and it matches only an 32190075Sobrienidentical-looking expression. 32290075Sobrien 32390075SobrienNote that @code{match_dup} should not be used to tell the compiler that 32490075Sobriena particular register is being used for two operands (example: 32590075Sobrien@code{add} that adds one register to another; the second register is 32690075Sobrienboth an input operand and the output operand). Use a matching 32790075Sobrienconstraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one 32890075Sobrienoperand is used in two places in the template, such as an instruction 32990075Sobrienthat computes both a quotient and a remainder, where the opcode takes 33090075Sobrientwo input operands but the RTL template has to refer to each of those 33190075Sobrientwice; once for the quotient pattern and once for the remainder pattern. 33290075Sobrien 33390075Sobrien@findex match_operator 33490075Sobrien@item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}]) 33590075SobrienThis pattern is a kind of placeholder for a variable RTL expression 33690075Sobriencode. 33790075Sobrien 33890075SobrienWhen constructing an insn, it stands for an RTL expression whose 33990075Sobrienexpression code is taken from that of operand @var{n}, and whose 34090075Sobrienoperands are constructed from the patterns @var{operands}. 34190075Sobrien 34290075SobrienWhen matching an expression, it matches an expression if the function 34390075Sobrien@var{predicate} returns nonzero on that expression @emph{and} the 34490075Sobrienpatterns @var{operands} match the operands of the expression. 34590075Sobrien 34690075SobrienSuppose that the function @code{commutative_operator} is defined as 34790075Sobrienfollows, to match any expression whose operator is one of the 34890075Sobriencommutative arithmetic operators of RTL and whose mode is @var{mode}: 34990075Sobrien 35090075Sobrien@smallexample 35190075Sobrienint 352169689Skancommutative_integer_operator (x, mode) 35390075Sobrien rtx x; 35490075Sobrien enum machine_mode mode; 35590075Sobrien@{ 35690075Sobrien enum rtx_code code = GET_CODE (x); 35790075Sobrien if (GET_MODE (x) != mode) 35890075Sobrien return 0; 359169689Skan return (GET_RTX_CLASS (code) == RTX_COMM_ARITH 36090075Sobrien || code == EQ || code == NE); 36190075Sobrien@} 36290075Sobrien@end smallexample 36390075Sobrien 36490075SobrienThen the following pattern will match any RTL expression consisting 36590075Sobrienof a commutative operator applied to two general operands: 36690075Sobrien 36790075Sobrien@smallexample 36890075Sobrien(match_operator:SI 3 "commutative_operator" 36990075Sobrien [(match_operand:SI 1 "general_operand" "g") 37090075Sobrien (match_operand:SI 2 "general_operand" "g")]) 37190075Sobrien@end smallexample 37290075Sobrien 37390075SobrienHere the vector @code{[@var{operands}@dots{}]} contains two patterns 37490075Sobrienbecause the expressions to be matched all contain two operands. 37590075Sobrien 37690075SobrienWhen this pattern does match, the two operands of the commutative 37790075Sobrienoperator are recorded as operands 1 and 2 of the insn. (This is done 37890075Sobrienby the two instances of @code{match_operand}.) Operand 3 of the insn 37990075Sobrienwill be the entire commutative expression: use @code{GET_CODE 38090075Sobrien(operands[3])} to see which commutative operator was used. 38190075Sobrien 38290075SobrienThe machine mode @var{m} of @code{match_operator} works like that of 38390075Sobrien@code{match_operand}: it is passed as the second argument to the 38490075Sobrienpredicate function, and that function is solely responsible for 38590075Sobriendeciding whether the expression to be matched ``has'' that mode. 38690075Sobrien 38790075SobrienWhen constructing an insn, argument 3 of the gen-function will specify 38890075Sobrienthe operation (i.e.@: the expression code) for the expression to be 38990075Sobrienmade. It should be an RTL expression, whose expression code is copied 39090075Sobrieninto a new expression whose operands are arguments 1 and 2 of the 39190075Sobriengen-function. The subexpressions of argument 3 are not used; 39290075Sobrienonly its expression code matters. 39390075Sobrien 39490075SobrienWhen @code{match_operator} is used in a pattern for matching an insn, 39590075Sobrienit usually best if the operand number of the @code{match_operator} 39690075Sobrienis higher than that of the actual operands of the insn. This improves 39790075Sobrienregister allocation because the register allocator often looks at 39890075Sobrienoperands 1 and 2 of insns to see if it can do register tying. 39990075Sobrien 40090075SobrienThere is no way to specify constraints in @code{match_operator}. The 40190075Sobrienoperand of the insn which corresponds to the @code{match_operator} 40290075Sobriennever has any constraints because it is never reloaded as a whole. 40390075SobrienHowever, if parts of its @var{operands} are matched by 40490075Sobrien@code{match_operand} patterns, those parts may have constraints of 40590075Sobrientheir own. 40690075Sobrien 40790075Sobrien@findex match_op_dup 40890075Sobrien@item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}]) 40990075SobrienLike @code{match_dup}, except that it applies to operators instead of 41090075Sobrienoperands. When constructing an insn, operand number @var{n} will be 41190075Sobriensubstituted at this point. But in matching, @code{match_op_dup} behaves 41290075Sobriendifferently. It assumes that operand number @var{n} has already been 41390075Sobriendetermined by a @code{match_operator} appearing earlier in the 41490075Sobrienrecognition template, and it matches only an identical-looking 41590075Sobrienexpression. 41690075Sobrien 41790075Sobrien@findex match_parallel 41890075Sobrien@item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}]) 41990075SobrienThis pattern is a placeholder for an insn that consists of a 42090075Sobrien@code{parallel} expression with a variable number of elements. This 42190075Sobrienexpression should only appear at the top level of an insn pattern. 42290075Sobrien 42390075SobrienWhen constructing an insn, operand number @var{n} will be substituted at 42490075Sobrienthis point. When matching an insn, it matches if the body of the insn 42590075Sobrienis a @code{parallel} expression with at least as many elements as the 42690075Sobrienvector of @var{subpat} expressions in the @code{match_parallel}, if each 42790075Sobrien@var{subpat} matches the corresponding element of the @code{parallel}, 42890075Sobrien@emph{and} the function @var{predicate} returns nonzero on the 42990075Sobrien@code{parallel} that is the body of the insn. It is the responsibility 43090075Sobrienof the predicate to validate elements of the @code{parallel} beyond 43190075Sobrienthose listed in the @code{match_parallel}. 43290075Sobrien 43390075SobrienA typical use of @code{match_parallel} is to match load and store 43490075Sobrienmultiple expressions, which can contain a variable number of elements 43590075Sobrienin a @code{parallel}. For example, 43690075Sobrien 43790075Sobrien@smallexample 43890075Sobrien(define_insn "" 43990075Sobrien [(match_parallel 0 "load_multiple_operation" 44090075Sobrien [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 44190075Sobrien (match_operand:SI 2 "memory_operand" "m")) 44290075Sobrien (use (reg:SI 179)) 44390075Sobrien (clobber (reg:SI 179))])] 44490075Sobrien "" 44590075Sobrien "loadm 0,0,%1,%2") 44690075Sobrien@end smallexample 44790075Sobrien 44890075SobrienThis example comes from @file{a29k.md}. The function 44990075Sobrien@code{load_multiple_operation} is defined in @file{a29k.c} and checks 45090075Sobrienthat subsequent elements in the @code{parallel} are the same as the 45190075Sobrien@code{set} in the pattern, except that they are referencing subsequent 45290075Sobrienregisters and memory locations. 45390075Sobrien 45490075SobrienAn insn that matches this pattern might look like: 45590075Sobrien 45690075Sobrien@smallexample 45790075Sobrien(parallel 45890075Sobrien [(set (reg:SI 20) (mem:SI (reg:SI 100))) 45990075Sobrien (use (reg:SI 179)) 46090075Sobrien (clobber (reg:SI 179)) 46190075Sobrien (set (reg:SI 21) 46290075Sobrien (mem:SI (plus:SI (reg:SI 100) 46390075Sobrien (const_int 4)))) 46490075Sobrien (set (reg:SI 22) 46590075Sobrien (mem:SI (plus:SI (reg:SI 100) 46690075Sobrien (const_int 8))))]) 46790075Sobrien@end smallexample 46890075Sobrien 46990075Sobrien@findex match_par_dup 47090075Sobrien@item (match_par_dup @var{n} [@var{subpat}@dots{}]) 47190075SobrienLike @code{match_op_dup}, but for @code{match_parallel} instead of 47290075Sobrien@code{match_operator}. 47390075Sobrien 47490075Sobrien@end table 47590075Sobrien 47690075Sobrien@node Output Template 47790075Sobrien@section Output Templates and Operand Substitution 47890075Sobrien@cindex output templates 47990075Sobrien@cindex operand substitution 48090075Sobrien 48190075Sobrien@cindex @samp{%} in template 48290075Sobrien@cindex percent sign 48390075SobrienThe @dfn{output template} is a string which specifies how to output the 48490075Sobrienassembler code for an instruction pattern. Most of the template is a 48590075Sobrienfixed string which is output literally. The character @samp{%} is used 48690075Sobriento specify where to substitute an operand; it can also be used to 48790075Sobrienidentify places where different variants of the assembler require 48890075Sobriendifferent syntax. 48990075Sobrien 49090075SobrienIn the simplest case, a @samp{%} followed by a digit @var{n} says to output 49190075Sobrienoperand @var{n} at that point in the string. 49290075Sobrien 49390075Sobrien@samp{%} followed by a letter and a digit says to output an operand in an 49490075Sobrienalternate fashion. Four letters have standard, built-in meanings described 49590075Sobrienbelow. The machine description macro @code{PRINT_OPERAND} can define 49690075Sobrienadditional letters with nonstandard meanings. 49790075Sobrien 49890075Sobrien@samp{%c@var{digit}} can be used to substitute an operand that is a 49990075Sobrienconstant value without the syntax that normally indicates an immediate 50090075Sobrienoperand. 50190075Sobrien 50290075Sobrien@samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of 50390075Sobrienthe constant is negated before printing. 50490075Sobrien 50590075Sobrien@samp{%a@var{digit}} can be used to substitute an operand as if it were a 50690075Sobrienmemory reference, with the actual operand treated as the address. This may 50790075Sobrienbe useful when outputting a ``load address'' instruction, because often the 50890075Sobrienassembler syntax for such an instruction requires you to write the operand 50990075Sobrienas if it were a memory reference. 51090075Sobrien 51190075Sobrien@samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump 51290075Sobrieninstruction. 51390075Sobrien 51490075Sobrien@samp{%=} outputs a number which is unique to each instruction in the 51590075Sobrienentire compilation. This is useful for making local labels to be 51690075Sobrienreferred to more than once in a single template that generates multiple 51790075Sobrienassembler instructions. 51890075Sobrien 51990075Sobrien@samp{%} followed by a punctuation character specifies a substitution that 52090075Sobriendoes not use an operand. Only one case is standard: @samp{%%} outputs a 52190075Sobrien@samp{%} into the assembler code. Other nonstandard cases can be 52290075Sobriendefined in the @code{PRINT_OPERAND} macro. You must also define 52390075Sobrienwhich punctuation characters are valid with the 52490075Sobrien@code{PRINT_OPERAND_PUNCT_VALID_P} macro. 52590075Sobrien 52690075Sobrien@cindex \ 52790075Sobrien@cindex backslash 52890075SobrienThe template may generate multiple assembler instructions. Write the text 52990075Sobrienfor the instructions, with @samp{\;} between them. 53090075Sobrien 53190075Sobrien@cindex matching operands 53290075SobrienWhen the RTL contains two operands which are required by constraint to match 53390075Sobrieneach other, the output template must refer only to the lower-numbered operand. 53490075SobrienMatching operands are not always identical, and the rest of the compiler 53590075Sobrienarranges to put the proper RTL expression for printing into the lower-numbered 53690075Sobrienoperand. 53790075Sobrien 53890075SobrienOne use of nonstandard letters or punctuation following @samp{%} is to 53990075Sobriendistinguish between different assembler languages for the same machine; for 54090075Sobrienexample, Motorola syntax versus MIT syntax for the 68000. Motorola syntax 54190075Sobrienrequires periods in most opcode names, while MIT syntax does not. For 54290075Sobrienexample, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola 54390075Sobriensyntax. The same file of patterns is used for both kinds of output syntax, 54490075Sobrienbut the character sequence @samp{%.} is used in each place where Motorola 54590075Sobriensyntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax 54690075Sobriendefines the sequence to output a period; the macro for MIT syntax defines 54790075Sobrienit to do nothing. 54890075Sobrien 54990075Sobrien@cindex @code{#} in template 55090075SobrienAs a special case, a template consisting of the single character @code{#} 55190075Sobrieninstructs the compiler to first split the insn, and then output the 55290075Sobrienresulting instructions separately. This helps eliminate redundancy in the 55390075Sobrienoutput templates. If you have a @code{define_insn} that needs to emit 55490075Sobrienmultiple assembler instructions, and there is an matching @code{define_split} 55590075Sobrienalready defined, then you can simply use @code{#} as the output template 55690075Sobrieninstead of writing an output template that emits the multiple assembler 55790075Sobrieninstructions. 55890075Sobrien 55990075SobrienIf the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct 56090075Sobrienof the form @samp{@{option0|option1|option2@}} in the templates. These 56190075Sobriendescribe multiple variants of assembler language syntax. 56290075Sobrien@xref{Instruction Output}. 56390075Sobrien 56490075Sobrien@node Output Statement 56590075Sobrien@section C Statements for Assembler Output 56690075Sobrien@cindex output statements 56790075Sobrien@cindex C statements for assembler output 56890075Sobrien@cindex generating assembler output 56990075Sobrien 57090075SobrienOften a single fixed template string cannot produce correct and efficient 57190075Sobrienassembler code for all the cases that are recognized by a single 57290075Sobrieninstruction pattern. For example, the opcodes may depend on the kinds of 57390075Sobrienoperands; or some unfortunate combinations of operands may require extra 57490075Sobrienmachine instructions. 57590075Sobrien 57690075SobrienIf the output control string starts with a @samp{@@}, then it is actually 57790075Sobriena series of templates, each on a separate line. (Blank lines and 57890075Sobrienleading spaces and tabs are ignored.) The templates correspond to the 57990075Sobrienpattern's constraint alternatives (@pxref{Multi-Alternative}). For example, 58090075Sobrienif a target machine has a two-address add instruction @samp{addr} to add 58190075Sobrieninto a register and another @samp{addm} to add a register to memory, you 58290075Sobrienmight write this pattern: 58390075Sobrien 58490075Sobrien@smallexample 58590075Sobrien(define_insn "addsi3" 58690075Sobrien [(set (match_operand:SI 0 "general_operand" "=r,m") 58790075Sobrien (plus:SI (match_operand:SI 1 "general_operand" "0,0") 58890075Sobrien (match_operand:SI 2 "general_operand" "g,r")))] 58990075Sobrien "" 59090075Sobrien "@@ 59190075Sobrien addr %2,%0 59290075Sobrien addm %2,%0") 59390075Sobrien@end smallexample 59490075Sobrien 59590075Sobrien@cindex @code{*} in template 59690075Sobrien@cindex asterisk in template 59790075SobrienIf the output control string starts with a @samp{*}, then it is not an 59890075Sobrienoutput template but rather a piece of C program that should compute a 59990075Sobrientemplate. It should execute a @code{return} statement to return the 60090075Sobrientemplate-string you want. Most such templates use C string literals, which 60190075Sobrienrequire doublequote characters to delimit them. To include these 60290075Sobriendoublequote characters in the string, prefix each one with @samp{\}. 60390075Sobrien 60490075SobrienIf the output control string is written as a brace block instead of a 60590075Sobriendouble-quoted string, it is automatically assumed to be C code. In that 60690075Sobriencase, it is not necessary to put in a leading asterisk, or to escape the 60790075Sobriendoublequotes surrounding C string literals. 60890075Sobrien 60990075SobrienThe operands may be found in the array @code{operands}, whose C data type 61090075Sobrienis @code{rtx []}. 61190075Sobrien 61290075SobrienIt is very common to select different ways of generating assembler code 61390075Sobrienbased on whether an immediate operand is within a certain range. Be 61490075Sobriencareful when doing this, because the result of @code{INTVAL} is an 61590075Sobrieninteger on the host machine. If the host machine has more bits in an 61690075Sobrien@code{int} than the target machine has in the mode in which the constant 61790075Sobrienwill be used, then some of the bits you get from @code{INTVAL} will be 61890075Sobriensuperfluous. For proper results, you must carefully disregard the 61990075Sobrienvalues of those bits. 62090075Sobrien 62190075Sobrien@findex output_asm_insn 62290075SobrienIt is possible to output an assembler instruction and then go on to output 62390075Sobrienor compute more of them, using the subroutine @code{output_asm_insn}. This 62490075Sobrienreceives two arguments: a template-string and a vector of operands. The 62590075Sobrienvector may be @code{operands}, or it may be another array of @code{rtx} 62690075Sobrienthat you declare locally and initialize yourself. 62790075Sobrien 62890075Sobrien@findex which_alternative 62990075SobrienWhen an insn pattern has multiple alternatives in its constraints, often 63090075Sobrienthe appearance of the assembler code is determined mostly by which alternative 63190075Sobrienwas matched. When this is so, the C code can test the variable 63290075Sobrien@code{which_alternative}, which is the ordinal number of the alternative 63390075Sobrienthat was actually satisfied (0 for the first, 1 for the second alternative, 63490075Sobrienetc.). 63590075Sobrien 63690075SobrienFor example, suppose there are two opcodes for storing zero, @samp{clrreg} 63790075Sobrienfor registers and @samp{clrmem} for memory locations. Here is how 63890075Sobriena pattern could use @code{which_alternative} to choose between them: 63990075Sobrien 64090075Sobrien@smallexample 64190075Sobrien(define_insn "" 64290075Sobrien [(set (match_operand:SI 0 "general_operand" "=r,m") 64390075Sobrien (const_int 0))] 64490075Sobrien "" 64590075Sobrien @{ 64690075Sobrien return (which_alternative == 0 64790075Sobrien ? "clrreg %0" : "clrmem %0"); 64890075Sobrien @}) 64990075Sobrien@end smallexample 65090075Sobrien 65190075SobrienThe example above, where the assembler code to generate was 65290075Sobrien@emph{solely} determined by the alternative, could also have been specified 65390075Sobrienas follows, having the output control string start with a @samp{@@}: 65490075Sobrien 65590075Sobrien@smallexample 65690075Sobrien@group 65790075Sobrien(define_insn "" 65890075Sobrien [(set (match_operand:SI 0 "general_operand" "=r,m") 65990075Sobrien (const_int 0))] 66090075Sobrien "" 66190075Sobrien "@@ 66290075Sobrien clrreg %0 66390075Sobrien clrmem %0") 66490075Sobrien@end group 66590075Sobrien@end smallexample 666169689Skan 667169689Skan@node Predicates 668169689Skan@section Predicates 669169689Skan@cindex predicates 670169689Skan@cindex operand predicates 671169689Skan@cindex operator predicates 672169689Skan 673169689SkanA predicate determines whether a @code{match_operand} or 674169689Skan@code{match_operator} expression matches, and therefore whether the 675169689Skansurrounding instruction pattern will be used for that combination of 676169689Skanoperands. GCC has a number of machine-independent predicates, and you 677169689Skancan define machine-specific predicates as needed. By convention, 678169689Skanpredicates used with @code{match_operand} have names that end in 679169689Skan@samp{_operand}, and those used with @code{match_operator} have names 680169689Skanthat end in @samp{_operator}. 681169689Skan 682169689SkanAll predicates are Boolean functions (in the mathematical sense) of 683169689Skantwo arguments: the RTL expression that is being considered at that 684169689Skanposition in the instruction pattern, and the machine mode that the 685169689Skan@code{match_operand} or @code{match_operator} specifies. In this 686169689Skansection, the first argument is called @var{op} and the second argument 687169689Skan@var{mode}. Predicates can be called from C as ordinary two-argument 688169689Skanfunctions; this can be useful in output templates or other 689169689Skanmachine-specific code. 690169689Skan 691169689SkanOperand predicates can allow operands that are not actually acceptable 692169689Skanto the hardware, as long as the constraints give reload the ability to 693169689Skanfix them up (@pxref{Constraints}). However, GCC will usually generate 694169689Skanbetter code if the predicates specify the requirements of the machine 695169689Skaninstructions as closely as possible. Reload cannot fix up operands 696169689Skanthat must be constants (``immediate operands''); you must use a 697169689Skanpredicate that allows only constants, or else enforce the requirement 698169689Skanin the extra condition. 699169689Skan 700169689Skan@cindex predicates and machine modes 701169689Skan@cindex normal predicates 702169689Skan@cindex special predicates 703169689SkanMost predicates handle their @var{mode} argument in a uniform manner. 704169689SkanIf @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have 705169689Skanany mode. If @var{mode} is anything else, then @var{op} must have the 706169689Skansame mode, unless @var{op} is a @code{CONST_INT} or integer 707169689Skan@code{CONST_DOUBLE}. These RTL expressions always have 708169689Skan@code{VOIDmode}, so it would be counterproductive to check that their 709169689Skanmode matches. Instead, predicates that accept @code{CONST_INT} and/or 710169689Skaninteger @code{CONST_DOUBLE} check that the value stored in the 711169689Skanconstant will fit in the requested mode. 712169689Skan 713169689SkanPredicates with this behavior are called @dfn{normal}. 714169689Skan@command{genrecog} can optimize the instruction recognizer based on 715169689Skanknowledge of how normal predicates treat modes. It can also diagnose 716169689Skancertain kinds of common errors in the use of normal predicates; for 717169689Skaninstance, it is almost always an error to use a normal predicate 718169689Skanwithout specifying a mode. 719169689Skan 720169689SkanPredicates that do something different with their @var{mode} argument 721169689Skanare called @dfn{special}. The generic predicates 722169689Skan@code{address_operand} and @code{pmode_register_operand} are special 723169689Skanpredicates. @command{genrecog} does not do any optimizations or 724169689Skandiagnosis when special predicates are used. 725169689Skan 726169689Skan@menu 727169689Skan* Machine-Independent Predicates:: Predicates available to all back ends. 728169689Skan* Defining Predicates:: How to write machine-specific predicate 729169689Skan functions. 730169689Skan@end menu 731169689Skan 732169689Skan@node Machine-Independent Predicates 733169689Skan@subsection Machine-Independent Predicates 734169689Skan@cindex machine-independent predicates 735169689Skan@cindex generic predicates 736169689Skan 737169689SkanThese are the generic predicates available to all back ends. They are 738169689Skandefined in @file{recog.c}. The first category of predicates allow 739169689Skanonly constant, or @dfn{immediate}, operands. 740169689Skan 741169689Skan@defun immediate_operand 742169689SkanThis predicate allows any sort of constant that fits in @var{mode}. 743169689SkanIt is an appropriate choice for instructions that take operands that 744169689Skanmust be constant. 745169689Skan@end defun 746169689Skan 747169689Skan@defun const_int_operand 748169689SkanThis predicate allows any @code{CONST_INT} expression that fits in 749169689Skan@var{mode}. It is an appropriate choice for an immediate operand that 750169689Skandoes not allow a symbol or label. 751169689Skan@end defun 752169689Skan 753169689Skan@defun const_double_operand 754169689SkanThis predicate accepts any @code{CONST_DOUBLE} expression that has 755169689Skanexactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also 756169689Skanaccept @code{CONST_INT}. It is intended for immediate floating point 757169689Skanconstants. 758169689Skan@end defun 759169689Skan 760169689Skan@noindent 761169689SkanThe second category of predicates allow only some kind of machine 762169689Skanregister. 763169689Skan 764169689Skan@defun register_operand 765169689SkanThis predicate allows any @code{REG} or @code{SUBREG} expression that 766169689Skanis valid for @var{mode}. It is often suitable for arithmetic 767169689Skaninstruction operands on a RISC machine. 768169689Skan@end defun 769169689Skan 770169689Skan@defun pmode_register_operand 771169689SkanThis is a slight variant on @code{register_operand} which works around 772169689Skana limitation in the machine-description reader. 773169689Skan 774169689Skan@smallexample 775169689Skan(match_operand @var{n} "pmode_register_operand" @var{constraint}) 776169689Skan@end smallexample 777169689Skan 778169689Skan@noindent 779169689Skanmeans exactly what 780169689Skan 781169689Skan@smallexample 782169689Skan(match_operand:P @var{n} "register_operand" @var{constraint}) 783169689Skan@end smallexample 784169689Skan 785169689Skan@noindent 786169689Skanwould mean, if the machine-description reader accepted @samp{:P} 787169689Skanmode suffixes. Unfortunately, it cannot, because @code{Pmode} is an 788169689Skanalias for some other mode, and might vary with machine-specific 789169689Skanoptions. @xref{Misc}. 790169689Skan@end defun 791169689Skan 792169689Skan@defun scratch_operand 793169689SkanThis predicate allows hard registers and @code{SCRATCH} expressions, 794169689Skanbut not pseudo-registers. It is used internally by @code{match_scratch}; 795169689Skanit should not be used directly. 796169689Skan@end defun 797169689Skan 798169689Skan@noindent 799169689SkanThe third category of predicates allow only some kind of memory reference. 800169689Skan 801169689Skan@defun memory_operand 802169689SkanThis predicate allows any valid reference to a quantity of mode 803169689Skan@var{mode} in memory, as determined by the weak form of 804169689Skan@code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}). 805169689Skan@end defun 806169689Skan 807169689Skan@defun address_operand 808169689SkanThis predicate is a little unusual; it allows any operand that is a 809169689Skanvalid expression for the @emph{address} of a quantity of mode 810169689Skan@var{mode}, again determined by the weak form of 811169689Skan@code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if 812169689Skan@samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to 813169689Skan@code{memory_operand}, then @var{exp} is acceptable to 814169689Skan@code{address_operand}. Note that @var{exp} does not necessarily have 815169689Skanthe mode @var{mode}. 816169689Skan@end defun 817169689Skan 818169689Skan@defun indirect_operand 819169689SkanThis is a stricter form of @code{memory_operand} which allows only 820169689Skanmemory references with a @code{general_operand} as the address 821169689Skanexpression. New uses of this predicate are discouraged, because 822169689Skan@code{general_operand} is very permissive, so it's hard to tell what 823169689Skanan @code{indirect_operand} does or does not allow. If a target has 824169689Skandifferent requirements for memory operands for different instructions, 825169689Skanit is better to define target-specific predicates which enforce the 826169689Skanhardware's requirements explicitly. 827169689Skan@end defun 828169689Skan 829169689Skan@defun push_operand 830169689SkanThis predicate allows a memory reference suitable for pushing a value 831169689Skanonto the stack. This will be a @code{MEM} which refers to 832169689Skan@code{stack_pointer_rtx}, with a side-effect in its address expression 833169689Skan(@pxref{Incdec}); which one is determined by the 834169689Skan@code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}). 835169689Skan@end defun 836169689Skan 837169689Skan@defun pop_operand 838169689SkanThis predicate allows a memory reference suitable for popping a value 839169689Skanoff the stack. Again, this will be a @code{MEM} referring to 840169689Skan@code{stack_pointer_rtx}, with a side-effect in its address 841169689Skanexpression. However, this time @code{STACK_POP_CODE} is expected. 842169689Skan@end defun 843169689Skan 844169689Skan@noindent 845169689SkanThe fourth category of predicates allow some combination of the above 846169689Skanoperands. 847169689Skan 848169689Skan@defun nonmemory_operand 849169689SkanThis predicate allows any immediate or register operand valid for @var{mode}. 850169689Skan@end defun 851169689Skan 852169689Skan@defun nonimmediate_operand 853169689SkanThis predicate allows any register or memory operand valid for @var{mode}. 854169689Skan@end defun 855169689Skan 856169689Skan@defun general_operand 857169689SkanThis predicate allows any immediate, register, or memory operand 858169689Skanvalid for @var{mode}. 859169689Skan@end defun 860169689Skan 861169689Skan@noindent 862169689SkanFinally, there is one generic operator predicate. 863169689Skan 864169689Skan@defun comparison_operator 865169689SkanThis predicate matches any expression which performs an arithmetic 866169689Skancomparison in @var{mode}; that is, @code{COMPARISON_P} is true for the 867169689Skanexpression code. 868169689Skan@end defun 869169689Skan 870169689Skan@node Defining Predicates 871169689Skan@subsection Defining Machine-Specific Predicates 872169689Skan@cindex defining predicates 873169689Skan@findex define_predicate 874169689Skan@findex define_special_predicate 875169689Skan 876169689SkanMany machines have requirements for their operands that cannot be 877169689Skanexpressed precisely using the generic predicates. You can define 878169689Skanadditional predicates using @code{define_predicate} and 879169689Skan@code{define_special_predicate} expressions. These expressions have 880169689Skanthree operands: 881169689Skan 882169689Skan@itemize @bullet 883169689Skan@item 884169689SkanThe name of the predicate, as it will be referred to in 885169689Skan@code{match_operand} or @code{match_operator} expressions. 886169689Skan 887169689Skan@item 888169689SkanAn RTL expression which evaluates to true if the predicate allows the 889169689Skanoperand @var{op}, false if it does not. This expression can only use 890169689Skanthe following RTL codes: 891169689Skan 892169689Skan@table @code 893169689Skan@item MATCH_OPERAND 894169689SkanWhen written inside a predicate expression, a @code{MATCH_OPERAND} 895169689Skanexpression evaluates to true if the predicate it names would allow 896169689Skan@var{op}. The operand number and constraint are ignored. Due to 897169689Skanlimitations in @command{genrecog}, you can only refer to generic 898169689Skanpredicates and predicates that have already been defined. 899169689Skan 900169689Skan@item MATCH_CODE 901169689SkanThis expression evaluates to true if @var{op} or a specified 902169689Skansubexpression of @var{op} has one of a given list of RTX codes. 903169689Skan 904169689SkanThe first operand of this expression is a string constant containing a 905169689Skancomma-separated list of RTX code names (in lower case). These are the 906169689Skancodes for which the @code{MATCH_CODE} will be true. 907169689Skan 908169689SkanThe second operand is a string constant which indicates what 909169689Skansubexpression of @var{op} to examine. If it is absent or the empty 910169689Skanstring, @var{op} itself is examined. Otherwise, the string constant 911169689Skanmust be a sequence of digits and/or lowercase letters. Each character 912169689Skanindicates a subexpression to extract from the current expression; for 913169689Skanthe first character this is @var{op}, for the second and subsequent 914169689Skancharacters it is the result of the previous character. A digit 915169689Skan@var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l} 916169689Skanextracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the 917169689Skanalphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The 918169689Skan@code{MATCH_CODE} then examines the RTX code of the subexpression 919169689Skanextracted by the complete string. It is not possible to extract 920169689Skancomponents of an @code{rtvec} that is not at position 0 within its RTX 921169689Skanobject. 922169689Skan 923169689Skan@item MATCH_TEST 924169689SkanThis expression has one operand, a string constant containing a C 925169689Skanexpression. The predicate's arguments, @var{op} and @var{mode}, are 926169689Skanavailable with those names in the C expression. The @code{MATCH_TEST} 927169689Skanevaluates to true if the C expression evaluates to a nonzero value. 928169689Skan@code{MATCH_TEST} expressions must not have side effects. 929169689Skan 930169689Skan@item AND 931169689Skan@itemx IOR 932169689Skan@itemx NOT 933169689Skan@itemx IF_THEN_ELSE 934169689SkanThe basic @samp{MATCH_} expressions can be combined using these 935169689Skanlogical operators, which have the semantics of the C operators 936169689Skan@samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As 937169689Skanin Common Lisp, you may give an @code{AND} or @code{IOR} expression an 938169689Skanarbitrary number of arguments; this has exactly the same effect as 939169689Skanwriting a chain of two-argument @code{AND} or @code{IOR} expressions. 940169689Skan@end table 941169689Skan 942169689Skan@item 943169689SkanAn optional block of C code, which should execute 944169689Skan@samp{@w{return true}} if the predicate is found to match and 945169689Skan@samp{@w{return false}} if it does not. It must not have any side 946169689Skaneffects. The predicate arguments, @var{op} and @var{mode}, are 947169689Skanavailable with those names. 948169689Skan 949169689SkanIf a code block is present in a predicate definition, then the RTL 950169689Skanexpression must evaluate to true @emph{and} the code block must 951169689Skanexecute @samp{@w{return true}} for the predicate to allow the operand. 952169689SkanThe RTL expression is evaluated first; do not re-check anything in the 953169689Skancode block that was checked in the RTL expression. 954169689Skan@end itemize 955169689Skan 956169689SkanThe program @command{genrecog} scans @code{define_predicate} and 957169689Skan@code{define_special_predicate} expressions to determine which RTX 958169689Skancodes are possibly allowed. You should always make this explicit in 959169689Skanthe RTL predicate expression, using @code{MATCH_OPERAND} and 960169689Skan@code{MATCH_CODE}. 961169689Skan 962169689SkanHere is an example of a simple predicate definition, from the IA64 963169689Skanmachine description: 964169689Skan 965169689Skan@smallexample 966169689Skan@group 967169689Skan;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.} 968169689Skan(define_predicate "small_addr_symbolic_operand" 969169689Skan (and (match_code "symbol_ref") 970169689Skan (match_test "SYMBOL_REF_SMALL_ADDR_P (op)"))) 971169689Skan@end group 972169689Skan@end smallexample 973169689Skan 974169689Skan@noindent 975169689SkanAnd here is another, showing the use of the C block. 976169689Skan 977169689Skan@smallexample 978169689Skan@group 979169689Skan;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.} 980169689Skan(define_predicate "gr_register_operand" 981169689Skan (match_operand 0 "register_operand") 982169689Skan@{ 983169689Skan unsigned int regno; 984169689Skan if (GET_CODE (op) == SUBREG) 985169689Skan op = SUBREG_REG (op); 986169689Skan 987169689Skan regno = REGNO (op); 988169689Skan return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno)); 989169689Skan@}) 990169689Skan@end group 991169689Skan@end smallexample 992169689Skan 993169689SkanPredicates written with @code{define_predicate} automatically include 994169689Skana test that @var{mode} is @code{VOIDmode}, or @var{op} has the same 995169689Skanmode as @var{mode}, or @var{op} is a @code{CONST_INT} or 996169689Skan@code{CONST_DOUBLE}. They do @emph{not} check specifically for 997169689Skaninteger @code{CONST_DOUBLE}, nor do they test that the value of either 998169689Skankind of constant fits in the requested mode. This is because 999169689Skantarget-specific predicates that take constants usually have to do more 1000169689Skanstringent value checks anyway. If you need the exact same treatment 1001169689Skanof @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates 1002169689Skanprovide, use a @code{MATCH_OPERAND} subexpression to call 1003169689Skan@code{const_int_operand}, @code{const_double_operand}, or 1004169689Skan@code{immediate_operand}. 1005169689Skan 1006169689SkanPredicates written with @code{define_special_predicate} do not get any 1007169689Skanautomatic mode checks, and are treated as having special mode handling 1008169689Skanby @command{genrecog}. 1009169689Skan 1010169689SkanThe program @command{genpreds} is responsible for generating code to 1011169689Skantest predicates. It also writes a header file containing function 1012169689Skandeclarations for all machine-specific predicates. It is not necessary 1013169689Skanto declare these predicates in @file{@var{cpu}-protos.h}. 101490075Sobrien@end ifset 101590075Sobrien 101690075Sobrien@c Most of this node appears by itself (in a different place) even 101790075Sobrien@c when the INTERNALS flag is clear. Passages that require the internals 101890075Sobrien@c manual's context are conditionalized to appear only in the internals manual. 101990075Sobrien@ifset INTERNALS 102090075Sobrien@node Constraints 102190075Sobrien@section Operand Constraints 102290075Sobrien@cindex operand constraints 102390075Sobrien@cindex constraints 102490075Sobrien 1025169689SkanEach @code{match_operand} in an instruction pattern can specify 1026169689Skanconstraints for the operands allowed. The constraints allow you to 1027169689Skanfine-tune matching within the set of operands allowed by the 1028169689Skanpredicate. 1029169689Skan 103090075Sobrien@end ifset 103190075Sobrien@ifclear INTERNALS 103290075Sobrien@node Constraints 103390075Sobrien@section Constraints for @code{asm} Operands 103490075Sobrien@cindex operand constraints, @code{asm} 103590075Sobrien@cindex constraints, @code{asm} 103690075Sobrien@cindex @code{asm} constraints 103790075Sobrien 103890075SobrienHere are specific details on what constraint letters you can use with 103990075Sobrien@code{asm} operands. 104090075Sobrien@end ifclear 104190075SobrienConstraints can say whether 104290075Sobrienan operand may be in a register, and which kinds of register; whether the 104390075Sobrienoperand can be a memory reference, and which kinds of address; whether the 104490075Sobrienoperand may be an immediate constant, and which possible values it may 104590075Sobrienhave. Constraints can also require two operands to match. 104690075Sobrien 104790075Sobrien@ifset INTERNALS 104890075Sobrien@menu 104990075Sobrien* Simple Constraints:: Basic use of constraints. 105090075Sobrien* Multi-Alternative:: When an insn has two alternative constraint-patterns. 105190075Sobrien* Class Preferences:: Constraints guide which hard register to put things in. 105290075Sobrien* Modifiers:: More precise control over effects of constraints. 105390075Sobrien* Machine Constraints:: Existing constraints for some particular machines. 1054169689Skan* Define Constraints:: How to define machine-specific constraints. 1055169689Skan* C Constraint Interface:: How to test constraints from C code. 105690075Sobrien@end menu 105790075Sobrien@end ifset 105890075Sobrien 105990075Sobrien@ifclear INTERNALS 106090075Sobrien@menu 106190075Sobrien* Simple Constraints:: Basic use of constraints. 106290075Sobrien* Multi-Alternative:: When an insn has two alternative constraint-patterns. 106390075Sobrien* Modifiers:: More precise control over effects of constraints. 106490075Sobrien* Machine Constraints:: Special constraints for some particular machines. 106590075Sobrien@end menu 106690075Sobrien@end ifclear 106790075Sobrien 106890075Sobrien@node Simple Constraints 106990075Sobrien@subsection Simple Constraints 107090075Sobrien@cindex simple constraints 107190075Sobrien 107290075SobrienThe simplest kind of constraint is a string full of letters, each of 107390075Sobrienwhich describes one kind of operand that is permitted. Here are 107490075Sobrienthe letters that are allowed: 107590075Sobrien 107690075Sobrien@table @asis 107790075Sobrien@item whitespace 107890075SobrienWhitespace characters are ignored and can be inserted at any position 107990075Sobrienexcept the first. This enables each alternative for different operands to 108090075Sobrienbe visually aligned in the machine description even if they have different 108190075Sobriennumber of constraints and modifiers. 108290075Sobrien 108390075Sobrien@cindex @samp{m} in constraint 108490075Sobrien@cindex memory references in constraints 108590075Sobrien@item @samp{m} 108690075SobrienA memory operand is allowed, with any kind of address that the machine 108790075Sobriensupports in general. 108890075Sobrien 108990075Sobrien@cindex offsettable address 109090075Sobrien@cindex @samp{o} in constraint 109190075Sobrien@item @samp{o} 109290075SobrienA memory operand is allowed, but only if the address is 109390075Sobrien@dfn{offsettable}. This means that adding a small integer (actually, 109490075Sobrienthe width in bytes of the operand, as determined by its machine mode) 109590075Sobrienmay be added to the address and the result is also a valid memory 109690075Sobrienaddress. 109790075Sobrien 109890075Sobrien@cindex autoincrement/decrement addressing 109990075SobrienFor example, an address which is constant is offsettable; so is an 110090075Sobrienaddress that is the sum of a register and a constant (as long as a 110190075Sobrienslightly larger constant is also within the range of address-offsets 110290075Sobriensupported by the machine); but an autoincrement or autodecrement 110390075Sobrienaddress is not offsettable. More complicated indirect/indexed 110490075Sobrienaddresses may or may not be offsettable depending on the other 110590075Sobrienaddressing modes that the machine supports. 110690075Sobrien 110790075SobrienNote that in an output operand which can be matched by another 110890075Sobrienoperand, the constraint letter @samp{o} is valid only when accompanied 110990075Sobrienby both @samp{<} (if the target machine has predecrement addressing) 111090075Sobrienand @samp{>} (if the target machine has preincrement addressing). 111190075Sobrien 111290075Sobrien@cindex @samp{V} in constraint 111390075Sobrien@item @samp{V} 111490075SobrienA memory operand that is not offsettable. In other words, anything that 111590075Sobrienwould fit the @samp{m} constraint but not the @samp{o} constraint. 111690075Sobrien 111790075Sobrien@cindex @samp{<} in constraint 111890075Sobrien@item @samp{<} 111990075SobrienA memory operand with autodecrement addressing (either predecrement or 112090075Sobrienpostdecrement) is allowed. 112190075Sobrien 112290075Sobrien@cindex @samp{>} in constraint 112390075Sobrien@item @samp{>} 112490075SobrienA memory operand with autoincrement addressing (either preincrement or 112590075Sobrienpostincrement) is allowed. 112690075Sobrien 112790075Sobrien@cindex @samp{r} in constraint 112890075Sobrien@cindex registers in constraints 112990075Sobrien@item @samp{r} 113090075SobrienA register operand is allowed provided that it is in a general 113190075Sobrienregister. 113290075Sobrien 113390075Sobrien@cindex constants in constraints 113490075Sobrien@cindex @samp{i} in constraint 113590075Sobrien@item @samp{i} 113690075SobrienAn immediate integer operand (one with constant value) is allowed. 113790075SobrienThis includes symbolic constants whose values will be known only at 1138169689Skanassembly time or later. 113990075Sobrien 114090075Sobrien@cindex @samp{n} in constraint 114190075Sobrien@item @samp{n} 114290075SobrienAn immediate integer operand with a known numeric value is allowed. 114390075SobrienMany systems cannot support assembly-time constants for operands less 114490075Sobrienthan a word wide. Constraints for these operands should use @samp{n} 114590075Sobrienrather than @samp{i}. 114690075Sobrien 114790075Sobrien@cindex @samp{I} in constraint 114890075Sobrien@item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P} 114990075SobrienOther letters in the range @samp{I} through @samp{P} may be defined in 115090075Sobriena machine-dependent fashion to permit immediate integer operands with 115190075Sobrienexplicit integer values in specified ranges. For example, on the 115290075Sobrien68000, @samp{I} is defined to stand for the range of values 1 to 8. 115390075SobrienThis is the range permitted as a shift count in the shift 115490075Sobrieninstructions. 115590075Sobrien 115690075Sobrien@cindex @samp{E} in constraint 115790075Sobrien@item @samp{E} 115890075SobrienAn immediate floating operand (expression code @code{const_double}) is 115990075Sobrienallowed, but only if the target floating point format is the same as 116090075Sobrienthat of the host machine (on which the compiler is running). 116190075Sobrien 116290075Sobrien@cindex @samp{F} in constraint 116390075Sobrien@item @samp{F} 1164117395SkanAn immediate floating operand (expression code @code{const_double} or 1165117395Skan@code{const_vector}) is allowed. 116690075Sobrien 116790075Sobrien@cindex @samp{G} in constraint 116890075Sobrien@cindex @samp{H} in constraint 116990075Sobrien@item @samp{G}, @samp{H} 117090075Sobrien@samp{G} and @samp{H} may be defined in a machine-dependent fashion to 117190075Sobrienpermit immediate floating operands in particular ranges of values. 117290075Sobrien 117390075Sobrien@cindex @samp{s} in constraint 117490075Sobrien@item @samp{s} 117590075SobrienAn immediate integer operand whose value is not an explicit integer is 117690075Sobrienallowed. 117790075Sobrien 117890075SobrienThis might appear strange; if an insn allows a constant operand with a 117990075Sobrienvalue not known at compile time, it certainly must allow any known 118090075Sobrienvalue. So why use @samp{s} instead of @samp{i}? Sometimes it allows 118190075Sobrienbetter code to be generated. 118290075Sobrien 118390075SobrienFor example, on the 68000 in a fullword instruction it is possible to 118490075Sobrienuse an immediate operand; but if the immediate value is between @minus{}128 118590075Sobrienand 127, better code results from loading the value into a register and 118690075Sobrienusing the register. This is because the load into the register can be 118790075Sobriendone with a @samp{moveq} instruction. We arrange for this to happen 118890075Sobrienby defining the letter @samp{K} to mean ``any integer outside the 118990075Sobrienrange @minus{}128 to 127'', and then specifying @samp{Ks} in the operand 119090075Sobrienconstraints. 119190075Sobrien 119290075Sobrien@cindex @samp{g} in constraint 119390075Sobrien@item @samp{g} 119490075SobrienAny register, memory or immediate integer operand is allowed, except for 119590075Sobrienregisters that are not general registers. 119690075Sobrien 119790075Sobrien@cindex @samp{X} in constraint 119890075Sobrien@item @samp{X} 119990075Sobrien@ifset INTERNALS 120090075SobrienAny operand whatsoever is allowed, even if it does not satisfy 120190075Sobrien@code{general_operand}. This is normally used in the constraint of 120290075Sobriena @code{match_scratch} when certain alternatives will not actually 120390075Sobrienrequire a scratch register. 120490075Sobrien@end ifset 120590075Sobrien@ifclear INTERNALS 120690075SobrienAny operand whatsoever is allowed. 120790075Sobrien@end ifclear 120890075Sobrien 120990075Sobrien@cindex @samp{0} in constraint 121090075Sobrien@cindex digits in constraint 121190075Sobrien@item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9} 121290075SobrienAn operand that matches the specified operand number is allowed. If a 121390075Sobriendigit is used together with letters within the same alternative, the 121490075Sobriendigit should come last. 121590075Sobrien 121690075SobrienThis number is allowed to be more than a single digit. If multiple 1217117395Skandigits are encountered consecutively, they are interpreted as a single 121890075Sobriendecimal integer. There is scant chance for ambiguity, since to-date 121990075Sobrienit has never been desirable that @samp{10} be interpreted as matching 122090075Sobrieneither operand 1 @emph{or} operand 0. Should this be desired, one 122190075Sobriencan use multiple alternatives instead. 122290075Sobrien 122390075Sobrien@cindex matching constraint 122490075Sobrien@cindex constraint, matching 122590075SobrienThis is called a @dfn{matching constraint} and what it really means is 122690075Sobrienthat the assembler has only a single operand that fills two roles 122790075Sobrien@ifset INTERNALS 122890075Sobrienconsidered separate in the RTL insn. For example, an add insn has two 122990075Sobrieninput operands and one output operand in the RTL, but on most CISC 123090075Sobrien@end ifset 123190075Sobrien@ifclear INTERNALS 123290075Sobrienwhich @code{asm} distinguishes. For example, an add instruction uses 123390075Sobrientwo input operands and an output operand, but on most CISC 123490075Sobrien@end ifclear 123590075Sobrienmachines an add instruction really has only two operands, one of them an 123690075Sobrieninput-output operand: 123790075Sobrien 123890075Sobrien@smallexample 123990075Sobrienaddl #35,r12 124090075Sobrien@end smallexample 124190075Sobrien 124290075SobrienMatching constraints are used in these circumstances. 124390075SobrienMore precisely, the two operands that match must include one input-only 124490075Sobrienoperand and one output-only operand. Moreover, the digit must be a 124590075Sobriensmaller number than the number of the operand that uses it in the 124690075Sobrienconstraint. 124790075Sobrien 124890075Sobrien@ifset INTERNALS 124990075SobrienFor operands to match in a particular case usually means that they 125090075Sobrienare identical-looking RTL expressions. But in a few special cases 125190075Sobrienspecific kinds of dissimilarity are allowed. For example, @code{*x} 125290075Sobrienas an input operand will match @code{*x++} as an output operand. 125390075SobrienFor proper results in such cases, the output template should always 125490075Sobrienuse the output-operand's number when printing the operand. 125590075Sobrien@end ifset 125690075Sobrien 125790075Sobrien@cindex load address instruction 125890075Sobrien@cindex push address instruction 125990075Sobrien@cindex address constraints 126090075Sobrien@cindex @samp{p} in constraint 126190075Sobrien@item @samp{p} 126290075SobrienAn operand that is a valid memory address is allowed. This is 126390075Sobrienfor ``load address'' and ``push address'' instructions. 126490075Sobrien 126590075Sobrien@findex address_operand 126690075Sobrien@samp{p} in the constraint must be accompanied by @code{address_operand} 126790075Sobrienas the predicate in the @code{match_operand}. This predicate interprets 126890075Sobrienthe mode specified in the @code{match_operand} as the mode of the memory 126990075Sobrienreference for which the address would be valid. 127090075Sobrien 127190075Sobrien@cindex other register constraints 127290075Sobrien@cindex extensible constraints 127390075Sobrien@item @var{other-letters} 127490075SobrienOther letters can be defined in machine-dependent fashion to stand for 127590075Sobrienparticular classes of registers or other arbitrary operand types. 127690075Sobrien@samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand 127790075Sobrienfor data, address and floating point registers. 127890075Sobrien@end table 127990075Sobrien 128090075Sobrien@ifset INTERNALS 128190075SobrienIn order to have valid assembler code, each operand must satisfy 128290075Sobrienits constraint. But a failure to do so does not prevent the pattern 128390075Sobrienfrom applying to an insn. Instead, it directs the compiler to modify 128490075Sobrienthe code so that the constraint will be satisfied. Usually this is 128590075Sobriendone by copying an operand into a register. 128690075Sobrien 128790075SobrienContrast, therefore, the two instruction patterns that follow: 128890075Sobrien 128990075Sobrien@smallexample 129090075Sobrien(define_insn "" 129190075Sobrien [(set (match_operand:SI 0 "general_operand" "=r") 129290075Sobrien (plus:SI (match_dup 0) 129390075Sobrien (match_operand:SI 1 "general_operand" "r")))] 129490075Sobrien "" 129590075Sobrien "@dots{}") 129690075Sobrien@end smallexample 129790075Sobrien 129890075Sobrien@noindent 129990075Sobrienwhich has two operands, one of which must appear in two places, and 130090075Sobrien 130190075Sobrien@smallexample 130290075Sobrien(define_insn "" 130390075Sobrien [(set (match_operand:SI 0 "general_operand" "=r") 130490075Sobrien (plus:SI (match_operand:SI 1 "general_operand" "0") 130590075Sobrien (match_operand:SI 2 "general_operand" "r")))] 130690075Sobrien "" 130790075Sobrien "@dots{}") 130890075Sobrien@end smallexample 130990075Sobrien 131090075Sobrien@noindent 131190075Sobrienwhich has three operands, two of which are required by a constraint to be 131290075Sobrienidentical. If we are considering an insn of the form 131390075Sobrien 131490075Sobrien@smallexample 131590075Sobrien(insn @var{n} @var{prev} @var{next} 131690075Sobrien (set (reg:SI 3) 131790075Sobrien (plus:SI (reg:SI 6) (reg:SI 109))) 131890075Sobrien @dots{}) 131990075Sobrien@end smallexample 132090075Sobrien 132190075Sobrien@noindent 132290075Sobrienthe first pattern would not apply at all, because this insn does not 132390075Sobriencontain two identical subexpressions in the right place. The pattern would 1324169689Skansay, ``That does not look like an add instruction; try other patterns''. 132590075SobrienThe second pattern would say, ``Yes, that's an add instruction, but there 1326169689Skanis something wrong with it''. It would direct the reload pass of the 132790075Sobriencompiler to generate additional insns to make the constraint true. The 132890075Sobrienresults might look like this: 132990075Sobrien 133090075Sobrien@smallexample 133190075Sobrien(insn @var{n2} @var{prev} @var{n} 133290075Sobrien (set (reg:SI 3) (reg:SI 6)) 133390075Sobrien @dots{}) 133490075Sobrien 133590075Sobrien(insn @var{n} @var{n2} @var{next} 133690075Sobrien (set (reg:SI 3) 133790075Sobrien (plus:SI (reg:SI 3) (reg:SI 109))) 133890075Sobrien @dots{}) 133990075Sobrien@end smallexample 134090075Sobrien 134190075SobrienIt is up to you to make sure that each operand, in each pattern, has 134290075Sobrienconstraints that can handle any RTL expression that could be present for 134390075Sobrienthat operand. (When multiple alternatives are in use, each pattern must, 134490075Sobrienfor each possible combination of operand expressions, have at least one 134590075Sobrienalternative which can handle that combination of operands.) The 134690075Sobrienconstraints don't need to @emph{allow} any possible operand---when this is 134790075Sobrienthe case, they do not constrain---but they must at least point the way to 134890075Sobrienreloading any possible operand so that it will fit. 134990075Sobrien 135090075Sobrien@itemize @bullet 135190075Sobrien@item 135290075SobrienIf the constraint accepts whatever operands the predicate permits, 135390075Sobrienthere is no problem: reloading is never necessary for this operand. 135490075Sobrien 135590075SobrienFor example, an operand whose constraints permit everything except 135690075Sobrienregisters is safe provided its predicate rejects registers. 135790075Sobrien 135890075SobrienAn operand whose predicate accepts only constant values is safe 135990075Sobrienprovided its constraints include the letter @samp{i}. If any possible 136090075Sobrienconstant value is accepted, then nothing less than @samp{i} will do; 136190075Sobrienif the predicate is more selective, then the constraints may also be 136290075Sobrienmore selective. 136390075Sobrien 136490075Sobrien@item 136590075SobrienAny operand expression can be reloaded by copying it into a register. 136690075SobrienSo if an operand's constraints allow some kind of register, it is 136790075Sobriencertain to be safe. It need not permit all classes of registers; the 136890075Sobriencompiler knows how to copy a register into another register of the 136990075Sobrienproper class in order to make an instruction valid. 137090075Sobrien 137190075Sobrien@cindex nonoffsettable memory reference 137290075Sobrien@cindex memory reference, nonoffsettable 137390075Sobrien@item 137490075SobrienA nonoffsettable memory reference can be reloaded by copying the 137590075Sobrienaddress into a register. So if the constraint uses the letter 137690075Sobrien@samp{o}, all memory references are taken care of. 137790075Sobrien 137890075Sobrien@item 137990075SobrienA constant operand can be reloaded by allocating space in memory to 138090075Sobrienhold it as preinitialized data. Then the memory reference can be used 138190075Sobrienin place of the constant. So if the constraint uses the letters 138290075Sobrien@samp{o} or @samp{m}, constant operands are not a problem. 138390075Sobrien 138490075Sobrien@item 138590075SobrienIf the constraint permits a constant and a pseudo register used in an insn 138690075Sobrienwas not allocated to a hard register and is equivalent to a constant, 138790075Sobrienthe register will be replaced with the constant. If the predicate does 138890075Sobriennot permit a constant and the insn is re-recognized for some reason, the 138990075Sobriencompiler will crash. Thus the predicate must always recognize any 139090075Sobrienobjects allowed by the constraint. 139190075Sobrien@end itemize 139290075Sobrien 139390075SobrienIf the operand's predicate can recognize registers, but the constraint does 139490075Sobriennot permit them, it can make the compiler crash. When this operand happens 139590075Sobriento be a register, the reload pass will be stymied, because it does not know 139690075Sobrienhow to copy a register temporarily into memory. 139790075Sobrien 139890075SobrienIf the predicate accepts a unary operator, the constraint applies to the 139990075Sobrienoperand. For example, the MIPS processor at ISA level 3 supports an 140090075Sobrieninstruction which adds two registers in @code{SImode} to produce a 140190075Sobrien@code{DImode} result, but only if the registers are correctly sign 140290075Sobrienextended. This predicate for the input operands accepts a 140390075Sobrien@code{sign_extend} of an @code{SImode} register. Write the constraint 140490075Sobriento indicate the type of register that is required for the operand of the 140590075Sobrien@code{sign_extend}. 140690075Sobrien@end ifset 140790075Sobrien 140890075Sobrien@node Multi-Alternative 140990075Sobrien@subsection Multiple Alternative Constraints 141090075Sobrien@cindex multiple alternative constraints 141190075Sobrien 141290075SobrienSometimes a single instruction has multiple alternative sets of possible 141390075Sobrienoperands. For example, on the 68000, a logical-or instruction can combine 141490075Sobrienregister or an immediate value into memory, or it can combine any kind of 141590075Sobrienoperand into a register; but it cannot combine one memory location into 141690075Sobrienanother. 141790075Sobrien 141890075SobrienThese constraints are represented as multiple alternatives. An alternative 141990075Sobriencan be described by a series of letters for each operand. The overall 142090075Sobrienconstraint for an operand is made from the letters for this operand 142190075Sobrienfrom the first alternative, a comma, the letters for this operand from 142290075Sobrienthe second alternative, a comma, and so on until the last alternative. 142390075Sobrien@ifset INTERNALS 142490075SobrienHere is how it is done for fullword logical-or on the 68000: 142590075Sobrien 142690075Sobrien@smallexample 142790075Sobrien(define_insn "iorsi3" 142890075Sobrien [(set (match_operand:SI 0 "general_operand" "=m,d") 142990075Sobrien (ior:SI (match_operand:SI 1 "general_operand" "%0,0") 143090075Sobrien (match_operand:SI 2 "general_operand" "dKs,dmKs")))] 143190075Sobrien @dots{}) 143290075Sobrien@end smallexample 143390075Sobrien 143490075SobrienThe first alternative has @samp{m} (memory) for operand 0, @samp{0} for 143590075Sobrienoperand 1 (meaning it must match operand 0), and @samp{dKs} for operand 143690075Sobrien2. The second alternative has @samp{d} (data register) for operand 0, 143790075Sobrien@samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and 143890075Sobrien@samp{%} in the constraints apply to all the alternatives; their 143990075Sobrienmeaning is explained in the next section (@pxref{Class Preferences}). 144090075Sobrien@end ifset 144190075Sobrien 144290075Sobrien@c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL 144390075SobrienIf all the operands fit any one alternative, the instruction is valid. 144490075SobrienOtherwise, for each alternative, the compiler counts how many instructions 144590075Sobrienmust be added to copy the operands so that that alternative applies. 144690075SobrienThe alternative requiring the least copying is chosen. If two alternatives 144790075Sobrienneed the same amount of copying, the one that comes first is chosen. 144890075SobrienThese choices can be altered with the @samp{?} and @samp{!} characters: 144990075Sobrien 145090075Sobrien@table @code 145190075Sobrien@cindex @samp{?} in constraint 145290075Sobrien@cindex question mark 145390075Sobrien@item ? 145490075SobrienDisparage slightly the alternative that the @samp{?} appears in, 145590075Sobrienas a choice when no alternative applies exactly. The compiler regards 145690075Sobrienthis alternative as one unit more costly for each @samp{?} that appears 145790075Sobrienin it. 145890075Sobrien 145990075Sobrien@cindex @samp{!} in constraint 146090075Sobrien@cindex exclamation point 146190075Sobrien@item ! 146290075SobrienDisparage severely the alternative that the @samp{!} appears in. 146390075SobrienThis alternative can still be used if it fits without reloading, 146490075Sobrienbut if reloading is needed, some other alternative will be used. 146590075Sobrien@end table 146690075Sobrien 146790075Sobrien@ifset INTERNALS 146890075SobrienWhen an insn pattern has multiple alternatives in its constraints, often 146990075Sobrienthe appearance of the assembler code is determined mostly by which 147090075Sobrienalternative was matched. When this is so, the C code for writing the 147190075Sobrienassembler code can use the variable @code{which_alternative}, which is 147290075Sobrienthe ordinal number of the alternative that was actually satisfied (0 for 147390075Sobrienthe first, 1 for the second alternative, etc.). @xref{Output Statement}. 147490075Sobrien@end ifset 147590075Sobrien 147690075Sobrien@ifset INTERNALS 147790075Sobrien@node Class Preferences 147890075Sobrien@subsection Register Class Preferences 147990075Sobrien@cindex class preference constraints 148090075Sobrien@cindex register class preference constraints 148190075Sobrien 148290075Sobrien@cindex voting between constraint alternatives 148390075SobrienThe operand constraints have another function: they enable the compiler 148490075Sobriento decide which kind of hardware register a pseudo register is best 148590075Sobrienallocated to. The compiler examines the constraints that apply to the 148690075Sobrieninsns that use the pseudo register, looking for the machine-dependent 148790075Sobrienletters such as @samp{d} and @samp{a} that specify classes of registers. 148890075SobrienThe pseudo register is put in whichever class gets the most ``votes''. 148990075SobrienThe constraint letters @samp{g} and @samp{r} also vote: they vote in 149090075Sobrienfavor of a general register. The machine description says which registers 149190075Sobrienare considered general. 149290075Sobrien 149390075SobrienOf course, on some machines all registers are equivalent, and no register 149490075Sobrienclasses are defined. Then none of this complexity is relevant. 149590075Sobrien@end ifset 149690075Sobrien 149790075Sobrien@node Modifiers 149890075Sobrien@subsection Constraint Modifier Characters 149990075Sobrien@cindex modifiers in constraints 150090075Sobrien@cindex constraint modifier characters 150190075Sobrien 150290075Sobrien@c prevent bad page break with this line 150390075SobrienHere are constraint modifier characters. 150490075Sobrien 150590075Sobrien@table @samp 150690075Sobrien@cindex @samp{=} in constraint 150790075Sobrien@item = 150890075SobrienMeans that this operand is write-only for this instruction: the previous 150990075Sobrienvalue is discarded and replaced by output data. 151090075Sobrien 151190075Sobrien@cindex @samp{+} in constraint 151290075Sobrien@item + 151390075SobrienMeans that this operand is both read and written by the instruction. 151490075Sobrien 151590075SobrienWhen the compiler fixes up the operands to satisfy the constraints, 151690075Sobrienit needs to know which operands are inputs to the instruction and 151790075Sobrienwhich are outputs from it. @samp{=} identifies an output; @samp{+} 151890075Sobrienidentifies an operand that is both input and output; all other operands 151990075Sobrienare assumed to be input only. 152090075Sobrien 152190075SobrienIf you specify @samp{=} or @samp{+} in a constraint, you put it in the 152290075Sobrienfirst character of the constraint string. 152390075Sobrien 152490075Sobrien@cindex @samp{&} in constraint 152590075Sobrien@cindex earlyclobber operand 152690075Sobrien@item & 152790075SobrienMeans (in a particular alternative) that this operand is an 152890075Sobrien@dfn{earlyclobber} operand, which is modified before the instruction is 152990075Sobrienfinished using the input operands. Therefore, this operand may not lie 153090075Sobrienin a register that is used as an input operand or as part of any memory 153190075Sobrienaddress. 153290075Sobrien 153390075Sobrien@samp{&} applies only to the alternative in which it is written. In 153490075Sobrienconstraints with multiple alternatives, sometimes one alternative 153590075Sobrienrequires @samp{&} while others do not. See, for example, the 153690075Sobrien@samp{movdf} insn of the 68000. 153790075Sobrien 153890075SobrienAn input operand can be tied to an earlyclobber operand if its only 153990075Sobrienuse as an input occurs before the early result is written. Adding 154090075Sobrienalternatives of this form often allows GCC to produce better code 154190075Sobrienwhen only some of the inputs can be affected by the earlyclobber. 154290075SobrienSee, for example, the @samp{mulsi3} insn of the ARM@. 154390075Sobrien 154490075Sobrien@samp{&} does not obviate the need to write @samp{=}. 154590075Sobrien 154690075Sobrien@cindex @samp{%} in constraint 154790075Sobrien@item % 154890075SobrienDeclares the instruction to be commutative for this operand and the 154990075Sobrienfollowing operand. This means that the compiler may interchange the 155090075Sobrientwo operands if that is the cheapest way to make all operands fit the 155190075Sobrienconstraints. 155290075Sobrien@ifset INTERNALS 155390075SobrienThis is often used in patterns for addition instructions 155490075Sobrienthat really have only two operands: the result must go in one of the 155590075Sobrienarguments. Here for example, is how the 68000 halfword-add 155690075Sobrieninstruction is defined: 155790075Sobrien 155890075Sobrien@smallexample 155990075Sobrien(define_insn "addhi3" 156090075Sobrien [(set (match_operand:HI 0 "general_operand" "=m,r") 156190075Sobrien (plus:HI (match_operand:HI 1 "general_operand" "%0,0") 156290075Sobrien (match_operand:HI 2 "general_operand" "di,g")))] 156390075Sobrien @dots{}) 156490075Sobrien@end smallexample 156590075Sobrien@end ifset 1566132718SkanGCC can only handle one commutative pair in an asm; if you use more, 1567146895Skanthe compiler may fail. Note that you need not use the modifier if 1568146895Skanthe two alternatives are strictly identical; this would only waste 1569169689Skantime in the reload pass. The modifier is not operational after 1570169689Skanregister allocation, so the result of @code{define_peephole2} 1571169689Skanand @code{define_split}s performed after reload cannot rely on 1572169689Skan@samp{%} to make the intended insn match. 157390075Sobrien 157490075Sobrien@cindex @samp{#} in constraint 157590075Sobrien@item # 157690075SobrienSays that all following characters, up to the next comma, are to be 157790075Sobrienignored as a constraint. They are significant only for choosing 157890075Sobrienregister preferences. 157990075Sobrien 158090075Sobrien@cindex @samp{*} in constraint 158190075Sobrien@item * 158290075SobrienSays that the following character should be ignored when choosing 158390075Sobrienregister preferences. @samp{*} has no effect on the meaning of the 158490075Sobrienconstraint as a constraint, and no effect on reloading. 158590075Sobrien 158690075Sobrien@ifset INTERNALS 158790075SobrienHere is an example: the 68000 has an instruction to sign-extend a 158890075Sobrienhalfword in a data register, and can also sign-extend a value by 158990075Sobriencopying it into an address register. While either kind of register is 159090075Sobrienacceptable, the constraints on an address-register destination are 159190075Sobrienless strict, so it is best if register allocation makes an address 159290075Sobrienregister its goal. Therefore, @samp{*} is used so that the @samp{d} 159390075Sobrienconstraint letter (for data register) is ignored when computing 159490075Sobrienregister preferences. 159590075Sobrien 159690075Sobrien@smallexample 159790075Sobrien(define_insn "extendhisi2" 159890075Sobrien [(set (match_operand:SI 0 "general_operand" "=*d,a") 159990075Sobrien (sign_extend:SI 160090075Sobrien (match_operand:HI 1 "general_operand" "0,g")))] 160190075Sobrien @dots{}) 160290075Sobrien@end smallexample 160390075Sobrien@end ifset 160490075Sobrien@end table 160590075Sobrien 160690075Sobrien@node Machine Constraints 160790075Sobrien@subsection Constraints for Particular Machines 160890075Sobrien@cindex machine specific constraints 160990075Sobrien@cindex constraints, machine specific 161090075Sobrien 161190075SobrienWhenever possible, you should use the general-purpose constraint letters 161290075Sobrienin @code{asm} arguments, since they will convey meaning more readily to 161390075Sobrienpeople reading your code. Failing that, use the constraint letters 161490075Sobrienthat usually have very similar meanings across architectures. The most 161590075Sobriencommonly used constraints are @samp{m} and @samp{r} (for memory and 161690075Sobriengeneral-purpose registers respectively; @pxref{Simple Constraints}), and 161790075Sobrien@samp{I}, usually the letter indicating the most common 161890075Sobrienimmediate-constant format. 161990075Sobrien 1620169689SkanEach architecture defines additional constraints. These constraints 1621169689Skanare used by the compiler itself for instruction generation, as well as 1622169689Skanfor @code{asm} statements; therefore, some of the constraints are not 1623169689Skanparticularly useful for @code{asm}. Here is a summary of some of the 1624169689Skanmachine-dependent constraints available on some particular machines; 1625169689Skanit includes both constraints that are useful for @code{asm} and 1626169689Skanconstraints that aren't. The compiler source file mentioned in the 1627169689Skantable heading for each architecture is the definitive reference for 1628169689Skanthe meanings of that architecture's constraints. 1629169689Skan 163090075Sobrien@table @emph 1631169689Skan@item ARM family---@file{config/arm/arm.h} 163290075Sobrien@table @code 163390075Sobrien@item f 163490075SobrienFloating-point register 163590075Sobrien 1636169689Skan@item w 1637169689SkanVFP floating-point register 1638169689Skan 163990075Sobrien@item F 164090075SobrienOne of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0 164190075Sobrienor 10.0 164290075Sobrien 164390075Sobrien@item G 164490075SobrienFloating-point constant that would satisfy the constraint @samp{F} if it 164590075Sobrienwere negated 164690075Sobrien 164790075Sobrien@item I 164890075SobrienInteger that is valid as an immediate operand in a data processing 164990075Sobrieninstruction. That is, an integer in the range 0 to 255 rotated by a 165090075Sobrienmultiple of 2 165190075Sobrien 165290075Sobrien@item J 165390075SobrienInteger in the range @minus{}4095 to 4095 165490075Sobrien 165590075Sobrien@item K 165690075SobrienInteger that satisfies constraint @samp{I} when inverted (ones complement) 165790075Sobrien 165890075Sobrien@item L 165990075SobrienInteger that satisfies constraint @samp{I} when negated (twos complement) 166090075Sobrien 166190075Sobrien@item M 166290075SobrienInteger in the range 0 to 32 166390075Sobrien 166490075Sobrien@item Q 166590075SobrienA memory reference where the exact address is in a single register 166690075Sobrien(`@samp{m}' is preferable for @code{asm} statements) 166790075Sobrien 166890075Sobrien@item R 166990075SobrienAn item in the constant pool 167090075Sobrien 167190075Sobrien@item S 167290075SobrienA symbol in the text segment of the current file 1673169689Skan 1674169689Skan@item Uv 1675169689SkanA memory reference suitable for VFP load/store insns (reg+constant offset) 1676169689Skan 1677169689Skan@item Uy 1678169689SkanA memory reference suitable for iWMMXt load/store instructions. 1679169689Skan 1680169689Skan@item Uq 1681169689SkanA memory reference suitable for the ARMv4 ldrsb instruction. 168290075Sobrien@end table 168390075Sobrien 1684169689Skan@item AVR family---@file{config/avr/constraints.md} 168590075Sobrien@table @code 168690075Sobrien@item l 168790075SobrienRegisters from r0 to r15 168890075Sobrien 168990075Sobrien@item a 169090075SobrienRegisters from r16 to r23 169190075Sobrien 169290075Sobrien@item d 169390075SobrienRegisters from r16 to r31 169490075Sobrien 169590075Sobrien@item w 169690075SobrienRegisters from r24 to r31. These registers can be used in @samp{adiw} command 169790075Sobrien 169890075Sobrien@item e 169990075SobrienPointer register (r26--r31) 170090075Sobrien 170190075Sobrien@item b 170290075SobrienBase pointer register (r28--r31) 170390075Sobrien 170490075Sobrien@item q 170590075SobrienStack pointer register (SPH:SPL) 170690075Sobrien 170790075Sobrien@item t 170890075SobrienTemporary register r0 170990075Sobrien 171090075Sobrien@item x 171190075SobrienRegister pair X (r27:r26) 171290075Sobrien 171390075Sobrien@item y 171490075SobrienRegister pair Y (r29:r28) 171590075Sobrien 171690075Sobrien@item z 171790075SobrienRegister pair Z (r31:r30) 171890075Sobrien 171990075Sobrien@item I 172090075SobrienConstant greater than @minus{}1, less than 64 172190075Sobrien 172290075Sobrien@item J 172390075SobrienConstant greater than @minus{}64, less than 1 172490075Sobrien 172590075Sobrien@item K 172690075SobrienConstant integer 2 172790075Sobrien 172890075Sobrien@item L 172990075SobrienConstant integer 0 173090075Sobrien 173190075Sobrien@item M 173290075SobrienConstant that fits in 8 bits 173390075Sobrien 173490075Sobrien@item N 173590075SobrienConstant integer @minus{}1 173690075Sobrien 173790075Sobrien@item O 173890075SobrienConstant integer 8, 16, or 24 173990075Sobrien 174090075Sobrien@item P 174190075SobrienConstant integer 1 174290075Sobrien 174390075Sobrien@item G 174490075SobrienA floating point constant 0.0 174590075Sobrien@end table 174690075Sobrien 1747169689Skan@item CRX Architecture---@file{config/crx/crx.h} 174890075Sobrien@table @code 1749169689Skan 175090075Sobrien@item b 1751169689SkanRegisters from r0 to r14 (registers without stack pointer) 1752169689Skan 1753169689Skan@item l 1754169689SkanRegister r16 (64-bit accumulator lo register) 1755169689Skan 1756169689Skan@item h 1757169689SkanRegister r17 (64-bit accumulator hi register) 1758169689Skan 1759169689Skan@item k 1760169689SkanRegister pair r16-r17. (64-bit accumulator lo-hi pair) 1761169689Skan 1762169689Skan@item I 1763169689SkanConstant that fits in 3 bits 1764169689Skan 1765169689Skan@item J 1766169689SkanConstant that fits in 4 bits 1767169689Skan 1768169689Skan@item K 1769169689SkanConstant that fits in 5 bits 1770169689Skan 1771169689Skan@item L 1772169689SkanConstant that is one of -1, 4, -4, 7, 8, 12, 16, 20, 32, 48 1773169689Skan 1774169689Skan@item G 1775169689SkanFloating point constant that is legal for store immediate 1776169689Skan@end table 1777169689Skan 1778169689Skan@item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h} 1779169689Skan@table @code 1780169689Skan@item b 178190075SobrienAddress base register 178290075Sobrien 178390075Sobrien@item f 178490075SobrienFloating point register 178590075Sobrien 1786132718Skan@item v 1787132718SkanVector register 1788132718Skan 178990075Sobrien@item h 179090075Sobrien@samp{MQ}, @samp{CTR}, or @samp{LINK} register 179190075Sobrien 179290075Sobrien@item q 179390075Sobrien@samp{MQ} register 179490075Sobrien 179590075Sobrien@item c 179690075Sobrien@samp{CTR} register 179790075Sobrien 179890075Sobrien@item l 179990075Sobrien@samp{LINK} register 180090075Sobrien 180190075Sobrien@item x 180290075Sobrien@samp{CR} register (condition register) number 0 180390075Sobrien 180490075Sobrien@item y 180590075Sobrien@samp{CR} register (condition register) 180690075Sobrien 180790075Sobrien@item z 180890075Sobrien@samp{FPMEM} stack memory for FPR-GPR transfers 180990075Sobrien 181090075Sobrien@item I 181190075SobrienSigned 16-bit constant 181290075Sobrien 181390075Sobrien@item J 181490075SobrienUnsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for 181590075Sobrien@code{SImode} constants) 181690075Sobrien 181790075Sobrien@item K 181890075SobrienUnsigned 16-bit constant 181990075Sobrien 182090075Sobrien@item L 182190075SobrienSigned 16-bit constant shifted left 16 bits 182290075Sobrien 182390075Sobrien@item M 182490075SobrienConstant larger than 31 182590075Sobrien 182690075Sobrien@item N 182790075SobrienExact power of 2 182890075Sobrien 182990075Sobrien@item O 183090075SobrienZero 183190075Sobrien 183290075Sobrien@item P 183390075SobrienConstant whose negation is a signed 16-bit constant 183490075Sobrien 183590075Sobrien@item G 183690075SobrienFloating point constant that can be loaded into a register with one 183790075Sobrieninstruction per word 183890075Sobrien 183990075Sobrien@item Q 184090075SobrienMemory operand that is an offset from a register (@samp{m} is preferable 184190075Sobrienfor @code{asm} statements) 184290075Sobrien 184390075Sobrien@item R 184490075SobrienAIX TOC entry 184590075Sobrien 184690075Sobrien@item S 184790075SobrienConstant suitable as a 64-bit mask operand 184890075Sobrien 184990075Sobrien@item T 185090075SobrienConstant suitable as a 32-bit mask operand 185190075Sobrien 185290075Sobrien@item U 185390075SobrienSystem V Release 4 small data area reference 185490075Sobrien@end table 185590075Sobrien 1856169689Skan@item MorphoTech family---@file{config/mt/mt.h} 185790075Sobrien@table @code 1858169689Skan@item I 1859169689SkanConstant for an arithmetic insn (16-bit signed integer). 186090075Sobrien 1861169689Skan@item J 1862169689SkanThe constant 0. 186390075Sobrien 1864169689Skan@item K 1865169689SkanConstant for a logical insn (16-bit zero-extended integer). 1866169689Skan 1867169689Skan@item L 1868169689SkanA constant that can be loaded with @code{lui} (i.e.@: the bottom 16 1869169689Skanbits are zero). 1870169689Skan 1871169689Skan@item M 1872169689SkanA constant that takes two words to load (i.e.@: not matched by 1873169689Skan@code{I}, @code{K}, or @code{L}). 1874169689Skan 1875169689Skan@item N 1876169689SkanNegative 16-bit constants other than -65536. 1877169689Skan 1878169689Skan@item O 1879169689SkanA 15-bit signed integer constant. 1880169689Skan 1881169689Skan@item P 1882169689SkanA positive 16-bit constant. 1883169689Skan@end table 1884169689Skan 1885169689Skan@item Intel 386---@file{config/i386/constraints.md} 1886169689Skan@table @code 188790075Sobrien@item R 1888169689SkanLegacy register---the eight integer registers available on all 1889169689Skani386 processors (@code{a}, @code{b}, @code{c}, @code{d}, 1890169689Skan@code{si}, @code{di}, @code{bp}, @code{sp}). 189190075Sobrien 1892169689Skan@item q 1893169689SkanAny register accessible as @code{@var{r}l}. In 32-bit mode, @code{a}, 1894169689Skan@code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register. 189590075Sobrien 1896169689Skan@item Q 1897169689SkanAny register accessible as @code{@var{r}h}: @code{a}, @code{b}, 1898169689Skan@code{c}, and @code{d}. 189990075Sobrien 1900169689Skan@ifset INTERNALS 1901169689Skan@item l 1902169689SkanAny register that can be used as the index in a base+index memory 1903169689Skanaccess: that is, any general register except the stack pointer. 1904169689Skan@end ifset 190590075Sobrien 190690075Sobrien@item a 1907169689SkanThe @code{a} register. 190890075Sobrien 190990075Sobrien@item b 1910169689SkanThe @code{b} register. 191190075Sobrien 191290075Sobrien@item c 1913169689SkanThe @code{c} register. 191490075Sobrien 191590075Sobrien@item d 1916169689SkanThe @code{d} register. 191790075Sobrien 1918169689Skan@item S 1919169689SkanThe @code{si} register. 1920169689Skan 192190075Sobrien@item D 1922169689SkanThe @code{di} register. 192390075Sobrien 1924169689Skan@item A 1925169689SkanThe @code{a} and @code{d} registers, as a pair (for instructions that 1926169689Skanreturn half the result in one and half in the other). 192790075Sobrien 1928169689Skan@item f 1929169689SkanAny 80387 floating-point (stack) register. 193090075Sobrien 1931169689Skan@item t 1932169689SkanTop of 80387 floating-point stack (@code{%st(0)}). 1933169689Skan 1934169689Skan@item u 1935169689SkanSecond from top of 80387 floating-point stack (@code{%st(1)}). 1936169689Skan 193790075Sobrien@item y 1938169689SkanAny MMX register. 193990075Sobrien 1940169689Skan@item x 1941169689SkanAny SSE register. 1942169689Skan 1943169689Skan@ifset INTERNALS 1944169689Skan@item Y 1945169689SkanAny SSE2 register. 1946169689Skan@end ifset 1947169689Skan 194890075Sobrien@item I 1949169689SkanInteger constant in the range 0 @dots{} 31, for 32-bit shifts. 195090075Sobrien 195190075Sobrien@item J 1952169689SkanInteger constant in the range 0 @dots{} 63, for 64-bit shifts. 195390075Sobrien 195490075Sobrien@item K 1955169689SkanSigned 8-bit integer constant. 195690075Sobrien 195790075Sobrien@item L 1958169689Skan@code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move. 195990075Sobrien 196090075Sobrien@item M 1961169689Skan0, 1, 2, or 3 (shifts for the @code{lea} instruction). 196290075Sobrien 196390075Sobrien@item N 1964169689SkanUnsigned 8-bit integer constant (for @code{in} and @code{out} 1965169689Skaninstructions). 196690075Sobrien 1967169689Skan@ifset INTERNALS 1968169689Skan@item O 1969169689SkanInteger constant in the range 0 @dots{} 127, for 128-bit shifts. 1970169689Skan@end ifset 197190075Sobrien 197290075Sobrien@item G 1973169689SkanStandard 80387 floating point constant. 197490075Sobrien 1975169689Skan@item C 1976169689SkanStandard SSE floating point constant. 197790075Sobrien 1978169689Skan@item e 1979169689Skan32-bit signed integer constant, or a symbolic reference known 1980169689Skanto fit that range (for immediate operands in sign-extending x86-64 1981169689Skaninstructions). 198290075Sobrien 1983169689Skan@item Z 1984169689Skan32-bit unsigned integer constant, or a symbolic reference known 1985169689Skanto fit that range (for immediate operands in zero-extending x86-64 1986169689Skaninstructions). 198790075Sobrien 198890075Sobrien@end table 198990075Sobrien 1990169689Skan@item Intel IA-64---@file{config/ia64/ia64.h} 1991117395Skan@table @code 1992117395Skan@item a 1993117395SkanGeneral register @code{r0} to @code{r3} for @code{addl} instruction 1994117395Skan 1995117395Skan@item b 1996117395SkanBranch register 1997117395Skan 1998117395Skan@item c 1999117395SkanPredicate register (@samp{c} as in ``conditional'') 2000117395Skan 2001117395Skan@item d 2002117395SkanApplication register residing in M-unit 2003117395Skan 2004117395Skan@item e 2005117395SkanApplication register residing in I-unit 2006117395Skan 2007117395Skan@item f 2008117395SkanFloating-point register 2009117395Skan 2010117395Skan@item m 2011117395SkanMemory operand. 2012117395SkanRemember that @samp{m} allows postincrement and postdecrement which 2013117395Skanrequire printing with @samp{%Pn} on IA-64. 2014117395SkanUse @samp{S} to disallow postincrement and postdecrement. 2015117395Skan 2016117395Skan@item G 2017117395SkanFloating-point constant 0.0 or 1.0 2018117395Skan 2019117395Skan@item I 2020117395Skan14-bit signed integer constant 2021117395Skan 2022117395Skan@item J 2023117395Skan22-bit signed integer constant 2024117395Skan 2025117395Skan@item K 2026117395Skan8-bit signed integer constant for logical instructions 2027117395Skan 2028117395Skan@item L 2029117395Skan8-bit adjusted signed integer constant for compare pseudo-ops 2030117395Skan 2031117395Skan@item M 2032117395Skan6-bit unsigned integer constant for shift counts 2033117395Skan 2034117395Skan@item N 2035117395Skan9-bit signed integer constant for load and store postincrements 2036117395Skan 2037117395Skan@item O 2038117395SkanThe constant zero 2039117395Skan 2040117395Skan@item P 2041169689Skan0 or @minus{}1 for @code{dep} instruction 2042117395Skan 2043117395Skan@item Q 2044117395SkanNon-volatile memory for floating-point loads and stores 2045117395Skan 2046117395Skan@item R 2047117395SkanInteger constant in the range 1 to 4 for @code{shladd} instruction 2048117395Skan 2049117395Skan@item S 2050117395SkanMemory operand except postincrement and postdecrement 2051117395Skan@end table 2052117395Skan 2053169689Skan@item FRV---@file{config/frv/frv.h} 2054117395Skan@table @code 2055117395Skan@item a 2056117395SkanRegister in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}). 2057117395Skan 2058117395Skan@item b 2059117395SkanRegister in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}). 2060117395Skan 2061117395Skan@item c 2062117395SkanRegister in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and 2063117395Skan@code{icc0} to @code{icc3}). 2064117395Skan 2065117395Skan@item d 2066117395SkanRegister in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}). 2067117395Skan 2068117395Skan@item e 2069117395SkanRegister in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}). 2070117395SkanOdd registers are excluded not in the class but through the use of a machine 2071117395Skanmode larger than 4 bytes. 2072117395Skan 2073117395Skan@item f 2074117395SkanRegister in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}). 2075117395Skan 2076117395Skan@item h 2077117395SkanRegister in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}). 2078117395SkanOdd registers are excluded not in the class but through the use of a machine 2079117395Skanmode larger than 4 bytes. 2080117395Skan 2081117395Skan@item l 2082117395SkanRegister in the class @code{LR_REG} (the @code{lr} register). 2083117395Skan 2084117395Skan@item q 2085117395SkanRegister in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}). 2086117395SkanRegister numbers not divisible by 4 are excluded not in the class but through 2087117395Skanthe use of a machine mode larger than 8 bytes. 2088117395Skan 2089117395Skan@item t 2090117395SkanRegister in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}). 2091117395Skan 2092117395Skan@item u 2093117395SkanRegister in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}). 2094117395Skan 2095117395Skan@item v 2096117395SkanRegister in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}). 2097117395Skan 2098117395Skan@item w 2099117395SkanRegister in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}). 2100117395Skan 2101117395Skan@item x 2102117395SkanRegister in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}). 2103117395SkanRegister numbers not divisible by 4 are excluded not in the class but through 2104117395Skanthe use of a machine mode larger than 8 bytes. 2105117395Skan 2106117395Skan@item z 2107117395SkanRegister in the class @code{SPR_REGS} (@code{lcr} and @code{lr}). 2108117395Skan 2109117395Skan@item A 2110117395SkanRegister in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}). 2111117395Skan 2112117395Skan@item B 2113117395SkanRegister in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}). 2114117395Skan 2115117395Skan@item C 2116117395SkanRegister in the class @code{CR_REGS} (@code{cc0} to @code{cc7}). 2117117395Skan 2118117395Skan@item G 2119117395SkanFloating point constant zero 2120117395Skan 2121117395Skan@item I 2122117395Skan6-bit signed integer constant 2123117395Skan 2124117395Skan@item J 2125117395Skan10-bit signed integer constant 2126117395Skan 2127117395Skan@item L 2128117395Skan16-bit signed integer constant 2129117395Skan 2130117395Skan@item M 2131117395Skan16-bit unsigned integer constant 2132117395Skan 2133117395Skan@item N 2134117395Skan12-bit signed integer constant that is negative---i.e.@: in the 2135117395Skanrange of @minus{}2048 to @minus{}1 2136117395Skan 2137117395Skan@item O 2138117395SkanConstant zero 2139117395Skan 2140117395Skan@item P 2141117395Skan12-bit signed integer constant that is greater than zero---i.e.@: in the 2142117395Skanrange of 1 to 2047. 2143117395Skan 2144117395Skan@end table 2145117395Skan 2146169689Skan@item Blackfin family---@file{config/bfin/bfin.h} 2147117395Skan@table @code 2148117395Skan@item a 2149169689SkanP register 2150117395Skan 2151169689Skan@item d 2152169689SkanD register 2153169689Skan 2154169689Skan@item z 2155169689SkanA call clobbered P register. 2156169689Skan 2157169689Skan@item D 2158169689SkanEven-numbered D register 2159169689Skan 2160169689Skan@item W 2161169689SkanOdd-numbered D register 2162169689Skan 2163169689Skan@item e 2164169689SkanAccumulator register. 2165169689Skan 2166169689Skan@item A 2167169689SkanEven-numbered accumulator register. 2168169689Skan 2169169689Skan@item B 2170169689SkanOdd-numbered accumulator register. 2171169689Skan 2172169689Skan@item b 2173169689SkanI register 2174169689Skan 2175169689Skan@item v 2176169689SkanB register 2177169689Skan 2178117395Skan@item f 2179169689SkanM register 2180117395Skan 2181169689Skan@item c 2182169689SkanRegisters used for circular buffering, i.e. I, B, or L registers. 2183117395Skan 2184169689Skan@item C 2185169689SkanThe CC register. 2186169689Skan 2187169689Skan@item t 2188169689SkanLT0 or LT1. 2189169689Skan 2190117395Skan@item k 2191169689SkanLC0 or LC1. 2192117395Skan 2193169689Skan@item u 2194169689SkanLB0 or LB1. 2195117395Skan 2196169689Skan@item x 2197169689SkanAny D, P, B, M, I or L register. 2198169689Skan 2199117395Skan@item y 2200169689SkanAdditional registers typically used only in prologues and epilogues: RETS, 2201169689SkanRETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP. 2202117395Skan 2203169689Skan@item w 2204169689SkanAny register except accumulators or CC. 2205117395Skan 2206169689Skan@item Ksh 2207169689SkanSigned 16 bit integer (in the range -32768 to 32767) 2208117395Skan 2209169689Skan@item Kuh 2210169689SkanUnsigned 16 bit integer (in the range 0 to 65535) 2211117395Skan 2212169689Skan@item Ks7 2213169689SkanSigned 7 bit integer (in the range -64 to 63) 2214117395Skan 2215169689Skan@item Ku7 2216169689SkanUnsigned 7 bit integer (in the range 0 to 127) 2217117395Skan 2218169689Skan@item Ku5 2219169689SkanUnsigned 5 bit integer (in the range 0 to 31) 2220117395Skan 2221169689Skan@item Ks4 2222169689SkanSigned 4 bit integer (in the range -8 to 7) 2223117395Skan 2224169689Skan@item Ks3 2225169689SkanSigned 3 bit integer (in the range -3 to 4) 2226117395Skan 2227169689Skan@item Ku3 2228169689SkanUnsigned 3 bit integer (in the range 0 to 7) 2229117395Skan 2230169689Skan@item P@var{n} 2231169689SkanConstant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4. 2232169689Skan 2233169689Skan@item M1 2234169689SkanConstant 255. 2235169689Skan 2236169689Skan@item M2 2237169689SkanConstant 65535. 2238169689Skan 2239117395Skan@item J 2240169689SkanAn integer constant with exactly a single bit set. 2241117395Skan 2242117395Skan@item L 2243169689SkanAn integer constant with all bits set except exactly one. 2244117395Skan 2245169689Skan@item H 2246117395Skan 2247169689Skan@item Q 2248169689SkanAny SYMBOL_REF. 2249169689Skan@end table 2250117395Skan 2251169689Skan@item M32C---@file{config/m32c/m32c.c} 2252169689Skan@table @code 2253169689Skan@item Rsp 2254169689Skan@itemx Rfb 2255169689Skan@itemx Rsb 2256169689Skan@samp{$sp}, @samp{$fb}, @samp{$sb}. 2257117395Skan 2258169689Skan@item Rcr 2259169689SkanAny control register, when they're 16 bits wide (nothing if control 2260169689Skanregisters are 24 bits wide) 2261169689Skan 2262169689Skan@item Rcl 2263169689SkanAny control register, when they're 24 bits wide. 2264169689Skan 2265169689Skan@item R0w 2266169689Skan@itemx R1w 2267169689Skan@itemx R2w 2268169689Skan@itemx R3w 2269169689Skan$r0, $r1, $r2, $r3. 2270169689Skan 2271169689Skan@item R02 2272169689Skan$r0 or $r2, or $r2r0 for 32 bit values. 2273169689Skan 2274169689Skan@item R13 2275169689Skan$r1 or $r3, or $r3r1 for 32 bit values. 2276169689Skan 2277169689Skan@item Rdi 2278169689SkanA register that can hold a 64 bit value. 2279169689Skan 2280169689Skan@item Rhl 2281169689Skan$r0 or $r1 (registers with addressable high/low bytes) 2282169689Skan 2283169689Skan@item R23 2284169689Skan$r2 or $r3 2285169689Skan 2286169689Skan@item Raa 2287169689SkanAddress registers 2288169689Skan 2289169689Skan@item Raw 2290169689SkanAddress registers when they're 16 bits wide. 2291169689Skan 2292169689Skan@item Ral 2293169689SkanAddress registers when they're 24 bits wide. 2294169689Skan 2295169689Skan@item Rqi 2296169689SkanRegisters that can hold QI values. 2297169689Skan 2298169689Skan@item Rad 2299169689SkanRegisters that can be used with displacements ($a0, $a1, $sb). 2300169689Skan 2301169689Skan@item Rsi 2302169689SkanRegisters that can hold 32 bit values. 2303169689Skan 2304169689Skan@item Rhi 2305169689SkanRegisters that can hold 16 bit values. 2306169689Skan 2307169689Skan@item Rhc 2308169689SkanRegisters chat can hold 16 bit values, including all control 2309169689Skanregisters. 2310169689Skan 2311169689Skan@item Rra 2312169689Skan$r0 through R1, plus $a0 and $a1. 2313169689Skan 2314169689Skan@item Rfl 2315169689SkanThe flags register. 2316169689Skan 2317169689Skan@item Rmm 2318169689SkanThe memory-based pseudo-registers $mem0 through $mem15. 2319169689Skan 2320169689Skan@item Rpi 2321169689SkanRegisters that can hold pointers (16 bit registers for r8c, m16c; 24 2322169689Skanbit registers for m32cm, m32c). 2323169689Skan 2324169689Skan@item Rpa 2325169689SkanMatches multiple registers in a PARALLEL to form a larger register. 2326169689SkanUsed to match function return values. 2327169689Skan 2328169689Skan@item Is3 2329169689Skan-8 @dots{} 7 2330169689Skan 2331169689Skan@item IS1 2332169689Skan-128 @dots{} 127 2333169689Skan 2334169689Skan@item IS2 2335169689Skan-32768 @dots{} 32767 2336169689Skan 2337169689Skan@item IU2 2338169689Skan0 @dots{} 65535 2339169689Skan 2340169689Skan@item In4 2341169689Skan-8 @dots{} -1 or 1 @dots{} 8 2342169689Skan 2343169689Skan@item In5 2344169689Skan-16 @dots{} -1 or 1 @dots{} 16 2345169689Skan 2346169689Skan@item In6 2347169689Skan-32 @dots{} -1 or 1 @dots{} 32 2348169689Skan 2349169689Skan@item IM2 2350169689Skan-65536 @dots{} -1 2351169689Skan 2352169689Skan@item Ilb 2353169689SkanAn 8 bit value with exactly one bit set. 2354169689Skan 2355169689Skan@item Ilw 2356169689SkanA 16 bit value with exactly one bit set. 2357169689Skan 2358169689Skan@item Sd 2359169689SkanThe common src/dest memory addressing modes. 2360169689Skan 2361169689Skan@item Sa 2362169689SkanMemory addressed using $a0 or $a1. 2363169689Skan 2364169689Skan@item Si 2365169689SkanMemory addressed with immediate addresses. 2366169689Skan 2367169689Skan@item Ss 2368169689SkanMemory addressed using the stack pointer ($sp). 2369169689Skan 2370169689Skan@item Sf 2371169689SkanMemory addressed using the frame base register ($fb). 2372169689Skan 2373169689Skan@item Ss 2374169689SkanMemory addressed using the small base register ($sb). 2375169689Skan 2376169689Skan@item S1 2377169689Skan$r1h 2378117395Skan@end table 2379117395Skan 2380169689Skan@item MIPS---@file{config/mips/constraints.md} 238190075Sobrien@table @code 238290075Sobrien@item d 2383169689SkanAn address register. This is equivalent to @code{r} unless 2384169689Skangenerating MIPS16 code. 238590075Sobrien 238690075Sobrien@item f 2387169689SkanA floating-point register (if available). 238890075Sobrien 238990075Sobrien@item h 2390169689SkanThe @code{hi} register. 239190075Sobrien 239290075Sobrien@item l 2393169689SkanThe @code{lo} register. 239490075Sobrien 239590075Sobrien@item x 2396169689SkanThe @code{hi} and @code{lo} registers. 239790075Sobrien 2398169689Skan@item c 2399169689SkanA register suitable for use in an indirect jump. This will always be 2400169689Skan@code{$25} for @option{-mabicalls}. 2401169689Skan 240290075Sobrien@item y 2403169689SkanEquivalent to @code{r}; retained for backwards compatibility. 240490075Sobrien 240590075Sobrien@item z 2406169689SkanA floating-point condition code register. 240790075Sobrien 240890075Sobrien@item I 2409169689SkanA signed 16-bit constant (for arithmetic instructions). 241090075Sobrien 241190075Sobrien@item J 2412169689SkanInteger zero. 241390075Sobrien 241490075Sobrien@item K 2415169689SkanAn unsigned 16-bit constant (for logic instructions). 241690075Sobrien 241790075Sobrien@item L 2418169689SkanA signed 32-bit constant in which the lower 16 bits are zero. 2419169689SkanSuch constants can be loaded using @code{lui}. 242090075Sobrien 242190075Sobrien@item M 2422169689SkanA constant that cannot be loaded using @code{lui}, @code{addiu} 2423169689Skanor @code{ori}. 242490075Sobrien 242590075Sobrien@item N 2426169689SkanA constant in the range -65535 to -1 (inclusive). 242790075Sobrien 242890075Sobrien@item O 2429169689SkanA signed 15-bit constant. 243090075Sobrien 243190075Sobrien@item P 2432169689SkanA constant in the range 1 to 65535 (inclusive). 243390075Sobrien 243490075Sobrien@item G 2435169689SkanFloating-point zero. 243690075Sobrien 243790075Sobrien@item R 2438169689SkanAn address that can be used in a non-macro load or store. 243990075Sobrien@end table 244090075Sobrien 2441169689Skan@item Motorola 680x0---@file{config/m68k/m68k.h} 244290075Sobrien@table @code 244390075Sobrien@item a 244490075SobrienAddress register 244590075Sobrien 244690075Sobrien@item d 244790075SobrienData register 244890075Sobrien 244990075Sobrien@item f 245090075Sobrien68881 floating-point register, if available 245190075Sobrien 245290075Sobrien@item I 245390075SobrienInteger in the range 1 to 8 245490075Sobrien 245590075Sobrien@item J 245690075Sobrien16-bit signed number 245790075Sobrien 245890075Sobrien@item K 245990075SobrienSigned number whose magnitude is greater than 0x80 246090075Sobrien 246190075Sobrien@item L 246290075SobrienInteger in the range @minus{}8 to @minus{}1 246390075Sobrien 246490075Sobrien@item M 246590075SobrienSigned number whose magnitude is greater than 0x100 246690075Sobrien 246790075Sobrien@item G 246890075SobrienFloating point constant that is not a 68881 constant 246990075Sobrien@end table 247090075Sobrien 2471169689Skan@item Motorola 68HC11 & 68HC12 families---@file{config/m68hc11/m68hc11.h} 247290075Sobrien@table @code 247390075Sobrien@item a 2474169689SkanRegister `a' 247590075Sobrien 247690075Sobrien@item b 2477169689SkanRegister `b' 247890075Sobrien 247990075Sobrien@item d 2480169689SkanRegister `d' 248190075Sobrien 248290075Sobrien@item q 248390075SobrienAn 8-bit register 248490075Sobrien 248590075Sobrien@item t 248690075SobrienTemporary soft register _.tmp 248790075Sobrien 248890075Sobrien@item u 248990075SobrienA soft register _.d1 to _.d31 249090075Sobrien 249190075Sobrien@item w 249290075SobrienStack pointer register 249390075Sobrien 249490075Sobrien@item x 2495169689SkanRegister `x' 249690075Sobrien 249790075Sobrien@item y 2498169689SkanRegister `y' 249990075Sobrien 250090075Sobrien@item z 2501169689SkanPseudo register `z' (replaced by `x' or `y' at the end) 250290075Sobrien 250390075Sobrien@item A 250490075SobrienAn address register: x, y or z 250590075Sobrien 250690075Sobrien@item B 250790075SobrienAn address register: x or y 250890075Sobrien 250990075Sobrien@item D 251090075SobrienRegister pair (x:d) to form a 32-bit value 251190075Sobrien 251290075Sobrien@item L 251390075SobrienConstants in the range @minus{}65536 to 65535 251490075Sobrien 251590075Sobrien@item M 251690075SobrienConstants whose 16-bit low part is zero 251790075Sobrien 251890075Sobrien@item N 251990075SobrienConstant integer 1 or @minus{}1 252090075Sobrien 252190075Sobrien@item O 252290075SobrienConstant integer 16 252390075Sobrien 252490075Sobrien@item P 252590075SobrienConstants in the range @minus{}8 to 2 252690075Sobrien 252790075Sobrien@end table 252890075Sobrien 252990075Sobrien@need 1000 2530169689Skan@item SPARC---@file{config/sparc/sparc.h} 253190075Sobrien@table @code 253290075Sobrien@item f 2533117395SkanFloating-point register on the SPARC-V8 architecture and 2534117395Skanlower floating-point register on the SPARC-V9 architecture. 253590075Sobrien 253690075Sobrien@item e 2537169689SkanFloating-point register. It is equivalent to @samp{f} on the 2538117395SkanSPARC-V8 architecture and contains both lower and upper 2539117395Skanfloating-point registers on the SPARC-V9 architecture. 254090075Sobrien 2541117395Skan@item c 2542117395SkanFloating-point condition code register. 2543117395Skan 2544117395Skan@item d 2545169689SkanLower floating-point register. It is only valid on the SPARC-V9 2546117395Skanarchitecture when the Visual Instruction Set is available. 2547117395Skan 2548117395Skan@item b 2549169689SkanFloating-point register. It is only valid on the SPARC-V9 architecture 2550117395Skanwhen the Visual Instruction Set is available. 2551117395Skan 2552117395Skan@item h 2553117395Skan64-bit global or out register for the SPARC-V8+ architecture. 2554117395Skan 255590075Sobrien@item I 255690075SobrienSigned 13-bit constant 255790075Sobrien 255890075Sobrien@item J 255990075SobrienZero 256090075Sobrien 256190075Sobrien@item K 256290075Sobrien32-bit constant with the low 12 bits clear (a constant that can be 256390075Sobrienloaded with the @code{sethi} instruction) 256490075Sobrien 256596263Sobrien@item L 256696263SobrienA constant in the range supported by @code{movcc} instructions 256796263Sobrien 256896263Sobrien@item M 256996263SobrienA constant in the range supported by @code{movrcc} instructions 257096263Sobrien 257196263Sobrien@item N 257296263SobrienSame as @samp{K}, except that it verifies that bits that are not in the 2573102780Skanlower 32-bit range are all zero. Must be used instead of @samp{K} for 257496263Sobrienmodes wider than @code{SImode} 257596263Sobrien 2576117395Skan@item O 2577117395SkanThe constant 4096 2578117395Skan 257990075Sobrien@item G 258090075SobrienFloating-point zero 258190075Sobrien 258290075Sobrien@item H 258390075SobrienSigned 13-bit constant, sign-extended to 32 or 64 bits 258490075Sobrien 258590075Sobrien@item Q 258690075SobrienFloating-point constant whose integral representation can 258790075Sobrienbe moved into an integer register using a single sethi 258890075Sobrieninstruction 258990075Sobrien 259090075Sobrien@item R 259190075SobrienFloating-point constant whose integral representation can 259290075Sobrienbe moved into an integer register using a single mov 259390075Sobrieninstruction 259490075Sobrien 259590075Sobrien@item S 259690075SobrienFloating-point constant whose integral representation can 259790075Sobrienbe moved into an integer register using a high/lo_sum 259890075Sobrieninstruction sequence 259990075Sobrien 260090075Sobrien@item T 260190075SobrienMemory address aligned to an 8-byte boundary 260290075Sobrien 260390075Sobrien@item U 260490075SobrienEven register 260590075Sobrien 260696263Sobrien@item W 2607169689SkanMemory address for @samp{e} constraint registers 260896263Sobrien 2609169689Skan@item Y 2610169689SkanVector zero 2611169689Skan 261290075Sobrien@end table 261390075Sobrien 2614169689Skan@item TMS320C3x/C4x---@file{config/c4x/c4x.h} 261590075Sobrien@table @code 261690075Sobrien@item a 261790075SobrienAuxiliary (address) register (ar0-ar7) 261890075Sobrien 261990075Sobrien@item b 262090075SobrienStack pointer register (sp) 262190075Sobrien 262290075Sobrien@item c 262390075SobrienStandard (32-bit) precision integer register 262490075Sobrien 262590075Sobrien@item f 262690075SobrienExtended (40-bit) precision register (r0-r11) 262790075Sobrien 262890075Sobrien@item k 262990075SobrienBlock count register (bk) 263090075Sobrien 263190075Sobrien@item q 263290075SobrienExtended (40-bit) precision low register (r0-r7) 263390075Sobrien 263490075Sobrien@item t 263590075SobrienExtended (40-bit) precision register (r0-r1) 263690075Sobrien 263790075Sobrien@item u 263890075SobrienExtended (40-bit) precision register (r2-r3) 263990075Sobrien 264090075Sobrien@item v 264190075SobrienRepeat count register (rc) 264290075Sobrien 264390075Sobrien@item x 264490075SobrienIndex register (ir0-ir1) 264590075Sobrien 264690075Sobrien@item y 264790075SobrienStatus (condition code) register (st) 264890075Sobrien 264990075Sobrien@item z 265090075SobrienData page register (dp) 265190075Sobrien 265290075Sobrien@item G 265390075SobrienFloating-point zero 265490075Sobrien 265590075Sobrien@item H 265690075SobrienImmediate 16-bit floating-point constant 265790075Sobrien 265890075Sobrien@item I 265990075SobrienSigned 16-bit constant 266090075Sobrien 266190075Sobrien@item J 266290075SobrienSigned 8-bit constant 266390075Sobrien 266490075Sobrien@item K 266590075SobrienSigned 5-bit constant 266690075Sobrien 266790075Sobrien@item L 266890075SobrienUnsigned 16-bit constant 266990075Sobrien 267090075Sobrien@item M 267190075SobrienUnsigned 8-bit constant 267290075Sobrien 267390075Sobrien@item N 267490075SobrienOnes complement of unsigned 16-bit constant 267590075Sobrien 267690075Sobrien@item O 267790075SobrienHigh 16-bit constant (32-bit constant with 16 LSBs zero) 267890075Sobrien 267990075Sobrien@item Q 268090075SobrienIndirect memory reference with signed 8-bit or index register displacement 268190075Sobrien 268290075Sobrien@item R 268390075SobrienIndirect memory reference with unsigned 5-bit displacement 268490075Sobrien 268590075Sobrien@item S 268690075SobrienIndirect memory reference with 1 bit or index register displacement 268790075Sobrien 268890075Sobrien@item T 268990075SobrienDirect memory reference 269090075Sobrien 269190075Sobrien@item U 269290075SobrienSymbolic address 269390075Sobrien 269490075Sobrien@end table 269590075Sobrien 2696169689Skan@item S/390 and zSeries---@file{config/s390/s390.h} 269790075Sobrien@table @code 269890075Sobrien@item a 269990075SobrienAddress register (general purpose register except r0) 270090075Sobrien 2701169689Skan@item c 2702169689SkanCondition code register 2703169689Skan 270490075Sobrien@item d 270590075SobrienData register (arbitrary general purpose register) 270690075Sobrien 270790075Sobrien@item f 270890075SobrienFloating-point register 270990075Sobrien 271090075Sobrien@item I 271190075SobrienUnsigned 8-bit constant (0--255) 271290075Sobrien 271390075Sobrien@item J 271490075SobrienUnsigned 12-bit constant (0--4095) 271590075Sobrien 271690075Sobrien@item K 271790075SobrienSigned 16-bit constant (@minus{}32768--32767) 271890075Sobrien 271990075Sobrien@item L 2720132718SkanValue appropriate as displacement. 2721132718Skan@table @code 2722132718Skan @item (0..4095) 2723132718Skan for short displacement 2724132718Skan @item (-524288..524287) 2725132718Skan for long displacement 2726132718Skan@end table 272790075Sobrien 2728132718Skan@item M 2729132718SkanConstant integer with a value of 0x7fffffff. 2730132718Skan 2731132718Skan@item N 2732132718SkanMultiple letter constraint followed by 4 parameter letters. 2733132718Skan@table @code 2734132718Skan @item 0..9: 2735132718Skan number of the part counting from most to least significant 2736132718Skan @item H,Q: 2737132718Skan mode of the part 2738132718Skan @item D,S,H: 2739132718Skan mode of the containing operand 2740132718Skan @item 0,F: 2741169689Skan value of the other parts (F---all bits set) 2742132718Skan@end table 2743132718SkanThe constraint matches if the specified part of a constant 2744132718Skanhas a value different from it's other parts. 2745132718Skan 274690075Sobrien@item Q 2747132718SkanMemory reference without index register and with short displacement. 274890075Sobrien 2749132718Skan@item R 2750132718SkanMemory reference with index register and short displacement. 2751132718Skan 275290075Sobrien@item S 2753132718SkanMemory reference without index register but with long displacement. 275490075Sobrien 2755132718Skan@item T 2756132718SkanMemory reference with index register and long displacement. 2757132718Skan 2758132718Skan@item U 2759132718SkanPointer with short displacement. 2760132718Skan 2761132718Skan@item W 2762132718SkanPointer with long displacement. 2763132718Skan 2764132718Skan@item Y 2765132718SkanShift count operand. 2766132718Skan 276790075Sobrien@end table 276890075Sobrien 2769169689Skan@item Score family---@file{config/score/score.h} 277090075Sobrien@table @code 2771169689Skan@item d 2772169689SkanRegisters from r0 to r32. 2773169689Skan 2774169689Skan@item e 2775169689SkanRegisters from r0 to r16. 2776169689Skan 2777169689Skan@item t 2778169689Skanr8---r11 or r22---r27 registers. 2779169689Skan 2780169689Skan@item h 2781169689Skanhi register. 2782169689Skan 2783169689Skan@item l 2784169689Skanlo register. 2785169689Skan 2786169689Skan@item x 2787169689Skanhi + lo register. 2788169689Skan 2789169689Skan@item q 2790169689Skancnt register. 2791169689Skan 2792169689Skan@item y 2793169689Skanlcb register. 2794169689Skan 2795169689Skan@item z 2796169689Skanscb register. 2797169689Skan 279890075Sobrien@item a 2799169689Skancnt + lcb + scb register. 2800169689Skan 2801169689Skan@item c 2802169689Skancr0---cr15 register. 2803169689Skan 2804169689Skan@item b 2805169689Skancp1 registers. 2806169689Skan 2807169689Skan@item f 2808169689Skancp2 registers. 2809169689Skan 2810169689Skan@item i 2811169689Skancp3 registers. 2812169689Skan 2813169689Skan@item j 2814169689Skancp1 + cp2 + cp3 registers. 2815169689Skan 2816169689Skan@item I 2817169689SkanHigh 16-bit constant (32-bit constant with 16 LSBs zero). 2818169689Skan 2819169689Skan@item J 2820169689SkanUnsigned 5 bit integer (in the range 0 to 31). 2821169689Skan 2822169689Skan@item K 2823169689SkanUnsigned 16 bit integer (in the range 0 to 65535). 2824169689Skan 2825169689Skan@item L 2826169689SkanSigned 16 bit integer (in the range @minus{}32768 to 32767). 2827169689Skan 2828169689Skan@item M 2829169689SkanUnsigned 14 bit integer (in the range 0 to 16383). 2830169689Skan 2831169689Skan@item N 2832169689SkanSigned 14 bit integer (in the range @minus{}8192 to 8191). 2833169689Skan 2834169689Skan@item Z 2835169689SkanAny SYMBOL_REF. 2836169689Skan@end table 2837169689Skan 2838169689Skan@item Xstormy16---@file{config/stormy16/stormy16.h} 2839169689Skan@table @code 2840169689Skan@item a 284190075SobrienRegister r0. 284290075Sobrien 284390075Sobrien@item b 284490075SobrienRegister r1. 284590075Sobrien 284690075Sobrien@item c 284790075SobrienRegister r2. 284890075Sobrien 284990075Sobrien@item d 285090075SobrienRegister r8. 285190075Sobrien 285290075Sobrien@item e 285390075SobrienRegisters r0 through r7. 285490075Sobrien 285590075Sobrien@item t 285690075SobrienRegisters r0 and r1. 285790075Sobrien 285890075Sobrien@item y 285990075SobrienThe carry register. 286090075Sobrien 286190075Sobrien@item z 286290075SobrienRegisters r8 and r9. 286390075Sobrien 286490075Sobrien@item I 286590075SobrienA constant between 0 and 3 inclusive. 286690075Sobrien 286790075Sobrien@item J 286890075SobrienA constant that has exactly one bit set. 286990075Sobrien 287090075Sobrien@item K 287190075SobrienA constant that has exactly one bit clear. 287290075Sobrien 287390075Sobrien@item L 287490075SobrienA constant between 0 and 255 inclusive. 287590075Sobrien 287690075Sobrien@item M 287790075SobrienA constant between @minus{}255 and 0 inclusive. 287890075Sobrien 287990075Sobrien@item N 288090075SobrienA constant between @minus{}3 and 0 inclusive. 288190075Sobrien 288290075Sobrien@item O 288390075SobrienA constant between 1 and 4 inclusive. 288490075Sobrien 288590075Sobrien@item P 288690075SobrienA constant between @minus{}4 and @minus{}1 inclusive. 288790075Sobrien 288890075Sobrien@item Q 288990075SobrienA memory reference that is a stack push. 289090075Sobrien 289190075Sobrien@item R 289290075SobrienA memory reference that is a stack pop. 289390075Sobrien 289490075Sobrien@item S 2895117395SkanA memory reference that refers to a constant address of known value. 289690075Sobrien 289790075Sobrien@item T 289890075SobrienThe register indicated by Rx (not implemented yet). 289990075Sobrien 290090075Sobrien@item U 290190075SobrienA constant that is not between 2 and 15 inclusive. 290290075Sobrien 2903132718Skan@item Z 2904132718SkanThe constant 0. 2905132718Skan 290690075Sobrien@end table 290790075Sobrien 2908169689Skan@item Xtensa---@file{config/xtensa/xtensa.h} 290990075Sobrien@table @code 291090075Sobrien@item a 291190075SobrienGeneral-purpose 32-bit register 291290075Sobrien 291390075Sobrien@item b 291490075SobrienOne-bit boolean register 291590075Sobrien 291690075Sobrien@item A 291790075SobrienMAC16 40-bit accumulator register 291890075Sobrien 291990075Sobrien@item I 292090075SobrienSigned 12-bit integer constant, for use in MOVI instructions 292190075Sobrien 292290075Sobrien@item J 292390075SobrienSigned 8-bit integer constant, for use in ADDI instructions 292490075Sobrien 292590075Sobrien@item K 292690075SobrienInteger constant valid for BccI instructions 292790075Sobrien 292890075Sobrien@item L 292990075SobrienUnsigned constant valid for BccUI instructions 293090075Sobrien 293190075Sobrien@end table 293290075Sobrien 293390075Sobrien@end table 293490075Sobrien 293590075Sobrien@ifset INTERNALS 2936169689Skan@node Define Constraints 2937169689Skan@subsection Defining Machine-Specific Constraints 2938169689Skan@cindex defining constraints 2939169689Skan@cindex constraints, defining 2940169689Skan 2941169689SkanMachine-specific constraints fall into two categories: register and 2942169689Skannon-register constraints. Within the latter category, constraints 2943169689Skanwhich allow subsets of all possible memory or address operands should 2944169689Skanbe specially marked, to give @code{reload} more information. 2945169689Skan 2946169689SkanMachine-specific constraints can be given names of arbitrary length, 2947169689Skanbut they must be entirely composed of letters, digits, underscores 2948169689Skan(@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they 2949169689Skanmust begin with a letter or underscore. 2950169689Skan 2951169689SkanIn order to avoid ambiguity in operand constraint strings, no 2952169689Skanconstraint can have a name that begins with any other constraint's 2953169689Skanname. For example, if @code{x} is defined as a constraint name, 2954169689Skan@code{xy} may not be, and vice versa. As a consequence of this rule, 2955169689Skanno constraint may begin with one of the generic constraint letters: 2956169689Skan@samp{E F V X g i m n o p r s}. 2957169689Skan 2958169689SkanRegister constraints correspond directly to register classes. 2959169689Skan@xref{Register Classes}. There is thus not much flexibility in their 2960169689Skandefinitions. 2961169689Skan 2962169689Skan@deffn {MD Expression} define_register_constraint name regclass docstring 2963169689SkanAll three arguments are string constants. 2964169689Skan@var{name} is the name of the constraint, as it will appear in 2965169689Skan@code{match_operand} expressions. @var{regclass} can be either the 2966169689Skanname of the corresponding register class (@pxref{Register Classes}), 2967169689Skanor a C expression which evaluates to the appropriate register class. 2968169689SkanIf it is an expression, it must have no side effects, and it cannot 2969169689Skanlook at the operand. The usual use of expressions is to map some 2970169689Skanregister constraints to @code{NO_REGS} when the register class 2971169689Skanis not available on a given subarchitecture. 2972169689Skan 2973169689Skan@var{docstring} is a sentence documenting the meaning of the 2974169689Skanconstraint. Docstrings are explained further below. 2975169689Skan@end deffn 2976169689Skan 2977169689SkanNon-register constraints are more like predicates: the constraint 2978169689Skandefinition gives a Boolean expression which indicates whether the 2979169689Skanconstraint matches. 2980169689Skan 2981169689Skan@deffn {MD Expression} define_constraint name docstring exp 2982169689SkanThe @var{name} and @var{docstring} arguments are the same as for 2983169689Skan@code{define_register_constraint}, but note that the docstring comes 2984169689Skanimmediately after the name for these expressions. @var{exp} is an RTL 2985169689Skanexpression, obeying the same rules as the RTL expressions in predicate 2986169689Skandefinitions. @xref{Defining Predicates}, for details. If it 2987169689Skanevaluates true, the constraint matches; if it evaluates false, it 2988169689Skandoesn't. Constraint expressions should indicate which RTL codes they 2989169689Skanmight match, just like predicate expressions. 2990169689Skan 2991169689Skan@code{match_test} C expressions have access to the 2992169689Skanfollowing variables: 2993169689Skan 2994169689Skan@table @var 2995169689Skan@item op 2996169689SkanThe RTL object defining the operand. 2997169689Skan@item mode 2998169689SkanThe machine mode of @var{op}. 2999169689Skan@item ival 3000169689Skan@samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}. 3001169689Skan@item hval 3002169689Skan@samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer 3003169689Skan@code{const_double}. 3004169689Skan@item lval 3005169689Skan@samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer 3006169689Skan@code{const_double}. 3007169689Skan@item rval 3008169689Skan@samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point 3009169689Skan@code{const_double}. 3010169689Skan@end table 3011169689Skan 3012169689SkanThe @var{*val} variables should only be used once another piece of the 3013169689Skanexpression has verified that @var{op} is the appropriate kind of RTL 3014169689Skanobject. 3015169689Skan@end deffn 3016169689Skan 3017169689SkanMost non-register constraints should be defined with 3018169689Skan@code{define_constraint}. The remaining two definition expressions 3019169689Skanare only appropriate for constraints that should be handled specially 3020169689Skanby @code{reload} if they fail to match. 3021169689Skan 3022169689Skan@deffn {MD Expression} define_memory_constraint name docstring exp 3023169689SkanUse this expression for constraints that match a subset of all memory 3024169689Skanoperands: that is, @code{reload} can make them match by converting the 3025169689Skanoperand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a 3026169689Skanbase register (from the register class specified by 3027169689Skan@code{BASE_REG_CLASS}, @pxref{Register Classes}). 3028169689Skan 3029169689SkanFor example, on the S/390, some instructions do not accept arbitrary 3030169689Skanmemory references, but only those that do not make use of an index 3031169689Skanregister. The constraint letter @samp{Q} is defined to represent a 3032169689Skanmemory address of this type. If @samp{Q} is defined with 3033169689Skan@code{define_memory_constraint}, a @samp{Q} constraint can handle any 3034169689Skanmemory operand, because @code{reload} knows it can simply copy the 3035169689Skanmemory address into a base register if required. This is analogous to 3036169689Skanthe way a @samp{o} constraint can handle any memory operand. 3037169689Skan 3038169689SkanThe syntax and semantics are otherwise identical to 3039169689Skan@code{define_constraint}. 3040169689Skan@end deffn 3041169689Skan 3042169689Skan@deffn {MD Expression} define_address_constraint name docstring exp 3043169689SkanUse this expression for constraints that match a subset of all address 3044169689Skanoperands: that is, @code{reload} can make the constraint match by 3045169689Skanconverting the operand to the form @samp{@w{(reg @var{X})}}, again 3046169689Skanwith @var{X} a base register. 3047169689Skan 3048169689SkanConstraints defined with @code{define_address_constraint} can only be 3049169689Skanused with the @code{address_operand} predicate, or machine-specific 3050169689Skanpredicates that work the same way. They are treated analogously to 3051169689Skanthe generic @samp{p} constraint. 3052169689Skan 3053169689SkanThe syntax and semantics are otherwise identical to 3054169689Skan@code{define_constraint}. 3055169689Skan@end deffn 3056169689Skan 3057169689SkanFor historical reasons, names beginning with the letters @samp{G H} 3058169689Skanare reserved for constraints that match only @code{const_double}s, and 3059169689Skannames beginning with the letters @samp{I J K L M N O P} are reserved 3060169689Skanfor constraints that match only @code{const_int}s. This may change in 3061169689Skanthe future. For the time being, constraints with these names must be 3062169689Skanwritten in a stylized form, so that @code{genpreds} can tell you did 3063169689Skanit correctly: 3064169689Skan 3065169689Skan@smallexample 3066169689Skan@group 3067169689Skan(define_constraint "[@var{GHIJKLMNOP}]@dots{}" 3068169689Skan "@var{doc}@dots{}" 3069169689Skan (and (match_code "const_int") ; @r{@code{const_double} for G/H} 3070169689Skan @var{condition}@dots{})) ; @r{usually a @code{match_test}} 3071169689Skan@end group 3072169689Skan@end smallexample 3073169689Skan@c the semicolons line up in the formatted manual 3074169689Skan 3075169689SkanIt is fine to use names beginning with other letters for constraints 3076169689Skanthat match @code{const_double}s or @code{const_int}s. 3077169689Skan 3078169689SkanEach docstring in a constraint definition should be one or more complete 3079169689Skansentences, marked up in Texinfo format. @emph{They are currently unused.} 3080169689SkanIn the future they will be copied into the GCC manual, in @ref{Machine 3081169689SkanConstraints}, replacing the hand-maintained tables currently found in 3082169689Skanthat section. Also, in the future the compiler may use this to give 3083169689Skanmore helpful diagnostics when poor choice of @code{asm} constraints 3084169689Skancauses a reload failure. 3085169689Skan 3086169689SkanIf you put the pseudo-Texinfo directive @samp{@@internal} at the 3087169689Skanbeginning of a docstring, then (in the future) it will appear only in 3088169689Skanthe internals manual's version of the machine-specific constraint tables. 3089169689SkanUse this for constraints that should not appear in @code{asm} statements. 3090169689Skan 3091169689Skan@node C Constraint Interface 3092169689Skan@subsection Testing constraints from C 3093169689Skan@cindex testing constraints 3094169689Skan@cindex constraints, testing 3095169689Skan 3096169689SkanIt is occasionally useful to test a constraint from C code rather than 3097169689Skanimplicitly via the constraint string in a @code{match_operand}. The 3098169689Skangenerated file @file{tm_p.h} declares a few interfaces for working 3099169689Skanwith machine-specific constraints. None of these interfaces work with 3100169689Skanthe generic constraints described in @ref{Simple Constraints}. This 3101169689Skanmay change in the future. 3102169689Skan 3103169689Skan@strong{Warning:} @file{tm_p.h} may declare other functions that 3104169689Skanoperate on constraints, besides the ones documented here. Do not use 3105169689Skanthose functions from machine-dependent code. They exist to implement 3106169689Skanthe old constraint interface that machine-independent components of 3107169689Skanthe compiler still expect. They will change or disappear in the 3108169689Skanfuture. 3109169689Skan 3110169689SkanSome valid constraint names are not valid C identifiers, so there is a 3111169689Skanmangling scheme for referring to them from C@. Constraint names that 3112169689Skando not contain angle brackets or underscores are left unchanged. 3113169689SkanUnderscores are doubled, each @samp{<} is replaced with @samp{_l}, and 3114169689Skaneach @samp{>} with @samp{_g}. Here are some examples: 3115169689Skan 3116169689Skan@c the @c's prevent double blank lines in the printed manual. 3117169689Skan@example 3118169689Skan@multitable {Original} {Mangled} 3119169689Skan@item @strong{Original} @tab @strong{Mangled} @c 3120169689Skan@item @code{x} @tab @code{x} @c 3121169689Skan@item @code{P42x} @tab @code{P42x} @c 3122169689Skan@item @code{P4_x} @tab @code{P4__x} @c 3123169689Skan@item @code{P4>x} @tab @code{P4_gx} @c 3124169689Skan@item @code{P4>>} @tab @code{P4_g_g} @c 3125169689Skan@item @code{P4_g>} @tab @code{P4__g_g} @c 3126169689Skan@end multitable 3127169689Skan@end example 3128169689Skan 3129169689SkanThroughout this section, the variable @var{c} is either a constraint 3130169689Skanin the abstract sense, or a constant from @code{enum constraint_num}; 3131169689Skanthe variable @var{m} is a mangled constraint name (usually as part of 3132169689Skana larger identifier). 3133169689Skan 3134169689Skan@deftp Enum constraint_num 3135169689SkanFor each machine-specific constraint, there is a corresponding 3136169689Skanenumeration constant: @samp{CONSTRAINT_} plus the mangled name of the 3137169689Skanconstraint. Functions that take an @code{enum constraint_num} as an 3138169689Skanargument expect one of these constants. 3139169689Skan 3140169689SkanMachine-independent constraints do not have associated constants. 3141169689SkanThis may change in the future. 3142169689Skan@end deftp 3143169689Skan 3144169689Skan@deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp}) 3145169689SkanFor each machine-specific, non-register constraint @var{m}, there is 3146169689Skanone of these functions; it returns @code{true} if @var{exp} satisfies the 3147169689Skanconstraint. These functions are only visible if @file{rtl.h} was included 3148169689Skanbefore @file{tm_p.h}. 3149169689Skan@end deftypefun 3150169689Skan 3151169689Skan@deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c}) 3152169689SkanLike the @code{satisfies_constraint_@var{m}} functions, but the 3153169689Skanconstraint to test is given as an argument, @var{c}. If @var{c} 3154169689Skanspecifies a register constraint, this function will always return 3155169689Skan@code{false}. 3156169689Skan@end deftypefun 3157169689Skan 3158169689Skan@deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c}) 3159169689SkanReturns the register class associated with @var{c}. If @var{c} is not 3160169689Skana register constraint, or those registers are not available for the 3161169689Skancurrently selected subtarget, returns @code{NO_REGS}. 3162169689Skan@end deftypefun 3163169689Skan 3164169689SkanHere is an example use of @code{satisfies_constraint_@var{m}}. In 3165169689Skanpeephole optimizations (@pxref{Peephole Definitions}), operand 3166169689Skanconstraint strings are ignored, so if there are relevant constraints, 3167169689Skanthey must be tested in the C condition. In the example, the 3168169689Skanoptimization is applied if operand 2 does @emph{not} satisfy the 3169169689Skan@samp{K} constraint. (This is a simplified version of a peephole 3170169689Skandefinition from the i386 machine description.) 3171169689Skan 3172169689Skan@smallexample 3173169689Skan(define_peephole2 3174169689Skan [(match_scratch:SI 3 "r") 3175169689Skan (set (match_operand:SI 0 "register_operand" "") 3176169689Skan (mult:SI (match_operand:SI 1 "memory_operand" "") 3177169689Skan (match_operand:SI 2 "immediate_operand" "")))] 3178169689Skan 3179169689Skan "!satisfies_constraint_K (operands[2])" 3180169689Skan 3181169689Skan [(set (match_dup 3) (match_dup 1)) 3182169689Skan (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))] 3183169689Skan 3184169689Skan "") 3185169689Skan@end smallexample 3186169689Skan 318790075Sobrien@node Standard Names 318890075Sobrien@section Standard Pattern Names For Generation 318990075Sobrien@cindex standard pattern names 319090075Sobrien@cindex pattern names 319190075Sobrien@cindex names, pattern 319290075Sobrien 319390075SobrienHere is a table of the instruction names that are meaningful in the RTL 319490075Sobriengeneration pass of the compiler. Giving one of these names to an 319590075Sobrieninstruction pattern tells the RTL generation pass that it can use the 319690075Sobrienpattern to accomplish a certain task. 319790075Sobrien 319890075Sobrien@table @asis 319990075Sobrien@cindex @code{mov@var{m}} instruction pattern 320090075Sobrien@item @samp{mov@var{m}} 3201132718SkanHere @var{m} stands for a two-letter machine mode name, in lowercase. 320290075SobrienThis instruction pattern moves data with that machine mode from operand 320390075Sobrien1 to operand 0. For example, @samp{movsi} moves full-word data. 320490075Sobrien 320590075SobrienIf operand 0 is a @code{subreg} with mode @var{m} of a register whose 320690075Sobrienown mode is wider than @var{m}, the effect of this instruction is 320790075Sobriento store the specified value in the part of the register that corresponds 320890075Sobriento mode @var{m}. Bits outside of @var{m}, but which are within the 320990075Sobriensame target word as the @code{subreg} are undefined. Bits which are 321090075Sobrienoutside the target word are left unchanged. 321190075Sobrien 321290075SobrienThis class of patterns is special in several ways. First of all, each 321390075Sobrienof these names up to and including full word size @emph{must} be defined, 321490075Sobrienbecause there is no other way to copy a datum from one place to another. 321590075SobrienIf there are patterns accepting operands in larger modes, 321690075Sobrien@samp{mov@var{m}} must be defined for integer modes of those sizes. 321790075Sobrien 321890075SobrienSecond, these patterns are not used solely in the RTL generation pass. 321990075SobrienEven the reload pass can generate move insns to copy values from stack 322090075Sobrienslots into temporary registers. When it does so, one of the operands is 322190075Sobriena hard register and the other is an operand that can need to be reloaded 322290075Sobrieninto a register. 322390075Sobrien 322490075Sobrien@findex force_reg 322590075SobrienTherefore, when given such a pair of operands, the pattern must generate 322690075SobrienRTL which needs no reloading and needs no temporary registers---no 322790075Sobrienregisters other than the operands. For example, if you support the 322890075Sobrienpattern with a @code{define_expand}, then in such a case the 322990075Sobrien@code{define_expand} mustn't call @code{force_reg} or any other such 323090075Sobrienfunction which might generate new pseudo registers. 323190075Sobrien 323290075SobrienThis requirement exists even for subword modes on a RISC machine where 323390075Sobrienfetching those modes from memory normally requires several insns and 323490075Sobriensome temporary registers. 323590075Sobrien 323690075Sobrien@findex change_address 323790075SobrienDuring reload a memory reference with an invalid address may be passed 323890075Sobrienas an operand. Such an address will be replaced with a valid address 323990075Sobrienlater in the reload pass. In this case, nothing may be done with the 324090075Sobrienaddress except to use it as it stands. If it is copied, it will not be 324190075Sobrienreplaced with a valid address. No attempt should be made to make such 324290075Sobrienan address into a valid address and no routine (such as 324390075Sobrien@code{change_address}) that will do so may be called. Note that 324490075Sobrien@code{general_operand} will fail when applied to such an address. 324590075Sobrien 324690075Sobrien@findex reload_in_progress 324790075SobrienThe global variable @code{reload_in_progress} (which must be explicitly 324890075Sobriendeclared if required) can be used to determine whether such special 324990075Sobrienhandling is required. 325090075Sobrien 325190075SobrienThe variety of operands that have reloads depends on the rest of the 325290075Sobrienmachine description, but typically on a RISC machine these can only be 325390075Sobrienpseudo registers that did not get hard registers, while on other 325490075Sobrienmachines explicit memory references will get optional reloads. 325590075Sobrien 325690075SobrienIf a scratch register is required to move an object to or from memory, 325790075Sobrienit can be allocated using @code{gen_reg_rtx} prior to life analysis. 325890075Sobrien 325990075SobrienIf there are cases which need scratch registers during or after reload, 3260169689Skanyou must provide an appropriate secondary_reload target hook. 326190075Sobrien 326290075Sobrien@findex no_new_pseudos 326390075SobrienThe global variable @code{no_new_pseudos} can be used to determine if it 326490075Sobrienis unsafe to create new pseudo registers. If this variable is nonzero, then 326590075Sobrienit is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo. 326690075Sobrien 326790075SobrienThe constraints on a @samp{mov@var{m}} must permit moving any hard 326890075Sobrienregister to any other hard register provided that 326990075Sobrien@code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and 327090075Sobrien@code{REGISTER_MOVE_COST} applied to their classes returns a value of 2. 327190075Sobrien 327290075SobrienIt is obligatory to support floating point @samp{mov@var{m}} 327390075Sobrieninstructions into and out of any registers that can hold fixed point 327490075Sobrienvalues, because unions and structures (which have modes @code{SImode} or 327590075Sobrien@code{DImode}) can be in those registers and they may have floating 327690075Sobrienpoint members. 327790075Sobrien 327890075SobrienThere may also be a need to support fixed point @samp{mov@var{m}} 327990075Sobrieninstructions in and out of floating point registers. Unfortunately, I 328090075Sobrienhave forgotten why this was so, and I don't know whether it is still 328190075Sobrientrue. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in 328290075Sobrienfloating point registers, then the constraints of the fixed point 328390075Sobrien@samp{mov@var{m}} instructions must be designed to avoid ever trying to 328490075Sobrienreload into a floating point register. 328590075Sobrien 328690075Sobrien@cindex @code{reload_in} instruction pattern 328790075Sobrien@cindex @code{reload_out} instruction pattern 328890075Sobrien@item @samp{reload_in@var{m}} 328990075Sobrien@itemx @samp{reload_out@var{m}} 3290169689SkanThese named patterns have been obsoleted by the target hook 3291169689Skan@code{secondary_reload}. 3292169689Skan 329390075SobrienLike @samp{mov@var{m}}, but used when a scratch register is required to 329490075Sobrienmove between operand 0 and operand 1. Operand 2 describes the scratch 329590075Sobrienregister. See the discussion of the @code{SECONDARY_RELOAD_CLASS} 329690075Sobrienmacro in @pxref{Register Classes}. 329790075Sobrien 329890075SobrienThere are special restrictions on the form of the @code{match_operand}s 329996263Sobrienused in these patterns. First, only the predicate for the reload 330090075Sobrienoperand is examined, i.e., @code{reload_in} examines operand 1, but not 330190075Sobrienthe predicates for operand 0 or 2. Second, there may be only one 330290075Sobrienalternative in the constraints. Third, only a single register class 330390075Sobrienletter may be used for the constraint; subsequent constraint letters 330490075Sobrienare ignored. As a special exception, an empty constraint string 330590075Sobrienmatches the @code{ALL_REGS} register class. This may relieve ports 330690075Sobrienof the burden of defining an @code{ALL_REGS} constraint letter just 330790075Sobrienfor these patterns. 330890075Sobrien 330990075Sobrien@cindex @code{movstrict@var{m}} instruction pattern 331090075Sobrien@item @samp{movstrict@var{m}} 331190075SobrienLike @samp{mov@var{m}} except that if operand 0 is a @code{subreg} 331290075Sobrienwith mode @var{m} of a register whose natural mode is wider, 331390075Sobrienthe @samp{movstrict@var{m}} instruction is guaranteed not to alter 331490075Sobrienany of the register except the part which belongs to mode @var{m}. 331590075Sobrien 3316169689Skan@cindex @code{movmisalign@var{m}} instruction pattern 3317169689Skan@item @samp{movmisalign@var{m}} 3318169689SkanThis variant of a move pattern is designed to load or store a value 3319169689Skanfrom a memory address that is not naturally aligned for its mode. 3320169689SkanFor a store, the memory will be in operand 0; for a load, the memory 3321169689Skanwill be in operand 1. The other operand is guaranteed not to be a 3322169689Skanmemory, so that it's easy to tell whether this is a load or store. 3323169689Skan 3324169689SkanThis pattern is used by the autovectorizer, and when expanding a 3325169689Skan@code{MISALIGNED_INDIRECT_REF} expression. 3326169689Skan 332790075Sobrien@cindex @code{load_multiple} instruction pattern 332890075Sobrien@item @samp{load_multiple} 332990075SobrienLoad several consecutive memory locations into consecutive registers. 333090075SobrienOperand 0 is the first of the consecutive registers, operand 1 333190075Sobrienis the first memory location, and operand 2 is a constant: the 333290075Sobriennumber of consecutive registers. 333390075Sobrien 333490075SobrienDefine this only if the target machine really has such an instruction; 333590075Sobriendo not define this if the most efficient way of loading consecutive 333690075Sobrienregisters from memory is to do them one at a time. 333790075Sobrien 333890075SobrienOn some machines, there are restrictions as to which consecutive 333990075Sobrienregisters can be stored into memory, such as particular starting or 334090075Sobrienending register numbers or only a range of valid counts. For those 334190075Sobrienmachines, use a @code{define_expand} (@pxref{Expander Definitions}) 334290075Sobrienand make the pattern fail if the restrictions are not met. 334390075Sobrien 334490075SobrienWrite the generated insn as a @code{parallel} with elements being a 334590075Sobrien@code{set} of one register from the appropriate memory location (you may 334690075Sobrienalso need @code{use} or @code{clobber} elements). Use a 334790075Sobrien@code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See 3348117395Skan@file{rs6000.md} for examples of the use of this insn pattern. 334990075Sobrien 335090075Sobrien@cindex @samp{store_multiple} instruction pattern 335190075Sobrien@item @samp{store_multiple} 335290075SobrienSimilar to @samp{load_multiple}, but store several consecutive registers 335390075Sobrieninto consecutive memory locations. Operand 0 is the first of the 335490075Sobrienconsecutive memory locations, operand 1 is the first register, and 335590075Sobrienoperand 2 is a constant: the number of consecutive registers. 335690075Sobrien 3357169689Skan@cindex @code{vec_set@var{m}} instruction pattern 3358169689Skan@item @samp{vec_set@var{m}} 3359169689SkanSet given field in the vector value. Operand 0 is the vector to modify, 3360169689Skanoperand 1 is new value of field and operand 2 specify the field index. 3361169689Skan 3362169689Skan@cindex @code{vec_extract@var{m}} instruction pattern 3363169689Skan@item @samp{vec_extract@var{m}} 3364169689SkanExtract given field from the vector value. Operand 1 is the vector, operand 2 3365169689Skanspecify field index and operand 0 place to store value into. 3366169689Skan 3367169689Skan@cindex @code{vec_init@var{m}} instruction pattern 3368169689Skan@item @samp{vec_init@var{m}} 3369169689SkanInitialize the vector to given values. Operand 0 is the vector to initialize 3370169689Skanand operand 1 is parallel containing values for individual fields. 3371169689Skan 3372169689Skan@cindex @code{push@var{m}1} instruction pattern 3373169689Skan@item @samp{push@var{m}1} 3374117395SkanOutput a push instruction. Operand 0 is value to push. Used only when 337590075Sobrien@code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be 337690075Sobrienmissing and in such case an @code{mov} expander is used instead, with a 337790075Sobrien@code{MEM} expression forming the push operation. The @code{mov} expander 337890075Sobrienmethod is deprecated. 337990075Sobrien 338090075Sobrien@cindex @code{add@var{m}3} instruction pattern 338190075Sobrien@item @samp{add@var{m}3} 338290075SobrienAdd operand 2 and operand 1, storing the result in operand 0. All operands 338390075Sobrienmust have mode @var{m}. This can be used even on two-address machines, by 338490075Sobrienmeans of constraints requiring operands 1 and 0 to be the same location. 338590075Sobrien 338690075Sobrien@cindex @code{sub@var{m}3} instruction pattern 338790075Sobrien@cindex @code{mul@var{m}3} instruction pattern 338890075Sobrien@cindex @code{div@var{m}3} instruction pattern 338990075Sobrien@cindex @code{udiv@var{m}3} instruction pattern 339090075Sobrien@cindex @code{mod@var{m}3} instruction pattern 339190075Sobrien@cindex @code{umod@var{m}3} instruction pattern 339290075Sobrien@cindex @code{umin@var{m}3} instruction pattern 339390075Sobrien@cindex @code{umax@var{m}3} instruction pattern 339490075Sobrien@cindex @code{and@var{m}3} instruction pattern 339590075Sobrien@cindex @code{ior@var{m}3} instruction pattern 339690075Sobrien@cindex @code{xor@var{m}3} instruction pattern 339790075Sobrien@item @samp{sub@var{m}3}, @samp{mul@var{m}3} 3398169689Skan@itemx @samp{div@var{m}3}, @samp{udiv@var{m}3} 3399169689Skan@itemx @samp{mod@var{m}3}, @samp{umod@var{m}3} 3400169689Skan@itemx @samp{umin@var{m}3}, @samp{umax@var{m}3} 340190075Sobrien@itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} 340290075SobrienSimilar, for other arithmetic operations. 3403169689Skan 340490075Sobrien@cindex @code{min@var{m}3} instruction pattern 340590075Sobrien@cindex @code{max@var{m}3} instruction pattern 3406169689Skan@item @samp{smin@var{m}3}, @samp{smax@var{m}3} 3407169689SkanSigned minimum and maximum operations. When used with floating point, 3408169689Skanif both operands are zeros, or if either operand is @code{NaN}, then 3409169689Skanit is unspecified which of the two operands is returned as the result. 341090075Sobrien 3411169689Skan@cindex @code{reduc_smin_@var{m}} instruction pattern 3412169689Skan@cindex @code{reduc_smax_@var{m}} instruction pattern 3413169689Skan@item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}} 3414169689SkanFind the signed minimum/maximum of the elements of a vector. The vector is 3415169689Skanoperand 1, and the scalar result is stored in the least significant bits of 3416169689Skanoperand 0 (also a vector). The output and input vector should have the same 3417169689Skanmodes. 341890075Sobrien 3419169689Skan@cindex @code{reduc_umin_@var{m}} instruction pattern 3420169689Skan@cindex @code{reduc_umax_@var{m}} instruction pattern 3421169689Skan@item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}} 3422169689SkanFind the unsigned minimum/maximum of the elements of a vector. The vector is 3423169689Skanoperand 1, and the scalar result is stored in the least significant bits of 3424169689Skanoperand 0 (also a vector). The output and input vector should have the same 3425169689Skanmodes. 3426169689Skan 3427169689Skan@cindex @code{reduc_splus_@var{m}} instruction pattern 3428169689Skan@item @samp{reduc_splus_@var{m}} 3429169689SkanCompute the sum of the signed elements of a vector. The vector is operand 1, 3430169689Skanand the scalar result is stored in the least significant bits of operand 0 3431169689Skan(also a vector). The output and input vector should have the same modes. 3432169689Skan 3433169689Skan@cindex @code{reduc_uplus_@var{m}} instruction pattern 3434169689Skan@item @samp{reduc_uplus_@var{m}} 3435169689SkanCompute the sum of the unsigned elements of a vector. The vector is operand 1, 3436169689Skanand the scalar result is stored in the least significant bits of operand 0 3437169689Skan(also a vector). The output and input vector should have the same modes. 3438169689Skan 3439169689Skan@cindex @code{sdot_prod@var{m}} instruction pattern 3440169689Skan@item @samp{sdot_prod@var{m}} 3441169689Skan@cindex @code{udot_prod@var{m}} instruction pattern 3442169689Skan@item @samp{udot_prod@var{m}} 3443169689SkanCompute the sum of the products of two signed/unsigned elements. 3444169689SkanOperand 1 and operand 2 are of the same mode. Their product, which is of a 3445169689Skanwider mode, is computed and added to operand 3. Operand 3 is of a mode equal or 3446169689Skanwider than the mode of the product. The result is placed in operand 0, which 3447169689Skanis of the same mode as operand 3. 3448169689Skan 3449169689Skan@cindex @code{ssum_widen@var{m3}} instruction pattern 3450169689Skan@item @samp{ssum_widen@var{m3}} 3451169689Skan@cindex @code{usum_widen@var{m3}} instruction pattern 3452169689Skan@item @samp{usum_widen@var{m3}} 3453169689SkanOperands 0 and 2 are of the same mode, which is wider than the mode of 3454169689Skanoperand 1. Add operand 1 to operand 2 and place the widened result in 3455169689Skanoperand 0. (This is used express accumulation of elements into an accumulator 3456169689Skanof a wider mode.) 3457169689Skan 3458169689Skan@cindex @code{vec_shl_@var{m}} instruction pattern 3459169689Skan@cindex @code{vec_shr_@var{m}} instruction pattern 3460169689Skan@item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}} 3461169689SkanWhole vector left/right shift in bits. 3462169689SkanOperand 1 is a vector to be shifted. 3463169689SkanOperand 2 is an integer shift amount in bits. 3464169689SkanOperand 0 is where the resulting shifted vector is stored. 3465169689SkanThe output and input vectors should have the same modes. 3466169689Skan 346790075Sobrien@cindex @code{mulhisi3} instruction pattern 346890075Sobrien@item @samp{mulhisi3} 346990075SobrienMultiply operands 1 and 2, which have mode @code{HImode}, and store 347090075Sobriena @code{SImode} product in operand 0. 347190075Sobrien 347290075Sobrien@cindex @code{mulqihi3} instruction pattern 347390075Sobrien@cindex @code{mulsidi3} instruction pattern 347490075Sobrien@item @samp{mulqihi3}, @samp{mulsidi3} 347590075SobrienSimilar widening-multiplication instructions of other widths. 347690075Sobrien 347790075Sobrien@cindex @code{umulqihi3} instruction pattern 347890075Sobrien@cindex @code{umulhisi3} instruction pattern 347990075Sobrien@cindex @code{umulsidi3} instruction pattern 348090075Sobrien@item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3} 348190075SobrienSimilar widening-multiplication instructions that do unsigned 348290075Sobrienmultiplication. 348390075Sobrien 3484169689Skan@cindex @code{usmulqihi3} instruction pattern 3485169689Skan@cindex @code{usmulhisi3} instruction pattern 3486169689Skan@cindex @code{usmulsidi3} instruction pattern 3487169689Skan@item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3} 3488169689SkanSimilar widening-multiplication instructions that interpret the first 3489169689Skanoperand as unsigned and the second operand as signed, then do a signed 3490169689Skanmultiplication. 3491169689Skan 349290075Sobrien@cindex @code{smul@var{m}3_highpart} instruction pattern 349390075Sobrien@item @samp{smul@var{m}3_highpart} 349490075SobrienPerform a signed multiplication of operands 1 and 2, which have mode 349590075Sobrien@var{m}, and store the most significant half of the product in operand 0. 349690075SobrienThe least significant half of the product is discarded. 349790075Sobrien 349890075Sobrien@cindex @code{umul@var{m}3_highpart} instruction pattern 349990075Sobrien@item @samp{umul@var{m}3_highpart} 350090075SobrienSimilar, but the multiplication is unsigned. 350190075Sobrien 350290075Sobrien@cindex @code{divmod@var{m}4} instruction pattern 350390075Sobrien@item @samp{divmod@var{m}4} 350490075SobrienSigned division that produces both a quotient and a remainder. 350590075SobrienOperand 1 is divided by operand 2 to produce a quotient stored 350690075Sobrienin operand 0 and a remainder stored in operand 3. 350790075Sobrien 350890075SobrienFor machines with an instruction that produces both a quotient and a 350990075Sobrienremainder, provide a pattern for @samp{divmod@var{m}4} but do not 351090075Sobrienprovide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This 351190075Sobrienallows optimization in the relatively common case when both the quotient 351290075Sobrienand remainder are computed. 351390075Sobrien 351490075SobrienIf an instruction that just produces a quotient or just a remainder 351590075Sobrienexists and is more efficient than the instruction that produces both, 351690075Sobrienwrite the output routine of @samp{divmod@var{m}4} to call 351790075Sobrien@code{find_reg_note} and look for a @code{REG_UNUSED} note on the 351890075Sobrienquotient or remainder and generate the appropriate instruction. 351990075Sobrien 352090075Sobrien@cindex @code{udivmod@var{m}4} instruction pattern 352190075Sobrien@item @samp{udivmod@var{m}4} 352290075SobrienSimilar, but does unsigned division. 352390075Sobrien 3524169689Skan@anchor{shift patterns} 352590075Sobrien@cindex @code{ashl@var{m}3} instruction pattern 352690075Sobrien@item @samp{ashl@var{m}3} 352790075SobrienArithmetic-shift operand 1 left by a number of bits specified by operand 352890075Sobrien2, and store the result in operand 0. Here @var{m} is the mode of 352990075Sobrienoperand 0 and operand 1; operand 2's mode is specified by the 353090075Sobrieninstruction pattern, and the compiler will convert the operand to that 3531169689Skanmode before generating the instruction. The meaning of out-of-range shift 3532169689Skancounts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}. 3533169689Skan@xref{TARGET_SHIFT_TRUNCATION_MASK}. 353490075Sobrien 353590075Sobrien@cindex @code{ashr@var{m}3} instruction pattern 353690075Sobrien@cindex @code{lshr@var{m}3} instruction pattern 353790075Sobrien@cindex @code{rotl@var{m}3} instruction pattern 353890075Sobrien@cindex @code{rotr@var{m}3} instruction pattern 353990075Sobrien@item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3} 354090075SobrienOther shift and rotate instructions, analogous to the 354190075Sobrien@code{ashl@var{m}3} instructions. 354290075Sobrien 354390075Sobrien@cindex @code{neg@var{m}2} instruction pattern 354490075Sobrien@item @samp{neg@var{m}2} 354590075SobrienNegate operand 1 and store the result in operand 0. 354690075Sobrien 354790075Sobrien@cindex @code{abs@var{m}2} instruction pattern 354890075Sobrien@item @samp{abs@var{m}2} 354990075SobrienStore the absolute value of operand 1 into operand 0. 355090075Sobrien 355190075Sobrien@cindex @code{sqrt@var{m}2} instruction pattern 355290075Sobrien@item @samp{sqrt@var{m}2} 355390075SobrienStore the square root of operand 1 into operand 0. 355490075Sobrien 355590075SobrienThe @code{sqrt} built-in function of C always uses the mode which 3556117395Skancorresponds to the C data type @code{double} and the @code{sqrtf} 3557117395Skanbuilt-in function uses the mode which corresponds to the C data 3558117395Skantype @code{float}. 355990075Sobrien 3560117395Skan@cindex @code{cos@var{m}2} instruction pattern 3561117395Skan@item @samp{cos@var{m}2} 3562117395SkanStore the cosine of operand 1 into operand 0. 3563117395Skan 3564117395SkanThe @code{cos} built-in function of C always uses the mode which 3565117395Skancorresponds to the C data type @code{double} and the @code{cosf} 3566117395Skanbuilt-in function uses the mode which corresponds to the C data 3567117395Skantype @code{float}. 3568117395Skan 3569117395Skan@cindex @code{sin@var{m}2} instruction pattern 3570117395Skan@item @samp{sin@var{m}2} 3571117395SkanStore the sine of operand 1 into operand 0. 3572117395Skan 3573117395SkanThe @code{sin} built-in function of C always uses the mode which 3574117395Skancorresponds to the C data type @code{double} and the @code{sinf} 3575117395Skanbuilt-in function uses the mode which corresponds to the C data 3576117395Skantype @code{float}. 3577117395Skan 3578117395Skan@cindex @code{exp@var{m}2} instruction pattern 3579117395Skan@item @samp{exp@var{m}2} 3580117395SkanStore the exponential of operand 1 into operand 0. 3581117395Skan 3582117395SkanThe @code{exp} built-in function of C always uses the mode which 3583117395Skancorresponds to the C data type @code{double} and the @code{expf} 3584117395Skanbuilt-in function uses the mode which corresponds to the C data 3585117395Skantype @code{float}. 3586117395Skan 3587117395Skan@cindex @code{log@var{m}2} instruction pattern 3588117395Skan@item @samp{log@var{m}2} 3589117395SkanStore the natural logarithm of operand 1 into operand 0. 3590117395Skan 3591117395SkanThe @code{log} built-in function of C always uses the mode which 3592117395Skancorresponds to the C data type @code{double} and the @code{logf} 3593117395Skanbuilt-in function uses the mode which corresponds to the C data 3594117395Skantype @code{float}. 3595117395Skan 3596132718Skan@cindex @code{pow@var{m}3} instruction pattern 3597132718Skan@item @samp{pow@var{m}3} 3598132718SkanStore the value of operand 1 raised to the exponent operand 2 3599132718Skaninto operand 0. 3600132718Skan 3601132718SkanThe @code{pow} built-in function of C always uses the mode which 3602132718Skancorresponds to the C data type @code{double} and the @code{powf} 3603132718Skanbuilt-in function uses the mode which corresponds to the C data 3604132718Skantype @code{float}. 3605132718Skan 3606132718Skan@cindex @code{atan2@var{m}3} instruction pattern 3607132718Skan@item @samp{atan2@var{m}3} 3608132718SkanStore the arc tangent (inverse tangent) of operand 1 divided by 3609132718Skanoperand 2 into operand 0, using the signs of both arguments to 3610132718Skandetermine the quadrant of the result. 3611132718Skan 3612132718SkanThe @code{atan2} built-in function of C always uses the mode which 3613132718Skancorresponds to the C data type @code{double} and the @code{atan2f} 3614132718Skanbuilt-in function uses the mode which corresponds to the C data 3615132718Skantype @code{float}. 3616132718Skan 3617132718Skan@cindex @code{floor@var{m}2} instruction pattern 3618132718Skan@item @samp{floor@var{m}2} 3619132718SkanStore the largest integral value not greater than argument. 3620132718Skan 3621132718SkanThe @code{floor} built-in function of C always uses the mode which 3622132718Skancorresponds to the C data type @code{double} and the @code{floorf} 3623132718Skanbuilt-in function uses the mode which corresponds to the C data 3624132718Skantype @code{float}. 3625132718Skan 3626169689Skan@cindex @code{btrunc@var{m}2} instruction pattern 3627169689Skan@item @samp{btrunc@var{m}2} 3628132718SkanStore the argument rounded to integer towards zero. 3629132718Skan 3630132718SkanThe @code{trunc} built-in function of C always uses the mode which 3631132718Skancorresponds to the C data type @code{double} and the @code{truncf} 3632132718Skanbuilt-in function uses the mode which corresponds to the C data 3633132718Skantype @code{float}. 3634132718Skan 3635132718Skan@cindex @code{round@var{m}2} instruction pattern 3636132718Skan@item @samp{round@var{m}2} 3637132718SkanStore the argument rounded to integer away from zero. 3638132718Skan 3639132718SkanThe @code{round} built-in function of C always uses the mode which 3640132718Skancorresponds to the C data type @code{double} and the @code{roundf} 3641132718Skanbuilt-in function uses the mode which corresponds to the C data 3642132718Skantype @code{float}. 3643132718Skan 3644132718Skan@cindex @code{ceil@var{m}2} instruction pattern 3645132718Skan@item @samp{ceil@var{m}2} 3646132718SkanStore the argument rounded to integer away from zero. 3647132718Skan 3648132718SkanThe @code{ceil} built-in function of C always uses the mode which 3649132718Skancorresponds to the C data type @code{double} and the @code{ceilf} 3650132718Skanbuilt-in function uses the mode which corresponds to the C data 3651132718Skantype @code{float}. 3652132718Skan 3653132718Skan@cindex @code{nearbyint@var{m}2} instruction pattern 3654132718Skan@item @samp{nearbyint@var{m}2} 3655132718SkanStore the argument rounded according to the default rounding mode 3656132718Skan 3657132718SkanThe @code{nearbyint} built-in function of C always uses the mode which 3658132718Skancorresponds to the C data type @code{double} and the @code{nearbyintf} 3659132718Skanbuilt-in function uses the mode which corresponds to the C data 3660132718Skantype @code{float}. 3661132718Skan 3662169689Skan@cindex @code{rint@var{m}2} instruction pattern 3663169689Skan@item @samp{rint@var{m}2} 3664169689SkanStore the argument rounded according to the default rounding mode and 3665169689Skanraise the inexact exception when the result differs in value from 3666169689Skanthe argument 3667169689Skan 3668169689SkanThe @code{rint} built-in function of C always uses the mode which 3669169689Skancorresponds to the C data type @code{double} and the @code{rintf} 3670169689Skanbuilt-in function uses the mode which corresponds to the C data 3671169689Skantype @code{float}. 3672169689Skan 3673169689Skan@cindex @code{copysign@var{m}3} instruction pattern 3674169689Skan@item @samp{copysign@var{m}3} 3675169689SkanStore a value with the magnitude of operand 1 and the sign of operand 3676169689Skan2 into operand 0. 3677169689Skan 3678169689SkanThe @code{copysign} built-in function of C always uses the mode which 3679169689Skancorresponds to the C data type @code{double} and the @code{copysignf} 3680169689Skanbuilt-in function uses the mode which corresponds to the C data 3681169689Skantype @code{float}. 3682169689Skan 368390075Sobrien@cindex @code{ffs@var{m}2} instruction pattern 368490075Sobrien@item @samp{ffs@var{m}2} 368590075SobrienStore into operand 0 one plus the index of the least significant 1-bit 368690075Sobrienof operand 1. If operand 1 is zero, store zero. @var{m} is the mode 368790075Sobrienof operand 0; operand 1's mode is specified by the instruction 368890075Sobrienpattern, and the compiler will convert the operand to that mode before 368990075Sobriengenerating the instruction. 369090075Sobrien 369190075SobrienThe @code{ffs} built-in function of C always uses the mode which 369290075Sobriencorresponds to the C data type @code{int}. 369390075Sobrien 3694132718Skan@cindex @code{clz@var{m}2} instruction pattern 3695132718Skan@item @samp{clz@var{m}2} 3696132718SkanStore into operand 0 the number of leading 0-bits in @var{x}, starting 3697132718Skanat the most significant bit position. If @var{x} is 0, the result is 3698132718Skanundefined. @var{m} is the mode of operand 0; operand 1's mode is 3699132718Skanspecified by the instruction pattern, and the compiler will convert the 3700132718Skanoperand to that mode before generating the instruction. 3701132718Skan 3702132718Skan@cindex @code{ctz@var{m}2} instruction pattern 3703132718Skan@item @samp{ctz@var{m}2} 3704132718SkanStore into operand 0 the number of trailing 0-bits in @var{x}, starting 3705132718Skanat the least significant bit position. If @var{x} is 0, the result is 3706132718Skanundefined. @var{m} is the mode of operand 0; operand 1's mode is 3707132718Skanspecified by the instruction pattern, and the compiler will convert the 3708132718Skanoperand to that mode before generating the instruction. 3709132718Skan 3710132718Skan@cindex @code{popcount@var{m}2} instruction pattern 3711132718Skan@item @samp{popcount@var{m}2} 3712132718SkanStore into operand 0 the number of 1-bits in @var{x}. @var{m} is the 3713132718Skanmode of operand 0; operand 1's mode is specified by the instruction 3714132718Skanpattern, and the compiler will convert the operand to that mode before 3715132718Skangenerating the instruction. 3716132718Skan 3717132718Skan@cindex @code{parity@var{m}2} instruction pattern 3718132718Skan@item @samp{parity@var{m}2} 3719169689SkanStore into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits 3720132718Skanin @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode 3721132718Skanis specified by the instruction pattern, and the compiler will convert 3722132718Skanthe operand to that mode before generating the instruction. 3723132718Skan 372490075Sobrien@cindex @code{one_cmpl@var{m}2} instruction pattern 372590075Sobrien@item @samp{one_cmpl@var{m}2} 372690075SobrienStore the bitwise-complement of operand 1 into operand 0. 372790075Sobrien 372890075Sobrien@cindex @code{cmp@var{m}} instruction pattern 372990075Sobrien@item @samp{cmp@var{m}} 373090075SobrienCompare operand 0 and operand 1, and set the condition codes. 373190075SobrienThe RTL pattern should look like this: 373290075Sobrien 373390075Sobrien@smallexample 373490075Sobrien(set (cc0) (compare (match_operand:@var{m} 0 @dots{}) 373590075Sobrien (match_operand:@var{m} 1 @dots{}))) 373690075Sobrien@end smallexample 373790075Sobrien 373890075Sobrien@cindex @code{tst@var{m}} instruction pattern 373990075Sobrien@item @samp{tst@var{m}} 374090075SobrienCompare operand 0 against zero, and set the condition codes. 374190075SobrienThe RTL pattern should look like this: 374290075Sobrien 374390075Sobrien@smallexample 374490075Sobrien(set (cc0) (match_operand:@var{m} 0 @dots{})) 374590075Sobrien@end smallexample 374690075Sobrien 374790075Sobrien@samp{tst@var{m}} patterns should not be defined for machines that do 374890075Sobriennot use @code{(cc0)}. Doing so would confuse the optimizer since it 374990075Sobrienwould no longer be clear which @code{set} operations were comparisons. 375090075SobrienThe @samp{cmp@var{m}} patterns should be used instead. 375190075Sobrien 3752169689Skan@cindex @code{movmem@var{m}} instruction pattern 3753169689Skan@item @samp{movmem@var{m}} 3754169689SkanBlock move instruction. The destination and source blocks of memory 3755169689Skanare the first two operands, and both are @code{mem:BLK}s with an 3756169689Skanaddress in mode @code{Pmode}. 375790075Sobrien 375890075SobrienThe number of bytes to move is the third operand, in mode @var{m}. 375990075SobrienUsually, you specify @code{word_mode} for @var{m}. However, if you can 376090075Sobriengenerate better code knowing the range of valid lengths is smaller than 376190075Sobrienthose representable in a full word, you should provide a pattern with a 376290075Sobrienmode corresponding to the range of values you can handle efficiently 376390075Sobrien(e.g., @code{QImode} for values in the range 0--127; note we avoid numbers 376490075Sobrienthat appear negative) and also a pattern with @code{word_mode}. 376590075Sobrien 376690075SobrienThe fourth operand is the known shared alignment of the source and 376790075Sobriendestination, in the form of a @code{const_int} rtx. Thus, if the 376890075Sobriencompiler knows that both source and destination are word-aligned, 376990075Sobrienit may provide the value 4 for this operand. 377090075Sobrien 3771169689SkanDescriptions of multiple @code{movmem@var{m}} patterns can only be 377290075Sobrienbeneficial if the patterns for smaller modes have fewer restrictions 377390075Sobrienon their first, second and fourth operands. Note that the mode @var{m} 3774169689Skanin @code{movmem@var{m}} does not impose any restriction on the mode of 377590075Sobrienindividually moved data units in the block. 377690075Sobrien 377790075SobrienThese patterns need not give special consideration to the possibility 377890075Sobrienthat the source and destination strings might overlap. 377990075Sobrien 3780169689Skan@cindex @code{movstr} instruction pattern 3781169689Skan@item @samp{movstr} 3782169689SkanString copy instruction, with @code{stpcpy} semantics. Operand 0 is 3783169689Skanan output operand in mode @code{Pmode}. The addresses of the 3784169689Skandestination and source strings are operands 1 and 2, and both are 3785169689Skan@code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of 3786169689Skanthe expansion of this pattern should store in operand 0 the address in 3787169689Skanwhich the @code{NUL} terminator was stored in the destination string. 378890075Sobrien 3789169689Skan@cindex @code{setmem@var{m}} instruction pattern 3790169689Skan@item @samp{setmem@var{m}} 3791169689SkanBlock set instruction. The destination string is the first operand, 3792169689Skangiven as a @code{mem:BLK} whose address is in mode @code{Pmode}. The 3793169689Skannumber of bytes to set is the second operand, in mode @var{m}. The value to 3794169689Skaninitialize the memory with is the third operand. Targets that only support the 3795169689Skanclearing of memory should reject any value that is not the constant 0. See 3796169689Skan@samp{movmem@var{m}} for a discussion of the choice of mode. 3797169689Skan 3798169689SkanThe fourth operand is the known alignment of the destination, in the form 379990075Sobrienof a @code{const_int} rtx. Thus, if the compiler knows that the 380090075Sobriendestination is word-aligned, it may provide the value 4 for this 380190075Sobrienoperand. 380290075Sobrien 3803169689SkanThe use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}. 380490075Sobrien 3805169689Skan@cindex @code{cmpstrn@var{m}} instruction pattern 3806169689Skan@item @samp{cmpstrn@var{m}} 3807132718SkanString compare instruction, with five operands. Operand 0 is the output; 380890075Sobrienit has mode @var{m}. The remaining four operands are like the operands 3809169689Skanof @samp{movmem@var{m}}. The two memory blocks specified are compared 3810132718Skanbyte by byte in lexicographic order starting at the beginning of each 3811132718Skanstring. The instruction is not allowed to prefetch more than one byte 3812132718Skanat a time since either string may end in the first byte and reading past 3813132718Skanthat may access an invalid page or segment and cause a fault. The 3814132718Skaneffect of the instruction is to store a value in operand 0 whose sign 3815132718Skanindicates the result of the comparison. 3816132718Skan 3817169689Skan@cindex @code{cmpstr@var{m}} instruction pattern 3818169689Skan@item @samp{cmpstr@var{m}} 3819169689SkanString compare instruction, without known maximum length. Operand 0 is the 3820169689Skanoutput; it has mode @var{m}. The second and third operand are the blocks of 3821169689Skanmemory to be compared; both are @code{mem:BLK} with an address in mode 3822169689Skan@code{Pmode}. 3823169689Skan 3824169689SkanThe fourth operand is the known shared alignment of the source and 3825169689Skandestination, in the form of a @code{const_int} rtx. Thus, if the 3826169689Skancompiler knows that both source and destination are word-aligned, 3827169689Skanit may provide the value 4 for this operand. 3828169689Skan 3829169689SkanThe two memory blocks specified are compared byte by byte in lexicographic 3830169689Skanorder starting at the beginning of each string. The instruction is not allowed 3831169689Skanto prefetch more than one byte at a time since either string may end in the 3832169689Skanfirst byte and reading past that may access an invalid page or segment and 3833169689Skancause a fault. The effect of the instruction is to store a value in operand 0 3834169689Skanwhose sign indicates the result of the comparison. 3835169689Skan 3836132718Skan@cindex @code{cmpmem@var{m}} instruction pattern 3837132718Skan@item @samp{cmpmem@var{m}} 3838132718SkanBlock compare instruction, with five operands like the operands 3839132718Skanof @samp{cmpstr@var{m}}. The two memory blocks specified are compared 3840132718Skanbyte by byte in lexicographic order starting at the beginning of each 3841132718Skanblock. Unlike @samp{cmpstr@var{m}} the instruction can prefetch 3842132718Skanany bytes in the two memory blocks. The effect of the instruction is 384390075Sobriento store a value in operand 0 whose sign indicates the result of the 384490075Sobriencomparison. 384590075Sobrien 384690075Sobrien@cindex @code{strlen@var{m}} instruction pattern 384790075Sobrien@item @samp{strlen@var{m}} 384890075SobrienCompute the length of a string, with three operands. 384990075SobrienOperand 0 is the result (of mode @var{m}), operand 1 is 385090075Sobriena @code{mem} referring to the first character of the string, 385190075Sobrienoperand 2 is the character to search for (normally zero), 385290075Sobrienand operand 3 is a constant describing the known alignment 385390075Sobrienof the beginning of the string. 385490075Sobrien 385590075Sobrien@cindex @code{float@var{mn}2} instruction pattern 385690075Sobrien@item @samp{float@var{m}@var{n}2} 385790075SobrienConvert signed integer operand 1 (valid for fixed point mode @var{m}) to 385890075Sobrienfloating point mode @var{n} and store in operand 0 (which has mode 385990075Sobrien@var{n}). 386090075Sobrien 386190075Sobrien@cindex @code{floatuns@var{mn}2} instruction pattern 386290075Sobrien@item @samp{floatuns@var{m}@var{n}2} 386390075SobrienConvert unsigned integer operand 1 (valid for fixed point mode @var{m}) 386490075Sobriento floating point mode @var{n} and store in operand 0 (which has mode 386590075Sobrien@var{n}). 386690075Sobrien 386790075Sobrien@cindex @code{fix@var{mn}2} instruction pattern 386890075Sobrien@item @samp{fix@var{m}@var{n}2} 386990075SobrienConvert operand 1 (valid for floating point mode @var{m}) to fixed 387090075Sobrienpoint mode @var{n} as a signed number and store in operand 0 (which 387190075Sobrienhas mode @var{n}). This instruction's result is defined only when 387290075Sobrienthe value of operand 1 is an integer. 387390075Sobrien 3874169689SkanIf the machine description defines this pattern, it also needs to 3875169689Skandefine the @code{ftrunc} pattern. 3876169689Skan 387790075Sobrien@cindex @code{fixuns@var{mn}2} instruction pattern 387890075Sobrien@item @samp{fixuns@var{m}@var{n}2} 387990075SobrienConvert operand 1 (valid for floating point mode @var{m}) to fixed 388090075Sobrienpoint mode @var{n} as an unsigned number and store in operand 0 (which 388190075Sobrienhas mode @var{n}). This instruction's result is defined only when the 388290075Sobrienvalue of operand 1 is an integer. 388390075Sobrien 388490075Sobrien@cindex @code{ftrunc@var{m}2} instruction pattern 388590075Sobrien@item @samp{ftrunc@var{m}2} 388690075SobrienConvert operand 1 (valid for floating point mode @var{m}) to an 388790075Sobrieninteger value, still represented in floating point mode @var{m}, and 388890075Sobrienstore it in operand 0 (valid for floating point mode @var{m}). 388990075Sobrien 389090075Sobrien@cindex @code{fix_trunc@var{mn}2} instruction pattern 389190075Sobrien@item @samp{fix_trunc@var{m}@var{n}2} 389290075SobrienLike @samp{fix@var{m}@var{n}2} but works for any floating point value 389390075Sobrienof mode @var{m} by converting the value to an integer. 389490075Sobrien 389590075Sobrien@cindex @code{fixuns_trunc@var{mn}2} instruction pattern 389690075Sobrien@item @samp{fixuns_trunc@var{m}@var{n}2} 389790075SobrienLike @samp{fixuns@var{m}@var{n}2} but works for any floating point 389890075Sobrienvalue of mode @var{m} by converting the value to an integer. 389990075Sobrien 390090075Sobrien@cindex @code{trunc@var{mn}2} instruction pattern 390190075Sobrien@item @samp{trunc@var{m}@var{n}2} 390290075SobrienTruncate operand 1 (valid for mode @var{m}) to mode @var{n} and 390390075Sobrienstore in operand 0 (which has mode @var{n}). Both modes must be fixed 390490075Sobrienpoint or both floating point. 390590075Sobrien 390690075Sobrien@cindex @code{extend@var{mn}2} instruction pattern 390790075Sobrien@item @samp{extend@var{m}@var{n}2} 390890075SobrienSign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and 390990075Sobrienstore in operand 0 (which has mode @var{n}). Both modes must be fixed 391090075Sobrienpoint or both floating point. 391190075Sobrien 391290075Sobrien@cindex @code{zero_extend@var{mn}2} instruction pattern 391390075Sobrien@item @samp{zero_extend@var{m}@var{n}2} 391490075SobrienZero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and 391590075Sobrienstore in operand 0 (which has mode @var{n}). Both modes must be fixed 391690075Sobrienpoint. 391790075Sobrien 391890075Sobrien@cindex @code{extv} instruction pattern 391990075Sobrien@item @samp{extv} 392090075SobrienExtract a bit-field from operand 1 (a register or memory operand), where 392190075Sobrienoperand 2 specifies the width in bits and operand 3 the starting bit, 392290075Sobrienand store it in operand 0. Operand 0 must have mode @code{word_mode}. 392390075SobrienOperand 1 may have mode @code{byte_mode} or @code{word_mode}; often 392490075Sobrien@code{word_mode} is allowed only for registers. Operands 2 and 3 must 392590075Sobrienbe valid for @code{word_mode}. 392690075Sobrien 392790075SobrienThe RTL generation pass generates this instruction only with constants 3928169689Skanfor operands 2 and 3 and the constant is never zero for operand 2. 392990075Sobrien 393090075SobrienThe bit-field value is sign-extended to a full word integer 393190075Sobrienbefore it is stored in operand 0. 393290075Sobrien 393390075Sobrien@cindex @code{extzv} instruction pattern 393490075Sobrien@item @samp{extzv} 393590075SobrienLike @samp{extv} except that the bit-field value is zero-extended. 393690075Sobrien 393790075Sobrien@cindex @code{insv} instruction pattern 393890075Sobrien@item @samp{insv} 393990075SobrienStore operand 3 (which must be valid for @code{word_mode}) into a 394090075Sobrienbit-field in operand 0, where operand 1 specifies the width in bits and 394190075Sobrienoperand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or 394290075Sobrien@code{word_mode}; often @code{word_mode} is allowed only for registers. 394390075SobrienOperands 1 and 2 must be valid for @code{word_mode}. 394490075Sobrien 394590075SobrienThe RTL generation pass generates this instruction only with constants 3946169689Skanfor operands 1 and 2 and the constant is never zero for operand 1. 394790075Sobrien 394890075Sobrien@cindex @code{mov@var{mode}cc} instruction pattern 394990075Sobrien@item @samp{mov@var{mode}cc} 395090075SobrienConditionally move operand 2 or operand 3 into operand 0 according to the 395190075Sobriencomparison in operand 1. If the comparison is true, operand 2 is moved 395290075Sobrieninto operand 0, otherwise operand 3 is moved. 395390075Sobrien 395490075SobrienThe mode of the operands being compared need not be the same as the operands 395590075Sobrienbeing moved. Some machines, sparc64 for example, have instructions that 395690075Sobrienconditionally move an integer value based on the floating point condition 395790075Sobriencodes and vice versa. 395890075Sobrien 395990075SobrienIf the machine does not have conditional move instructions, do not 396090075Sobriendefine these patterns. 396190075Sobrien 3962132718Skan@cindex @code{add@var{mode}cc} instruction pattern 3963132718Skan@item @samp{add@var{mode}cc} 3964132718SkanSimilar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally 3965132718Skanmove operand 2 or (operands 2 + operand 3) into operand 0 according to the 3966132718Skancomparison in operand 1. If the comparison is true, operand 2 is moved into 3967132718Skanoperand 0, otherwise (operand 2 + operand 3) is moved. 3968132718Skan 396990075Sobrien@cindex @code{s@var{cond}} instruction pattern 397090075Sobrien@item @samp{s@var{cond}} 397190075SobrienStore zero or nonzero in the operand according to the condition codes. 397290075SobrienValue stored is nonzero iff the condition @var{cond} is true. 397390075Sobrien@var{cond} is the name of a comparison operation expression code, such 397490075Sobrienas @code{eq}, @code{lt} or @code{leu}. 397590075Sobrien 397690075SobrienYou specify the mode that the operand must have when you write the 397790075Sobrien@code{match_operand} expression. The compiler automatically sees 397890075Sobrienwhich mode you have used and supplies an operand of that mode. 397990075Sobrien 398090075SobrienThe value stored for a true condition must have 1 as its low bit, or 398190075Sobrienelse must be negative. Otherwise the instruction is not suitable and 398290075Sobrienyou should omit it from the machine description. You describe to the 398390075Sobriencompiler exactly which value is stored by defining the macro 398490075Sobrien@code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be 398590075Sobrienfound that can be used for all the @samp{s@var{cond}} patterns, you 398690075Sobrienshould omit those operations from the machine description. 398790075Sobrien 398890075SobrienThese operations may fail, but should do so only in relatively 398990075Sobrienuncommon cases; if they would fail for common cases involving 399090075Sobrieninteger comparisons, it is best to omit these patterns. 399190075Sobrien 399290075SobrienIf these operations are omitted, the compiler will usually generate code 399390075Sobrienthat copies the constant one to the target and branches around an 399490075Sobrienassignment of zero to the target. If this code is more efficient than 399590075Sobrienthe potential instructions used for the @samp{s@var{cond}} pattern 399690075Sobrienfollowed by those required to convert the result into a 1 or a zero in 399790075Sobrien@code{SImode}, you should omit the @samp{s@var{cond}} operations from 399890075Sobrienthe machine description. 399990075Sobrien 400090075Sobrien@cindex @code{b@var{cond}} instruction pattern 400190075Sobrien@item @samp{b@var{cond}} 400290075SobrienConditional branch instruction. Operand 0 is a @code{label_ref} that 400390075Sobrienrefers to the label to jump to. Jump if the condition codes meet 400490075Sobriencondition @var{cond}. 400590075Sobrien 400690075SobrienSome machines do not follow the model assumed here where a comparison 400790075Sobrieninstruction is followed by a conditional branch instruction. In that 400890075Sobriencase, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should 400990075Sobriensimply store the operands away and generate all the required insns in a 401090075Sobrien@code{define_expand} (@pxref{Expander Definitions}) for the conditional 401190075Sobrienbranch operations. All calls to expand @samp{b@var{cond}} patterns are 401290075Sobrienimmediately preceded by calls to expand either a @samp{cmp@var{m}} 401390075Sobrienpattern or a @samp{tst@var{m}} pattern. 401490075Sobrien 401590075SobrienMachines that use a pseudo register for the condition code value, or 401690075Sobrienwhere the mode used for the comparison depends on the condition being 401790075Sobrientested, should also use the above mechanism. @xref{Jump Patterns}. 401890075Sobrien 401990075SobrienThe above discussion also applies to the @samp{mov@var{mode}cc} and 402090075Sobrien@samp{s@var{cond}} patterns. 402190075Sobrien 4022169689Skan@cindex @code{cbranch@var{mode}4} instruction pattern 4023169689Skan@item @samp{cbranch@var{mode}4} 4024169689SkanConditional branch instruction combined with a compare instruction. 4025169689SkanOperand 0 is a comparison operator. Operand 1 and operand 2 are the 4026169689Skanfirst and second operands of the comparison, respectively. Operand 3 4027169689Skanis a @code{label_ref} that refers to the label to jump to. 4028169689Skan 402990075Sobrien@cindex @code{jump} instruction pattern 403090075Sobrien@item @samp{jump} 403190075SobrienA jump inside a function; an unconditional branch. Operand 0 is the 403290075Sobrien@code{label_ref} of the label to jump to. This pattern name is mandatory 403390075Sobrienon all machines. 403490075Sobrien 403590075Sobrien@cindex @code{call} instruction pattern 403690075Sobrien@item @samp{call} 403790075SobrienSubroutine call instruction returning no value. Operand 0 is the 403890075Sobrienfunction to call; operand 1 is the number of bytes of arguments pushed 403990075Sobrienas a @code{const_int}; operand 2 is the number of registers used as 404090075Sobrienoperands. 404190075Sobrien 404290075SobrienOn most machines, operand 2 is not actually stored into the RTL 404390075Sobrienpattern. It is supplied for the sake of some RISC machines which need 404490075Sobriento put this information into the assembler code; they can put it in 404590075Sobrienthe RTL instead of operand 1. 404690075Sobrien 404790075SobrienOperand 0 should be a @code{mem} RTX whose address is the address of the 404890075Sobrienfunction. Note, however, that this address can be a @code{symbol_ref} 404990075Sobrienexpression even if it would not be a legitimate memory address on the 405090075Sobrientarget machine. If it is also not a valid argument for a call 405190075Sobrieninstruction, the pattern for this operation should be a 405290075Sobrien@code{define_expand} (@pxref{Expander Definitions}) that places the 405390075Sobrienaddress into a register and uses that register in the call instruction. 405490075Sobrien 405590075Sobrien@cindex @code{call_value} instruction pattern 405690075Sobrien@item @samp{call_value} 405790075SobrienSubroutine call instruction returning a value. Operand 0 is the hard 405890075Sobrienregister in which the value is returned. There are three more 405990075Sobrienoperands, the same as the three operands of the @samp{call} 406090075Sobrieninstruction (but with numbers increased by one). 406190075Sobrien 406290075SobrienSubroutines that return @code{BLKmode} objects use the @samp{call} 406390075Sobrieninsn. 406490075Sobrien 406590075Sobrien@cindex @code{call_pop} instruction pattern 406690075Sobrien@cindex @code{call_value_pop} instruction pattern 406790075Sobrien@item @samp{call_pop}, @samp{call_value_pop} 406890075SobrienSimilar to @samp{call} and @samp{call_value}, except used if defined and 406990075Sobrienif @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel} 407090075Sobrienthat contains both the function call and a @code{set} to indicate the 407190075Sobrienadjustment made to the frame pointer. 407290075Sobrien 407390075SobrienFor machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these 407490075Sobrienpatterns increases the number of functions for which the frame pointer 407590075Sobriencan be eliminated, if desired. 407690075Sobrien 407790075Sobrien@cindex @code{untyped_call} instruction pattern 407890075Sobrien@item @samp{untyped_call} 407990075SobrienSubroutine call instruction returning a value of any type. Operand 0 is 408090075Sobrienthe function to call; operand 1 is a memory location where the result of 408190075Sobriencalling the function is to be stored; operand 2 is a @code{parallel} 408290075Sobrienexpression where each element is a @code{set} expression that indicates 408390075Sobrienthe saving of a function return value into the result block. 408490075Sobrien 408590075SobrienThis instruction pattern should be defined to support 408690075Sobrien@code{__builtin_apply} on machines where special instructions are needed 408790075Sobriento call a subroutine with arbitrary arguments or to save the value 408890075Sobrienreturned. This instruction pattern is required on machines that have 408990075Sobrienmultiple registers that can hold a return value 409090075Sobrien(i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register). 409190075Sobrien 409290075Sobrien@cindex @code{return} instruction pattern 409390075Sobrien@item @samp{return} 409490075SobrienSubroutine return instruction. This instruction pattern name should be 409590075Sobriendefined only if a single instruction can do all the work of returning 409690075Sobrienfrom a function. 409790075Sobrien 409890075SobrienLike the @samp{mov@var{m}} patterns, this pattern is also used after the 409990075SobrienRTL generation phase. In this case it is to support machines where 410090075Sobrienmultiple instructions are usually needed to return from a function, but 410190075Sobriensome class of functions only requires one instruction to implement a 410290075Sobrienreturn. Normally, the applicable functions are those which do not need 410390075Sobriento save any registers or allocate stack space. 410490075Sobrien 410590075Sobrien@findex reload_completed 410690075Sobrien@findex leaf_function_p 410790075SobrienFor such machines, the condition specified in this pattern should only 410890075Sobrienbe true when @code{reload_completed} is nonzero and the function's 410990075Sobrienepilogue would only be a single instruction. For machines with register 411090075Sobrienwindows, the routine @code{leaf_function_p} may be used to determine if 411190075Sobriena register window push is required. 411290075Sobrien 411390075SobrienMachines that have conditional return instructions should define patterns 411490075Sobriensuch as 411590075Sobrien 411690075Sobrien@smallexample 411790075Sobrien(define_insn "" 411890075Sobrien [(set (pc) 411990075Sobrien (if_then_else (match_operator 412090075Sobrien 0 "comparison_operator" 412190075Sobrien [(cc0) (const_int 0)]) 412290075Sobrien (return) 412390075Sobrien (pc)))] 412490075Sobrien "@var{condition}" 412590075Sobrien "@dots{}") 412690075Sobrien@end smallexample 412790075Sobrien 412890075Sobrienwhere @var{condition} would normally be the same condition specified on the 412990075Sobriennamed @samp{return} pattern. 413090075Sobrien 413190075Sobrien@cindex @code{untyped_return} instruction pattern 413290075Sobrien@item @samp{untyped_return} 413390075SobrienUntyped subroutine return instruction. This instruction pattern should 413490075Sobrienbe defined to support @code{__builtin_return} on machines where special 413590075Sobrieninstructions are needed to return a value of any type. 413690075Sobrien 413790075SobrienOperand 0 is a memory location where the result of calling a function 413890075Sobrienwith @code{__builtin_apply} is stored; operand 1 is a @code{parallel} 413990075Sobrienexpression where each element is a @code{set} expression that indicates 414090075Sobrienthe restoring of a function return value from the result block. 414190075Sobrien 414290075Sobrien@cindex @code{nop} instruction pattern 414390075Sobrien@item @samp{nop} 414490075SobrienNo-op instruction. This instruction pattern name should always be defined 414590075Sobriento output a no-op in assembler code. @code{(const_int 0)} will do as an 414690075SobrienRTL pattern. 414790075Sobrien 414890075Sobrien@cindex @code{indirect_jump} instruction pattern 414990075Sobrien@item @samp{indirect_jump} 415090075SobrienAn instruction to jump to an address which is operand zero. 415190075SobrienThis pattern name is mandatory on all machines. 415290075Sobrien 415390075Sobrien@cindex @code{casesi} instruction pattern 415490075Sobrien@item @samp{casesi} 415590075SobrienInstruction to jump through a dispatch table, including bounds checking. 415690075SobrienThis instruction takes five operands: 415790075Sobrien 415890075Sobrien@enumerate 415990075Sobrien@item 416090075SobrienThe index to dispatch on, which has mode @code{SImode}. 416190075Sobrien 416290075Sobrien@item 416390075SobrienThe lower bound for indices in the table, an integer constant. 416490075Sobrien 416590075Sobrien@item 416690075SobrienThe total range of indices in the table---the largest index 416790075Sobrienminus the smallest one (both inclusive). 416890075Sobrien 416990075Sobrien@item 417090075SobrienA label that precedes the table itself. 417190075Sobrien 417290075Sobrien@item 417390075SobrienA label to jump to if the index has a value outside the bounds. 417490075Sobrien@end enumerate 417590075Sobrien 417690075SobrienThe table is a @code{addr_vec} or @code{addr_diff_vec} inside of a 417790075Sobrien@code{jump_insn}. The number of elements in the table is one plus the 417890075Sobriendifference between the upper bound and the lower bound. 417990075Sobrien 418090075Sobrien@cindex @code{tablejump} instruction pattern 418190075Sobrien@item @samp{tablejump} 418290075SobrienInstruction to jump to a variable address. This is a low-level 418390075Sobriencapability which can be used to implement a dispatch table when there 418490075Sobrienis no @samp{casesi} pattern. 418590075Sobrien 418690075SobrienThis pattern requires two operands: the address or offset, and a label 418790075Sobrienwhich should immediately precede the jump table. If the macro 418890075Sobrien@code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first 418990075Sobrienoperand is an offset which counts from the address of the table; otherwise, 419090075Sobrienit is an absolute address to jump to. In either case, the first operand has 419190075Sobrienmode @code{Pmode}. 419290075Sobrien 419390075SobrienThe @samp{tablejump} insn is always the last insn before the jump 419490075Sobrientable it uses. Its assembler code normally has no need to use the 419590075Sobriensecond operand, but you should incorporate it in the RTL pattern so 419690075Sobrienthat the jump optimizer will not delete the table as unreachable code. 419790075Sobrien 419890075Sobrien 419990075Sobrien@cindex @code{decrement_and_branch_until_zero} instruction pattern 420090075Sobrien@item @samp{decrement_and_branch_until_zero} 420190075SobrienConditional branch instruction that decrements a register and 420290075Sobrienjumps if the register is nonzero. Operand 0 is the register to 420390075Sobriendecrement and test; operand 1 is the label to jump to if the 420490075Sobrienregister is nonzero. @xref{Looping Patterns}. 420590075Sobrien 420690075SobrienThis optional instruction pattern is only used by the combiner, 420790075Sobrientypically for loops reversed by the loop optimizer when strength 420890075Sobrienreduction is enabled. 420990075Sobrien 421090075Sobrien@cindex @code{doloop_end} instruction pattern 421190075Sobrien@item @samp{doloop_end} 421290075SobrienConditional branch instruction that decrements a register and jumps if 421390075Sobrienthe register is nonzero. This instruction takes five operands: Operand 421490075Sobrien0 is the register to decrement and test; operand 1 is the number of loop 421590075Sobrieniterations as a @code{const_int} or @code{const0_rtx} if this cannot be 421690075Sobriendetermined until run-time; operand 2 is the actual or estimated maximum 421790075Sobriennumber of iterations as a @code{const_int}; operand 3 is the number of 421890075Sobrienenclosed loops as a @code{const_int} (an innermost loop has a value of 421990075Sobrien1); operand 4 is the label to jump to if the register is nonzero. 422090075Sobrien@xref{Looping Patterns}. 422190075Sobrien 422290075SobrienThis optional instruction pattern should be defined for machines with 422390075Sobrienlow-overhead looping instructions as the loop optimizer will try to 422490075Sobrienmodify suitable loops to utilize it. If nested low-overhead looping is 422590075Sobriennot supported, use a @code{define_expand} (@pxref{Expander Definitions}) 422690075Sobrienand make the pattern fail if operand 3 is not @code{const1_rtx}. 422790075SobrienSimilarly, if the actual or estimated maximum number of iterations is 422890075Sobrientoo large for this instruction, make it fail. 422990075Sobrien 423090075Sobrien@cindex @code{doloop_begin} instruction pattern 423190075Sobrien@item @samp{doloop_begin} 423290075SobrienCompanion instruction to @code{doloop_end} required for machines that 423390075Sobrienneed to perform some initialization, such as loading special registers 423490075Sobrienused by a low-overhead looping instruction. If initialization insns do 423590075Sobriennot always need to be emitted, use a @code{define_expand} 423690075Sobrien(@pxref{Expander Definitions}) and make it fail. 423790075Sobrien 423890075Sobrien 423990075Sobrien@cindex @code{canonicalize_funcptr_for_compare} instruction pattern 424090075Sobrien@item @samp{canonicalize_funcptr_for_compare} 424190075SobrienCanonicalize the function pointer in operand 1 and store the result 424290075Sobrieninto operand 0. 424390075Sobrien 424490075SobrienOperand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1 424590075Sobrienmay be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc 424690075Sobrienand also has mode @code{Pmode}. 424790075Sobrien 424890075SobrienCanonicalization of a function pointer usually involves computing 424990075Sobrienthe address of the function which would be called if the function 425090075Sobrienpointer were used in an indirect call. 425190075Sobrien 425290075SobrienOnly define this pattern if function pointers on the target machine 425390075Sobriencan have different values but still call the same function when 425490075Sobrienused in an indirect call. 425590075Sobrien 425690075Sobrien@cindex @code{save_stack_block} instruction pattern 425790075Sobrien@cindex @code{save_stack_function} instruction pattern 425890075Sobrien@cindex @code{save_stack_nonlocal} instruction pattern 425990075Sobrien@cindex @code{restore_stack_block} instruction pattern 426090075Sobrien@cindex @code{restore_stack_function} instruction pattern 426190075Sobrien@cindex @code{restore_stack_nonlocal} instruction pattern 426290075Sobrien@item @samp{save_stack_block} 426390075Sobrien@itemx @samp{save_stack_function} 426490075Sobrien@itemx @samp{save_stack_nonlocal} 426590075Sobrien@itemx @samp{restore_stack_block} 426690075Sobrien@itemx @samp{restore_stack_function} 426790075Sobrien@itemx @samp{restore_stack_nonlocal} 426890075SobrienMost machines save and restore the stack pointer by copying it to or 426990075Sobrienfrom an object of mode @code{Pmode}. Do not define these patterns on 427090075Sobriensuch machines. 427190075Sobrien 427290075SobrienSome machines require special handling for stack pointer saves and 427390075Sobrienrestores. On those machines, define the patterns corresponding to the 427490075Sobriennon-standard cases by using a @code{define_expand} (@pxref{Expander 427590075SobrienDefinitions}) that produces the required insns. The three types of 427690075Sobriensaves and restores are: 427790075Sobrien 427890075Sobrien@enumerate 427990075Sobrien@item 428090075Sobrien@samp{save_stack_block} saves the stack pointer at the start of a block 428190075Sobrienthat allocates a variable-sized object, and @samp{restore_stack_block} 428290075Sobrienrestores the stack pointer when the block is exited. 428390075Sobrien 428490075Sobrien@item 428590075Sobrien@samp{save_stack_function} and @samp{restore_stack_function} do a 428690075Sobriensimilar job for the outermost block of a function and are used when the 428790075Sobrienfunction allocates variable-sized objects or calls @code{alloca}. Only 428890075Sobrienthe epilogue uses the restored stack pointer, allowing a simpler save or 428990075Sobrienrestore sequence on some machines. 429090075Sobrien 429190075Sobrien@item 429290075Sobrien@samp{save_stack_nonlocal} is used in functions that contain labels 429390075Sobrienbranched to by nested functions. It saves the stack pointer in such a 429490075Sobrienway that the inner function can use @samp{restore_stack_nonlocal} to 429590075Sobrienrestore the stack pointer. The compiler generates code to restore the 429690075Sobrienframe and argument pointer registers, but some machines require saving 429790075Sobrienand restoring additional data such as register window information or 429890075Sobrienstack backchains. Place insns in these patterns to save and restore any 429990075Sobriensuch required data. 430090075Sobrien@end enumerate 430190075Sobrien 430290075SobrienWhen saving the stack pointer, operand 0 is the save area and operand 1 430390075Sobrienis the stack pointer. The mode used to allocate the save area defaults 430490075Sobriento @code{Pmode} but you can override that choice by defining the 430590075Sobrien@code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must 430690075Sobrienspecify an integral mode, or @code{VOIDmode} if no save area is needed 430790075Sobrienfor a particular type of save (either because no save is needed or 430890075Sobrienbecause a machine-specific save area can be used). Operand 0 is the 430990075Sobrienstack pointer and operand 1 is the save area for restore operations. If 431090075Sobrien@samp{save_stack_block} is defined, operand 0 must not be 431190075Sobrien@code{VOIDmode} since these saves can be arbitrarily nested. 431290075Sobrien 431390075SobrienA save area is a @code{mem} that is at a constant offset from 431490075Sobrien@code{virtual_stack_vars_rtx} when the stack pointer is saved for use by 431590075Sobriennonlocal gotos and a @code{reg} in the other two cases. 431690075Sobrien 431790075Sobrien@cindex @code{allocate_stack} instruction pattern 431890075Sobrien@item @samp{allocate_stack} 431990075SobrienSubtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from 432090075Sobrienthe stack pointer to create space for dynamically allocated data. 432190075Sobrien 432290075SobrienStore the resultant pointer to this space into operand 0. If you 432390075Sobrienare allocating space from the main stack, do this by emitting a 432490075Sobrienmove insn to copy @code{virtual_stack_dynamic_rtx} to operand 0. 432590075SobrienIf you are allocating the space elsewhere, generate code to copy the 432690075Sobrienlocation of the space to operand 0. In the latter case, you must 432790075Sobrienensure this space gets freed when the corresponding space on the main 432890075Sobrienstack is free. 432990075Sobrien 433090075SobrienDo not define this pattern if all that must be done is the subtraction. 433190075SobrienSome machines require other operations such as stack probes or 433290075Sobrienmaintaining the back chain. Define this pattern to emit those 433390075Sobrienoperations in addition to updating the stack pointer. 433490075Sobrien 433590075Sobrien@cindex @code{check_stack} instruction pattern 433690075Sobrien@item @samp{check_stack} 433790075SobrienIf stack checking cannot be done on your system by probing the stack with 433890075Sobriena load or store instruction (@pxref{Stack Checking}), define this pattern 433990075Sobriento perform the needed check and signaling an error if the stack 434090075Sobrienhas overflowed. The single operand is the location in the stack furthest 434190075Sobrienfrom the current stack pointer that you need to validate. Normally, 434290075Sobrienon machines where this pattern is needed, you would obtain the stack 434390075Sobrienlimit from a global or thread-specific variable or register. 434490075Sobrien 434590075Sobrien@cindex @code{nonlocal_goto} instruction pattern 434690075Sobrien@item @samp{nonlocal_goto} 434790075SobrienEmit code to generate a non-local goto, e.g., a jump from one function 434890075Sobriento a label in an outer function. This pattern has four arguments, 434990075Sobrieneach representing a value to be used in the jump. The first 435090075Sobrienargument is to be loaded into the frame pointer, the second is 435190075Sobrienthe address to branch to (code to dispatch to the actual label), 435290075Sobrienthe third is the address of a location where the stack is saved, 435390075Sobrienand the last is the address of the label, to be placed in the 435490075Sobrienlocation for the incoming static chain. 435590075Sobrien 435690075SobrienOn most machines you need not define this pattern, since GCC will 435790075Sobrienalready generate the correct code, which is to load the frame pointer 435890075Sobrienand static chain, restore the stack (using the 435990075Sobrien@samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly 436090075Sobriento the dispatcher. You need only define this pattern if this code will 436190075Sobriennot work on your machine. 436290075Sobrien 436390075Sobrien@cindex @code{nonlocal_goto_receiver} instruction pattern 436490075Sobrien@item @samp{nonlocal_goto_receiver} 436590075SobrienThis pattern, if defined, contains code needed at the target of a 436690075Sobriennonlocal goto after the code already generated by GCC@. You will not 436790075Sobriennormally need to define this pattern. A typical reason why you might 436890075Sobrienneed this pattern is if some value, such as a pointer to a global table, 436990075Sobrienmust be restored when the frame pointer is restored. Note that a nonlocal 437090075Sobriengoto only occurs within a unit-of-translation, so a global table pointer 437190075Sobrienthat is shared by all functions of a given module need not be restored. 437290075SobrienThere are no arguments. 437390075Sobrien 437490075Sobrien@cindex @code{exception_receiver} instruction pattern 437590075Sobrien@item @samp{exception_receiver} 437690075SobrienThis pattern, if defined, contains code needed at the site of an 437790075Sobrienexception handler that isn't needed at the site of a nonlocal goto. You 437890075Sobrienwill not normally need to define this pattern. A typical reason why you 437990075Sobrienmight need this pattern is if some value, such as a pointer to a global 438090075Sobrientable, must be restored after control flow is branched to the handler of 438190075Sobrienan exception. There are no arguments. 438290075Sobrien 438390075Sobrien@cindex @code{builtin_setjmp_setup} instruction pattern 438490075Sobrien@item @samp{builtin_setjmp_setup} 438590075SobrienThis pattern, if defined, contains additional code needed to initialize 438690075Sobrienthe @code{jmp_buf}. You will not normally need to define this pattern. 438790075SobrienA typical reason why you might need this pattern is if some value, such 438890075Sobrienas a pointer to a global table, must be restored. Though it is 438990075Sobrienpreferred that the pointer value be recalculated if possible (given the 439090075Sobrienaddress of a label for instance). The single argument is a pointer to 439190075Sobrienthe @code{jmp_buf}. Note that the buffer is five words long and that 439290075Sobrienthe first three are normally used by the generic mechanism. 439390075Sobrien 439490075Sobrien@cindex @code{builtin_setjmp_receiver} instruction pattern 439590075Sobrien@item @samp{builtin_setjmp_receiver} 439690075SobrienThis pattern, if defined, contains code needed at the site of an 439790075Sobrienbuilt-in setjmp that isn't needed at the site of a nonlocal goto. You 439890075Sobrienwill not normally need to define this pattern. A typical reason why you 439990075Sobrienmight need this pattern is if some value, such as a pointer to a global 440090075Sobrientable, must be restored. It takes one argument, which is the label 440190075Sobriento which builtin_longjmp transfered control; this pattern may be emitted 440290075Sobrienat a small offset from that label. 440390075Sobrien 440490075Sobrien@cindex @code{builtin_longjmp} instruction pattern 440590075Sobrien@item @samp{builtin_longjmp} 440690075SobrienThis pattern, if defined, performs the entire action of the longjmp. 440790075SobrienYou will not normally need to define this pattern unless you also define 440890075Sobrien@code{builtin_setjmp_setup}. The single argument is a pointer to the 440990075Sobrien@code{jmp_buf}. 441090075Sobrien 441190075Sobrien@cindex @code{eh_return} instruction pattern 441290075Sobrien@item @samp{eh_return} 441390075SobrienThis pattern, if defined, affects the way @code{__builtin_eh_return}, 441490075Sobrienand thence the call frame exception handling library routines, are 441590075Sobrienbuilt. It is intended to handle non-trivial actions needed along 441690075Sobrienthe abnormal return path. 441790075Sobrien 4418132718SkanThe address of the exception handler to which the function should return 4419132718Skanis passed as operand to this pattern. It will normally need to copied by 4420132718Skanthe pattern to some special register or memory location. 4421132718SkanIf the pattern needs to determine the location of the target call 4422132718Skanframe in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX}, 4423132718Skanif defined; it will have already been assigned. 442490075Sobrien 4425132718SkanIf this pattern is not defined, the default action will be to simply 4426132718Skancopy the return address to @code{EH_RETURN_HANDLER_RTX}. Either 4427132718Skanthat macro or this pattern needs to be defined if call frame exception 4428132718Skanhandling is to be used. 442990075Sobrien 443090075Sobrien@cindex @code{prologue} instruction pattern 443190075Sobrien@anchor{prologue instruction pattern} 443290075Sobrien@item @samp{prologue} 443390075SobrienThis pattern, if defined, emits RTL for entry to a function. The function 443490075Sobrienentry is responsible for setting up the stack frame, initializing the frame 443590075Sobrienpointer register, saving callee saved registers, etc. 443690075Sobrien 443790075SobrienUsing a prologue pattern is generally preferred over defining 443890075Sobrien@code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue. 443990075Sobrien 444090075SobrienThe @code{prologue} pattern is particularly useful for targets which perform 444190075Sobrieninstruction scheduling. 444290075Sobrien 444390075Sobrien@cindex @code{epilogue} instruction pattern 444490075Sobrien@anchor{epilogue instruction pattern} 444590075Sobrien@item @samp{epilogue} 444690075SobrienThis pattern emits RTL for exit from a function. The function 444790075Sobrienexit is responsible for deallocating the stack frame, restoring callee saved 444890075Sobrienregisters and emitting the return instruction. 444990075Sobrien 445090075SobrienUsing an epilogue pattern is generally preferred over defining 445190075Sobrien@code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue. 445290075Sobrien 445390075SobrienThe @code{epilogue} pattern is particularly useful for targets which perform 445490075Sobrieninstruction scheduling or which have delay slots for their return instruction. 445590075Sobrien 445690075Sobrien@cindex @code{sibcall_epilogue} instruction pattern 445790075Sobrien@item @samp{sibcall_epilogue} 445890075SobrienThis pattern, if defined, emits RTL for exit from a function without the final 445990075Sobrienbranch back to the calling function. This pattern will be emitted before any 446090075Sobriensibling call (aka tail call) sites. 446190075Sobrien 446290075SobrienThe @code{sibcall_epilogue} pattern must not clobber any arguments used for 446390075Sobrienparameter passing or any stack slots for arguments passed to the current 446490075Sobrienfunction. 446590075Sobrien 446690075Sobrien@cindex @code{trap} instruction pattern 446790075Sobrien@item @samp{trap} 446890075SobrienThis pattern, if defined, signals an error, typically by causing some 446990075Sobrienkind of signal to be raised. Among other places, it is used by the Java 447090075Sobrienfront end to signal `invalid array index' exceptions. 447190075Sobrien 447290075Sobrien@cindex @code{conditional_trap} instruction pattern 447390075Sobrien@item @samp{conditional_trap} 447490075SobrienConditional trap instruction. Operand 0 is a piece of RTL which 447590075Sobrienperforms a comparison. Operand 1 is the trap code, an integer. 447690075Sobrien 447790075SobrienA typical @code{conditional_trap} pattern looks like 447890075Sobrien 447990075Sobrien@smallexample 448090075Sobrien(define_insn "conditional_trap" 448190075Sobrien [(trap_if (match_operator 0 "trap_operator" 448290075Sobrien [(cc0) (const_int 0)]) 448390075Sobrien (match_operand 1 "const_int_operand" "i"))] 448490075Sobrien "" 448590075Sobrien "@dots{}") 448690075Sobrien@end smallexample 448790075Sobrien 448890075Sobrien@cindex @code{prefetch} instruction pattern 448990075Sobrien@item @samp{prefetch} 449090075Sobrien 449190075SobrienThis pattern, if defined, emits code for a non-faulting data prefetch 449290075Sobrieninstruction. Operand 0 is the address of the memory to prefetch. Operand 1 449390075Sobrienis a constant 1 if the prefetch is preparing for a write to the memory 449490075Sobrienaddress, or a constant 0 otherwise. Operand 2 is the expected degree of 449590075Sobrientemporal locality of the data and is a value between 0 and 3, inclusive; 0 449690075Sobrienmeans that the data has no temporal locality, so it need not be left in the 449790075Sobriencache after the access; 3 means that the data has a high degree of temporal 449890075Sobrienlocality and should be left in all levels of cache possible; 1 and 2 mean, 449990075Sobrienrespectively, a low or moderate degree of temporal locality. 450090075Sobrien 450190075SobrienTargets that do not support write prefetches or locality hints can ignore 450290075Sobrienthe values of operands 1 and 2. 450390075Sobrien 4504169689Skan@cindex @code{memory_barrier} instruction pattern 4505169689Skan@item @samp{memory_barrier} 4506169689Skan 4507169689SkanIf the target memory model is not fully synchronous, then this pattern 4508169689Skanshould be defined to an instruction that orders both loads and stores 4509169689Skanbefore the instruction with respect to loads and stores after the instruction. 4510169689SkanThis pattern has no operands. 4511169689Skan 4512169689Skan@cindex @code{sync_compare_and_swap@var{mode}} instruction pattern 4513169689Skan@item @samp{sync_compare_and_swap@var{mode}} 4514169689Skan 4515169689SkanThis pattern, if defined, emits code for an atomic compare-and-swap 4516169689Skanoperation. Operand 1 is the memory on which the atomic operation is 4517169689Skanperformed. Operand 2 is the ``old'' value to be compared against the 4518169689Skancurrent contents of the memory location. Operand 3 is the ``new'' value 4519169689Skanto store in the memory if the compare succeeds. Operand 0 is the result 4520169689Skanof the operation; it should contain the contents of the memory 4521169689Skanbefore the operation. If the compare succeeds, this should obviously be 4522169689Skana copy of operand 2. 4523169689Skan 4524169689SkanThis pattern must show that both operand 0 and operand 1 are modified. 4525169689Skan 4526169689SkanThis pattern must issue any memory barrier instructions such that all 4527169689Skanmemory operations before the atomic operation occur before the atomic 4528169689Skanoperation and all memory operations after the atomic operation occur 4529169689Skanafter the atomic operation. 4530169689Skan 4531169689Skan@cindex @code{sync_compare_and_swap_cc@var{mode}} instruction pattern 4532169689Skan@item @samp{sync_compare_and_swap_cc@var{mode}} 4533169689Skan 4534169689SkanThis pattern is just like @code{sync_compare_and_swap@var{mode}}, except 4535169689Skanit should act as if compare part of the compare-and-swap were issued via 4536169689Skan@code{cmp@var{m}}. This comparison will only be used with @code{EQ} and 4537169689Skan@code{NE} branches and @code{setcc} operations. 4538169689Skan 4539169689SkanSome targets do expose the success or failure of the compare-and-swap 4540169689Skanoperation via the status flags. Ideally we wouldn't need a separate 4541169689Skannamed pattern in order to take advantage of this, but the combine pass 4542169689Skandoes not handle patterns with multiple sets, which is required by 4543169689Skandefinition for @code{sync_compare_and_swap@var{mode}}. 4544169689Skan 4545169689Skan@cindex @code{sync_add@var{mode}} instruction pattern 4546169689Skan@cindex @code{sync_sub@var{mode}} instruction pattern 4547169689Skan@cindex @code{sync_ior@var{mode}} instruction pattern 4548169689Skan@cindex @code{sync_and@var{mode}} instruction pattern 4549169689Skan@cindex @code{sync_xor@var{mode}} instruction pattern 4550169689Skan@cindex @code{sync_nand@var{mode}} instruction pattern 4551169689Skan@item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}} 4552169689Skan@itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}} 4553169689Skan@itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}} 4554169689Skan 4555169689SkanThese patterns emit code for an atomic operation on memory. 4556169689SkanOperand 0 is the memory on which the atomic operation is performed. 4557169689SkanOperand 1 is the second operand to the binary operator. 4558169689Skan 4559169689SkanThe ``nand'' operation is @code{~op0 & op1}. 4560169689Skan 4561169689SkanThis pattern must issue any memory barrier instructions such that all 4562169689Skanmemory operations before the atomic operation occur before the atomic 4563169689Skanoperation and all memory operations after the atomic operation occur 4564169689Skanafter the atomic operation. 4565169689Skan 4566169689SkanIf these patterns are not defined, the operation will be constructed 4567169689Skanfrom a compare-and-swap operation, if defined. 4568169689Skan 4569169689Skan@cindex @code{sync_old_add@var{mode}} instruction pattern 4570169689Skan@cindex @code{sync_old_sub@var{mode}} instruction pattern 4571169689Skan@cindex @code{sync_old_ior@var{mode}} instruction pattern 4572169689Skan@cindex @code{sync_old_and@var{mode}} instruction pattern 4573169689Skan@cindex @code{sync_old_xor@var{mode}} instruction pattern 4574169689Skan@cindex @code{sync_old_nand@var{mode}} instruction pattern 4575169689Skan@item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}} 4576169689Skan@itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}} 4577169689Skan@itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}} 4578169689Skan 4579169689SkanThese patterns are emit code for an atomic operation on memory, 4580169689Skanand return the value that the memory contained before the operation. 4581169689SkanOperand 0 is the result value, operand 1 is the memory on which the 4582169689Skanatomic operation is performed, and operand 2 is the second operand 4583169689Skanto the binary operator. 4584169689Skan 4585169689SkanThis pattern must issue any memory barrier instructions such that all 4586169689Skanmemory operations before the atomic operation occur before the atomic 4587169689Skanoperation and all memory operations after the atomic operation occur 4588169689Skanafter the atomic operation. 4589169689Skan 4590169689SkanIf these patterns are not defined, the operation will be constructed 4591169689Skanfrom a compare-and-swap operation, if defined. 4592169689Skan 4593169689Skan@cindex @code{sync_new_add@var{mode}} instruction pattern 4594169689Skan@cindex @code{sync_new_sub@var{mode}} instruction pattern 4595169689Skan@cindex @code{sync_new_ior@var{mode}} instruction pattern 4596169689Skan@cindex @code{sync_new_and@var{mode}} instruction pattern 4597169689Skan@cindex @code{sync_new_xor@var{mode}} instruction pattern 4598169689Skan@cindex @code{sync_new_nand@var{mode}} instruction pattern 4599169689Skan@item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}} 4600169689Skan@itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}} 4601169689Skan@itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}} 4602169689Skan 4603169689SkanThese patterns are like their @code{sync_old_@var{op}} counterparts, 4604169689Skanexcept that they return the value that exists in the memory location 4605169689Skanafter the operation, rather than before the operation. 4606169689Skan 4607169689Skan@cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern 4608169689Skan@item @samp{sync_lock_test_and_set@var{mode}} 4609169689Skan 4610169689SkanThis pattern takes two forms, based on the capabilities of the target. 4611169689SkanIn either case, operand 0 is the result of the operand, operand 1 is 4612169689Skanthe memory on which the atomic operation is performed, and operand 2 4613169689Skanis the value to set in the lock. 4614169689Skan 4615169689SkanIn the ideal case, this operation is an atomic exchange operation, in 4616169689Skanwhich the previous value in memory operand is copied into the result 4617169689Skanoperand, and the value operand is stored in the memory operand. 4618169689Skan 4619169689SkanFor less capable targets, any value operand that is not the constant 1 4620169689Skanshould be rejected with @code{FAIL}. In this case the target may use 4621169689Skanan atomic test-and-set bit operation. The result operand should contain 4622169689Skan1 if the bit was previously set and 0 if the bit was previously clear. 4623169689SkanThe true contents of the memory operand are implementation defined. 4624169689Skan 4625169689SkanThis pattern must issue any memory barrier instructions such that the 4626169689Skanpattern as a whole acts as an acquire barrier, that is all memory 4627169689Skanoperations after the pattern do not occur until the lock is acquired. 4628169689Skan 4629169689SkanIf this pattern is not defined, the operation will be constructed from 4630169689Skana compare-and-swap operation, if defined. 4631169689Skan 4632169689Skan@cindex @code{sync_lock_release@var{mode}} instruction pattern 4633169689Skan@item @samp{sync_lock_release@var{mode}} 4634169689Skan 4635169689SkanThis pattern, if defined, releases a lock set by 4636169689Skan@code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory 4637169689Skanthat contains the lock; operand 1 is the value to store in the lock. 4638169689Skan 4639169689SkanIf the target doesn't implement full semantics for 4640169689Skan@code{sync_lock_test_and_set@var{mode}}, any value operand which is not 4641169689Skanthe constant 0 should be rejected with @code{FAIL}, and the true contents 4642169689Skanof the memory operand are implementation defined. 4643169689Skan 4644169689SkanThis pattern must issue any memory barrier instructions such that the 4645169689Skanpattern as a whole acts as a release barrier, that is the lock is 4646169689Skanreleased only after all previous memory operations have completed. 4647169689Skan 4648169689SkanIf this pattern is not defined, then a @code{memory_barrier} pattern 4649169689Skanwill be emitted, followed by a store of the value to the memory operand. 4650169689Skan 4651169689Skan@cindex @code{stack_protect_set} instruction pattern 4652169689Skan@item @samp{stack_protect_set} 4653169689Skan 4654169689SkanThis pattern, if defined, moves a @code{Pmode} value from the memory 4655169689Skanin operand 1 to the memory in operand 0 without leaving the value in 4656169689Skana register afterward. This is to avoid leaking the value some place 4657169689Skanthat an attacker might use to rewrite the stack guard slot after 4658169689Skanhaving clobbered it. 4659169689Skan 4660169689SkanIf this pattern is not defined, then a plain move pattern is generated. 4661169689Skan 4662169689Skan@cindex @code{stack_protect_test} instruction pattern 4663169689Skan@item @samp{stack_protect_test} 4664169689Skan 4665169689SkanThis pattern, if defined, compares a @code{Pmode} value from the 4666169689Skanmemory in operand 1 with the memory in operand 0 without leaving the 4667169689Skanvalue in a register afterward and branches to operand 2 if the values 4668169689Skanweren't equal. 4669169689Skan 4670169689SkanIf this pattern is not defined, then a plain compare pattern and 4671169689Skanconditional branch pattern is used. 4672169689Skan 467390075Sobrien@end table 467490075Sobrien 4675132718Skan@end ifset 4676132718Skan@c Each of the following nodes are wrapped in separate 4677132718Skan@c "@ifset INTERNALS" to work around memory limits for the default 4678132718Skan@c configuration in older tetex distributions. Known to not work: 4679132718Skan@c tetex-1.0.7, known to work: tetex-2.0.2. 4680132718Skan@ifset INTERNALS 468190075Sobrien@node Pattern Ordering 468290075Sobrien@section When the Order of Patterns Matters 468390075Sobrien@cindex Pattern Ordering 468490075Sobrien@cindex Ordering of Patterns 468590075Sobrien 468690075SobrienSometimes an insn can match more than one instruction pattern. Then the 468790075Sobrienpattern that appears first in the machine description is the one used. 468890075SobrienTherefore, more specific patterns (patterns that will match fewer things) 468990075Sobrienand faster instructions (those that will produce better code when they 469090075Sobriendo match) should usually go first in the description. 469190075Sobrien 469290075SobrienIn some cases the effect of ordering the patterns can be used to hide 469390075Sobriena pattern when it is not valid. For example, the 68000 has an 469490075Sobrieninstruction for converting a fullword to floating point and another 469590075Sobrienfor converting a byte to floating point. An instruction converting 469690075Sobrienan integer to floating point could match either one. We put the 469790075Sobrienpattern to convert the fullword first to make sure that one will 469890075Sobrienbe used rather than the other. (Otherwise a large integer might 469990075Sobrienbe generated as a single-byte immediate quantity, which would not work.) 470090075SobrienInstead of using this pattern ordering it would be possible to make the 470190075Sobrienpattern for convert-a-byte smart enough to deal properly with any 470290075Sobrienconstant value. 470390075Sobrien 4704132718Skan@end ifset 4705132718Skan@ifset INTERNALS 470690075Sobrien@node Dependent Patterns 470790075Sobrien@section Interdependence of Patterns 470890075Sobrien@cindex Dependent Patterns 470990075Sobrien@cindex Interdependence of Patterns 471090075Sobrien 471190075SobrienEvery machine description must have a named pattern for each of the 471290075Sobrienconditional branch names @samp{b@var{cond}}. The recognition template 471390075Sobrienmust always have the form 471490075Sobrien 4715132718Skan@smallexample 471690075Sobrien(set (pc) 471790075Sobrien (if_then_else (@var{cond} (cc0) (const_int 0)) 471890075Sobrien (label_ref (match_operand 0 "" "")) 471990075Sobrien (pc))) 4720132718Skan@end smallexample 472190075Sobrien 472290075Sobrien@noindent 472390075SobrienIn addition, every machine description must have an anonymous pattern 472490075Sobrienfor each of the possible reverse-conditional branches. Their templates 472590075Sobrienlook like 472690075Sobrien 4727132718Skan@smallexample 472890075Sobrien(set (pc) 472990075Sobrien (if_then_else (@var{cond} (cc0) (const_int 0)) 473090075Sobrien (pc) 473190075Sobrien (label_ref (match_operand 0 "" "")))) 4732132718Skan@end smallexample 473390075Sobrien 473490075Sobrien@noindent 473590075SobrienThey are necessary because jump optimization can turn direct-conditional 473690075Sobrienbranches into reverse-conditional branches. 473790075Sobrien 473890075SobrienIt is often convenient to use the @code{match_operator} construct to 473990075Sobrienreduce the number of patterns that must be specified for branches. For 474090075Sobrienexample, 474190075Sobrien 4742132718Skan@smallexample 474390075Sobrien(define_insn "" 474490075Sobrien [(set (pc) 474590075Sobrien (if_then_else (match_operator 0 "comparison_operator" 474690075Sobrien [(cc0) (const_int 0)]) 474790075Sobrien (pc) 474890075Sobrien (label_ref (match_operand 1 "" ""))))] 474990075Sobrien "@var{condition}" 475090075Sobrien "@dots{}") 4751132718Skan@end smallexample 475290075Sobrien 475390075SobrienIn some cases machines support instructions identical except for the 475490075Sobrienmachine mode of one or more operands. For example, there may be 475590075Sobrien``sign-extend halfword'' and ``sign-extend byte'' instructions whose 475690075Sobrienpatterns are 475790075Sobrien 4758132718Skan@smallexample 475990075Sobrien(set (match_operand:SI 0 @dots{}) 476090075Sobrien (extend:SI (match_operand:HI 1 @dots{}))) 476190075Sobrien 476290075Sobrien(set (match_operand:SI 0 @dots{}) 476390075Sobrien (extend:SI (match_operand:QI 1 @dots{}))) 4764132718Skan@end smallexample 476590075Sobrien 476690075Sobrien@noindent 476790075SobrienConstant integers do not specify a machine mode, so an instruction to 476890075Sobrienextend a constant value could match either pattern. The pattern it 476990075Sobrienactually will match is the one that appears first in the file. For correct 477090075Sobrienresults, this must be the one for the widest possible mode (@code{HImode}, 477190075Sobrienhere). If the pattern matches the @code{QImode} instruction, the results 477290075Sobrienwill be incorrect if the constant value does not actually fit that mode. 477390075Sobrien 477490075SobrienSuch instructions to extend constants are rarely generated because they are 477590075Sobrienoptimized away, but they do occasionally happen in nonoptimized 477690075Sobriencompilations. 477790075Sobrien 477890075SobrienIf a constraint in a pattern allows a constant, the reload pass may 477990075Sobrienreplace a register with a constant permitted by the constraint in some 478090075Sobriencases. Similarly for memory references. Because of this substitution, 478190075Sobrienyou should not provide separate patterns for increment and decrement 478290075Sobrieninstructions. Instead, they should be generated from the same pattern 478390075Sobrienthat supports register-register add insns by examining the operands and 478490075Sobriengenerating the appropriate machine instruction. 478590075Sobrien 4786132718Skan@end ifset 4787132718Skan@ifset INTERNALS 478890075Sobrien@node Jump Patterns 478990075Sobrien@section Defining Jump Instruction Patterns 479090075Sobrien@cindex jump instruction patterns 479190075Sobrien@cindex defining jump instruction patterns 479290075Sobrien 479390075SobrienFor most machines, GCC assumes that the machine has a condition code. 479490075SobrienA comparison insn sets the condition code, recording the results of both 479590075Sobriensigned and unsigned comparison of the given operands. A separate branch 479690075Sobrieninsn tests the condition code and branches or not according its value. 479790075SobrienThe branch insns come in distinct signed and unsigned flavors. Many 479890075Sobriencommon machines, such as the VAX, the 68000 and the 32000, work this 479990075Sobrienway. 480090075Sobrien 480190075SobrienSome machines have distinct signed and unsigned compare instructions, and 480290075Sobrienonly one set of conditional branch instructions. The easiest way to handle 480390075Sobrienthese machines is to treat them just like the others until the final stage 480490075Sobrienwhere assembly code is written. At this time, when outputting code for the 480590075Sobriencompare instruction, peek ahead at the following branch using 480690075Sobrien@code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn 480790075Sobrienbeing output, in the output-writing code in an instruction pattern.) If 480890075Sobrienthe RTL says that is an unsigned branch, output an unsigned compare; 480990075Sobrienotherwise output a signed compare. When the branch itself is output, you 481090075Sobriencan treat signed and unsigned branches identically. 481190075Sobrien 481290075SobrienThe reason you can do this is that GCC always generates a pair of 481390075Sobrienconsecutive RTL insns, possibly separated by @code{note} insns, one to 481490075Sobrienset the condition code and one to test it, and keeps the pair inviolate 481590075Sobrienuntil the end. 481690075Sobrien 481790075SobrienTo go with this technique, you must define the machine-description macro 481890075Sobrien@code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no 481990075Sobriencompare instruction is superfluous. 482090075Sobrien 482190075SobrienSome machines have compare-and-branch instructions and no condition code. 482290075SobrienA similar technique works for them. When it is time to ``output'' a 482390075Sobriencompare instruction, record its operands in two static variables. When 482490075Sobrienoutputting the branch-on-condition-code instruction that follows, actually 482590075Sobrienoutput a compare-and-branch instruction that uses the remembered operands. 482690075Sobrien 482790075SobrienIt also works to define patterns for compare-and-branch instructions. 482890075SobrienIn optimizing compilation, the pair of compare and branch instructions 482990075Sobrienwill be combined according to these patterns. But this does not happen 483090075Sobrienif optimization is not requested. So you must use one of the solutions 483190075Sobrienabove in addition to any special patterns you define. 483290075Sobrien 483390075SobrienIn many RISC machines, most instructions do not affect the condition 483490075Sobriencode and there may not even be a separate condition code register. On 483590075Sobrienthese machines, the restriction that the definition and use of the 483690075Sobriencondition code be adjacent insns is not necessary and can prevent 483790075Sobrienimportant optimizations. For example, on the IBM RS/6000, there is a 483890075Sobriendelay for taken branches unless the condition code register is set three 483990075Sobrieninstructions earlier than the conditional branch. The instruction 484090075Sobrienscheduler cannot perform this optimization if it is not permitted to 484190075Sobrienseparate the definition and use of the condition code register. 484290075Sobrien 484390075SobrienOn these machines, do not use @code{(cc0)}, but instead use a register 484490075Sobriento represent the condition code. If there is a specific condition code 484590075Sobrienregister in the machine, use a hard register. If the condition code or 484690075Sobriencomparison result can be placed in any general register, or if there are 484790075Sobrienmultiple condition registers, use a pseudo register. 484890075Sobrien 484990075Sobrien@findex prev_cc0_setter 485090075Sobrien@findex next_cc0_user 485190075SobrienOn some machines, the type of branch instruction generated may depend on 485290075Sobrienthe way the condition code was produced; for example, on the 68k and 4853117395SkanSPARC, setting the condition code directly from an add or subtract 485490075Sobrieninstruction does not clear the overflow bit the way that a test 485590075Sobrieninstruction does, so a different branch instruction must be used for 485690075Sobriensome conditional branches. For machines that use @code{(cc0)}, the set 485790075Sobrienand use of the condition code must be adjacent (separated only by 485890075Sobrien@code{note} insns) allowing flags in @code{cc_status} to be used. 485990075Sobrien(@xref{Condition Code}.) Also, the comparison and branch insns can be 486090075Sobrienlocated from each other by using the functions @code{prev_cc0_setter} 486190075Sobrienand @code{next_cc0_user}. 486290075Sobrien 486390075SobrienHowever, this is not true on machines that do not use @code{(cc0)}. On 486490075Sobrienthose machines, no assumptions can be made about the adjacency of the 486590075Sobriencompare and branch insns and the above methods cannot be used. Instead, 486690075Sobrienwe use the machine mode of the condition code register to record 486790075Sobriendifferent formats of the condition code register. 486890075Sobrien 486990075SobrienRegisters used to store the condition code value should have a mode that 487090075Sobrienis in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If 487190075Sobrienadditional modes are required (as for the add example mentioned above in 4872169689Skanthe SPARC), define them in @file{@var{machine}-modes.def} 4873169689Skan(@pxref{Condition Code}). Also define @code{SELECT_CC_MODE} to choose 4874169689Skana mode given an operand of a compare. 487590075Sobrien 487690075SobrienIf it is known during RTL generation that a different mode will be 487790075Sobrienrequired (for example, if the machine has separate compare instructions 487890075Sobrienfor signed and unsigned quantities, like most IBM processors), they can 487990075Sobrienbe specified at that time. 488090075Sobrien 488190075SobrienIf the cases that require different modes would be made by instruction 488290075Sobriencombination, the macro @code{SELECT_CC_MODE} determines which machine 488390075Sobrienmode should be used for the comparison result. The patterns should be 4884117395Skanwritten using that mode. To support the case of the add on the SPARC 488590075Sobriendiscussed above, we have the pattern 488690075Sobrien 488790075Sobrien@smallexample 488890075Sobrien(define_insn "" 488990075Sobrien [(set (reg:CC_NOOV 0) 489090075Sobrien (compare:CC_NOOV 489190075Sobrien (plus:SI (match_operand:SI 0 "register_operand" "%r") 489290075Sobrien (match_operand:SI 1 "arith_operand" "rI")) 489390075Sobrien (const_int 0)))] 489490075Sobrien "" 489590075Sobrien "@dots{}") 489690075Sobrien@end smallexample 489790075Sobrien 4898117395SkanThe @code{SELECT_CC_MODE} macro on the SPARC returns @code{CC_NOOVmode} 489990075Sobrienfor comparisons whose argument is a @code{plus}. 490090075Sobrien 4901132718Skan@end ifset 4902132718Skan@ifset INTERNALS 490390075Sobrien@node Looping Patterns 490490075Sobrien@section Defining Looping Instruction Patterns 490590075Sobrien@cindex looping instruction patterns 490690075Sobrien@cindex defining looping instruction patterns 490790075Sobrien 4908117395SkanSome machines have special jump instructions that can be utilized to 490990075Sobrienmake loops more efficient. A common example is the 68000 @samp{dbra} 491090075Sobrieninstruction which performs a decrement of a register and a branch if the 491190075Sobrienresult was greater than zero. Other machines, in particular digital 491290075Sobriensignal processors (DSPs), have special block repeat instructions to 491390075Sobrienprovide low-overhead loop support. For example, the TI TMS320C3x/C4x 491490075SobrienDSPs have a block repeat instruction that loads special registers to 491590075Sobrienmark the top and end of a loop and to count the number of loop 491690075Sobrieniterations. This avoids the need for fetching and executing a 491790075Sobrien@samp{dbra}-like instruction and avoids pipeline stalls associated with 491890075Sobrienthe jump. 491990075Sobrien 492090075SobrienGCC has three special named patterns to support low overhead looping. 492190075SobrienThey are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin}, 492290075Sobrienand @samp{doloop_end}. The first pattern, 492390075Sobrien@samp{decrement_and_branch_until_zero}, is not emitted during RTL 492490075Sobriengeneration but may be emitted during the instruction combination phase. 492590075SobrienThis requires the assistance of the loop optimizer, using information 492690075Sobriencollected during strength reduction, to reverse a loop to count down to 492790075Sobrienzero. Some targets also require the loop optimizer to add a 492890075Sobrien@code{REG_NONNEG} note to indicate that the iteration count is always 492990075Sobrienpositive. This is needed if the target performs a signed loop 493090075Sobrientermination test. For example, the 68000 uses a pattern similar to the 493190075Sobrienfollowing for its @code{dbra} instruction: 493290075Sobrien 493390075Sobrien@smallexample 493490075Sobrien@group 493590075Sobrien(define_insn "decrement_and_branch_until_zero" 493690075Sobrien [(set (pc) 493790075Sobrien (if_then_else 493890075Sobrien (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am") 493990075Sobrien (const_int -1)) 494090075Sobrien (const_int 0)) 494190075Sobrien (label_ref (match_operand 1 "" "")) 494290075Sobrien (pc))) 494390075Sobrien (set (match_dup 0) 494490075Sobrien (plus:SI (match_dup 0) 494590075Sobrien (const_int -1)))] 494690075Sobrien "find_reg_note (insn, REG_NONNEG, 0)" 494790075Sobrien "@dots{}") 494890075Sobrien@end group 494990075Sobrien@end smallexample 495090075Sobrien 495190075SobrienNote that since the insn is both a jump insn and has an output, it must 495290075Sobriendeal with its own reloads, hence the `m' constraints. Also note that 495390075Sobriensince this insn is generated by the instruction combination phase 495490075Sobriencombining two sequential insns together into an implicit parallel insn, 495590075Sobrienthe iteration counter needs to be biased by the same amount as the 495690075Sobriendecrement operation, in this case @minus{}1. Note that the following similar 495790075Sobrienpattern will not be matched by the combiner. 495890075Sobrien 495990075Sobrien@smallexample 496090075Sobrien@group 496190075Sobrien(define_insn "decrement_and_branch_until_zero" 496290075Sobrien [(set (pc) 496390075Sobrien (if_then_else 496490075Sobrien (ge (match_operand:SI 0 "general_operand" "+d*am") 496590075Sobrien (const_int 1)) 496690075Sobrien (label_ref (match_operand 1 "" "")) 496790075Sobrien (pc))) 496890075Sobrien (set (match_dup 0) 496990075Sobrien (plus:SI (match_dup 0) 497090075Sobrien (const_int -1)))] 497190075Sobrien "find_reg_note (insn, REG_NONNEG, 0)" 497290075Sobrien "@dots{}") 497390075Sobrien@end group 497490075Sobrien@end smallexample 497590075Sobrien 497690075SobrienThe other two special looping patterns, @samp{doloop_begin} and 497790075Sobrien@samp{doloop_end}, are emitted by the loop optimizer for certain 497890075Sobrienwell-behaved loops with a finite number of loop iterations using 497990075Sobrieninformation collected during strength reduction. 498090075Sobrien 498190075SobrienThe @samp{doloop_end} pattern describes the actual looping instruction 498290075Sobrien(or the implicit looping operation) and the @samp{doloop_begin} pattern 498390075Sobrienis an optional companion pattern that can be used for initialization 498490075Sobrienneeded for some low-overhead looping instructions. 498590075Sobrien 498690075SobrienNote that some machines require the actual looping instruction to be 498790075Sobrienemitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting 498890075Sobrienthe true RTL for a looping instruction at the top of the loop can cause 498990075Sobrienproblems with flow analysis. So instead, a dummy @code{doloop} insn is 499090075Sobrienemitted at the end of the loop. The machine dependent reorg pass checks 499190075Sobrienfor the presence of this @code{doloop} insn and then searches back to 499290075Sobrienthe top of the loop, where it inserts the true looping insn (provided 499390075Sobrienthere are no instructions in the loop which would cause problems). Any 499490075Sobrienadditional labels can be emitted at this point. In addition, if the 499590075Sobriendesired special iteration counter register was not allocated, this 499690075Sobrienmachine dependent reorg pass could emit a traditional compare and jump 499790075Sobrieninstruction pair. 499890075Sobrien 499990075SobrienThe essential difference between the 500090075Sobrien@samp{decrement_and_branch_until_zero} and the @samp{doloop_end} 500190075Sobrienpatterns is that the loop optimizer allocates an additional pseudo 500290075Sobrienregister for the latter as an iteration counter. This pseudo register 500390075Sobriencannot be used within the loop (i.e., general induction variables cannot 500490075Sobrienbe derived from it), however, in many cases the loop induction variable 500590075Sobrienmay become redundant and removed by the flow pass. 500690075Sobrien 500790075Sobrien 5008132718Skan@end ifset 5009132718Skan@ifset INTERNALS 501090075Sobrien@node Insn Canonicalizations 501190075Sobrien@section Canonicalization of Instructions 501290075Sobrien@cindex canonicalization of instructions 501390075Sobrien@cindex insn canonicalization 501490075Sobrien 501590075SobrienThere are often cases where multiple RTL expressions could represent an 501690075Sobrienoperation performed by a single machine instruction. This situation is 501790075Sobrienmost commonly encountered with logical, branch, and multiply-accumulate 501890075Sobrieninstructions. In such cases, the compiler attempts to convert these 501990075Sobrienmultiple RTL expressions into a single canonical form to reduce the 502090075Sobriennumber of insn patterns required. 502190075Sobrien 502290075SobrienIn addition to algebraic simplifications, following canonicalizations 502390075Sobrienare performed: 502490075Sobrien 502590075Sobrien@itemize @bullet 502690075Sobrien@item 502790075SobrienFor commutative and comparison operators, a constant is always made the 502890075Sobriensecond operand. If a machine only supports a constant as the second 502990075Sobrienoperand, only patterns that match a constant in the second operand need 503090075Sobrienbe supplied. 503190075Sobrien 5032169689Skan@item 5033169689SkanFor associative operators, a sequence of operators will always chain 5034169689Skanto the left; for instance, only the left operand of an integer @code{plus} 5035169689Skancan itself be a @code{plus}. @code{and}, @code{ior}, @code{xor}, 5036169689Skan@code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and 5037169689Skan@code{umax} are associative when applied to integers, and sometimes to 5038169689Skanfloating-point. 5039169689Skan 5040169689Skan@item 504190075Sobrien@cindex @code{neg}, canonicalization of 504290075Sobrien@cindex @code{not}, canonicalization of 504390075Sobrien@cindex @code{mult}, canonicalization of 504490075Sobrien@cindex @code{plus}, canonicalization of 504590075Sobrien@cindex @code{minus}, canonicalization of 504690075SobrienFor these operators, if only one operand is a @code{neg}, @code{not}, 504790075Sobrien@code{mult}, @code{plus}, or @code{minus} expression, it will be the 504890075Sobrienfirst operand. 504990075Sobrien 5050117395Skan@item 5051117395SkanIn combinations of @code{neg}, @code{mult}, @code{plus}, and 5052117395Skan@code{minus}, the @code{neg} operations (if any) will be moved inside 5053132718Skanthe operations as far as possible. For instance, 5054117395Skan@code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but 5055117395Skan@code{(plus (mult (neg A) B) C)} is canonicalized as 5056117395Skan@code{(minus A (mult B C))}. 5057117395Skan 505890075Sobrien@cindex @code{compare}, canonicalization of 505990075Sobrien@item 506090075SobrienFor the @code{compare} operator, a constant is always the second operand 506190075Sobrienon machines where @code{cc0} is used (@pxref{Jump Patterns}). On other 506290075Sobrienmachines, there are rare cases where the compiler might want to construct 506390075Sobriena @code{compare} with a constant as the first operand. However, these 506490075Sobriencases are not common enough for it to be worthwhile to provide a pattern 506590075Sobrienmatching a constant as the first operand unless the machine actually has 506690075Sobriensuch an instruction. 506790075Sobrien 506890075SobrienAn operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or 506990075Sobrien@code{minus} is made the first operand under the same conditions as 507090075Sobrienabove. 507190075Sobrien 507290075Sobrien@item 507390075Sobrien@code{(minus @var{x} (const_int @var{n}))} is converted to 507490075Sobrien@code{(plus @var{x} (const_int @var{-n}))}. 507590075Sobrien 507690075Sobrien@item 507790075SobrienWithin address computations (i.e., inside @code{mem}), a left shift is 507890075Sobrienconverted into the appropriate multiplication by a power of two. 507990075Sobrien 508090075Sobrien@cindex @code{ior}, canonicalization of 508190075Sobrien@cindex @code{and}, canonicalization of 508290075Sobrien@cindex De Morgan's law 508390075Sobrien@item 5084169689SkanDe Morgan's Law is used to move bitwise negation inside a bitwise 508590075Sobrienlogical-and or logical-or operation. If this results in only one 508690075Sobrienoperand being a @code{not} expression, it will be the first one. 508790075Sobrien 508890075SobrienA machine that has an instruction that performs a bitwise logical-and of one 508990075Sobrienoperand with the bitwise negation of the other should specify the pattern 509090075Sobrienfor that instruction as 509190075Sobrien 5092132718Skan@smallexample 509390075Sobrien(define_insn "" 509490075Sobrien [(set (match_operand:@var{m} 0 @dots{}) 509590075Sobrien (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) 509690075Sobrien (match_operand:@var{m} 2 @dots{})))] 509790075Sobrien "@dots{}" 509890075Sobrien "@dots{}") 5099132718Skan@end smallexample 510090075Sobrien 510190075Sobrien@noindent 510290075SobrienSimilarly, a pattern for a ``NAND'' instruction should be written 510390075Sobrien 5104132718Skan@smallexample 510590075Sobrien(define_insn "" 510690075Sobrien [(set (match_operand:@var{m} 0 @dots{}) 510790075Sobrien (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) 510890075Sobrien (not:@var{m} (match_operand:@var{m} 2 @dots{}))))] 510990075Sobrien "@dots{}" 511090075Sobrien "@dots{}") 5111132718Skan@end smallexample 511290075Sobrien 511390075SobrienIn both cases, it is not necessary to include patterns for the many 511490075Sobrienlogically equivalent RTL expressions. 511590075Sobrien 511690075Sobrien@cindex @code{xor}, canonicalization of 511790075Sobrien@item 511890075SobrienThe only possible RTL expressions involving both bitwise exclusive-or 511990075Sobrienand bitwise negation are @code{(xor:@var{m} @var{x} @var{y})} 512090075Sobrienand @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}. 512190075Sobrien 512290075Sobrien@item 512390075SobrienThe sum of three items, one of which is a constant, will only appear in 512490075Sobrienthe form 512590075Sobrien 5126132718Skan@smallexample 512790075Sobrien(plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant}) 5128132718Skan@end smallexample 512990075Sobrien 513090075Sobrien@item 513190075SobrienOn machines that do not use @code{cc0}, 513290075Sobrien@code{(compare @var{x} (const_int 0))} will be converted to 513390075Sobrien@var{x}. 513490075Sobrien 513590075Sobrien@cindex @code{zero_extract}, canonicalization of 513690075Sobrien@cindex @code{sign_extract}, canonicalization of 513790075Sobrien@item 513890075SobrienEquality comparisons of a group of bits (usually a single bit) with zero 513990075Sobrienwill be written using @code{zero_extract} rather than the equivalent 514090075Sobrien@code{and} or @code{sign_extract} operations. 514190075Sobrien 514290075Sobrien@end itemize 514390075Sobrien 5144169689SkanFurther canonicalization rules are defined in the function 5145169689Skan@code{commutative_operand_precedence} in @file{gcc/rtlanal.c}. 5146169689Skan 5147132718Skan@end ifset 5148132718Skan@ifset INTERNALS 514990075Sobrien@node Expander Definitions 515090075Sobrien@section Defining RTL Sequences for Code Generation 515190075Sobrien@cindex expander definitions 515290075Sobrien@cindex code generation RTL sequences 515390075Sobrien@cindex defining RTL sequences for code generation 515490075Sobrien 515590075SobrienOn some target machines, some standard pattern names for RTL generation 515690075Sobriencannot be handled with single insn, but a sequence of RTL insns can 515790075Sobrienrepresent them. For these target machines, you can write a 515890075Sobrien@code{define_expand} to specify how to generate the sequence of RTL@. 515990075Sobrien 516090075Sobrien@findex define_expand 516190075SobrienA @code{define_expand} is an RTL expression that looks almost like a 516290075Sobrien@code{define_insn}; but, unlike the latter, a @code{define_expand} is used 516390075Sobrienonly for RTL generation and it can produce more than one RTL insn. 516490075Sobrien 516590075SobrienA @code{define_expand} RTX has four operands: 516690075Sobrien 516790075Sobrien@itemize @bullet 516890075Sobrien@item 516990075SobrienThe name. Each @code{define_expand} must have a name, since the only 517090075Sobrienuse for it is to refer to it by name. 517190075Sobrien 517290075Sobrien@item 517390075SobrienThe RTL template. This is a vector of RTL expressions representing 517490075Sobriena sequence of separate instructions. Unlike @code{define_insn}, there 517590075Sobrienis no implicit surrounding @code{PARALLEL}. 517690075Sobrien 517790075Sobrien@item 517890075SobrienThe condition, a string containing a C expression. This expression is 517990075Sobrienused to express how the availability of this pattern depends on 518090075Sobriensubclasses of target machine, selected by command-line options when GCC 518190075Sobrienis run. This is just like the condition of a @code{define_insn} that 518290075Sobrienhas a standard name. Therefore, the condition (if present) may not 518390075Sobriendepend on the data in the insn being matched, but only the 518490075Sobrientarget-machine-type flags. The compiler needs to test these conditions 518590075Sobrienduring initialization in order to learn exactly which named instructions 518690075Sobrienare available in a particular run. 518790075Sobrien 518890075Sobrien@item 518990075SobrienThe preparation statements, a string containing zero or more C 519090075Sobrienstatements which are to be executed before RTL code is generated from 519190075Sobrienthe RTL template. 519290075Sobrien 519390075SobrienUsually these statements prepare temporary registers for use as 519490075Sobrieninternal operands in the RTL template, but they can also generate RTL 519590075Sobrieninsns directly by calling routines such as @code{emit_insn}, etc. 519690075SobrienAny such insns precede the ones that come from the RTL template. 519790075Sobrien@end itemize 519890075Sobrien 519990075SobrienEvery RTL insn emitted by a @code{define_expand} must match some 520090075Sobrien@code{define_insn} in the machine description. Otherwise, the compiler 520190075Sobrienwill crash when trying to generate code for the insn or trying to optimize 520290075Sobrienit. 520390075Sobrien 520490075SobrienThe RTL template, in addition to controlling generation of RTL insns, 520590075Sobrienalso describes the operands that need to be specified when this pattern 520690075Sobrienis used. In particular, it gives a predicate for each operand. 520790075Sobrien 520890075SobrienA true operand, which needs to be specified in order to generate RTL from 520990075Sobrienthe pattern, should be described with a @code{match_operand} in its first 521090075Sobrienoccurrence in the RTL template. This enters information on the operand's 521190075Sobrienpredicate into the tables that record such things. GCC uses the 521290075Sobrieninformation to preload the operand into a register if that is required for 521390075Sobrienvalid RTL code. If the operand is referred to more than once, subsequent 521490075Sobrienreferences should use @code{match_dup}. 521590075Sobrien 521690075SobrienThe RTL template may also refer to internal ``operands'' which are 521790075Sobrientemporary registers or labels used only within the sequence made by the 521890075Sobrien@code{define_expand}. Internal operands are substituted into the RTL 521990075Sobrientemplate with @code{match_dup}, never with @code{match_operand}. The 522090075Sobrienvalues of the internal operands are not passed in as arguments by the 522190075Sobriencompiler when it requests use of this pattern. Instead, they are computed 522290075Sobrienwithin the pattern, in the preparation statements. These statements 522390075Sobriencompute the values and store them into the appropriate elements of 522490075Sobrien@code{operands} so that @code{match_dup} can find them. 522590075Sobrien 522690075SobrienThere are two special macros defined for use in the preparation statements: 522790075Sobrien@code{DONE} and @code{FAIL}. Use them with a following semicolon, 522890075Sobrienas a statement. 522990075Sobrien 523090075Sobrien@table @code 523190075Sobrien 523290075Sobrien@findex DONE 523390075Sobrien@item DONE 523490075SobrienUse the @code{DONE} macro to end RTL generation for the pattern. The 523590075Sobrienonly RTL insns resulting from the pattern on this occasion will be 523690075Sobrienthose already emitted by explicit calls to @code{emit_insn} within the 523790075Sobrienpreparation statements; the RTL template will not be generated. 523890075Sobrien 523990075Sobrien@findex FAIL 524090075Sobrien@item FAIL 524190075SobrienMake the pattern fail on this occasion. When a pattern fails, it means 524290075Sobrienthat the pattern was not truly available. The calling routines in the 524390075Sobriencompiler will try other strategies for code generation using other patterns. 524490075Sobrien 524590075SobrienFailure is currently supported only for binary (addition, multiplication, 524690075Sobrienshifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv}) 524790075Sobrienoperations. 524890075Sobrien@end table 524990075Sobrien 525090075SobrienIf the preparation falls through (invokes neither @code{DONE} nor 525190075Sobrien@code{FAIL}), then the @code{define_expand} acts like a 525290075Sobrien@code{define_insn} in that the RTL template is used to generate the 525390075Sobrieninsn. 525490075Sobrien 525590075SobrienThe RTL template is not used for matching, only for generating the 525690075Sobrieninitial insn list. If the preparation statement always invokes 525790075Sobrien@code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple 525890075Sobrienlist of operands, such as this example: 525990075Sobrien 526090075Sobrien@smallexample 526190075Sobrien@group 526290075Sobrien(define_expand "addsi3" 526390075Sobrien [(match_operand:SI 0 "register_operand" "") 526490075Sobrien (match_operand:SI 1 "register_operand" "") 526590075Sobrien (match_operand:SI 2 "register_operand" "")] 526690075Sobrien@end group 526790075Sobrien@group 526890075Sobrien "" 526990075Sobrien " 527090075Sobrien@{ 527190075Sobrien handle_add (operands[0], operands[1], operands[2]); 527290075Sobrien DONE; 527390075Sobrien@}") 527490075Sobrien@end group 527590075Sobrien@end smallexample 527690075Sobrien 527790075SobrienHere is an example, the definition of left-shift for the SPUR chip: 527890075Sobrien 527990075Sobrien@smallexample 528090075Sobrien@group 528190075Sobrien(define_expand "ashlsi3" 528290075Sobrien [(set (match_operand:SI 0 "register_operand" "") 528390075Sobrien (ashift:SI 528490075Sobrien@end group 528590075Sobrien@group 528690075Sobrien (match_operand:SI 1 "register_operand" "") 528790075Sobrien (match_operand:SI 2 "nonmemory_operand" "")))] 528890075Sobrien "" 528990075Sobrien " 529090075Sobrien@end group 529190075Sobrien@end smallexample 529290075Sobrien 529390075Sobrien@smallexample 529490075Sobrien@group 529590075Sobrien@{ 529690075Sobrien if (GET_CODE (operands[2]) != CONST_INT 529790075Sobrien || (unsigned) INTVAL (operands[2]) > 3) 529890075Sobrien FAIL; 529990075Sobrien@}") 530090075Sobrien@end group 530190075Sobrien@end smallexample 530290075Sobrien 530390075Sobrien@noindent 530490075SobrienThis example uses @code{define_expand} so that it can generate an RTL insn 530590075Sobrienfor shifting when the shift-count is in the supported range of 0 to 3 but 530690075Sobrienfail in other cases where machine insns aren't available. When it fails, 530790075Sobrienthe compiler tries another strategy using different patterns (such as, a 530890075Sobrienlibrary call). 530990075Sobrien 531090075SobrienIf the compiler were able to handle nontrivial condition-strings in 531190075Sobrienpatterns with names, then it would be possible to use a 531290075Sobrien@code{define_insn} in that case. Here is another case (zero-extension 531390075Sobrienon the 68000) which makes more use of the power of @code{define_expand}: 531490075Sobrien 531590075Sobrien@smallexample 531690075Sobrien(define_expand "zero_extendhisi2" 531790075Sobrien [(set (match_operand:SI 0 "general_operand" "") 531890075Sobrien (const_int 0)) 531990075Sobrien (set (strict_low_part 532090075Sobrien (subreg:HI 532190075Sobrien (match_dup 0) 532290075Sobrien 0)) 532390075Sobrien (match_operand:HI 1 "general_operand" ""))] 532490075Sobrien "" 532590075Sobrien "operands[1] = make_safe_from (operands[1], operands[0]);") 532690075Sobrien@end smallexample 532790075Sobrien 532890075Sobrien@noindent 532990075Sobrien@findex make_safe_from 533090075SobrienHere two RTL insns are generated, one to clear the entire output operand 533190075Sobrienand the other to copy the input operand into its low half. This sequence 533290075Sobrienis incorrect if the input operand refers to [the old value of] the output 533390075Sobrienoperand, so the preparation statement makes sure this isn't so. The 533490075Sobrienfunction @code{make_safe_from} copies the @code{operands[1]} into a 533590075Sobrientemporary register if it refers to @code{operands[0]}. It does this 533690075Sobrienby emitting another RTL insn. 533790075Sobrien 533890075SobrienFinally, a third example shows the use of an internal operand. 533990075SobrienZero-extension on the SPUR chip is done by @code{and}-ing the result 534090075Sobrienagainst a halfword mask. But this mask cannot be represented by a 534190075Sobrien@code{const_int} because the constant value is too large to be legitimate 534290075Sobrienon this machine. So it must be copied into a register with 534390075Sobrien@code{force_reg} and then the register used in the @code{and}. 534490075Sobrien 534590075Sobrien@smallexample 534690075Sobrien(define_expand "zero_extendhisi2" 534790075Sobrien [(set (match_operand:SI 0 "register_operand" "") 534890075Sobrien (and:SI (subreg:SI 534990075Sobrien (match_operand:HI 1 "register_operand" "") 535090075Sobrien 0) 535190075Sobrien (match_dup 2)))] 535290075Sobrien "" 535390075Sobrien "operands[2] 535490075Sobrien = force_reg (SImode, GEN_INT (65535)); ") 535590075Sobrien@end smallexample 535690075Sobrien 5357169689Skan@emph{Note:} If the @code{define_expand} is used to serve a 535890075Sobrienstandard binary or unary arithmetic operation or a bit-field operation, 535990075Sobrienthen the last insn it generates must not be a @code{code_label}, 536090075Sobrien@code{barrier} or @code{note}. It must be an @code{insn}, 536190075Sobrien@code{jump_insn} or @code{call_insn}. If you don't need a real insn 536290075Sobrienat the end, emit an insn to copy the result of the operation into 536390075Sobrienitself. Such an insn will generate no code, but it can avoid problems 536490075Sobrienin the compiler. 536590075Sobrien 5366132718Skan@end ifset 5367132718Skan@ifset INTERNALS 536890075Sobrien@node Insn Splitting 536990075Sobrien@section Defining How to Split Instructions 537090075Sobrien@cindex insn splitting 537190075Sobrien@cindex instruction splitting 537290075Sobrien@cindex splitting instructions 537390075Sobrien 5374117395SkanThere are two cases where you should specify how to split a pattern 5375117395Skaninto multiple insns. On machines that have instructions requiring 5376117395Skandelay slots (@pxref{Delay Slots}) or that have instructions whose 5377117395Skanoutput is not available for multiple cycles (@pxref{Processor pipeline 5378117395Skandescription}), the compiler phases that optimize these cases need to 5379117395Skanbe able to move insns into one-instruction delay slots. However, some 5380117395Skaninsns may generate more than one machine instruction. These insns 5381117395Skancannot be placed into a delay slot. 538290075Sobrien 538390075SobrienOften you can rewrite the single insn as a list of individual insns, 538490075Sobrieneach corresponding to one machine instruction. The disadvantage of 538590075Sobriendoing so is that it will cause the compilation to be slower and require 538690075Sobrienmore space. If the resulting insns are too complex, it may also 538790075Sobriensuppress some optimizations. The compiler splits the insn if there is a 538890075Sobrienreason to believe that it might improve instruction or delay slot 538990075Sobrienscheduling. 539090075Sobrien 539190075SobrienThe insn combiner phase also splits putative insns. If three insns are 539290075Sobrienmerged into one insn with a complex expression that cannot be matched by 539390075Sobriensome @code{define_insn} pattern, the combiner phase attempts to split 539490075Sobrienthe complex pattern into two insns that are recognized. Usually it can 539590075Sobrienbreak the complex pattern into two patterns by splitting out some 539690075Sobriensubexpression. However, in some other cases, such as performing an 539790075Sobrienaddition of a large constant in two insns on a RISC machine, the way to 539890075Sobriensplit the addition into two insns is machine-dependent. 539990075Sobrien 540090075Sobrien@findex define_split 540190075SobrienThe @code{define_split} definition tells the compiler how to split a 540290075Sobriencomplex insn into several simpler insns. It looks like this: 540390075Sobrien 540490075Sobrien@smallexample 540590075Sobrien(define_split 540690075Sobrien [@var{insn-pattern}] 540790075Sobrien "@var{condition}" 540890075Sobrien [@var{new-insn-pattern-1} 540990075Sobrien @var{new-insn-pattern-2} 541090075Sobrien @dots{}] 541190075Sobrien "@var{preparation-statements}") 541290075Sobrien@end smallexample 541390075Sobrien 541490075Sobrien@var{insn-pattern} is a pattern that needs to be split and 541590075Sobrien@var{condition} is the final condition to be tested, as in a 541690075Sobrien@code{define_insn}. When an insn matching @var{insn-pattern} and 541790075Sobriensatisfying @var{condition} is found, it is replaced in the insn list 541890075Sobrienwith the insns given by @var{new-insn-pattern-1}, 541990075Sobrien@var{new-insn-pattern-2}, etc. 542090075Sobrien 542190075SobrienThe @var{preparation-statements} are similar to those statements that 542290075Sobrienare specified for @code{define_expand} (@pxref{Expander Definitions}) 542390075Sobrienand are executed before the new RTL is generated to prepare for the 542490075Sobriengenerated code or emit some insns whose pattern is not fixed. Unlike 542590075Sobrienthose in @code{define_expand}, however, these statements must not 542690075Sobriengenerate any new pseudo-registers. Once reload has completed, they also 542790075Sobrienmust not allocate any space in the stack frame. 542890075Sobrien 542990075SobrienPatterns are matched against @var{insn-pattern} in two different 543090075Sobriencircumstances. If an insn needs to be split for delay slot scheduling 543190075Sobrienor insn scheduling, the insn is already known to be valid, which means 543290075Sobrienthat it must have been matched by some @code{define_insn} and, if 543390075Sobrien@code{reload_completed} is nonzero, is known to satisfy the constraints 543490075Sobrienof that @code{define_insn}. In that case, the new insn patterns must 543590075Sobrienalso be insns that are matched by some @code{define_insn} and, if 543690075Sobrien@code{reload_completed} is nonzero, must also satisfy the constraints 543790075Sobrienof those definitions. 543890075Sobrien 543990075SobrienAs an example of this usage of @code{define_split}, consider the following 544090075Sobrienexample from @file{a29k.md}, which splits a @code{sign_extend} from 544190075Sobrien@code{HImode} to @code{SImode} into a pair of shift insns: 544290075Sobrien 544390075Sobrien@smallexample 544490075Sobrien(define_split 544590075Sobrien [(set (match_operand:SI 0 "gen_reg_operand" "") 544690075Sobrien (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] 544790075Sobrien "" 544890075Sobrien [(set (match_dup 0) 544990075Sobrien (ashift:SI (match_dup 1) 545090075Sobrien (const_int 16))) 545190075Sobrien (set (match_dup 0) 545290075Sobrien (ashiftrt:SI (match_dup 0) 545390075Sobrien (const_int 16)))] 545490075Sobrien " 545590075Sobrien@{ operands[1] = gen_lowpart (SImode, operands[1]); @}") 545690075Sobrien@end smallexample 545790075Sobrien 545890075SobrienWhen the combiner phase tries to split an insn pattern, it is always the 545990075Sobriencase that the pattern is @emph{not} matched by any @code{define_insn}. 546090075SobrienThe combiner pass first tries to split a single @code{set} expression 546190075Sobrienand then the same @code{set} expression inside a @code{parallel}, but 546290075Sobrienfollowed by a @code{clobber} of a pseudo-reg to use as a scratch 546390075Sobrienregister. In these cases, the combiner expects exactly two new insn 546490075Sobrienpatterns to be generated. It will verify that these patterns match some 546590075Sobrien@code{define_insn} definitions, so you need not do this test in the 546690075Sobrien@code{define_split} (of course, there is no point in writing a 546790075Sobrien@code{define_split} that will never produce insns that match). 546890075Sobrien 546990075SobrienHere is an example of this use of @code{define_split}, taken from 547090075Sobrien@file{rs6000.md}: 547190075Sobrien 547290075Sobrien@smallexample 547390075Sobrien(define_split 547490075Sobrien [(set (match_operand:SI 0 "gen_reg_operand" "") 547590075Sobrien (plus:SI (match_operand:SI 1 "gen_reg_operand" "") 547690075Sobrien (match_operand:SI 2 "non_add_cint_operand" "")))] 547790075Sobrien "" 547890075Sobrien [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 547990075Sobrien (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 548090075Sobrien" 548190075Sobrien@{ 548290075Sobrien int low = INTVAL (operands[2]) & 0xffff; 548390075Sobrien int high = (unsigned) INTVAL (operands[2]) >> 16; 548490075Sobrien 548590075Sobrien if (low & 0x8000) 548690075Sobrien high++, low |= 0xffff0000; 548790075Sobrien 548890075Sobrien operands[3] = GEN_INT (high << 16); 548990075Sobrien operands[4] = GEN_INT (low); 549090075Sobrien@}") 549190075Sobrien@end smallexample 549290075Sobrien 549390075SobrienHere the predicate @code{non_add_cint_operand} matches any 549490075Sobrien@code{const_int} that is @emph{not} a valid operand of a single add 549590075Sobrieninsn. The add with the smaller displacement is written so that it 549690075Sobriencan be substituted into the address of a subsequent operation. 549790075Sobrien 549890075SobrienAn example that uses a scratch register, from the same file, generates 549990075Sobrienan equality comparison of a register and a large constant: 550090075Sobrien 550190075Sobrien@smallexample 550290075Sobrien(define_split 550390075Sobrien [(set (match_operand:CC 0 "cc_reg_operand" "") 550490075Sobrien (compare:CC (match_operand:SI 1 "gen_reg_operand" "") 550590075Sobrien (match_operand:SI 2 "non_short_cint_operand" ""))) 550690075Sobrien (clobber (match_operand:SI 3 "gen_reg_operand" ""))] 550790075Sobrien "find_single_use (operands[0], insn, 0) 550890075Sobrien && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ 550990075Sobrien || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" 551090075Sobrien [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) 551190075Sobrien (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] 551290075Sobrien " 551390075Sobrien@{ 5514169689Skan /* @r{Get the constant we are comparing against, C, and see what it 551590075Sobrien looks like sign-extended to 16 bits. Then see what constant 5516169689Skan could be XOR'ed with C to get the sign-extended value.} */ 551790075Sobrien 551890075Sobrien int c = INTVAL (operands[2]); 551990075Sobrien int sextc = (c << 16) >> 16; 552090075Sobrien int xorv = c ^ sextc; 552190075Sobrien 552290075Sobrien operands[4] = GEN_INT (xorv); 552390075Sobrien operands[5] = GEN_INT (sextc); 552490075Sobrien@}") 552590075Sobrien@end smallexample 552690075Sobrien 552790075SobrienTo avoid confusion, don't write a single @code{define_split} that 552890075Sobrienaccepts some insns that match some @code{define_insn} as well as some 552990075Sobrieninsns that don't. Instead, write two separate @code{define_split} 553090075Sobriendefinitions, one for the insns that are valid and one for the insns that 553190075Sobrienare not valid. 553290075Sobrien 553390075SobrienThe splitter is allowed to split jump instructions into sequence of 553490075Sobrienjumps or create new jumps in while splitting non-jump instructions. As 553590075Sobrienthe central flowgraph and branch prediction information needs to be updated, 553696263Sobrienseveral restriction apply. 553790075Sobrien 553890075SobrienSplitting of jump instruction into sequence that over by another jump 553990075Sobrieninstruction is always valid, as compiler expect identical behavior of new 554090075Sobrienjump. When new sequence contains multiple jump instructions or new labels, 554190075Sobrienmore assistance is needed. Splitter is required to create only unconditional 554290075Sobrienjumps, or simple conditional jump instructions. Additionally it must attach a 5543117395Skan@code{REG_BR_PROB} note to each conditional jump. A global variable 5544169689Skan@code{split_branch_probability} holds the probability of the original branch in case 554590075Sobrienit was an simple conditional jump, @minus{}1 otherwise. To simplify 5546169689Skanrecomputing of edge frequencies, the new sequence is required to have only 554790075Sobrienforward jumps to the newly created labels. 554890075Sobrien 554990075Sobrien@findex define_insn_and_split 555090075SobrienFor the common case where the pattern of a define_split exactly matches the 555190075Sobrienpattern of a define_insn, use @code{define_insn_and_split}. It looks like 555290075Sobrienthis: 555390075Sobrien 555490075Sobrien@smallexample 555590075Sobrien(define_insn_and_split 555690075Sobrien [@var{insn-pattern}] 555790075Sobrien "@var{condition}" 555890075Sobrien "@var{output-template}" 555990075Sobrien "@var{split-condition}" 556090075Sobrien [@var{new-insn-pattern-1} 556190075Sobrien @var{new-insn-pattern-2} 556290075Sobrien @dots{}] 556390075Sobrien "@var{preparation-statements}" 556490075Sobrien [@var{insn-attributes}]) 556590075Sobrien 556690075Sobrien@end smallexample 556790075Sobrien 556890075Sobrien@var{insn-pattern}, @var{condition}, @var{output-template}, and 556990075Sobrien@var{insn-attributes} are used as in @code{define_insn}. The 557090075Sobrien@var{new-insn-pattern} vector and the @var{preparation-statements} are used as 557190075Sobrienin a @code{define_split}. The @var{split-condition} is also used as in 557290075Sobrien@code{define_split}, with the additional behavior that if the condition starts 557390075Sobrienwith @samp{&&}, the condition used for the split will be the constructed as a 557490075Sobrienlogical ``and'' of the split condition with the insn condition. For example, 557590075Sobrienfrom i386.md: 557690075Sobrien 557790075Sobrien@smallexample 557890075Sobrien(define_insn_and_split "zero_extendhisi2_and" 557990075Sobrien [(set (match_operand:SI 0 "register_operand" "=r") 558090075Sobrien (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))) 558190075Sobrien (clobber (reg:CC 17))] 558290075Sobrien "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" 558390075Sobrien "#" 558490075Sobrien "&& reload_completed" 558596263Sobrien [(parallel [(set (match_dup 0) 558690075Sobrien (and:SI (match_dup 0) (const_int 65535))) 558790075Sobrien (clobber (reg:CC 17))])] 558890075Sobrien "" 558990075Sobrien [(set_attr "type" "alu1")]) 559090075Sobrien 559190075Sobrien@end smallexample 559290075Sobrien 559390075SobrienIn this case, the actual split condition will be 559490075Sobrien@samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}. 559590075Sobrien 559690075SobrienThe @code{define_insn_and_split} construction provides exactly the same 559790075Sobrienfunctionality as two separate @code{define_insn} and @code{define_split} 559890075Sobrienpatterns. It exists for compactness, and as a maintenance tool to prevent 559990075Sobrienhaving to ensure the two patterns' templates match. 560090075Sobrien 5601132718Skan@end ifset 5602132718Skan@ifset INTERNALS 560390075Sobrien@node Including Patterns 560490075Sobrien@section Including Patterns in Machine Descriptions. 560590075Sobrien@cindex insn includes 560690075Sobrien 560790075Sobrien@findex include 560890075SobrienThe @code{include} pattern tells the compiler tools where to 560990075Sobrienlook for patterns that are in files other than in the file 5610169689Skan@file{.md}. This is used only at build time and there is no preprocessing allowed. 561190075Sobrien 561290075SobrienIt looks like: 561390075Sobrien 561490075Sobrien@smallexample 561590075Sobrien 561690075Sobrien(include 561790075Sobrien @var{pathname}) 561890075Sobrien@end smallexample 561990075Sobrien 562090075SobrienFor example: 562190075Sobrien 562290075Sobrien@smallexample 562390075Sobrien 562496263Sobrien(include "filestuff") 562590075Sobrien 562690075Sobrien@end smallexample 562790075Sobrien 5628117395SkanWhere @var{pathname} is a string that specifies the location of the file, 5629169689Skanspecifies the include file to be in @file{gcc/config/target/filestuff}. The 563090075Sobriendirectory @file{gcc/config/target} is regarded as the default directory. 563190075Sobrien 563290075Sobrien 563396263SobrienMachine descriptions may be split up into smaller more manageable subsections 563496263Sobrienand placed into subdirectories. 563590075Sobrien 563690075SobrienBy specifying: 563790075Sobrien 563890075Sobrien@smallexample 563990075Sobrien 564096263Sobrien(include "BOGUS/filestuff") 564190075Sobrien 564290075Sobrien@end smallexample 564390075Sobrien 564490075Sobrienthe include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}. 564590075Sobrien 564690075SobrienSpecifying an absolute path for the include file such as; 564790075Sobrien@smallexample 564890075Sobrien 564996263Sobrien(include "/u2/BOGUS/filestuff") 565090075Sobrien 565190075Sobrien@end smallexample 565296263Sobrienis permitted but is not encouraged. 565390075Sobrien 565490075Sobrien@subsection RTL Generation Tool Options for Directory Search 565590075Sobrien@cindex directory options .md 565690075Sobrien@cindex options, directory search 565790075Sobrien@cindex search options 565890075Sobrien 565990075SobrienThe @option{-I@var{dir}} option specifies directories to search for machine descriptions. 566090075SobrienFor example: 566190075Sobrien 566290075Sobrien@smallexample 566390075Sobrien 566490075Sobriengenrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md 566590075Sobrien 566690075Sobrien@end smallexample 566790075Sobrien 566890075Sobrien 566990075SobrienAdd the directory @var{dir} to the head of the list of directories to be 567090075Sobriensearched for header files. This can be used to override a system machine definition 567190075Sobrienfile, substituting your own version, since these directories are 567290075Sobriensearched before the default machine description file directories. If you use more than 567390075Sobrienone @option{-I} option, the directories are scanned in left-to-right 567490075Sobrienorder; the standard default directory come after. 567590075Sobrien 567690075Sobrien 5677132718Skan@end ifset 5678132718Skan@ifset INTERNALS 567990075Sobrien@node Peephole Definitions 568090075Sobrien@section Machine-Specific Peephole Optimizers 568190075Sobrien@cindex peephole optimizer definitions 568290075Sobrien@cindex defining peephole optimizers 568390075Sobrien 568490075SobrienIn addition to instruction patterns the @file{md} file may contain 568590075Sobriendefinitions of machine-specific peephole optimizations. 568690075Sobrien 568790075SobrienThe combiner does not notice certain peephole optimizations when the data 568890075Sobrienflow in the program does not suggest that it should try them. For example, 568990075Sobriensometimes two consecutive insns related in purpose can be combined even 569090075Sobrienthough the second one does not appear to use a register computed in the 569190075Sobrienfirst one. A machine-specific peephole optimizer can detect such 569290075Sobrienopportunities. 569390075Sobrien 569490075SobrienThere are two forms of peephole definitions that may be used. The 569590075Sobrienoriginal @code{define_peephole} is run at assembly output time to 569690075Sobrienmatch insns and substitute assembly text. Use of @code{define_peephole} 569790075Sobrienis deprecated. 569890075Sobrien 569990075SobrienA newer @code{define_peephole2} matches insns and substitutes new 570090075Sobrieninsns. The @code{peephole2} pass is run after register allocation 570190075Sobrienbut before scheduling, which may result in much better code for 570290075Sobrientargets that do scheduling. 570390075Sobrien 570490075Sobrien@menu 570590075Sobrien* define_peephole:: RTL to Text Peephole Optimizers 570690075Sobrien* define_peephole2:: RTL to RTL Peephole Optimizers 570790075Sobrien@end menu 570890075Sobrien 5709132718Skan@end ifset 5710132718Skan@ifset INTERNALS 571190075Sobrien@node define_peephole 571290075Sobrien@subsection RTL to Text Peephole Optimizers 571390075Sobrien@findex define_peephole 571490075Sobrien 571590075Sobrien@need 1000 571690075SobrienA definition looks like this: 571790075Sobrien 571890075Sobrien@smallexample 571990075Sobrien(define_peephole 572090075Sobrien [@var{insn-pattern-1} 572190075Sobrien @var{insn-pattern-2} 572290075Sobrien @dots{}] 572390075Sobrien "@var{condition}" 572490075Sobrien "@var{template}" 572590075Sobrien "@var{optional-insn-attributes}") 572690075Sobrien@end smallexample 572790075Sobrien 572890075Sobrien@noindent 572990075SobrienThe last string operand may be omitted if you are not using any 573090075Sobrienmachine-specific information in this machine description. If present, 573190075Sobrienit must obey the same rules as in a @code{define_insn}. 573290075Sobrien 573390075SobrienIn this skeleton, @var{insn-pattern-1} and so on are patterns to match 573490075Sobrienconsecutive insns. The optimization applies to a sequence of insns when 573590075Sobrien@var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches 573690075Sobrienthe next, and so on. 573790075Sobrien 573890075SobrienEach of the insns matched by a peephole must also match a 573990075Sobrien@code{define_insn}. Peepholes are checked only at the last stage just 574090075Sobrienbefore code generation, and only optionally. Therefore, any insn which 574190075Sobrienwould match a peephole but no @code{define_insn} will cause a crash in code 574290075Sobriengeneration in an unoptimized compilation, or at various optimization 574390075Sobrienstages. 574490075Sobrien 574590075SobrienThe operands of the insns are matched with @code{match_operands}, 574690075Sobrien@code{match_operator}, and @code{match_dup}, as usual. What is not 574790075Sobrienusual is that the operand numbers apply to all the insn patterns in the 574890075Sobriendefinition. So, you can check for identical operands in two insns by 574990075Sobrienusing @code{match_operand} in one insn and @code{match_dup} in the 575090075Sobrienother. 575190075Sobrien 575290075SobrienThe operand constraints used in @code{match_operand} patterns do not have 575390075Sobrienany direct effect on the applicability of the peephole, but they will 575490075Sobrienbe validated afterward, so make sure your constraints are general enough 575590075Sobriento apply whenever the peephole matches. If the peephole matches 575690075Sobrienbut the constraints are not satisfied, the compiler will crash. 575790075Sobrien 575890075SobrienIt is safe to omit constraints in all the operands of the peephole; or 575990075Sobrienyou can write constraints which serve as a double-check on the criteria 576090075Sobrienpreviously tested. 576190075Sobrien 576290075SobrienOnce a sequence of insns matches the patterns, the @var{condition} is 576390075Sobrienchecked. This is a C expression which makes the final decision whether to 576490075Sobrienperform the optimization (we do so if the expression is nonzero). If 576590075Sobrien@var{condition} is omitted (in other words, the string is empty) then the 576690075Sobrienoptimization is applied to every sequence of insns that matches the 576790075Sobrienpatterns. 576890075Sobrien 576990075SobrienThe defined peephole optimizations are applied after register allocation 577090075Sobrienis complete. Therefore, the peephole definition can check which 577190075Sobrienoperands have ended up in which kinds of registers, just by looking at 577290075Sobrienthe operands. 577390075Sobrien 577490075Sobrien@findex prev_active_insn 577590075SobrienThe way to refer to the operands in @var{condition} is to write 577690075Sobrien@code{operands[@var{i}]} for operand number @var{i} (as matched by 577790075Sobrien@code{(match_operand @var{i} @dots{})}). Use the variable @code{insn} 577890075Sobriento refer to the last of the insns being matched; use 577990075Sobrien@code{prev_active_insn} to find the preceding insns. 578090075Sobrien 578190075Sobrien@findex dead_or_set_p 578290075SobrienWhen optimizing computations with intermediate results, you can use 578390075Sobrien@var{condition} to match only when the intermediate results are not used 578490075Sobrienelsewhere. Use the C expression @code{dead_or_set_p (@var{insn}, 578590075Sobrien@var{op})}, where @var{insn} is the insn in which you expect the value 578690075Sobriento be used for the last time (from the value of @code{insn}, together 578790075Sobrienwith use of @code{prev_nonnote_insn}), and @var{op} is the intermediate 578890075Sobrienvalue (from @code{operands[@var{i}]}). 578990075Sobrien 579090075SobrienApplying the optimization means replacing the sequence of insns with one 579190075Sobriennew insn. The @var{template} controls ultimate output of assembler code 579290075Sobrienfor this combined insn. It works exactly like the template of a 579390075Sobrien@code{define_insn}. Operand numbers in this template are the same ones 579490075Sobrienused in matching the original sequence of insns. 579590075Sobrien 579690075SobrienThe result of a defined peephole optimizer does not need to match any of 579790075Sobrienthe insn patterns in the machine description; it does not even have an 579890075Sobrienopportunity to match them. The peephole optimizer definition itself serves 579990075Sobrienas the insn pattern to control how the insn is output. 580090075Sobrien 580190075SobrienDefined peephole optimizers are run as assembler code is being output, 580290075Sobrienso the insns they produce are never combined or rearranged in any way. 580390075Sobrien 580490075SobrienHere is an example, taken from the 68000 machine description: 580590075Sobrien 580690075Sobrien@smallexample 580790075Sobrien(define_peephole 580890075Sobrien [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) 580990075Sobrien (set (match_operand:DF 0 "register_operand" "=f") 581090075Sobrien (match_operand:DF 1 "register_operand" "ad"))] 581190075Sobrien "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" 581290075Sobrien@{ 581390075Sobrien rtx xoperands[2]; 5814169689Skan xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 581590075Sobrien#ifdef MOTOROLA 581690075Sobrien output_asm_insn ("move.l %1,(sp)", xoperands); 581790075Sobrien output_asm_insn ("move.l %1,-(sp)", operands); 581890075Sobrien return "fmove.d (sp)+,%0"; 581990075Sobrien#else 582090075Sobrien output_asm_insn ("movel %1,sp@@", xoperands); 582190075Sobrien output_asm_insn ("movel %1,sp@@-", operands); 582290075Sobrien return "fmoved sp@@+,%0"; 582390075Sobrien#endif 582490075Sobrien@}) 582590075Sobrien@end smallexample 582690075Sobrien 582790075Sobrien@need 1000 582890075SobrienThe effect of this optimization is to change 582990075Sobrien 583090075Sobrien@smallexample 583190075Sobrien@group 583290075Sobrienjbsr _foobar 583390075Sobrienaddql #4,sp 583490075Sobrienmovel d1,sp@@- 583590075Sobrienmovel d0,sp@@- 583690075Sobrienfmoved sp@@+,fp0 583790075Sobrien@end group 583890075Sobrien@end smallexample 583990075Sobrien 584090075Sobrien@noindent 584190075Sobrieninto 584290075Sobrien 584390075Sobrien@smallexample 584490075Sobrien@group 584590075Sobrienjbsr _foobar 584690075Sobrienmovel d1,sp@@ 584790075Sobrienmovel d0,sp@@- 584890075Sobrienfmoved sp@@+,fp0 584990075Sobrien@end group 585090075Sobrien@end smallexample 585190075Sobrien 585290075Sobrien@ignore 585390075Sobrien@findex CC_REVERSED 585490075SobrienIf a peephole matches a sequence including one or more jump insns, you must 585590075Sobrientake account of the flags such as @code{CC_REVERSED} which specify that the 585690075Sobriencondition codes are represented in an unusual manner. The compiler 585790075Sobrienautomatically alters any ordinary conditional jumps which occur in such 585890075Sobriensituations, but the compiler cannot alter jumps which have been replaced by 585990075Sobrienpeephole optimizations. So it is up to you to alter the assembler code 586090075Sobrienthat the peephole produces. Supply C code to write the assembler output, 586190075Sobrienand in this C code check the condition code status flags and change the 586290075Sobrienassembler code as appropriate. 586390075Sobrien@end ignore 586490075Sobrien 586590075Sobrien@var{insn-pattern-1} and so on look @emph{almost} like the second 586690075Sobrienoperand of @code{define_insn}. There is one important difference: the 586790075Sobriensecond operand of @code{define_insn} consists of one or more RTX's 586890075Sobrienenclosed in square brackets. Usually, there is only one: then the same 586990075Sobrienaction can be written as an element of a @code{define_peephole}. But 587090075Sobrienwhen there are multiple actions in a @code{define_insn}, they are 587190075Sobrienimplicitly enclosed in a @code{parallel}. Then you must explicitly 587290075Sobrienwrite the @code{parallel}, and the square brackets within it, in the 587390075Sobrien@code{define_peephole}. Thus, if an insn pattern looks like this, 587490075Sobrien 587590075Sobrien@smallexample 587690075Sobrien(define_insn "divmodsi4" 587790075Sobrien [(set (match_operand:SI 0 "general_operand" "=d") 587890075Sobrien (div:SI (match_operand:SI 1 "general_operand" "0") 587990075Sobrien (match_operand:SI 2 "general_operand" "dmsK"))) 588090075Sobrien (set (match_operand:SI 3 "general_operand" "=d") 588190075Sobrien (mod:SI (match_dup 1) (match_dup 2)))] 588290075Sobrien "TARGET_68020" 588390075Sobrien "divsl%.l %2,%3:%0") 588490075Sobrien@end smallexample 588590075Sobrien 588690075Sobrien@noindent 588790075Sobrienthen the way to mention this insn in a peephole is as follows: 588890075Sobrien 588990075Sobrien@smallexample 589090075Sobrien(define_peephole 589190075Sobrien [@dots{} 589290075Sobrien (parallel 589390075Sobrien [(set (match_operand:SI 0 "general_operand" "=d") 589490075Sobrien (div:SI (match_operand:SI 1 "general_operand" "0") 589590075Sobrien (match_operand:SI 2 "general_operand" "dmsK"))) 589690075Sobrien (set (match_operand:SI 3 "general_operand" "=d") 589790075Sobrien (mod:SI (match_dup 1) (match_dup 2)))]) 589890075Sobrien @dots{}] 589990075Sobrien @dots{}) 590090075Sobrien@end smallexample 590190075Sobrien 5902132718Skan@end ifset 5903132718Skan@ifset INTERNALS 590490075Sobrien@node define_peephole2 590590075Sobrien@subsection RTL to RTL Peephole Optimizers 590690075Sobrien@findex define_peephole2 590790075Sobrien 590890075SobrienThe @code{define_peephole2} definition tells the compiler how to 590990075Sobriensubstitute one sequence of instructions for another sequence, 591090075Sobrienwhat additional scratch registers may be needed and what their 591190075Sobrienlifetimes must be. 591290075Sobrien 591390075Sobrien@smallexample 591490075Sobrien(define_peephole2 591590075Sobrien [@var{insn-pattern-1} 591690075Sobrien @var{insn-pattern-2} 591790075Sobrien @dots{}] 591890075Sobrien "@var{condition}" 591990075Sobrien [@var{new-insn-pattern-1} 592090075Sobrien @var{new-insn-pattern-2} 592190075Sobrien @dots{}] 592290075Sobrien "@var{preparation-statements}") 592390075Sobrien@end smallexample 592490075Sobrien 592590075SobrienThe definition is almost identical to @code{define_split} 592690075Sobrien(@pxref{Insn Splitting}) except that the pattern to match is not a 592790075Sobriensingle instruction, but a sequence of instructions. 592890075Sobrien 592990075SobrienIt is possible to request additional scratch registers for use in the 593090075Sobrienoutput template. If appropriate registers are not free, the pattern 593190075Sobrienwill simply not match. 593290075Sobrien 593390075Sobrien@findex match_scratch 593490075Sobrien@findex match_dup 593590075SobrienScratch registers are requested with a @code{match_scratch} pattern at 593690075Sobrienthe top level of the input pattern. The allocated register (initially) will 593790075Sobrienbe dead at the point requested within the original sequence. If the scratch 593890075Sobrienis used at more than a single point, a @code{match_dup} pattern at the 593990075Sobrientop level of the input pattern marks the last position in the input sequence 594090075Sobrienat which the register must be available. 594190075Sobrien 594290075SobrienHere is an example from the IA-32 machine description: 594390075Sobrien 594490075Sobrien@smallexample 594590075Sobrien(define_peephole2 594690075Sobrien [(match_scratch:SI 2 "r") 594790075Sobrien (parallel [(set (match_operand:SI 0 "register_operand" "") 594890075Sobrien (match_operator:SI 3 "arith_or_logical_operator" 594990075Sobrien [(match_dup 0) 595090075Sobrien (match_operand:SI 1 "memory_operand" "")])) 595190075Sobrien (clobber (reg:CC 17))])] 595290075Sobrien "! optimize_size && ! TARGET_READ_MODIFY" 595390075Sobrien [(set (match_dup 2) (match_dup 1)) 595490075Sobrien (parallel [(set (match_dup 0) 595590075Sobrien (match_op_dup 3 [(match_dup 0) (match_dup 2)])) 595690075Sobrien (clobber (reg:CC 17))])] 595790075Sobrien "") 595890075Sobrien@end smallexample 595990075Sobrien 596090075Sobrien@noindent 596190075SobrienThis pattern tries to split a load from its use in the hopes that we'll be 596290075Sobrienable to schedule around the memory load latency. It allocates a single 596390075Sobrien@code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs 596490075Sobriento be live only at the point just before the arithmetic. 596590075Sobrien 596690075SobrienA real example requiring extended scratch lifetimes is harder to come by, 596790075Sobrienso here's a silly made-up example: 596890075Sobrien 596990075Sobrien@smallexample 597090075Sobrien(define_peephole2 597190075Sobrien [(match_scratch:SI 4 "r") 597290075Sobrien (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" "")) 597390075Sobrien (set (match_operand:SI 2 "" "") (match_dup 1)) 597490075Sobrien (match_dup 4) 597590075Sobrien (set (match_operand:SI 3 "" "") (match_dup 1))] 597690075Sobrien "/* @r{determine 1 does not overlap 0 and 2} */" 597790075Sobrien [(set (match_dup 4) (match_dup 1)) 597890075Sobrien (set (match_dup 0) (match_dup 4)) 597990075Sobrien (set (match_dup 2) (match_dup 4))] 598090075Sobrien (set (match_dup 3) (match_dup 4))] 598190075Sobrien "") 598290075Sobrien@end smallexample 598390075Sobrien 598490075Sobrien@noindent 598590075SobrienIf we had not added the @code{(match_dup 4)} in the middle of the input 598690075Sobriensequence, it might have been the case that the register we chose at the 598790075Sobrienbeginning of the sequence is killed by the first or second @code{set}. 598890075Sobrien 5989132718Skan@end ifset 5990132718Skan@ifset INTERNALS 599190075Sobrien@node Insn Attributes 599290075Sobrien@section Instruction Attributes 599390075Sobrien@cindex insn attributes 599490075Sobrien@cindex instruction attributes 599590075Sobrien 599690075SobrienIn addition to describing the instruction supported by the target machine, 599790075Sobrienthe @file{md} file also defines a group of @dfn{attributes} and a set of 599890075Sobrienvalues for each. Every generated insn is assigned a value for each attribute. 599990075SobrienOne possible attribute would be the effect that the insn has on the machine's 600090075Sobriencondition code. This attribute can then be used by @code{NOTICE_UPDATE_CC} 600190075Sobriento track the condition codes. 600290075Sobrien 600390075Sobrien@menu 600490075Sobrien* Defining Attributes:: Specifying attributes and their values. 600590075Sobrien* Expressions:: Valid expressions for attribute values. 600690075Sobrien* Tagging Insns:: Assigning attribute values to insns. 600790075Sobrien* Attr Example:: An example of assigning attributes. 600890075Sobrien* Insn Lengths:: Computing the length of insns. 600990075Sobrien* Constant Attributes:: Defining attributes that are constant. 601090075Sobrien* Delay Slots:: Defining delay slots required for a machine. 6011117395Skan* Processor pipeline description:: Specifying information for insn scheduling. 601290075Sobrien@end menu 601390075Sobrien 6014132718Skan@end ifset 6015132718Skan@ifset INTERNALS 601690075Sobrien@node Defining Attributes 601790075Sobrien@subsection Defining Attributes and their Values 601890075Sobrien@cindex defining attributes and their values 601990075Sobrien@cindex attributes, defining 602090075Sobrien 602190075Sobrien@findex define_attr 602290075SobrienThe @code{define_attr} expression is used to define each attribute required 602390075Sobrienby the target machine. It looks like: 602490075Sobrien 602590075Sobrien@smallexample 602690075Sobrien(define_attr @var{name} @var{list-of-values} @var{default}) 602790075Sobrien@end smallexample 602890075Sobrien 602990075Sobrien@var{name} is a string specifying the name of the attribute being defined. 603090075Sobrien 603190075Sobrien@var{list-of-values} is either a string that specifies a comma-separated 603290075Sobrienlist of values that can be assigned to the attribute, or a null string to 603390075Sobrienindicate that the attribute takes numeric values. 603490075Sobrien 603590075Sobrien@var{default} is an attribute expression that gives the value of this 603690075Sobrienattribute for insns that match patterns whose definition does not include 603790075Sobrienan explicit value for this attribute. @xref{Attr Example}, for more 603890075Sobrieninformation on the handling of defaults. @xref{Constant Attributes}, 603990075Sobrienfor information on attributes that do not depend on any particular insn. 604090075Sobrien 604190075Sobrien@findex insn-attr.h 604290075SobrienFor each defined attribute, a number of definitions are written to the 604390075Sobrien@file{insn-attr.h} file. For cases where an explicit set of values is 604490075Sobrienspecified for an attribute, the following are defined: 604590075Sobrien 604690075Sobrien@itemize @bullet 604790075Sobrien@item 604890075SobrienA @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}. 604990075Sobrien 605090075Sobrien@item 6051132718SkanAn enumerated class is defined for @samp{attr_@var{name}} with 605290075Sobrienelements of the form @samp{@var{upper-name}_@var{upper-value}} where 6053132718Skanthe attribute name and value are first converted to uppercase. 605490075Sobrien 605590075Sobrien@item 605690075SobrienA function @samp{get_attr_@var{name}} is defined that is passed an insn and 605790075Sobrienreturns the attribute value for that insn. 605890075Sobrien@end itemize 605990075Sobrien 606090075SobrienFor example, if the following is present in the @file{md} file: 606190075Sobrien 606290075Sobrien@smallexample 606390075Sobrien(define_attr "type" "branch,fp,load,store,arith" @dots{}) 606490075Sobrien@end smallexample 606590075Sobrien 606690075Sobrien@noindent 606790075Sobrienthe following lines will be written to the file @file{insn-attr.h}. 606890075Sobrien 606990075Sobrien@smallexample 607090075Sobrien#define HAVE_ATTR_type 607190075Sobrienenum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD, 607290075Sobrien TYPE_STORE, TYPE_ARITH@}; 607390075Sobrienextern enum attr_type get_attr_type (); 607490075Sobrien@end smallexample 607590075Sobrien 607690075SobrienIf the attribute takes numeric values, no @code{enum} type will be 607790075Sobriendefined and the function to obtain the attribute's value will return 607890075Sobrien@code{int}. 607990075Sobrien 6080132718Skan@end ifset 6081132718Skan@ifset INTERNALS 608290075Sobrien@node Expressions 608390075Sobrien@subsection Attribute Expressions 608490075Sobrien@cindex attribute expressions 608590075Sobrien 608690075SobrienRTL expressions used to define attributes use the codes described above 608790075Sobrienplus a few specific to attribute definitions, to be discussed below. 608890075SobrienAttribute value expressions must have one of the following forms: 608990075Sobrien 609090075Sobrien@table @code 609190075Sobrien@cindex @code{const_int} and attributes 609290075Sobrien@item (const_int @var{i}) 609390075SobrienThe integer @var{i} specifies the value of a numeric attribute. @var{i} 609490075Sobrienmust be non-negative. 609590075Sobrien 609690075SobrienThe value of a numeric attribute can be specified either with a 609790075Sobrien@code{const_int}, or as an integer represented as a string in 609890075Sobrien@code{const_string}, @code{eq_attr} (see below), @code{attr}, 609990075Sobrien@code{symbol_ref}, simple arithmetic expressions, and @code{set_attr} 610090075Sobrienoverrides on specific instructions (@pxref{Tagging Insns}). 610190075Sobrien 610290075Sobrien@cindex @code{const_string} and attributes 610390075Sobrien@item (const_string @var{value}) 610490075SobrienThe string @var{value} specifies a constant attribute value. 610590075SobrienIf @var{value} is specified as @samp{"*"}, it means that the default value of 610690075Sobrienthe attribute is to be used for the insn containing this expression. 610790075Sobrien@samp{"*"} obviously cannot be used in the @var{default} expression 610890075Sobrienof a @code{define_attr}. 610990075Sobrien 611090075SobrienIf the attribute whose value is being specified is numeric, @var{value} 611190075Sobrienmust be a string containing a non-negative integer (normally 611290075Sobrien@code{const_int} would be used in this case). Otherwise, it must 611390075Sobriencontain one of the valid values for the attribute. 611490075Sobrien 611590075Sobrien@cindex @code{if_then_else} and attributes 611690075Sobrien@item (if_then_else @var{test} @var{true-value} @var{false-value}) 611790075Sobrien@var{test} specifies an attribute test, whose format is defined below. 611890075SobrienThe value of this expression is @var{true-value} if @var{test} is true, 611990075Sobrienotherwise it is @var{false-value}. 612090075Sobrien 612190075Sobrien@cindex @code{cond} and attributes 612290075Sobrien@item (cond [@var{test1} @var{value1} @dots{}] @var{default}) 612390075SobrienThe first operand of this expression is a vector containing an even 612490075Sobriennumber of expressions and consisting of pairs of @var{test} and @var{value} 612590075Sobrienexpressions. The value of the @code{cond} expression is that of the 612690075Sobrien@var{value} corresponding to the first true @var{test} expression. If 612790075Sobriennone of the @var{test} expressions are true, the value of the @code{cond} 612890075Sobrienexpression is that of the @var{default} expression. 612990075Sobrien@end table 613090075Sobrien 613190075Sobrien@var{test} expressions can have one of the following forms: 613290075Sobrien 613390075Sobrien@table @code 613490075Sobrien@cindex @code{const_int} and attribute tests 613590075Sobrien@item (const_int @var{i}) 613690075SobrienThis test is true if @var{i} is nonzero and false otherwise. 613790075Sobrien 613890075Sobrien@cindex @code{not} and attributes 613990075Sobrien@cindex @code{ior} and attributes 614090075Sobrien@cindex @code{and} and attributes 614190075Sobrien@item (not @var{test}) 614290075Sobrien@itemx (ior @var{test1} @var{test2}) 614390075Sobrien@itemx (and @var{test1} @var{test2}) 614490075SobrienThese tests are true if the indicated logical function is true. 614590075Sobrien 614690075Sobrien@cindex @code{match_operand} and attributes 614790075Sobrien@item (match_operand:@var{m} @var{n} @var{pred} @var{constraints}) 614890075SobrienThis test is true if operand @var{n} of the insn whose attribute value 614990075Sobrienis being determined has mode @var{m} (this part of the test is ignored 615090075Sobrienif @var{m} is @code{VOIDmode}) and the function specified by the string 615190075Sobrien@var{pred} returns a nonzero value when passed operand @var{n} and mode 615290075Sobrien@var{m} (this part of the test is ignored if @var{pred} is the null 615390075Sobrienstring). 615490075Sobrien 615590075SobrienThe @var{constraints} operand is ignored and should be the null string. 615690075Sobrien 615790075Sobrien@cindex @code{le} and attributes 615890075Sobrien@cindex @code{leu} and attributes 615990075Sobrien@cindex @code{lt} and attributes 616090075Sobrien@cindex @code{gt} and attributes 616190075Sobrien@cindex @code{gtu} and attributes 616290075Sobrien@cindex @code{ge} and attributes 616390075Sobrien@cindex @code{geu} and attributes 616490075Sobrien@cindex @code{ne} and attributes 616590075Sobrien@cindex @code{eq} and attributes 616690075Sobrien@cindex @code{plus} and attributes 616790075Sobrien@cindex @code{minus} and attributes 616890075Sobrien@cindex @code{mult} and attributes 616990075Sobrien@cindex @code{div} and attributes 617090075Sobrien@cindex @code{mod} and attributes 617190075Sobrien@cindex @code{abs} and attributes 617290075Sobrien@cindex @code{neg} and attributes 617390075Sobrien@cindex @code{ashift} and attributes 617490075Sobrien@cindex @code{lshiftrt} and attributes 617590075Sobrien@cindex @code{ashiftrt} and attributes 617690075Sobrien@item (le @var{arith1} @var{arith2}) 617790075Sobrien@itemx (leu @var{arith1} @var{arith2}) 617890075Sobrien@itemx (lt @var{arith1} @var{arith2}) 617990075Sobrien@itemx (ltu @var{arith1} @var{arith2}) 618090075Sobrien@itemx (gt @var{arith1} @var{arith2}) 618190075Sobrien@itemx (gtu @var{arith1} @var{arith2}) 618290075Sobrien@itemx (ge @var{arith1} @var{arith2}) 618390075Sobrien@itemx (geu @var{arith1} @var{arith2}) 618490075Sobrien@itemx (ne @var{arith1} @var{arith2}) 618590075Sobrien@itemx (eq @var{arith1} @var{arith2}) 618690075SobrienThese tests are true if the indicated comparison of the two arithmetic 618790075Sobrienexpressions is true. Arithmetic expressions are formed with 618890075Sobrien@code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod}, 618990075Sobrien@code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not}, 619090075Sobrien@code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions. 619190075Sobrien 619290075Sobrien@findex get_attr 619390075Sobrien@code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn 619490075SobrienLengths},for additional forms). @code{symbol_ref} is a string 619590075Sobriendenoting a C expression that yields an @code{int} when evaluated by the 619690075Sobrien@samp{get_attr_@dots{}} routine. It should normally be a global 619790075Sobrienvariable. 619890075Sobrien 619990075Sobrien@findex eq_attr 620090075Sobrien@item (eq_attr @var{name} @var{value}) 620190075Sobrien@var{name} is a string specifying the name of an attribute. 620290075Sobrien 620390075Sobrien@var{value} is a string that is either a valid value for attribute 620490075Sobrien@var{name}, a comma-separated list of values, or @samp{!} followed by a 620590075Sobrienvalue or list. If @var{value} does not begin with a @samp{!}, this 620690075Sobrientest is true if the value of the @var{name} attribute of the current 620790075Sobrieninsn is in the list specified by @var{value}. If @var{value} begins 620890075Sobrienwith a @samp{!}, this test is true if the attribute's value is 620990075Sobrien@emph{not} in the specified list. 621090075Sobrien 621190075SobrienFor example, 621290075Sobrien 621390075Sobrien@smallexample 621490075Sobrien(eq_attr "type" "load,store") 621590075Sobrien@end smallexample 621690075Sobrien 621790075Sobrien@noindent 621890075Sobrienis equivalent to 621990075Sobrien 622090075Sobrien@smallexample 622190075Sobrien(ior (eq_attr "type" "load") (eq_attr "type" "store")) 622290075Sobrien@end smallexample 622390075Sobrien 622490075SobrienIf @var{name} specifies an attribute of @samp{alternative}, it refers to the 622590075Sobrienvalue of the compiler variable @code{which_alternative} 622690075Sobrien(@pxref{Output Statement}) and the values must be small integers. For 622790075Sobrienexample, 622890075Sobrien 622990075Sobrien@smallexample 623090075Sobrien(eq_attr "alternative" "2,3") 623190075Sobrien@end smallexample 623290075Sobrien 623390075Sobrien@noindent 623490075Sobrienis equivalent to 623590075Sobrien 623690075Sobrien@smallexample 623790075Sobrien(ior (eq (symbol_ref "which_alternative") (const_int 2)) 623890075Sobrien (eq (symbol_ref "which_alternative") (const_int 3))) 623990075Sobrien@end smallexample 624090075Sobrien 624190075SobrienNote that, for most attributes, an @code{eq_attr} test is simplified in cases 624290075Sobrienwhere the value of the attribute being tested is known for all insns matching 624390075Sobriena particular pattern. This is by far the most common case. 624490075Sobrien 624590075Sobrien@findex attr_flag 624690075Sobrien@item (attr_flag @var{name}) 624790075SobrienThe value of an @code{attr_flag} expression is true if the flag 624890075Sobrienspecified by @var{name} is true for the @code{insn} currently being 624990075Sobrienscheduled. 625090075Sobrien 625190075Sobrien@var{name} is a string specifying one of a fixed set of flags to test. 625290075SobrienTest the flags @code{forward} and @code{backward} to determine the 625390075Sobriendirection of a conditional branch. Test the flags @code{very_likely}, 625490075Sobrien@code{likely}, @code{very_unlikely}, and @code{unlikely} to determine 625590075Sobrienif a conditional branch is expected to be taken. 625690075Sobrien 625790075SobrienIf the @code{very_likely} flag is true, then the @code{likely} flag is also 625890075Sobrientrue. Likewise for the @code{very_unlikely} and @code{unlikely} flags. 625990075Sobrien 626090075SobrienThis example describes a conditional branch delay slot which 626190075Sobriencan be nullified for forward branches that are taken (annul-true) or 626290075Sobrienfor backward branches which are not taken (annul-false). 626390075Sobrien 626490075Sobrien@smallexample 626590075Sobrien(define_delay (eq_attr "type" "cbranch") 626690075Sobrien [(eq_attr "in_branch_delay" "true") 626790075Sobrien (and (eq_attr "in_branch_delay" "true") 626890075Sobrien (attr_flag "forward")) 626990075Sobrien (and (eq_attr "in_branch_delay" "true") 627090075Sobrien (attr_flag "backward"))]) 627190075Sobrien@end smallexample 627290075Sobrien 627390075SobrienThe @code{forward} and @code{backward} flags are false if the current 627490075Sobrien@code{insn} being scheduled is not a conditional branch. 627590075Sobrien 627690075SobrienThe @code{very_likely} and @code{likely} flags are true if the 627790075Sobrien@code{insn} being scheduled is not a conditional branch. 627890075SobrienThe @code{very_unlikely} and @code{unlikely} flags are false if the 627990075Sobrien@code{insn} being scheduled is not a conditional branch. 628090075Sobrien 628190075Sobrien@code{attr_flag} is only used during delay slot scheduling and has no 628290075Sobrienmeaning to other passes of the compiler. 628390075Sobrien 628490075Sobrien@findex attr 628590075Sobrien@item (attr @var{name}) 628690075SobrienThe value of another attribute is returned. This is most useful 628790075Sobrienfor numeric attributes, as @code{eq_attr} and @code{attr_flag} 628890075Sobrienproduce more efficient code for non-numeric attributes. 628990075Sobrien@end table 629090075Sobrien 6291132718Skan@end ifset 6292132718Skan@ifset INTERNALS 629390075Sobrien@node Tagging Insns 629490075Sobrien@subsection Assigning Attribute Values to Insns 629590075Sobrien@cindex tagging insns 629690075Sobrien@cindex assigning attribute values to insns 629790075Sobrien 629890075SobrienThe value assigned to an attribute of an insn is primarily determined by 629990075Sobrienwhich pattern is matched by that insn (or which @code{define_peephole} 630090075Sobriengenerated it). Every @code{define_insn} and @code{define_peephole} can 630190075Sobrienhave an optional last argument to specify the values of attributes for 630290075Sobrienmatching insns. The value of any attribute not specified in a particular 630390075Sobrieninsn is set to the default value for that attribute, as specified in its 630490075Sobrien@code{define_attr}. Extensive use of default values for attributes 630590075Sobrienpermits the specification of the values for only one or two attributes 630690075Sobrienin the definition of most insn patterns, as seen in the example in the 630790075Sobriennext section. 630890075Sobrien 630990075SobrienThe optional last argument of @code{define_insn} and 631090075Sobrien@code{define_peephole} is a vector of expressions, each of which defines 631190075Sobrienthe value for a single attribute. The most general way of assigning an 631290075Sobrienattribute's value is to use a @code{set} expression whose first operand is an 631390075Sobrien@code{attr} expression giving the name of the attribute being set. The 631490075Sobriensecond operand of the @code{set} is an attribute expression 631590075Sobrien(@pxref{Expressions}) giving the value of the attribute. 631690075Sobrien 631790075SobrienWhen the attribute value depends on the @samp{alternative} attribute 631890075Sobrien(i.e., which is the applicable alternative in the constraint of the 631990075Sobrieninsn), the @code{set_attr_alternative} expression can be used. It 632090075Sobrienallows the specification of a vector of attribute expressions, one for 632190075Sobrieneach alternative. 632290075Sobrien 632390075Sobrien@findex set_attr 632490075SobrienWhen the generality of arbitrary attribute expressions is not required, 632590075Sobrienthe simpler @code{set_attr} expression can be used, which allows 632690075Sobrienspecifying a string giving either a single attribute value or a list 632790075Sobrienof attribute values, one for each alternative. 632890075Sobrien 632990075SobrienThe form of each of the above specifications is shown below. In each case, 633090075Sobrien@var{name} is a string specifying the attribute to be set. 633190075Sobrien 633290075Sobrien@table @code 633390075Sobrien@item (set_attr @var{name} @var{value-string}) 633490075Sobrien@var{value-string} is either a string giving the desired attribute value, 633590075Sobrienor a string containing a comma-separated list giving the values for 633690075Sobriensucceeding alternatives. The number of elements must match the number 633790075Sobrienof alternatives in the constraint of the insn pattern. 633890075Sobrien 633990075SobrienNote that it may be useful to specify @samp{*} for some alternative, in 634090075Sobrienwhich case the attribute will assume its default value for insns matching 634190075Sobrienthat alternative. 634290075Sobrien 634390075Sobrien@findex set_attr_alternative 634490075Sobrien@item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}]) 634590075SobrienDepending on the alternative of the insn, the value will be one of the 634690075Sobrienspecified values. This is a shorthand for using a @code{cond} with 634790075Sobrientests on the @samp{alternative} attribute. 634890075Sobrien 634990075Sobrien@findex attr 635090075Sobrien@item (set (attr @var{name}) @var{value}) 635190075SobrienThe first operand of this @code{set} must be the special RTL expression 635290075Sobrien@code{attr}, whose sole operand is a string giving the name of the 635390075Sobrienattribute being set. @var{value} is the value of the attribute. 635490075Sobrien@end table 635590075Sobrien 635690075SobrienThe following shows three different ways of representing the same 635790075Sobrienattribute value specification: 635890075Sobrien 635990075Sobrien@smallexample 636090075Sobrien(set_attr "type" "load,store,arith") 636190075Sobrien 636290075Sobrien(set_attr_alternative "type" 636390075Sobrien [(const_string "load") (const_string "store") 636490075Sobrien (const_string "arith")]) 636590075Sobrien 636690075Sobrien(set (attr "type") 636790075Sobrien (cond [(eq_attr "alternative" "1") (const_string "load") 636890075Sobrien (eq_attr "alternative" "2") (const_string "store")] 636990075Sobrien (const_string "arith"))) 637090075Sobrien@end smallexample 637190075Sobrien 637290075Sobrien@need 1000 637390075Sobrien@findex define_asm_attributes 637490075SobrienThe @code{define_asm_attributes} expression provides a mechanism to 637590075Sobrienspecify the attributes assigned to insns produced from an @code{asm} 637690075Sobrienstatement. It has the form: 637790075Sobrien 637890075Sobrien@smallexample 637990075Sobrien(define_asm_attributes [@var{attr-sets}]) 638090075Sobrien@end smallexample 638190075Sobrien 638290075Sobrien@noindent 638390075Sobrienwhere @var{attr-sets} is specified the same as for both the 638490075Sobrien@code{define_insn} and the @code{define_peephole} expressions. 638590075Sobrien 638690075SobrienThese values will typically be the ``worst case'' attribute values. For 638790075Sobrienexample, they might indicate that the condition code will be clobbered. 638890075Sobrien 638990075SobrienA specification for a @code{length} attribute is handled specially. The 639090075Sobrienway to compute the length of an @code{asm} insn is to multiply the 639190075Sobrienlength specified in the expression @code{define_asm_attributes} by the 639290075Sobriennumber of machine instructions specified in the @code{asm} statement, 639390075Sobriendetermined by counting the number of semicolons and newlines in the 639490075Sobrienstring. Therefore, the value of the @code{length} attribute specified 639590075Sobrienin a @code{define_asm_attributes} should be the maximum possible length 639690075Sobrienof a single machine instruction. 639790075Sobrien 6398132718Skan@end ifset 6399132718Skan@ifset INTERNALS 640090075Sobrien@node Attr Example 640190075Sobrien@subsection Example of Attribute Specifications 640290075Sobrien@cindex attribute specifications example 640390075Sobrien@cindex attribute specifications 640490075Sobrien 640590075SobrienThe judicious use of defaulting is important in the efficient use of 640690075Sobrieninsn attributes. Typically, insns are divided into @dfn{types} and an 640790075Sobrienattribute, customarily called @code{type}, is used to represent this 640890075Sobrienvalue. This attribute is normally used only to define the default value 640990075Sobrienfor other attributes. An example will clarify this usage. 641090075Sobrien 641190075SobrienAssume we have a RISC machine with a condition code and in which only 641290075Sobrienfull-word operations are performed in registers. Let us assume that we 641390075Sobriencan divide all insns into loads, stores, (integer) arithmetic 641490075Sobrienoperations, floating point operations, and branches. 641590075Sobrien 641690075SobrienHere we will concern ourselves with determining the effect of an insn on 641790075Sobrienthe condition code and will limit ourselves to the following possible 641890075Sobrieneffects: The condition code can be set unpredictably (clobbered), not 641990075Sobrienbe changed, be set to agree with the results of the operation, or only 642090075Sobrienchanged if the item previously set into the condition code has been 642190075Sobrienmodified. 642290075Sobrien 642390075SobrienHere is part of a sample @file{md} file for such a machine: 642490075Sobrien 642590075Sobrien@smallexample 642690075Sobrien(define_attr "type" "load,store,arith,fp,branch" (const_string "arith")) 642790075Sobrien 642890075Sobrien(define_attr "cc" "clobber,unchanged,set,change0" 642990075Sobrien (cond [(eq_attr "type" "load") 643090075Sobrien (const_string "change0") 643190075Sobrien (eq_attr "type" "store,branch") 643290075Sobrien (const_string "unchanged") 643390075Sobrien (eq_attr "type" "arith") 643490075Sobrien (if_then_else (match_operand:SI 0 "" "") 643590075Sobrien (const_string "set") 643690075Sobrien (const_string "clobber"))] 643790075Sobrien (const_string "clobber"))) 643890075Sobrien 643990075Sobrien(define_insn "" 644090075Sobrien [(set (match_operand:SI 0 "general_operand" "=r,r,m") 644190075Sobrien (match_operand:SI 1 "general_operand" "r,m,r"))] 644290075Sobrien "" 644390075Sobrien "@@ 644490075Sobrien move %0,%1 644590075Sobrien load %0,%1 644690075Sobrien store %0,%1" 644790075Sobrien [(set_attr "type" "arith,load,store")]) 644890075Sobrien@end smallexample 644990075Sobrien 645090075SobrienNote that we assume in the above example that arithmetic operations 645190075Sobrienperformed on quantities smaller than a machine word clobber the condition 645290075Sobriencode since they will set the condition code to a value corresponding to the 645390075Sobrienfull-word result. 645490075Sobrien 6455132718Skan@end ifset 6456132718Skan@ifset INTERNALS 645790075Sobrien@node Insn Lengths 645890075Sobrien@subsection Computing the Length of an Insn 645990075Sobrien@cindex insn lengths, computing 646090075Sobrien@cindex computing the length of an insn 646190075Sobrien 646290075SobrienFor many machines, multiple types of branch instructions are provided, each 646390075Sobrienfor different length branch displacements. In most cases, the assembler 646490075Sobrienwill choose the correct instruction to use. However, when the assembler 6465169689Skancannot do so, GCC can when a special attribute, the @code{length} 646690075Sobrienattribute, is defined. This attribute must be defined to have numeric 646790075Sobrienvalues by specifying a null string in its @code{define_attr}. 646890075Sobrien 6469169689SkanIn the case of the @code{length} attribute, two additional forms of 647090075Sobrienarithmetic terms are allowed in test expressions: 647190075Sobrien 647290075Sobrien@table @code 647390075Sobrien@cindex @code{match_dup} and attributes 647490075Sobrien@item (match_dup @var{n}) 647590075SobrienThis refers to the address of operand @var{n} of the current insn, which 647690075Sobrienmust be a @code{label_ref}. 647790075Sobrien 647890075Sobrien@cindex @code{pc} and attributes 647990075Sobrien@item (pc) 648090075SobrienThis refers to the address of the @emph{current} insn. It might have 648190075Sobrienbeen more consistent with other usage to make this the address of the 648290075Sobrien@emph{next} insn but this would be confusing because the length of the 648390075Sobriencurrent insn is to be computed. 648490075Sobrien@end table 648590075Sobrien 648690075Sobrien@cindex @code{addr_vec}, length of 648790075Sobrien@cindex @code{addr_diff_vec}, length of 648890075SobrienFor normal insns, the length will be determined by value of the 6489169689Skan@code{length} attribute. In the case of @code{addr_vec} and 649090075Sobrien@code{addr_diff_vec} insn patterns, the length is computed as 649190075Sobrienthe number of vectors multiplied by the size of each vector. 649290075Sobrien 649390075SobrienLengths are measured in addressable storage units (bytes). 649490075Sobrien 649590075SobrienThe following macros can be used to refine the length computation: 649690075Sobrien 649790075Sobrien@table @code 649890075Sobrien@findex ADJUST_INSN_LENGTH 649990075Sobrien@item ADJUST_INSN_LENGTH (@var{insn}, @var{length}) 650090075SobrienIf defined, modifies the length assigned to instruction @var{insn} as a 650190075Sobrienfunction of the context in which it is used. @var{length} is an lvalue 650290075Sobrienthat contains the initially computed length of the insn and should be 650390075Sobrienupdated with the correct length of the insn. 650490075Sobrien 650590075SobrienThis macro will normally not be required. A case in which it is 650690075Sobrienrequired is the ROMP@. On this machine, the size of an @code{addr_vec} 650790075Sobrieninsn must be increased by two to compensate for the fact that alignment 650890075Sobrienmay be required. 650990075Sobrien@end table 651090075Sobrien 651190075Sobrien@findex get_attr_length 651290075SobrienThe routine that returns @code{get_attr_length} (the value of the 651390075Sobrien@code{length} attribute) can be used by the output routine to 651490075Sobriendetermine the form of the branch instruction to be written, as the 651590075Sobrienexample below illustrates. 651690075Sobrien 651790075SobrienAs an example of the specification of variable-length branches, consider 651890075Sobrienthe IBM 360. If we adopt the convention that a register will be set to 651990075Sobrienthe starting address of a function, we can jump to labels within 4k of 652090075Sobrienthe start using a four-byte instruction. Otherwise, we need a six-byte 652190075Sobriensequence to load the address from memory and then branch to it. 652290075Sobrien 652390075SobrienOn such a machine, a pattern for a branch instruction might be specified 652490075Sobrienas follows: 652590075Sobrien 652690075Sobrien@smallexample 652790075Sobrien(define_insn "jump" 652890075Sobrien [(set (pc) 652990075Sobrien (label_ref (match_operand 0 "" "")))] 653090075Sobrien "" 653190075Sobrien@{ 653290075Sobrien return (get_attr_length (insn) == 4 653390075Sobrien ? "b %l0" : "l r15,=a(%l0); br r15"); 653490075Sobrien@} 653590075Sobrien [(set (attr "length") 653690075Sobrien (if_then_else (lt (match_dup 0) (const_int 4096)) 653790075Sobrien (const_int 4) 653890075Sobrien (const_int 6)))]) 653990075Sobrien@end smallexample 654090075Sobrien 6541132718Skan@end ifset 6542132718Skan@ifset INTERNALS 654390075Sobrien@node Constant Attributes 654490075Sobrien@subsection Constant Attributes 654590075Sobrien@cindex constant attributes 654690075Sobrien 654790075SobrienA special form of @code{define_attr}, where the expression for the 654890075Sobriendefault value is a @code{const} expression, indicates an attribute that 654990075Sobrienis constant for a given run of the compiler. Constant attributes may be 655090075Sobrienused to specify which variety of processor is used. For example, 655190075Sobrien 655290075Sobrien@smallexample 655390075Sobrien(define_attr "cpu" "m88100,m88110,m88000" 655490075Sobrien (const 655590075Sobrien (cond [(symbol_ref "TARGET_88100") (const_string "m88100") 655690075Sobrien (symbol_ref "TARGET_88110") (const_string "m88110")] 655790075Sobrien (const_string "m88000")))) 655890075Sobrien 655990075Sobrien(define_attr "memory" "fast,slow" 656090075Sobrien (const 656190075Sobrien (if_then_else (symbol_ref "TARGET_FAST_MEM") 656290075Sobrien (const_string "fast") 656390075Sobrien (const_string "slow")))) 656490075Sobrien@end smallexample 656590075Sobrien 656690075SobrienThe routine generated for constant attributes has no parameters as it 656790075Sobriendoes not depend on any particular insn. RTL expressions used to define 656890075Sobrienthe value of a constant attribute may use the @code{symbol_ref} form, 656990075Sobrienbut may not use either the @code{match_operand} form or @code{eq_attr} 657090075Sobrienforms involving insn attributes. 657190075Sobrien 6572132718Skan@end ifset 6573132718Skan@ifset INTERNALS 657490075Sobrien@node Delay Slots 657590075Sobrien@subsection Delay Slot Scheduling 657690075Sobrien@cindex delay slots, defining 657790075Sobrien 657890075SobrienThe insn attribute mechanism can be used to specify the requirements for 657990075Sobriendelay slots, if any, on a target machine. An instruction is said to 658090075Sobrienrequire a @dfn{delay slot} if some instructions that are physically 658190075Sobrienafter the instruction are executed as if they were located before it. 658290075SobrienClassic examples are branch and call instructions, which often execute 658390075Sobrienthe following instruction before the branch or call is performed. 658490075Sobrien 658590075SobrienOn some machines, conditional branch instructions can optionally 658690075Sobrien@dfn{annul} instructions in the delay slot. This means that the 658790075Sobrieninstruction will not be executed for certain branch outcomes. Both 658890075Sobrieninstructions that annul if the branch is true and instructions that 658990075Sobrienannul if the branch is false are supported. 659090075Sobrien 659190075SobrienDelay slot scheduling differs from instruction scheduling in that 659290075Sobriendetermining whether an instruction needs a delay slot is dependent only 659390075Sobrienon the type of instruction being generated, not on data flow between the 659490075Sobrieninstructions. See the next section for a discussion of data-dependent 659590075Sobrieninstruction scheduling. 659690075Sobrien 659790075Sobrien@findex define_delay 659890075SobrienThe requirement of an insn needing one or more delay slots is indicated 659990075Sobrienvia the @code{define_delay} expression. It has the following form: 660090075Sobrien 660190075Sobrien@smallexample 660290075Sobrien(define_delay @var{test} 660390075Sobrien [@var{delay-1} @var{annul-true-1} @var{annul-false-1} 660490075Sobrien @var{delay-2} @var{annul-true-2} @var{annul-false-2} 660590075Sobrien @dots{}]) 660690075Sobrien@end smallexample 660790075Sobrien 660890075Sobrien@var{test} is an attribute test that indicates whether this 660990075Sobrien@code{define_delay} applies to a particular insn. If so, the number of 661090075Sobrienrequired delay slots is determined by the length of the vector specified 661190075Sobrienas the second argument. An insn placed in delay slot @var{n} must 661290075Sobriensatisfy attribute test @var{delay-n}. @var{annul-true-n} is an 661390075Sobrienattribute test that specifies which insns may be annulled if the branch 661490075Sobrienis true. Similarly, @var{annul-false-n} specifies which insns in the 661590075Sobriendelay slot may be annulled if the branch is false. If annulling is not 661690075Sobriensupported for that delay slot, @code{(nil)} should be coded. 661790075Sobrien 661890075SobrienFor example, in the common case where branch and call insns require 661990075Sobriena single delay slot, which may contain any insn other than a branch or 662090075Sobriencall, the following would be placed in the @file{md} file: 662190075Sobrien 662290075Sobrien@smallexample 662390075Sobrien(define_delay (eq_attr "type" "branch,call") 662490075Sobrien [(eq_attr "type" "!branch,call") (nil) (nil)]) 662590075Sobrien@end smallexample 662690075Sobrien 662790075SobrienMultiple @code{define_delay} expressions may be specified. In this 662890075Sobriencase, each such expression specifies different delay slot requirements 662990075Sobrienand there must be no insn for which tests in two @code{define_delay} 663090075Sobrienexpressions are both true. 663190075Sobrien 663290075SobrienFor example, if we have a machine that requires one delay slot for branches 663390075Sobrienbut two for calls, no delay slot can contain a branch or call insn, 663490075Sobrienand any valid insn in the delay slot for the branch can be annulled if the 663590075Sobrienbranch is true, we might represent this as follows: 663690075Sobrien 663790075Sobrien@smallexample 663890075Sobrien(define_delay (eq_attr "type" "branch") 663990075Sobrien [(eq_attr "type" "!branch,call") 664090075Sobrien (eq_attr "type" "!branch,call") 664190075Sobrien (nil)]) 664290075Sobrien 664390075Sobrien(define_delay (eq_attr "type" "call") 664490075Sobrien [(eq_attr "type" "!branch,call") (nil) (nil) 664590075Sobrien (eq_attr "type" "!branch,call") (nil) (nil)]) 664690075Sobrien@end smallexample 664790075Sobrien@c the above is *still* too long. --mew 4feb93 664890075Sobrien 6649132718Skan@end ifset 6650132718Skan@ifset INTERNALS 6651117395Skan@node Processor pipeline description 6652117395Skan@subsection Specifying processor pipeline description 6653117395Skan@cindex processor pipeline description 6654117395Skan@cindex processor functional units 6655117395Skan@cindex instruction latency time 6656117395Skan@cindex interlock delays 6657117395Skan@cindex data dependence delays 6658117395Skan@cindex reservation delays 6659117395Skan@cindex pipeline hazard recognizer 6660117395Skan@cindex automaton based pipeline description 6661117395Skan@cindex regular expressions 6662117395Skan@cindex deterministic finite state automaton 6663117395Skan@cindex automaton based scheduler 6664117395Skan@cindex RISC 6665117395Skan@cindex VLIW 6666117395Skan 6667117395SkanTo achieve better performance, most modern processors 6668117395Skan(super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW} 6669117395Skanprocessors) have many @dfn{functional units} on which several 6670117395Skaninstructions can be executed simultaneously. An instruction starts 6671117395Skanexecution if its issue conditions are satisfied. If not, the 6672117395Skaninstruction is stalled until its conditions are satisfied. Such 6673117395Skan@dfn{interlock (pipeline) delay} causes interruption of the fetching 6674169689Skanof successor instructions (or demands nop instructions, e.g.@: for some 6675117395SkanMIPS processors). 6676117395Skan 6677117395SkanThere are two major kinds of interlock delays in modern processors. 6678117395SkanThe first one is a data dependence delay determining @dfn{instruction 6679117395Skanlatency time}. The instruction execution is not started until all 6680117395Skansource data have been evaluated by prior instructions (there are more 6681117395Skancomplex cases when the instruction execution starts even when the data 6682117395Skanare not available but will be ready in given time after the 6683117395Skaninstruction execution start). Taking the data dependence delays into 6684117395Skanaccount is simple. The data dependence (true, output, and 6685117395Skananti-dependence) delay between two instructions is given by a 6686117395Skanconstant. In most cases this approach is adequate. The second kind 6687117395Skanof interlock delays is a reservation delay. The reservation delay 6688117395Skanmeans that two instructions under execution will be in need of shared 6689169689Skanprocessors resources, i.e.@: buses, internal registers, and/or 6690117395Skanfunctional units, which are reserved for some time. Taking this kind 6691117395Skanof delay into account is complex especially for modern @acronym{RISC} 6692117395Skanprocessors. 6693117395Skan 6694117395SkanThe task of exploiting more processor parallelism is solved by an 6695117395Skaninstruction scheduler. For a better solution to this problem, the 6696117395Skaninstruction scheduler has to have an adequate description of the 6697169689Skanprocessor parallelism (or @dfn{pipeline description}). GCC 6698169689Skanmachine descriptions describe processor parallelism and functional 6699169689Skanunit reservations for groups of instructions with the aid of 6700169689Skan@dfn{regular expressions}. 6701117395Skan 6702117395SkanThe GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to 6703117395Skanfigure out the possibility of the instruction issue by the processor 6704117395Skanon a given simulated processor cycle. The pipeline hazard recognizer is 6705117395Skanautomatically generated from the processor pipeline description. The 6706169689Skanpipeline hazard recognizer generated from the machine description 6707169689Skanis based on a deterministic finite state automaton (@acronym{DFA}): 6708169689Skanthe instruction issue is possible if there is a transition from one 6709169689Skanautomaton state to another one. This algorithm is very fast, and 6710169689Skanfurthermore, its speed is not dependent on processor 6711169689Skancomplexity@footnote{However, the size of the automaton depends on 6712169689Skan processor complexity. To limit this effect, machine descriptions 6713169689Skan can split orthogonal parts of the machine description among several 6714169689Skan automata: but then, since each of these must be stepped independently, 6715169689Skan this does cause a small decrease in the algorithm's performance.}. 6716117395Skan 6717117395Skan@cindex automaton based pipeline description 6718169689SkanThe rest of this section describes the directives that constitute 6719169689Skanan automaton-based processor pipeline description. The order of 6720169689Skanthese constructions within the machine description file is not 6721169689Skanimportant. 6722117395Skan 6723117395Skan@findex define_automaton 6724117395Skan@cindex pipeline hazard recognizer 6725117395SkanThe following optional construction describes names of automata 6726117395Skangenerated and used for the pipeline hazards recognition. Sometimes 6727117395Skanthe generated finite state automaton used by the pipeline hazard 6728117395Skanrecognizer is large. If we use more than one automaton and bind functional 6729132718Skanunits to the automata, the total size of the automata is usually 6730117395Skanless than the size of the single automaton. If there is no one such 6731117395Skanconstruction, only one finite state automaton is generated. 6732117395Skan 6733117395Skan@smallexample 6734117395Skan(define_automaton @var{automata-names}) 6735117395Skan@end smallexample 6736117395Skan 6737117395Skan@var{automata-names} is a string giving names of the automata. The 6738117395Skannames are separated by commas. All the automata should have unique names. 6739119256SkanThe automaton name is used in the constructions @code{define_cpu_unit} and 6740117395Skan@code{define_query_cpu_unit}. 6741117395Skan 6742117395Skan@findex define_cpu_unit 6743117395Skan@cindex processor functional units 6744119256SkanEach processor functional unit used in the description of instruction 6745117395Skanreservations should be described by the following construction. 6746117395Skan 6747117395Skan@smallexample 6748117395Skan(define_cpu_unit @var{unit-names} [@var{automaton-name}]) 6749117395Skan@end smallexample 6750117395Skan 6751117395Skan@var{unit-names} is a string giving the names of the functional units 6752117395Skanseparated by commas. Don't use name @samp{nothing}, it is reserved 6753117395Skanfor other goals. 6754117395Skan 6755117395Skan@var{automaton-name} is a string giving the name of the automaton with 6756117395Skanwhich the unit is bound. The automaton should be described in 6757117395Skanconstruction @code{define_automaton}. You should give 6758117395Skan@dfn{automaton-name}, if there is a defined automaton. 6759117395Skan 6760132718SkanThe assignment of units to automata are constrained by the uses of the 6761132718Skanunits in insn reservations. The most important constraint is: if a 6762132718Skanunit reservation is present on a particular cycle of an alternative 6763132718Skanfor an insn reservation, then some unit from the same automaton must 6764132718Skanbe present on the same cycle for the other alternatives of the insn 6765132718Skanreservation. The rest of the constraints are mentioned in the 6766132718Skandescription of the subsequent constructions. 6767132718Skan 6768117395Skan@findex define_query_cpu_unit 6769117395Skan@cindex querying function unit reservations 6770117395SkanThe following construction describes CPU functional units analogously 6771132718Skanto @code{define_cpu_unit}. The reservation of such units can be 6772132718Skanqueried for an automaton state. The instruction scheduler never 6773132718Skanqueries reservation of functional units for given automaton state. So 6774132718Skanas a rule, you don't need this construction. This construction could 6775169689Skanbe used for future code generation goals (e.g.@: to generate 6776132718Skan@acronym{VLIW} insn templates). 6777117395Skan 6778117395Skan@smallexample 6779117395Skan(define_query_cpu_unit @var{unit-names} [@var{automaton-name}]) 6780117395Skan@end smallexample 6781117395Skan 6782117395Skan@var{unit-names} is a string giving names of the functional units 6783117395Skanseparated by commas. 6784117395Skan 6785117395Skan@var{automaton-name} is a string giving the name of the automaton with 6786117395Skanwhich the unit is bound. 6787117395Skan 6788117395Skan@findex define_insn_reservation 6789117395Skan@cindex instruction latency time 6790117395Skan@cindex regular expressions 6791117395Skan@cindex data bypass 6792117395SkanThe following construction is the major one to describe pipeline 6793117395Skancharacteristics of an instruction. 6794117395Skan 6795117395Skan@smallexample 6796117395Skan(define_insn_reservation @var{insn-name} @var{default_latency} 6797117395Skan @var{condition} @var{regexp}) 6798117395Skan@end smallexample 6799117395Skan 6800117395Skan@var{default_latency} is a number giving latency time of the 6801117395Skaninstruction. There is an important difference between the old 6802117395Skandescription and the automaton based pipeline description. The latency 6803117395Skantime is used for all dependencies when we use the old description. In 6804117395Skanthe automaton based pipeline description, the given latency time is only 6805117395Skanused for true dependencies. The cost of anti-dependencies is always 6806117395Skanzero and the cost of output dependencies is the difference between 6807117395Skanlatency times of the producing and consuming insns (if the difference 6808117395Skanis negative, the cost is considered to be zero). You can always 6809117395Skanchange the default costs for any description by using the target hook 6810117395Skan@code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}). 6811117395Skan 6812119256Skan@var{insn-name} is a string giving the internal name of the insn. The 6813117395Skaninternal names are used in constructions @code{define_bypass} and in 6814117395Skanthe automaton description file generated for debugging. The internal 6815117395Skanname has nothing in common with the names in @code{define_insn}. It is a 6816117395Skangood practice to use insn classes described in the processor manual. 6817117395Skan 6818117395Skan@var{condition} defines what RTL insns are described by this 6819117395Skanconstruction. You should remember that you will be in trouble if 6820117395Skan@var{condition} for two or more different 6821117395Skan@code{define_insn_reservation} constructions is TRUE for an insn. In 6822117395Skanthis case what reservation will be used for the insn is not defined. 6823117395SkanSuch cases are not checked during generation of the pipeline hazards 6824117395Skanrecognizer because in general recognizing that two conditions may have 6825117395Skanthe same value is quite difficult (especially if the conditions 6826117395Skancontain @code{symbol_ref}). It is also not checked during the 6827117395Skanpipeline hazard recognizer work because it would slow down the 6828117395Skanrecognizer considerably. 6829117395Skan 6830117395Skan@var{regexp} is a string describing the reservation of the cpu's functional 6831117395Skanunits by the instruction. The reservations are described by a regular 6832117395Skanexpression according to the following syntax: 6833117395Skan 6834117395Skan@smallexample 6835117395Skan regexp = regexp "," oneof 6836117395Skan | oneof 6837117395Skan 6838117395Skan oneof = oneof "|" allof 6839117395Skan | allof 6840117395Skan 6841117395Skan allof = allof "+" repeat 6842117395Skan | repeat 6843132718Skan 6844117395Skan repeat = element "*" number 6845117395Skan | element 6846117395Skan 6847117395Skan element = cpu_function_unit_name 6848117395Skan | reservation_name 6849117395Skan | result_name 6850117395Skan | "nothing" 6851117395Skan | "(" regexp ")" 6852117395Skan@end smallexample 6853117395Skan 6854117395Skan@itemize @bullet 6855117395Skan@item 6856117395Skan@samp{,} is used for describing the start of the next cycle in 6857117395Skanthe reservation. 6858117395Skan 6859117395Skan@item 6860117395Skan@samp{|} is used for describing a reservation described by the first 6861117395Skanregular expression @strong{or} a reservation described by the second 6862117395Skanregular expression @strong{or} etc. 6863117395Skan 6864117395Skan@item 6865117395Skan@samp{+} is used for describing a reservation described by the first 6866117395Skanregular expression @strong{and} a reservation described by the 6867117395Skansecond regular expression @strong{and} etc. 6868117395Skan 6869117395Skan@item 6870117395Skan@samp{*} is used for convenience and simply means a sequence in which 6871117395Skanthe regular expression are repeated @var{number} times with cycle 6872117395Skanadvancing (see @samp{,}). 6873117395Skan 6874117395Skan@item 6875117395Skan@samp{cpu_function_unit_name} denotes reservation of the named 6876117395Skanfunctional unit. 6877117395Skan 6878117395Skan@item 6879117395Skan@samp{reservation_name} --- see description of construction 6880117395Skan@samp{define_reservation}. 6881117395Skan 6882117395Skan@item 6883117395Skan@samp{nothing} denotes no unit reservations. 6884117395Skan@end itemize 6885117395Skan 6886117395Skan@findex define_reservation 6887117395SkanSometimes unit reservations for different insns contain common parts. 6888117395SkanIn such case, you can simplify the pipeline description by describing 6889117395Skanthe common part by the following construction 6890117395Skan 6891117395Skan@smallexample 6892117395Skan(define_reservation @var{reservation-name} @var{regexp}) 6893117395Skan@end smallexample 6894117395Skan 6895117395Skan@var{reservation-name} is a string giving name of @var{regexp}. 6896117395SkanFunctional unit names and reservation names are in the same name 6897117395Skanspace. So the reservation names should be different from the 6898119256Skanfunctional unit names and can not be the reserved name @samp{nothing}. 6899117395Skan 6900117395Skan@findex define_bypass 6901117395Skan@cindex instruction latency time 6902117395Skan@cindex data bypass 6903117395SkanThe following construction is used to describe exceptions in the 6904117395Skanlatency time for given instruction pair. This is so called bypasses. 6905117395Skan 6906117395Skan@smallexample 6907117395Skan(define_bypass @var{number} @var{out_insn_names} @var{in_insn_names} 6908117395Skan [@var{guard}]) 6909117395Skan@end smallexample 6910117395Skan 6911117395Skan@var{number} defines when the result generated by the instructions 6912117395Skangiven in string @var{out_insn_names} will be ready for the 6913117395Skaninstructions given in string @var{in_insn_names}. The instructions in 6914117395Skanthe string are separated by commas. 6915117395Skan 6916117395Skan@var{guard} is an optional string giving the name of a C function which 6917117395Skandefines an additional guard for the bypass. The function will get the 6918117395Skantwo insns as parameters. If the function returns zero the bypass will 6919117395Skanbe ignored for this case. The additional guard is necessary to 6920169689Skanrecognize complicated bypasses, e.g.@: when the consumer is only an address 6921117395Skanof insn @samp{store} (not a stored value). 6922117395Skan 6923117395Skan@findex exclusion_set 6924117395Skan@findex presence_set 6925132718Skan@findex final_presence_set 6926117395Skan@findex absence_set 6927132718Skan@findex final_absence_set 6928117395Skan@cindex VLIW 6929117395Skan@cindex RISC 6930132718SkanThe following five constructions are usually used to describe 6931132718Skan@acronym{VLIW} processors, or more precisely, to describe a placement 6932132718Skanof small instructions into @acronym{VLIW} instruction slots. They 6933132718Skancan be used for @acronym{RISC} processors, too. 6934117395Skan 6935117395Skan@smallexample 6936117395Skan(exclusion_set @var{unit-names} @var{unit-names}) 6937132718Skan(presence_set @var{unit-names} @var{patterns}) 6938132718Skan(final_presence_set @var{unit-names} @var{patterns}) 6939132718Skan(absence_set @var{unit-names} @var{patterns}) 6940132718Skan(final_absence_set @var{unit-names} @var{patterns}) 6941117395Skan@end smallexample 6942117395Skan 6943117395Skan@var{unit-names} is a string giving names of functional units 6944117395Skanseparated by commas. 6945117395Skan 6946132718Skan@var{patterns} is a string giving patterns of functional units 6947169689Skanseparated by comma. Currently pattern is one unit or units 6948132718Skanseparated by white-spaces. 6949132718Skan 6950117395SkanThe first construction (@samp{exclusion_set}) means that each 6951117395Skanfunctional unit in the first string can not be reserved simultaneously 6952117395Skanwith a unit whose name is in the second string and vice versa. For 6953117395Skanexample, the construction is useful for describing processors 6954169689Skan(e.g.@: some SPARC processors) with a fully pipelined floating point 6955117395Skanfunctional unit which can execute simultaneously only single floating 6956117395Skanpoint insns or only double floating point insns. 6957117395Skan 6958117395SkanThe second construction (@samp{presence_set}) means that each 6959117395Skanfunctional unit in the first string can not be reserved unless at 6960132718Skanleast one of pattern of units whose names are in the second string is 6961132718Skanreserved. This is an asymmetric relation. For example, it is useful 6962132718Skanfor description that @acronym{VLIW} @samp{slot1} is reserved after 6963132718Skan@samp{slot0} reservation. We could describe it by the following 6964132718Skanconstruction 6965117395Skan 6966132718Skan@smallexample 6967132718Skan(presence_set "slot1" "slot0") 6968132718Skan@end smallexample 6969117395Skan 6970132718SkanOr @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0} 6971132718Skanreservation. In this case we could write 6972132718Skan 6973132718Skan@smallexample 6974132718Skan(presence_set "slot1" "slot0 b0") 6975132718Skan@end smallexample 6976132718Skan 6977132718SkanThe third construction (@samp{final_presence_set}) is analogous to 6978132718Skan@samp{presence_set}. The difference between them is when checking is 6979132718Skandone. When an instruction is issued in given automaton state 6980132718Skanreflecting all current and planned unit reservations, the automaton 6981132718Skanstate is changed. The first state is a source state, the second one 6982132718Skanis a result state. Checking for @samp{presence_set} is done on the 6983132718Skansource state reservation, checking for @samp{final_presence_set} is 6984132718Skandone on the result reservation. This construction is useful to 6985132718Skandescribe a reservation which is actually two subsequent reservations. 6986132718SkanFor example, if we use 6987132718Skan 6988132718Skan@smallexample 6989132718Skan(presence_set "slot1" "slot0") 6990132718Skan@end smallexample 6991132718Skan 6992132718Skanthe following insn will be never issued (because @samp{slot1} requires 6993132718Skan@samp{slot0} which is absent in the source state). 6994132718Skan 6995132718Skan@smallexample 6996132718Skan(define_reservation "insn_and_nop" "slot0 + slot1") 6997132718Skan@end smallexample 6998132718Skan 6999132718Skanbut it can be issued if we use analogous @samp{final_presence_set}. 7000132718Skan 7001132718SkanThe forth construction (@samp{absence_set}) means that each functional 7002132718Skanunit in the first string can be reserved only if each pattern of units 7003132718Skanwhose names are in the second string is not reserved. This is an 7004132718Skanasymmetric relation (actually @samp{exclusion_set} is analogous to 7005169689Skanthis one but it is symmetric). For example it might be useful in a 7006169689Skan@acronym{VLIW} description to say that @samp{slot0} cannot be reserved 7007169689Skanafter either @samp{slot1} or @samp{slot2} have been reserved. This 7008169689Skancan be described as: 7009132718Skan 7010132718Skan@smallexample 7011169689Skan(absence_set "slot0" "slot1, slot2") 7012132718Skan@end smallexample 7013132718Skan 7014132718SkanOr @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0} 7015132718Skanare reserved or @samp{slot1} and unit @samp{b1} are reserved. In 7016132718Skanthis case we could write 7017132718Skan 7018132718Skan@smallexample 7019132718Skan(absence_set "slot2" "slot0 b0, slot1 b1") 7020132718Skan@end smallexample 7021132718Skan 7022117395SkanAll functional units mentioned in a set should belong to the same 7023117395Skanautomaton. 7024117395Skan 7025132718SkanThe last construction (@samp{final_absence_set}) is analogous to 7026132718Skan@samp{absence_set} but checking is done on the result (state) 7027132718Skanreservation. See comments for @samp{final_presence_set}. 7028132718Skan 7029117395Skan@findex automata_option 7030117395Skan@cindex deterministic finite state automaton 7031117395Skan@cindex nondeterministic finite state automaton 7032117395Skan@cindex finite state automaton minimization 7033117395SkanYou can control the generator of the pipeline hazard recognizer with 7034117395Skanthe following construction. 7035117395Skan 7036117395Skan@smallexample 7037117395Skan(automata_option @var{options}) 7038117395Skan@end smallexample 7039117395Skan 7040117395Skan@var{options} is a string giving options which affect the generated 7041117395Skancode. Currently there are the following options: 7042117395Skan 7043117395Skan@itemize @bullet 7044117395Skan@item 7045117395Skan@dfn{no-minimization} makes no minimization of the automaton. This is 7046119256Skanonly worth to do when we are debugging the description and need to 7047119256Skanlook more accurately at reservations of states. 7048117395Skan 7049117395Skan@item 7050117395Skan@dfn{time} means printing additional time statistics about 7051117395Skangeneration of automata. 7052117395Skan 7053117395Skan@item 7054117395Skan@dfn{v} means a generation of the file describing the result automata. 7055117395SkanThe file has suffix @samp{.dfa} and can be used for the description 7056117395Skanverification and debugging. 7057117395Skan 7058117395Skan@item 7059117395Skan@dfn{w} means a generation of warning instead of error for 7060117395Skannon-critical errors. 7061117395Skan 7062117395Skan@item 7063117395Skan@dfn{ndfa} makes nondeterministic finite state automata. This affects 7064117395Skanthe treatment of operator @samp{|} in the regular expressions. The 7065117395Skanusual treatment of the operator is to try the first alternative and, 7066117395Skanif the reservation is not possible, the second alternative. The 7067117395Skannondeterministic treatment means trying all alternatives, some of them 7068169689Skanmay be rejected by reservations in the subsequent insns. 7069132718Skan 7070132718Skan@item 7071132718Skan@dfn{progress} means output of a progress bar showing how many states 7072132718Skanwere generated so far for automaton being processed. This is useful 7073132718Skanduring debugging a @acronym{DFA} description. If you see too many 7074132718Skangenerated states, you could interrupt the generator of the pipeline 7075132718Skanhazard recognizer and try to figure out a reason for generation of the 7076132718Skanhuge automaton. 7077117395Skan@end itemize 7078117395Skan 7079117395SkanAs an example, consider a superscalar @acronym{RISC} machine which can 7080117395Skanissue three insns (two integer insns and one floating point insn) on 7081117395Skanthe cycle but can finish only two insns. To describe this, we define 7082117395Skanthe following functional units. 7083117395Skan 7084117395Skan@smallexample 7085117395Skan(define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline") 7086117395Skan(define_cpu_unit "port0, port1") 7087117395Skan@end smallexample 7088117395Skan 7089117395SkanAll simple integer insns can be executed in any integer pipeline and 7090117395Skantheir result is ready in two cycles. The simple integer insns are 7091117395Skanissued into the first pipeline unless it is reserved, otherwise they 7092117395Skanare issued into the second pipeline. Integer division and 7093117395Skanmultiplication insns can be executed only in the second integer 7094117395Skanpipeline and their results are ready correspondingly in 8 and 4 7095169689Skancycles. The integer division is not pipelined, i.e.@: the subsequent 7096117395Skaninteger division insn can not be issued until the current division 7097117395Skaninsn finished. Floating point insns are fully pipelined and their 7098117395Skanresults are ready in 3 cycles. Where the result of a floating point 7099117395Skaninsn is used by an integer insn, an additional delay of one cycle is 7100117395Skanincurred. To describe all of this we could specify 7101117395Skan 7102117395Skan@smallexample 7103117395Skan(define_cpu_unit "div") 7104117395Skan 7105117395Skan(define_insn_reservation "simple" 2 (eq_attr "type" "int") 7106117395Skan "(i0_pipeline | i1_pipeline), (port0 | port1)") 7107117395Skan 7108117395Skan(define_insn_reservation "mult" 4 (eq_attr "type" "mult") 7109117395Skan "i1_pipeline, nothing*2, (port0 | port1)") 7110117395Skan 7111117395Skan(define_insn_reservation "div" 8 (eq_attr "type" "div") 7112117395Skan "i1_pipeline, div*7, div + (port0 | port1)") 7113117395Skan 7114117395Skan(define_insn_reservation "float" 3 (eq_attr "type" "float") 7115117395Skan "f_pipeline, nothing, (port0 | port1)) 7116117395Skan 7117117395Skan(define_bypass 4 "float" "simple,mult,div") 7118117395Skan@end smallexample 7119117395Skan 7120117395SkanTo simplify the description we could describe the following reservation 7121117395Skan 7122117395Skan@smallexample 7123117395Skan(define_reservation "finish" "port0|port1") 7124117395Skan@end smallexample 7125117395Skan 7126117395Skanand use it in all @code{define_insn_reservation} as in the following 7127117395Skanconstruction 7128117395Skan 7129117395Skan@smallexample 7130117395Skan(define_insn_reservation "simple" 2 (eq_attr "type" "int") 7131117395Skan "(i0_pipeline | i1_pipeline), finish") 7132117395Skan@end smallexample 7133117395Skan 7134117395Skan 7135132718Skan@end ifset 7136132718Skan@ifset INTERNALS 713790075Sobrien@node Conditional Execution 713890075Sobrien@section Conditional Execution 713990075Sobrien@cindex conditional execution 714090075Sobrien@cindex predication 714190075Sobrien 714290075SobrienA number of architectures provide for some form of conditional 714390075Sobrienexecution, or predication. The hallmark of this feature is the 714490075Sobrienability to nullify most of the instructions in the instruction set. 714590075SobrienWhen the instruction set is large and not entirely symmetric, it 714690075Sobriencan be quite tedious to describe these forms directly in the 714790075Sobrien@file{.md} file. An alternative is the @code{define_cond_exec} template. 714890075Sobrien 714990075Sobrien@findex define_cond_exec 715090075Sobrien@smallexample 715190075Sobrien(define_cond_exec 715290075Sobrien [@var{predicate-pattern}] 715390075Sobrien "@var{condition}" 715490075Sobrien "@var{output-template}") 715590075Sobrien@end smallexample 715690075Sobrien 715790075Sobrien@var{predicate-pattern} is the condition that must be true for the 715890075Sobrieninsn to be executed at runtime and should match a relational operator. 715990075SobrienOne can use @code{match_operator} to match several relational operators 716090075Sobrienat once. Any @code{match_operand} operands must have no more than one 716190075Sobrienalternative. 716290075Sobrien 716390075Sobrien@var{condition} is a C expression that must be true for the generated 716490075Sobrienpattern to match. 716590075Sobrien 716690075Sobrien@findex current_insn_predicate 716790075Sobrien@var{output-template} is a string similar to the @code{define_insn} 716890075Sobrienoutput template (@pxref{Output Template}), except that the @samp{*} 716990075Sobrienand @samp{@@} special cases do not apply. This is only useful if the 717090075Sobrienassembly text for the predicate is a simple prefix to the main insn. 717190075SobrienIn order to handle the general case, there is a global variable 717290075Sobrien@code{current_insn_predicate} that will contain the entire predicate 717390075Sobrienif the current insn is predicated, and will otherwise be @code{NULL}. 717490075Sobrien 717590075SobrienWhen @code{define_cond_exec} is used, an implicit reference to 717690075Sobrienthe @code{predicable} instruction attribute is made. 717790075Sobrien@xref{Insn Attributes}. This attribute must be boolean (i.e.@: have 717890075Sobrienexactly two elements in its @var{list-of-values}). Further, it must 717990075Sobriennot be used with complex expressions. That is, the default and all 718090075Sobrienuses in the insns must be a simple constant, not dependent on the 718190075Sobrienalternative or anything else. 718290075Sobrien 718390075SobrienFor each @code{define_insn} for which the @code{predicable} 718490075Sobrienattribute is true, a new @code{define_insn} pattern will be 718590075Sobriengenerated that matches a predicated version of the instruction. 718690075SobrienFor example, 718790075Sobrien 718890075Sobrien@smallexample 718990075Sobrien(define_insn "addsi" 719090075Sobrien [(set (match_operand:SI 0 "register_operand" "r") 719190075Sobrien (plus:SI (match_operand:SI 1 "register_operand" "r") 719290075Sobrien (match_operand:SI 2 "register_operand" "r")))] 719390075Sobrien "@var{test1}" 719490075Sobrien "add %2,%1,%0") 719590075Sobrien 719690075Sobrien(define_cond_exec 719790075Sobrien [(ne (match_operand:CC 0 "register_operand" "c") 719890075Sobrien (const_int 0))] 719990075Sobrien "@var{test2}" 720090075Sobrien "(%0)") 720190075Sobrien@end smallexample 720290075Sobrien 720390075Sobrien@noindent 720490075Sobriengenerates a new pattern 720590075Sobrien 720690075Sobrien@smallexample 720790075Sobrien(define_insn "" 720890075Sobrien [(cond_exec 720990075Sobrien (ne (match_operand:CC 3 "register_operand" "c") (const_int 0)) 721090075Sobrien (set (match_operand:SI 0 "register_operand" "r") 721190075Sobrien (plus:SI (match_operand:SI 1 "register_operand" "r") 721290075Sobrien (match_operand:SI 2 "register_operand" "r"))))] 721390075Sobrien "(@var{test2}) && (@var{test1})" 721490075Sobrien "(%3) add %2,%1,%0") 721590075Sobrien@end smallexample 721690075Sobrien 7217132718Skan@end ifset 7218132718Skan@ifset INTERNALS 721990075Sobrien@node Constant Definitions 722090075Sobrien@section Constant Definitions 722190075Sobrien@cindex constant definitions 722290075Sobrien@findex define_constants 722390075Sobrien 722490075SobrienUsing literal constants inside instruction patterns reduces legibility and 722590075Sobriencan be a maintenance problem. 722690075Sobrien 722790075SobrienTo overcome this problem, you may use the @code{define_constants} 722890075Sobrienexpression. It contains a vector of name-value pairs. From that 722990075Sobrienpoint on, wherever any of the names appears in the MD file, it is as 723090075Sobrienif the corresponding value had been written instead. You may use 723190075Sobrien@code{define_constants} multiple times; each appearance adds more 723290075Sobrienconstants to the table. It is an error to redefine a constant with 723390075Sobriena different value. 723490075Sobrien 723590075SobrienTo come back to the a29k load multiple example, instead of 723690075Sobrien 723790075Sobrien@smallexample 723890075Sobrien(define_insn "" 723990075Sobrien [(match_parallel 0 "load_multiple_operation" 724090075Sobrien [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 724190075Sobrien (match_operand:SI 2 "memory_operand" "m")) 724290075Sobrien (use (reg:SI 179)) 724390075Sobrien (clobber (reg:SI 179))])] 724490075Sobrien "" 724590075Sobrien "loadm 0,0,%1,%2") 724690075Sobrien@end smallexample 724790075Sobrien 724890075SobrienYou could write: 724990075Sobrien 725090075Sobrien@smallexample 725190075Sobrien(define_constants [ 725290075Sobrien (R_BP 177) 725390075Sobrien (R_FC 178) 725490075Sobrien (R_CR 179) 725590075Sobrien (R_Q 180) 725690075Sobrien]) 725790075Sobrien 725890075Sobrien(define_insn "" 725990075Sobrien [(match_parallel 0 "load_multiple_operation" 726090075Sobrien [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 726190075Sobrien (match_operand:SI 2 "memory_operand" "m")) 726290075Sobrien (use (reg:SI R_CR)) 726390075Sobrien (clobber (reg:SI R_CR))])] 726490075Sobrien "" 726590075Sobrien "loadm 0,0,%1,%2") 726690075Sobrien@end smallexample 726790075Sobrien 726890075SobrienThe constants that are defined with a define_constant are also output 726990075Sobrienin the insn-codes.h header file as #defines. 727090075Sobrien@end ifset 7271169689Skan@ifset INTERNALS 7272169689Skan@node Macros 7273169689Skan@section Macros 7274169689Skan@cindex macros in @file{.md} files 7275169689Skan 7276169689SkanPorts often need to define similar patterns for more than one machine 7277169689Skanmode or for more than one rtx code. GCC provides some simple macro 7278169689Skanfacilities to make this process easier. 7279169689Skan 7280169689Skan@menu 7281169689Skan* Mode Macros:: Generating variations of patterns for different modes. 7282169689Skan* Code Macros:: Doing the same for codes. 7283169689Skan@end menu 7284169689Skan 7285169689Skan@node Mode Macros 7286169689Skan@subsection Mode Macros 7287169689Skan@cindex mode macros in @file{.md} files 7288169689Skan 7289169689SkanPorts often need to define similar patterns for two or more different modes. 7290169689SkanFor example: 7291169689Skan 7292169689Skan@itemize @bullet 7293169689Skan@item 7294169689SkanIf a processor has hardware support for both single and double 7295169689Skanfloating-point arithmetic, the @code{SFmode} patterns tend to be 7296169689Skanvery similar to the @code{DFmode} ones. 7297169689Skan 7298169689Skan@item 7299169689SkanIf a port uses @code{SImode} pointers in one configuration and 7300169689Skan@code{DImode} pointers in another, it will usually have very similar 7301169689Skan@code{SImode} and @code{DImode} patterns for manipulating pointers. 7302169689Skan@end itemize 7303169689Skan 7304169689SkanMode macros allow several patterns to be instantiated from one 7305169689Skan@file{.md} file template. They can be used with any type of 7306169689Skanrtx-based construct, such as a @code{define_insn}, 7307169689Skan@code{define_split}, or @code{define_peephole2}. 7308169689Skan 7309169689Skan@menu 7310169689Skan* Defining Mode Macros:: Defining a new mode macro. 7311169689Skan* Substitutions:: Combining mode macros with substitutions 7312169689Skan* Examples:: Examples 7313169689Skan@end menu 7314169689Skan 7315169689Skan@node Defining Mode Macros 7316169689Skan@subsubsection Defining Mode Macros 7317169689Skan@findex define_mode_macro 7318169689Skan 7319169689SkanThe syntax for defining a mode macro is: 7320169689Skan 7321169689Skan@smallexample 7322169689Skan(define_mode_macro @var{name} [(@var{mode1} "@var{cond1}") ... (@var{moden} "@var{condn}")]) 7323169689Skan@end smallexample 7324169689Skan 7325169689SkanThis allows subsequent @file{.md} file constructs to use the mode suffix 7326169689Skan@code{:@var{name}}. Every construct that does so will be expanded 7327169689Skan@var{n} times, once with every use of @code{:@var{name}} replaced by 7328169689Skan@code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}}, 7329169689Skanand so on. In the expansion for a particular @var{modei}, every 7330169689SkanC condition will also require that @var{condi} be true. 7331169689Skan 7332169689SkanFor example: 7333169689Skan 7334169689Skan@smallexample 7335169689Skan(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) 7336169689Skan@end smallexample 7337169689Skan 7338169689Skandefines a new mode suffix @code{:P}. Every construct that uses 7339169689Skan@code{:P} will be expanded twice, once with every @code{:P} replaced 7340169689Skanby @code{:SI} and once with every @code{:P} replaced by @code{:DI}. 7341169689SkanThe @code{:SI} version will only apply if @code{Pmode == SImode} and 7342169689Skanthe @code{:DI} version will only apply if @code{Pmode == DImode}. 7343169689Skan 7344169689SkanAs with other @file{.md} conditions, an empty string is treated 7345169689Skanas ``always true''. @code{(@var{mode} "")} can also be abbreviated 7346169689Skanto @code{@var{mode}}. For example: 7347169689Skan 7348169689Skan@smallexample 7349169689Skan(define_mode_macro GPR [SI (DI "TARGET_64BIT")]) 7350169689Skan@end smallexample 7351169689Skan 7352169689Skanmeans that the @code{:DI} expansion only applies if @code{TARGET_64BIT} 7353169689Skanbut that the @code{:SI} expansion has no such constraint. 7354169689Skan 7355169689SkanMacros are applied in the order they are defined. This can be 7356169689Skansignificant if two macros are used in a construct that requires 7357169689Skansubstitutions. @xref{Substitutions}. 7358169689Skan 7359169689Skan@node Substitutions 7360169689Skan@subsubsection Substitution in Mode Macros 7361169689Skan@findex define_mode_attr 7362169689Skan 7363169689SkanIf an @file{.md} file construct uses mode macros, each version of the 7364169689Skanconstruct will often need slightly different strings or modes. For 7365169689Skanexample: 7366169689Skan 7367169689Skan@itemize @bullet 7368169689Skan@item 7369169689SkanWhen a @code{define_expand} defines several @code{add@var{m}3} patterns 7370169689Skan(@pxref{Standard Names}), each expander will need to use the 7371169689Skanappropriate mode name for @var{m}. 7372169689Skan 7373169689Skan@item 7374169689SkanWhen a @code{define_insn} defines several instruction patterns, 7375169689Skaneach instruction will often use a different assembler mnemonic. 7376169689Skan 7377169689Skan@item 7378169689SkanWhen a @code{define_insn} requires operands with different modes, 7379169689Skanusing a macro for one of the operand modes usually requires a specific 7380169689Skanmode for the other operand(s). 7381169689Skan@end itemize 7382169689Skan 7383169689SkanGCC supports such variations through a system of ``mode attributes''. 7384169689SkanThere are two standard attributes: @code{mode}, which is the name of 7385169689Skanthe mode in lower case, and @code{MODE}, which is the same thing in 7386169689Skanupper case. You can define other attributes using: 7387169689Skan 7388169689Skan@smallexample 7389169689Skan(define_mode_attr @var{name} [(@var{mode1} "@var{value1}") ... (@var{moden} "@var{valuen}")]) 7390169689Skan@end smallexample 7391169689Skan 7392169689Skanwhere @var{name} is the name of the attribute and @var{valuei} 7393169689Skanis the value associated with @var{modei}. 7394169689Skan 7395169689SkanWhen GCC replaces some @var{:macro} with @var{:mode}, it will scan 7396169689Skaneach string and mode in the pattern for sequences of the form 7397169689Skan@code{<@var{macro}:@var{attr}>}, where @var{attr} is the name of a 7398169689Skanmode attribute. If the attribute is defined for @var{mode}, the whole 7399169689Skan@code{<...>} sequence will be replaced by the appropriate attribute 7400169689Skanvalue. 7401169689Skan 7402169689SkanFor example, suppose an @file{.md} file has: 7403169689Skan 7404169689Skan@smallexample 7405169689Skan(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) 7406169689Skan(define_mode_attr load [(SI "lw") (DI "ld")]) 7407169689Skan@end smallexample 7408169689Skan 7409169689SkanIf one of the patterns that uses @code{:P} contains the string 7410169689Skan@code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern 7411169689Skanwill use @code{"lw\t%0,%1"} and the @code{DI} version will use 7412169689Skan@code{"ld\t%0,%1"}. 7413169689Skan 7414169689SkanHere is an example of using an attribute for a mode: 7415169689Skan 7416169689Skan@smallexample 7417169689Skan(define_mode_macro LONG [SI DI]) 7418169689Skan(define_mode_attr SHORT [(SI "HI") (DI "SI")]) 7419169689Skan(define_insn ... 7420169689Skan (sign_extend:LONG (match_operand:<LONG:SHORT> ...)) ...) 7421169689Skan@end smallexample 7422169689Skan 7423169689SkanThe @code{@var{macro}:} prefix may be omitted, in which case the 7424169689Skansubstitution will be attempted for every macro expansion. 7425169689Skan 7426169689Skan@node Examples 7427169689Skan@subsubsection Mode Macro Examples 7428169689Skan 7429169689SkanHere is an example from the MIPS port. It defines the following 7430169689Skanmodes and attributes (among others): 7431169689Skan 7432169689Skan@smallexample 7433169689Skan(define_mode_macro GPR [SI (DI "TARGET_64BIT")]) 7434169689Skan(define_mode_attr d [(SI "") (DI "d")]) 7435169689Skan@end smallexample 7436169689Skan 7437169689Skanand uses the following template to define both @code{subsi3} 7438169689Skanand @code{subdi3}: 7439169689Skan 7440169689Skan@smallexample 7441169689Skan(define_insn "sub<mode>3" 7442169689Skan [(set (match_operand:GPR 0 "register_operand" "=d") 7443169689Skan (minus:GPR (match_operand:GPR 1 "register_operand" "d") 7444169689Skan (match_operand:GPR 2 "register_operand" "d")))] 7445169689Skan "" 7446169689Skan "<d>subu\t%0,%1,%2" 7447169689Skan [(set_attr "type" "arith") 7448169689Skan (set_attr "mode" "<MODE>")]) 7449169689Skan@end smallexample 7450169689Skan 7451169689SkanThis is exactly equivalent to: 7452169689Skan 7453169689Skan@smallexample 7454169689Skan(define_insn "subsi3" 7455169689Skan [(set (match_operand:SI 0 "register_operand" "=d") 7456169689Skan (minus:SI (match_operand:SI 1 "register_operand" "d") 7457169689Skan (match_operand:SI 2 "register_operand" "d")))] 7458169689Skan "" 7459169689Skan "subu\t%0,%1,%2" 7460169689Skan [(set_attr "type" "arith") 7461169689Skan (set_attr "mode" "SI")]) 7462169689Skan 7463169689Skan(define_insn "subdi3" 7464169689Skan [(set (match_operand:DI 0 "register_operand" "=d") 7465169689Skan (minus:DI (match_operand:DI 1 "register_operand" "d") 7466169689Skan (match_operand:DI 2 "register_operand" "d")))] 7467169689Skan "" 7468169689Skan "dsubu\t%0,%1,%2" 7469169689Skan [(set_attr "type" "arith") 7470169689Skan (set_attr "mode" "DI")]) 7471169689Skan@end smallexample 7472169689Skan 7473169689Skan@node Code Macros 7474169689Skan@subsection Code Macros 7475169689Skan@cindex code macros in @file{.md} files 7476169689Skan@findex define_code_macro 7477169689Skan@findex define_code_attr 7478169689Skan 7479169689SkanCode macros operate in a similar way to mode macros. @xref{Mode Macros}. 7480169689Skan 7481169689SkanThe construct: 7482169689Skan 7483169689Skan@smallexample 7484169689Skan(define_code_macro @var{name} [(@var{code1} "@var{cond1}") ... (@var{coden} "@var{condn}")]) 7485169689Skan@end smallexample 7486169689Skan 7487169689Skandefines a pseudo rtx code @var{name} that can be instantiated as 7488169689Skan@var{codei} if condition @var{condi} is true. Each @var{codei} 7489169689Skanmust have the same rtx format. @xref{RTL Classes}. 7490169689Skan 7491169689SkanAs with mode macros, each pattern that uses @var{name} will be 7492169689Skanexpanded @var{n} times, once with all uses of @var{name} replaced by 7493169689Skan@var{code1}, once with all uses replaced by @var{code2}, and so on. 7494169689Skan@xref{Defining Mode Macros}. 7495169689Skan 7496169689SkanIt is possible to define attributes for codes as well as for modes. 7497169689SkanThere are two standard code attributes: @code{code}, the name of the 7498169689Skancode in lower case, and @code{CODE}, the name of the code in upper case. 7499169689SkanOther attributes are defined using: 7500169689Skan 7501169689Skan@smallexample 7502169689Skan(define_code_attr @var{name} [(@var{code1} "@var{value1}") ... (@var{coden} "@var{valuen}")]) 7503169689Skan@end smallexample 7504169689Skan 7505169689SkanHere's an example of code macros in action, taken from the MIPS port: 7506169689Skan 7507169689Skan@smallexample 7508169689Skan(define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt 7509169689Skan eq ne gt ge lt le gtu geu ltu leu]) 7510169689Skan 7511169689Skan(define_expand "b<code>" 7512169689Skan [(set (pc) 7513169689Skan (if_then_else (any_cond:CC (cc0) 7514169689Skan (const_int 0)) 7515169689Skan (label_ref (match_operand 0 "")) 7516169689Skan (pc)))] 7517169689Skan "" 7518169689Skan@{ 7519169689Skan gen_conditional_branch (operands, <CODE>); 7520169689Skan DONE; 7521169689Skan@}) 7522169689Skan@end smallexample 7523169689Skan 7524169689SkanThis is equivalent to: 7525169689Skan 7526169689Skan@smallexample 7527169689Skan(define_expand "bunordered" 7528169689Skan [(set (pc) 7529169689Skan (if_then_else (unordered:CC (cc0) 7530169689Skan (const_int 0)) 7531169689Skan (label_ref (match_operand 0 "")) 7532169689Skan (pc)))] 7533169689Skan "" 7534169689Skan@{ 7535169689Skan gen_conditional_branch (operands, UNORDERED); 7536169689Skan DONE; 7537169689Skan@}) 7538169689Skan 7539169689Skan(define_expand "bordered" 7540169689Skan [(set (pc) 7541169689Skan (if_then_else (ordered:CC (cc0) 7542169689Skan (const_int 0)) 7543169689Skan (label_ref (match_operand 0 "")) 7544169689Skan (pc)))] 7545169689Skan "" 7546169689Skan@{ 7547169689Skan gen_conditional_branch (operands, ORDERED); 7548169689Skan DONE; 7549169689Skan@}) 7550169689Skan 7551169689Skan... 7552169689Skan@end smallexample 7553169689Skan 7554169689Skan@end ifset 7555