2084.md revision 169689
1;; Scheduling description for z990 (cpu 2084). 2;; Copyright (C) 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 3;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and 4;; Ulrich Weigand (uweigand@de.ibm.com). 5 6;; This file is part of GCC. 7 8;; GCC is free software; you can redistribute it and/or modify it under 9;; the terms of the GNU General Public License as published by the Free 10;; Software Foundation; either version 2, or (at your option) any later 11;; version. 12 13;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 14;; WARRANTY; without even the implied warranty of MERCHANTABILITY or 15;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16;; for more details. 17 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING. If not, write to the Free 20;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 21;; 02110-1301, USA. 22 23(define_automaton "x_ipu") 24 25(define_cpu_unit "x_e1_r,x_e1_s,x_e1_t" "x_ipu") 26(define_cpu_unit "x_wr_r,x_wr_s,x_wr_t,x_wr_fp" "x_ipu") 27(define_cpu_unit "x_s1,x_s2,x_s3,x_s4" "x_ipu") 28(define_cpu_unit "x_t1,x_t2,x_t3,x_t4" "x_ipu") 29(define_cpu_unit "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6" "x_ipu") 30(define_cpu_unit "x_store_tok" "x_ipu") 31(define_cpu_unit "x_ms,x_mt" "x_ipu") 32 33(define_reservation "x-e1-st" "(x_e1_s | x_e1_t)") 34 35(define_reservation "x-e1-np" "(x_e1_r + x_e1_s + x_e1_t)") 36 37(absence_set "x_e1_r" "x_e1_s,x_e1_t") 38(absence_set "x_e1_s" "x_e1_t") 39 40;; Try to avoid int <-> fp transitions. 41 42(define_reservation "x-x" "x_s1|x_t1,x_s2|x_t2,x_s3|x_t3,x_s4|x_t4") 43(define_reservation "x-f" "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6") 44(define_reservation "x-wr-st" "((x_wr_s | x_wr_t),x-x)") 45(define_reservation "x-wr-np" "((x_wr_r + x_wr_s + x_wr_t),x-x)") 46(define_reservation "x-wr-fp" "x_wr_fp,x-f") 47(define_reservation "x-mem" "x_ms|x_mt") 48 49(absence_set "x_wr_fp" 50 "x_s1,x_s2,x_s3,x_s4,x_t1,x_t2,x_t3,x_t4,x_wr_s,x_wr_t") 51 52(absence_set "x_e1_r,x_wr_r,x_wr_s,x_wr_t" 53 "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6,x_wr_fp") 54 55;; Don't have any load type insn in same group as store 56 57(absence_set "x_ms,x_mt" "x_store_tok") 58 59 60;; 61;; Simple insns 62;; 63 64(define_insn_reservation "x_int" 1 65 (and (eq_attr "cpu" "z990,z9_109") 66 (and (eq_attr "type" "integer") 67 (eq_attr "atype" "reg"))) 68 "x-e1-st,x-wr-st") 69 70(define_insn_reservation "x_agen" 1 71 (and (eq_attr "cpu" "z990,z9_109") 72 (and (eq_attr "type" "integer") 73 (eq_attr "atype" "agen"))) 74 "x-e1-st,x-wr-st") 75 76(define_insn_reservation "x_lr" 1 77 (and (eq_attr "cpu" "z990,z9_109") 78 (eq_attr "type" "lr")) 79 "x-e1-st,x-wr-st") 80 81(define_insn_reservation "x_la" 1 82 (and (eq_attr "cpu" "z990,z9_109") 83 (eq_attr "type" "la")) 84 "x-e1-st,x-wr-st") 85 86(define_insn_reservation "x_larl" 1 87 (and (eq_attr "cpu" "z990,z9_109") 88 (eq_attr "type" "larl")) 89 "x-e1-st,x-wr-st") 90 91(define_insn_reservation "x_load" 1 92 (and (eq_attr "cpu" "z990,z9_109") 93 (eq_attr "type" "load")) 94 "x-e1-st+x-mem,x-wr-st") 95 96(define_insn_reservation "x_store" 1 97 (and (eq_attr "cpu" "z990,z9_109") 98 (eq_attr "type" "store")) 99 "x-e1-st+x_store_tok,x-wr-st") 100 101(define_insn_reservation "x_branch" 1 102 (and (eq_attr "cpu" "z990,z9_109") 103 (eq_attr "type" "branch")) 104 "x_e1_r,x_wr_r") 105 106(define_insn_reservation "x_call" 5 107 (and (eq_attr "cpu" "z990,z9_109") 108 (eq_attr "type" "jsr")) 109 "x-e1-np*5,x-wr-np") 110 111(define_insn_reservation "x_mul_hi" 2 112 (and (eq_attr "cpu" "z990,z9_109") 113 (eq_attr "type" "imulhi")) 114 "x-e1-np*2,x-wr-np") 115 116(define_insn_reservation "x_mul_sidi" 4 117 (and (eq_attr "cpu" "z990,z9_109") 118 (eq_attr "type" "imulsi,imuldi")) 119 "x-e1-np*4,x-wr-np") 120 121(define_insn_reservation "x_div" 10 122 (and (eq_attr "cpu" "z990,z9_109") 123 (eq_attr "type" "idiv")) 124 "x-e1-np*10,x-wr-np") 125 126(define_insn_reservation "x_sem" 17 127 (and (eq_attr "cpu" "z990,z9_109") 128 (eq_attr "type" "sem")) 129 "x-e1-np+x-mem,x-e1-np*16,x-wr-st") 130 131;; 132;; Multicycle insns 133;; 134 135(define_insn_reservation "x_cs" 1 136 (and (eq_attr "cpu" "z990,z9_109") 137 (eq_attr "type" "cs")) 138 "x-e1-np,x-wr-np") 139 140(define_insn_reservation "x_vs" 1 141 (and (eq_attr "cpu" "z990,z9_109") 142 (eq_attr "type" "vs")) 143 "x-e1-np*10,x-wr-np") 144 145(define_insn_reservation "x_stm" 1 146 (and (eq_attr "cpu" "z990,z9_109") 147 (eq_attr "type" "stm")) 148 "(x-e1-np+x_store_tok)*10,x-wr-np") 149 150(define_insn_reservation "x_lm" 1 151 (and (eq_attr "cpu" "z990,z9_109") 152 (eq_attr "type" "lm")) 153 "x-e1-np*10,x-wr-np") 154 155(define_insn_reservation "x_other" 1 156 (and (eq_attr "cpu" "z990,z9_109") 157 (eq_attr "type" "other")) 158 "x-e1-np,x-wr-np") 159 160;; 161;; Floating point insns 162;; 163 164(define_insn_reservation "x_fsimptf" 7 165 (and (eq_attr "cpu" "z990,z9_109") 166 (eq_attr "type" "fsimptf")) 167 "x_e1_t*2,x-wr-fp") 168 169(define_insn_reservation "x_fsimpdf" 6 170 (and (eq_attr "cpu" "z990,z9_109") 171 (eq_attr "type" "fsimpdf,fmuldf")) 172 "x_e1_t,x-wr-fp") 173 174(define_insn_reservation "x_fsimpsf" 6 175 (and (eq_attr "cpu" "z990,z9_109") 176 (eq_attr "type" "fsimpsf,fmulsf")) 177 "x_e1_t,x-wr-fp") 178 179 180(define_insn_reservation "x_fmultf" 33 181 (and (eq_attr "cpu" "z990,z9_109") 182 (eq_attr "type" "fmultf")) 183 "x_e1_t*27,x-wr-fp") 184 185 186(define_insn_reservation "x_fdivtf" 82 187 (and (eq_attr "cpu" "z990,z9_109") 188 (eq_attr "type" "fdivtf,fsqrttf")) 189 "x_e1_t*76,x-wr-fp") 190 191(define_insn_reservation "x_fdivdf" 36 192 (and (eq_attr "cpu" "z990,z9_109") 193 (eq_attr "type" "fdivdf,fsqrtdf")) 194 "x_e1_t*30,x-wr-fp") 195 196(define_insn_reservation "x_fdivsf" 36 197 (and (eq_attr "cpu" "z990,z9_109") 198 (eq_attr "type" "fdivsf,fsqrtsf")) 199 "x_e1_t*30,x-wr-fp") 200 201 202(define_insn_reservation "x_floadtf" 6 203 (and (eq_attr "cpu" "z990,z9_109") 204 (eq_attr "type" "floadtf")) 205 "x_e1_t,x-wr-fp") 206 207(define_insn_reservation "x_floaddf" 6 208 (and (eq_attr "cpu" "z990,z9_109") 209 (eq_attr "type" "floaddf")) 210 "x_e1_t,x-wr-fp") 211 212(define_insn_reservation "x_floadsf" 6 213 (and (eq_attr "cpu" "z990,z9_109") 214 (eq_attr "type" "floadsf")) 215 "x_e1_t,x-wr-fp") 216 217 218(define_insn_reservation "x_fstoredf" 1 219 (and (eq_attr "cpu" "z990,z9_109") 220 (eq_attr "type" "fstoredf")) 221 "x_e1_t,x-wr-fp") 222 223(define_insn_reservation "x_fstoresf" 1 224 (and (eq_attr "cpu" "z990,z9_109") 225 (eq_attr "type" "fstoresf")) 226 "x_e1_t,x-wr-fp") 227 228 229(define_insn_reservation "x_ftrunctf" 16 230 (and (eq_attr "cpu" "z990,z9_109") 231 (eq_attr "type" "ftrunctf")) 232 "x_e1_t*10,x-wr-fp") 233 234(define_insn_reservation "x_ftruncdf" 11 235 (and (eq_attr "cpu" "z990,z9_109") 236 (eq_attr "type" "ftruncdf")) 237 "x_e1_t*5,x-wr-fp") 238 239 240(define_insn_reservation "x_ftoi" 1 241 (and (eq_attr "cpu" "z990,z9_109") 242 (eq_attr "type" "ftoi")) 243 "x_e1_t*3,x-wr-fp") 244 245(define_insn_reservation "x_itof" 7 246 (and (eq_attr "cpu" "z990,z9_109") 247 (eq_attr "type" "itof")) 248 "x_e1_t*3,x-wr-fp") 249 250(define_bypass 1 "x_fsimpdf" "x_fstoredf") 251 252(define_bypass 1 "x_fsimpsf" "x_fstoresf") 253 254(define_bypass 1 "x_floaddf" "x_fsimpdf,x_fstoredf,x_floaddf") 255 256(define_bypass 1 "x_floadsf" "x_fsimpsf,x_fstoresf,x_floadsf") 257 258;; 259;; s390_agen_dep_p returns 1, if a register is set in the 260;; first insn and used in the dependent insn to form a address. 261;; 262 263;; 264;; If an instruction uses a register to address memory, it needs 265;; to be set 5 cycles in advance. 266;; 267 268(define_bypass 5 "x_int,x_agen,x_lr" 269 "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" 270 "s390_agen_dep_p") 271 272(define_bypass 9 "x_int,x_agen,x_lr" 273 "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ 274 x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" 275 "s390_agen_dep_p") 276;; 277;; A load type instruction uses a bypass to feed the result back 278;; to the address generation pipeline stage. 279;; 280 281(define_bypass 4 "x_load" 282 "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" 283 "s390_agen_dep_p") 284 285(define_bypass 5 "x_load" 286 "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ 287 x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" 288 "s390_agen_dep_p") 289 290;; 291;; A load address type instruction uses a bypass to feed the 292;; result back to the address generation pipeline stage. 293;; 294 295(define_bypass 3 "x_larl,x_la" 296 "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" 297 "s390_agen_dep_p") 298 299(define_bypass 5 "x_larl, x_la" 300 "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ 301 x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" 302 "s390_agen_dep_p") 303 304;; 305;; Operand forwarding 306;; 307 308(define_bypass 0 "x_lr,x_la,x_load" "x_int,x_lr") 309 310 311