1132718Skan;; Scheduling description for z990 (cpu 2084). 2169689Skan;; Copyright (C) 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 3132718Skan;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and 4132718Skan;; Ulrich Weigand (uweigand@de.ibm.com). 5132718Skan 6132718Skan;; This file is part of GCC. 7132718Skan 8132718Skan;; GCC is free software; you can redistribute it and/or modify it under 9132718Skan;; the terms of the GNU General Public License as published by the Free 10132718Skan;; Software Foundation; either version 2, or (at your option) any later 11132718Skan;; version. 12132718Skan 13132718Skan;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 14132718Skan;; WARRANTY; without even the implied warranty of MERCHANTABILITY or 15132718Skan;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16132718Skan;; for more details. 17132718Skan 18132718Skan;; You should have received a copy of the GNU General Public License 19132718Skan;; along with GCC; see the file COPYING. If not, write to the Free 20169689Skan;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 21169689Skan;; 02110-1301, USA. 22132718Skan 23132718Skan(define_automaton "x_ipu") 24132718Skan 25132718Skan(define_cpu_unit "x_e1_r,x_e1_s,x_e1_t" "x_ipu") 26132718Skan(define_cpu_unit "x_wr_r,x_wr_s,x_wr_t,x_wr_fp" "x_ipu") 27132718Skan(define_cpu_unit "x_s1,x_s2,x_s3,x_s4" "x_ipu") 28132718Skan(define_cpu_unit "x_t1,x_t2,x_t3,x_t4" "x_ipu") 29132718Skan(define_cpu_unit "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6" "x_ipu") 30132718Skan(define_cpu_unit "x_store_tok" "x_ipu") 31132718Skan(define_cpu_unit "x_ms,x_mt" "x_ipu") 32132718Skan 33132718Skan(define_reservation "x-e1-st" "(x_e1_s | x_e1_t)") 34132718Skan 35132718Skan(define_reservation "x-e1-np" "(x_e1_r + x_e1_s + x_e1_t)") 36132718Skan 37132718Skan(absence_set "x_e1_r" "x_e1_s,x_e1_t") 38132718Skan(absence_set "x_e1_s" "x_e1_t") 39132718Skan 40132718Skan;; Try to avoid int <-> fp transitions. 41132718Skan 42132718Skan(define_reservation "x-x" "x_s1|x_t1,x_s2|x_t2,x_s3|x_t3,x_s4|x_t4") 43132718Skan(define_reservation "x-f" "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6") 44132718Skan(define_reservation "x-wr-st" "((x_wr_s | x_wr_t),x-x)") 45132718Skan(define_reservation "x-wr-np" "((x_wr_r + x_wr_s + x_wr_t),x-x)") 46132718Skan(define_reservation "x-wr-fp" "x_wr_fp,x-f") 47132718Skan(define_reservation "x-mem" "x_ms|x_mt") 48132718Skan 49132718Skan(absence_set "x_wr_fp" 50132718Skan "x_s1,x_s2,x_s3,x_s4,x_t1,x_t2,x_t3,x_t4,x_wr_s,x_wr_t") 51132718Skan 52132718Skan(absence_set "x_e1_r,x_wr_r,x_wr_s,x_wr_t" 53132718Skan "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6,x_wr_fp") 54132718Skan 55132718Skan;; Don't have any load type insn in same group as store 56132718Skan 57132718Skan(absence_set "x_ms,x_mt" "x_store_tok") 58132718Skan 59132718Skan 60132718Skan;; 61132718Skan;; Simple insns 62132718Skan;; 63132718Skan 64169689Skan(define_insn_reservation "x_int" 1 65169689Skan (and (eq_attr "cpu" "z990,z9_109") 66169689Skan (and (eq_attr "type" "integer") 67169689Skan (eq_attr "atype" "reg"))) 68169689Skan "x-e1-st,x-wr-st") 69169689Skan 70169689Skan(define_insn_reservation "x_agen" 1 71169689Skan (and (eq_attr "cpu" "z990,z9_109") 72169689Skan (and (eq_attr "type" "integer") 73169689Skan (eq_attr "atype" "agen"))) 74169689Skan "x-e1-st,x-wr-st") 75169689Skan 76132718Skan(define_insn_reservation "x_lr" 1 77169689Skan (and (eq_attr "cpu" "z990,z9_109") 78132718Skan (eq_attr "type" "lr")) 79132718Skan "x-e1-st,x-wr-st") 80132718Skan 81132718Skan(define_insn_reservation "x_la" 1 82169689Skan (and (eq_attr "cpu" "z990,z9_109") 83132718Skan (eq_attr "type" "la")) 84132718Skan "x-e1-st,x-wr-st") 85132718Skan 86132718Skan(define_insn_reservation "x_larl" 1 87169689Skan (and (eq_attr "cpu" "z990,z9_109") 88132718Skan (eq_attr "type" "larl")) 89132718Skan "x-e1-st,x-wr-st") 90132718Skan 91132718Skan(define_insn_reservation "x_load" 1 92169689Skan (and (eq_attr "cpu" "z990,z9_109") 93132718Skan (eq_attr "type" "load")) 94132718Skan "x-e1-st+x-mem,x-wr-st") 95132718Skan 96132718Skan(define_insn_reservation "x_store" 1 97169689Skan (and (eq_attr "cpu" "z990,z9_109") 98132718Skan (eq_attr "type" "store")) 99132718Skan "x-e1-st+x_store_tok,x-wr-st") 100132718Skan 101132718Skan(define_insn_reservation "x_branch" 1 102169689Skan (and (eq_attr "cpu" "z990,z9_109") 103132718Skan (eq_attr "type" "branch")) 104132718Skan "x_e1_r,x_wr_r") 105132718Skan 106132718Skan(define_insn_reservation "x_call" 5 107169689Skan (and (eq_attr "cpu" "z990,z9_109") 108132718Skan (eq_attr "type" "jsr")) 109169689Skan "x-e1-np*5,x-wr-np") 110169689Skan 111169689Skan(define_insn_reservation "x_mul_hi" 2 112169689Skan (and (eq_attr "cpu" "z990,z9_109") 113169689Skan (eq_attr "type" "imulhi")) 114169689Skan "x-e1-np*2,x-wr-np") 115132718Skan 116169689Skan(define_insn_reservation "x_mul_sidi" 4 117169689Skan (and (eq_attr "cpu" "z990,z9_109") 118169689Skan (eq_attr "type" "imulsi,imuldi")) 119169689Skan "x-e1-np*4,x-wr-np") 120169689Skan 121169689Skan(define_insn_reservation "x_div" 10 122169689Skan (and (eq_attr "cpu" "z990,z9_109") 123169689Skan (eq_attr "type" "idiv")) 124169689Skan "x-e1-np*10,x-wr-np") 125169689Skan 126169689Skan(define_insn_reservation "x_sem" 17 127169689Skan (and (eq_attr "cpu" "z990,z9_109") 128169689Skan (eq_attr "type" "sem")) 129169689Skan "x-e1-np+x-mem,x-e1-np*16,x-wr-st") 130169689Skan 131132718Skan;; 132132718Skan;; Multicycle insns 133132718Skan;; 134132718Skan 135169689Skan(define_insn_reservation "x_cs" 1 136169689Skan (and (eq_attr "cpu" "z990,z9_109") 137169689Skan (eq_attr "type" "cs")) 138132718Skan "x-e1-np,x-wr-np") 139132718Skan 140169689Skan(define_insn_reservation "x_vs" 1 141169689Skan (and (eq_attr "cpu" "z990,z9_109") 142169689Skan (eq_attr "type" "vs")) 143169689Skan "x-e1-np*10,x-wr-np") 144169689Skan 145132718Skan(define_insn_reservation "x_stm" 1 146169689Skan (and (eq_attr "cpu" "z990,z9_109") 147132718Skan (eq_attr "type" "stm")) 148132718Skan "(x-e1-np+x_store_tok)*10,x-wr-np") 149132718Skan 150132718Skan(define_insn_reservation "x_lm" 1 151169689Skan (and (eq_attr "cpu" "z990,z9_109") 152132718Skan (eq_attr "type" "lm")) 153132718Skan "x-e1-np*10,x-wr-np") 154132718Skan 155169689Skan(define_insn_reservation "x_other" 1 156169689Skan (and (eq_attr "cpu" "z990,z9_109") 157169689Skan (eq_attr "type" "other")) 158132718Skan "x-e1-np,x-wr-np") 159132718Skan 160132718Skan;; 161132718Skan;; Floating point insns 162132718Skan;; 163132718Skan 164169689Skan(define_insn_reservation "x_fsimptf" 7 165169689Skan (and (eq_attr "cpu" "z990,z9_109") 166169689Skan (eq_attr "type" "fsimptf")) 167169689Skan "x_e1_t*2,x-wr-fp") 168169689Skan 169169689Skan(define_insn_reservation "x_fsimpdf" 6 170169689Skan (and (eq_attr "cpu" "z990,z9_109") 171169689Skan (eq_attr "type" "fsimpdf,fmuldf")) 172132718Skan "x_e1_t,x-wr-fp") 173132718Skan 174169689Skan(define_insn_reservation "x_fsimpsf" 6 175169689Skan (and (eq_attr "cpu" "z990,z9_109") 176169689Skan (eq_attr "type" "fsimpsf,fmulsf")) 177132718Skan "x_e1_t,x-wr-fp") 178132718Skan 179169689Skan 180169689Skan(define_insn_reservation "x_fmultf" 33 181169689Skan (and (eq_attr "cpu" "z990,z9_109") 182169689Skan (eq_attr "type" "fmultf")) 183169689Skan "x_e1_t*27,x-wr-fp") 184169689Skan 185169689Skan 186169689Skan(define_insn_reservation "x_fdivtf" 82 187169689Skan (and (eq_attr "cpu" "z990,z9_109") 188169689Skan (eq_attr "type" "fdivtf,fsqrttf")) 189169689Skan "x_e1_t*76,x-wr-fp") 190169689Skan 191169689Skan(define_insn_reservation "x_fdivdf" 36 192169689Skan (and (eq_attr "cpu" "z990,z9_109") 193169689Skan (eq_attr "type" "fdivdf,fsqrtdf")) 194132718Skan "x_e1_t*30,x-wr-fp") 195132718Skan 196169689Skan(define_insn_reservation "x_fdivsf" 36 197169689Skan (and (eq_attr "cpu" "z990,z9_109") 198169689Skan (eq_attr "type" "fdivsf,fsqrtsf")) 199132718Skan "x_e1_t*30,x-wr-fp") 200132718Skan 201169689Skan 202169689Skan(define_insn_reservation "x_floadtf" 6 203169689Skan (and (eq_attr "cpu" "z990,z9_109") 204169689Skan (eq_attr "type" "floadtf")) 205132718Skan "x_e1_t,x-wr-fp") 206132718Skan 207169689Skan(define_insn_reservation "x_floaddf" 6 208169689Skan (and (eq_attr "cpu" "z990,z9_109") 209169689Skan (eq_attr "type" "floaddf")) 210132718Skan "x_e1_t,x-wr-fp") 211132718Skan 212169689Skan(define_insn_reservation "x_floadsf" 6 213169689Skan (and (eq_attr "cpu" "z990,z9_109") 214169689Skan (eq_attr "type" "floadsf")) 215132718Skan "x_e1_t,x-wr-fp") 216132718Skan 217169689Skan 218169689Skan(define_insn_reservation "x_fstoredf" 1 219169689Skan (and (eq_attr "cpu" "z990,z9_109") 220169689Skan (eq_attr "type" "fstoredf")) 221132718Skan "x_e1_t,x-wr-fp") 222132718Skan 223169689Skan(define_insn_reservation "x_fstoresf" 1 224169689Skan (and (eq_attr "cpu" "z990,z9_109") 225169689Skan (eq_attr "type" "fstoresf")) 226169689Skan "x_e1_t,x-wr-fp") 227169689Skan 228169689Skan 229169689Skan(define_insn_reservation "x_ftrunctf" 16 230169689Skan (and (eq_attr "cpu" "z990,z9_109") 231169689Skan (eq_attr "type" "ftrunctf")) 232169689Skan "x_e1_t*10,x-wr-fp") 233169689Skan 234169689Skan(define_insn_reservation "x_ftruncdf" 11 235169689Skan (and (eq_attr "cpu" "z990,z9_109") 236169689Skan (eq_attr "type" "ftruncdf")) 237169689Skan "x_e1_t*5,x-wr-fp") 238169689Skan 239169689Skan 240132718Skan(define_insn_reservation "x_ftoi" 1 241169689Skan (and (eq_attr "cpu" "z990,z9_109") 242132718Skan (eq_attr "type" "ftoi")) 243132718Skan "x_e1_t*3,x-wr-fp") 244132718Skan 245132718Skan(define_insn_reservation "x_itof" 7 246169689Skan (and (eq_attr "cpu" "z990,z9_109") 247132718Skan (eq_attr "type" "itof")) 248132718Skan "x_e1_t*3,x-wr-fp") 249132718Skan 250169689Skan(define_bypass 1 "x_fsimpdf" "x_fstoredf") 251132718Skan 252169689Skan(define_bypass 1 "x_fsimpsf" "x_fstoresf") 253132718Skan 254169689Skan(define_bypass 1 "x_floaddf" "x_fsimpdf,x_fstoredf,x_floaddf") 255132718Skan 256169689Skan(define_bypass 1 "x_floadsf" "x_fsimpsf,x_fstoresf,x_floadsf") 257132718Skan 258132718Skan;; 259132718Skan;; s390_agen_dep_p returns 1, if a register is set in the 260132718Skan;; first insn and used in the dependent insn to form a address. 261132718Skan;; 262132718Skan 263132718Skan;; 264132718Skan;; If an instruction uses a register to address memory, it needs 265132718Skan;; to be set 5 cycles in advance. 266132718Skan;; 267132718Skan 268132718Skan(define_bypass 5 "x_int,x_agen,x_lr" 269169689Skan "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" 270132718Skan "s390_agen_dep_p") 271132718Skan 272132718Skan(define_bypass 9 "x_int,x_agen,x_lr" 273169689Skan "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ 274169689Skan x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" 275132718Skan "s390_agen_dep_p") 276132718Skan;; 277132718Skan;; A load type instruction uses a bypass to feed the result back 278132718Skan;; to the address generation pipeline stage. 279132718Skan;; 280132718Skan 281132718Skan(define_bypass 4 "x_load" 282169689Skan "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" 283132718Skan "s390_agen_dep_p") 284132718Skan 285132718Skan(define_bypass 5 "x_load" 286169689Skan "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ 287169689Skan x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" 288132718Skan "s390_agen_dep_p") 289132718Skan 290132718Skan;; 291132718Skan;; A load address type instruction uses a bypass to feed the 292132718Skan;; result back to the address generation pipeline stage. 293132718Skan;; 294132718Skan 295132718Skan(define_bypass 3 "x_larl,x_la" 296169689Skan "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" 297132718Skan "s390_agen_dep_p") 298132718Skan 299132718Skan(define_bypass 5 "x_larl, x_la" 300169689Skan "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ 301169689Skan x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" 302132718Skan "s390_agen_dep_p") 303132718Skan 304132718Skan;; 305132718Skan;; Operand forwarding 306132718Skan;; 307132718Skan 308132718Skan(define_bypass 0 "x_lr,x_la,x_load" "x_int,x_lr") 309132718Skan 310132718Skan 311