mips.c revision 169689
1139826Simp/* Subroutines used for MIPS code generation. 253541Sshin Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 353541Sshin 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. 453541Sshin Contributed by A. Lichnewsky, lich@inria.inria.fr. 553541Sshin Changes by Michael Meissner, meissner@osf.org. 653541Sshin 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and 753541Sshin Brendan Eich, brendan@microunity.com. 853541Sshin 953541SshinThis file is part of GCC. 1053541Sshin 1153541SshinGCC is free software; you can redistribute it and/or modify 1253541Sshinit under the terms of the GNU General Public License as published by 1353541Sshinthe Free Software Foundation; either version 2, or (at your option) 1453541Sshinany later version. 1553541Sshin 1653541SshinGCC is distributed in the hope that it will be useful, 1753541Sshinbut WITHOUT ANY WARRANTY; without even the implied warranty of 1853541SshinMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1953541SshinGNU General Public License for more details. 2053541Sshin 2153541SshinYou should have received a copy of the GNU General Public License 2253541Sshinalong with GCC; see the file COPYING. If not, write to 2353541Sshinthe Free Software Foundation, 51 Franklin Street, Fifth Floor, 2453541SshinBoston, MA 02110-1301, USA. */ 2553541Sshin 2653541Sshin#include "config.h" 2753541Sshin#include "system.h" 2853541Sshin#include "coretypes.h" 29174510Sobrien#include "tm.h" 3053541Sshin#include <signal.h> 3153541Sshin#include "rtl.h" 32139826Simp#include "regs.h" 3353541Sshin#include "hard-reg-set.h" 3453541Sshin#include "real.h" 3553541Sshin#include "insn-config.h" 3653541Sshin#include "conditions.h" 3753541Sshin#include "insn-attr.h" 3853541Sshin#include "recog.h" 3953541Sshin#include "toplev.h" 4053541Sshin#include "output.h" 4153541Sshin#include "tree.h" 4253541Sshin#include "function.h" 4353541Sshin#include "expr.h" 4453541Sshin#include "optabs.h" 4553541Sshin#include "flags.h" 4653541Sshin#include "reload.h" 4753541Sshin#include "tm_p.h" 4853541Sshin#include "ggc.h" 4953541Sshin#include "gstab.h" 5053541Sshin#include "hashtab.h" 5153541Sshin#include "debug.h" 5253541Sshin#include "target.h" 5353541Sshin#include "target-def.h" 5453541Sshin#include "integrate.h" 5553541Sshin#include "langhooks.h" 5653541Sshin#include "cfglayout.h" 5753541Sshin#include "sched-int.h" 5853541Sshin#include "tree-gimple.h" 5953541Sshin#include "bitmap.h" 6053541Sshin 6153541Sshin/* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */ 6253541Sshin#define UNSPEC_ADDRESS_P(X) \ 63174510Sobrien (GET_CODE (X) == UNSPEC \ 64174510Sobrien && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \ 65174510Sobrien && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES) 6678064Sume 6778064Sume/* Extract the symbol or label from UNSPEC wrapper X. */ 6855009Sshin#define UNSPEC_ADDRESS(X) \ 6953541Sshin XVECEXP (X, 0, 0) 7053541Sshin 7153541Sshin/* Extract the symbol type from UNSPEC wrapper X. */ 7253541Sshin#define UNSPEC_ADDRESS_TYPE(X) \ 7353541Sshin ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST)) 7455679Sshin 7553541Sshin/* The maximum distance between the top of the stack frame and the 7653541Sshin value $sp has when we save & restore registers. 7753541Sshin 7853541Sshin Use a maximum gap of 0x100 in the mips16 case. We can then use 7953541Sshin unextended instructions to save and restore registers, and to 8053541Sshin allocate and deallocate the top part of the frame. 81164033Srwatson 8253541Sshin The value in the !mips16 case must be a SMALL_OPERAND and must 8353541Sshin preserve the maximum stack alignment. */ 8453541Sshin#define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0) 8592767Sjeff 8653541Sshin/* True if INSN is a mips.md pattern or asm statement. */ 8753541Sshin#define USEFUL_INSN_P(INSN) \ 8853541Sshin (INSN_P (INSN) \ 8953541Sshin && GET_CODE (PATTERN (INSN)) != USE \ 9053541Sshin && GET_CODE (PATTERN (INSN)) != CLOBBER \ 9153541Sshin && GET_CODE (PATTERN (INSN)) != ADDR_VEC \ 9253541Sshin && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC) 9353541Sshin 9498102Shsu/* If INSN is a delayed branch sequence, return the first instruction 9562587Sitojun in the sequence, otherwise return INSN itself. */ 9655679Sshin#define SEQ_BEGIN(INSN) \ 97181887Sjulian (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \ 9853541Sshin ? XVECEXP (PATTERN (INSN), 0, 0) \ 9953541Sshin : (INSN)) 10053541Sshin 10153541Sshin/* Likewise for the last instruction in a delayed branch sequence. */ 102148385Sume#define SEQ_END(INSN) \ 10353541Sshin (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \ 10453541Sshin ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \ 10553541Sshin : (INSN)) 10653541Sshin 107171259Sdelphij/* Execute the following loop body with SUBINSN set to each instruction 108171259Sdelphij between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */ 10953541Sshin#define FOR_EACH_SUBINSN(SUBINSN, INSN) \ 11053541Sshin for ((SUBINSN) = SEQ_BEGIN (INSN); \ 11153541Sshin (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \ 11253541Sshin (SUBINSN) = NEXT_INSN (SUBINSN)) 11353541Sshin 114188144Sjamie/* Classifies an address. 11553541Sshin 116132714Srwatson ADDRESS_REG 117178285Srwatson A natural register + offset address. The register satisfies 118132714Srwatson mips_valid_base_register_p and the offset is a const_arith_operand. 119194907Srwatson 12053541Sshin ADDRESS_LO_SUM 12153541Sshin A LO_SUM rtx. The first operand is a valid base register and 122120856Sume the second operand is a symbolic address. 12353541Sshin 124160024Sbz ADDRESS_CONST_INT 125188148Sjamie A signed 16-bit constant address. 126188148Sjamie 127188148Sjamie ADDRESS_SYMBOLIC: 128188148Sjamie A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */ 129188148Sjamieenum mips_address_type { 13053541Sshin ADDRESS_REG, 13153541Sshin ADDRESS_LO_SUM, 132120856Sume ADDRESS_CONST_INT, 13353541Sshin ADDRESS_SYMBOLIC 13453541Sshin}; 13553541Sshin 13653541Sshin/* Classifies the prototype of a builtin function. */ 137120856Sumeenum mips_function_type 13853541Sshin{ 139181803Sbz MIPS_V2SF_FTYPE_V2SF, 140148385Sume MIPS_V2SF_FTYPE_V2SF_V2SF, 14153541Sshin MIPS_V2SF_FTYPE_V2SF_V2SF_INT, 142188144Sjamie MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, 143188144Sjamie MIPS_V2SF_FTYPE_SF_SF, 144188144Sjamie MIPS_INT_FTYPE_V2SF_V2SF, 145185435Sbz MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, 14653541Sshin MIPS_INT_FTYPE_SF_SF, 14753541Sshin MIPS_INT_FTYPE_DF_DF, 14853541Sshin MIPS_SF_FTYPE_V2SF, 14953541Sshin MIPS_SF_FTYPE_SF, 15053541Sshin MIPS_SF_FTYPE_SF_SF, 15153541Sshin MIPS_DF_FTYPE_DF, 15253541Sshin MIPS_DF_FTYPE_DF_DF, 15353541Sshin 15453541Sshin /* For MIPS DSP ASE */ 15553541Sshin MIPS_DI_FTYPE_DI_SI, 15653541Sshin MIPS_DI_FTYPE_DI_SI_SI, 15753541Sshin MIPS_DI_FTYPE_DI_V2HI_V2HI, 158194760Srwatson MIPS_DI_FTYPE_DI_V4QI_V4QI, 15953541Sshin MIPS_SI_FTYPE_DI_SI, 16053541Sshin MIPS_SI_FTYPE_PTR_SI, 161194760Srwatson MIPS_SI_FTYPE_SI, 162194760Srwatson MIPS_SI_FTYPE_SI_SI, 163193217Spjd MIPS_SI_FTYPE_V2HI, 164120856Sume MIPS_SI_FTYPE_V2HI_V2HI, 165193217Spjd MIPS_SI_FTYPE_V4QI, 16653541Sshin MIPS_SI_FTYPE_V4QI_V4QI, 16753541Sshin MIPS_SI_FTYPE_VOID, 16853541Sshin MIPS_V2HI_FTYPE_SI, 16953541Sshin MIPS_V2HI_FTYPE_SI_SI, 17078064Sume MIPS_V2HI_FTYPE_V2HI, 171120913Sume MIPS_V2HI_FTYPE_V2HI_SI, 17253541Sshin MIPS_V2HI_FTYPE_V2HI_V2HI, 173194760Srwatson MIPS_V2HI_FTYPE_V4QI, 174194760Srwatson MIPS_V2HI_FTYPE_V4QI_V2HI, 17578064Sume MIPS_V4QI_FTYPE_SI, 176194760Srwatson MIPS_V4QI_FTYPE_V2HI_V2HI, 177120856Sume MIPS_V4QI_FTYPE_V4QI_SI, 17853541Sshin MIPS_V4QI_FTYPE_V4QI_V4QI, 179194760Srwatson MIPS_VOID_FTYPE_SI_SI, 180194760Srwatson MIPS_VOID_FTYPE_V2HI_V2HI, 18153541Sshin MIPS_VOID_FTYPE_V4QI_V4QI, 18253541Sshin 18353541Sshin /* The last type. */ 18453541Sshin MIPS_MAX_FTYPE_MAX 18553541Sshin}; 186181803Sbz 187181803Sbz/* Specifies how a builtin function should be converted into rtl. */ 188164033Srwatsonenum mips_builtin_type 189170587Srwatson{ 190120856Sume /* The builtin corresponds directly to an .md pattern. The return 191159976Spjd value is mapped to operand 0 and the arguments are mapped to 192183606Sbz operands 1 and above. */ 193170587Srwatson MIPS_BUILTIN_DIRECT, 19455679Sshin 19553541Sshin /* The builtin corresponds directly to an .md pattern. There is no return 196180427Sbz value and the arguments are mapped to operands 0 and above. */ 197132699Syar MIPS_BUILTIN_DIRECT_NO_TARGET, 198189848Srwatson 199132699Syar /* The builtin corresponds to a comparison instruction followed by 200132699Syar a mips_cond_move_tf_ps pattern. The first two arguments are the 20197658Stanimura values to compare and the second two arguments are the vector 202171260Sdelphij operands for the movt.ps or movf.ps instruction (in assembly order). */ 203171260Sdelphij MIPS_BUILTIN_MOVF, 204183606Sbz MIPS_BUILTIN_MOVT, 205183606Sbz 20697658Stanimura /* The builtin corresponds to a V2SF comparison instruction. Operand 0 207221247Sbz of this instruction is the result of the comparison, which has mode 20878064Sume CCV2 or CCV4. The function arguments are mapped to operands 1 and 20955679Sshin above. The function's return value is an SImode boolean that is 21055679Sshin true under the following conditions: 21155679Sshin 21255679Sshin MIPS_BUILTIN_CMP_ANY: one of the registers is true 21355679Sshin MIPS_BUILTIN_CMP_ALL: all of the registers are true 214180427Sbz MIPS_BUILTIN_CMP_LOWER: the first register is true 215180427Sbz MIPS_BUILTIN_CMP_UPPER: the second register is true. */ 216132699Syar MIPS_BUILTIN_CMP_ANY, 217189848Srwatson MIPS_BUILTIN_CMP_ALL, 218132699Syar MIPS_BUILTIN_CMP_UPPER, 219132699Syar MIPS_BUILTIN_CMP_LOWER, 220132699Syar 221132699Syar /* As above, but the instruction only sets a single $fcc register. */ 222183606Sbz MIPS_BUILTIN_CMP_SINGLE, 223183606Sbz 22455679Sshin /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */ 22555679Sshin MIPS_BUILTIN_BPOSGE32 226221247Sbz}; 22753541Sshin 22853541Sshin/* Invokes MACRO (COND) for each c.cond.fmt condition. */ 229180427Sbz#define MIPS_FP_CONDITIONS(MACRO) \ 230189848Srwatson MACRO (f), \ 231171260Sdelphij MACRO (un), \ 232116453Scognet MACRO (eq), \ 233120856Sume MACRO (ueq), \ 234221247Sbz MACRO (olt), \ 23578064Sume MACRO (ult), \ 23655679Sshin MACRO (ole), \ 23755679Sshin MACRO (ule), \ 23855679Sshin MACRO (sf), \ 23955679Sshin MACRO (ngle), \ 24055679Sshin MACRO (seq), \ 241180427Sbz MACRO (ngl), \ 242189848Srwatson MACRO (lt), \ 243171260Sdelphij MACRO (nge), \ 244116453Scognet MACRO (le), \ 245116453Scognet MACRO (ngt) 246171260Sdelphij 247171260Sdelphij/* Enumerates the codes above as MIPS_FP_COND_<X>. */ 248116453Scognet#define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X 249116453Scognetenum mips_fp_condition { 250116453Scognet MIPS_FP_CONDITIONS (DECLARE_MIPS_COND) 251171260Sdelphij}; 252171260Sdelphij 253171260Sdelphij/* Index X provides the string representation of MIPS_FP_COND_<X>. */ 254116453Scognet#define STRINGIFY(X) #X 25597658Stanimurastatic const char *const mips_fp_conditions[] = { 25697658Stanimura MIPS_FP_CONDITIONS (STRINGIFY) 25755679Sshin}; 258221247Sbz 25953541Sshin/* A function to save or store a register. The first argument is the 26053541Sshin register and the second is the stack slot. */ 26153541Sshintypedef void (*mips_save_restore_fn) (rtx, rtx); 26253541Sshin 263219570Sbzstruct mips16_constant; 264219570Sbzstruct mips_arg_info; 265219570Sbzstruct mips_address_info; 266188144Sjamiestruct mips_integer_op; 267219570Sbzstruct mips_sim; 268183611Sbz 26962587Sitojunstatic enum mips_symbol_type mips_classify_symbol (rtx); 27062587Sitojunstatic void mips_split_const (rtx, rtx *, HOST_WIDE_INT *); 27162587Sitojunstatic bool mips_offset_within_object_p (rtx, HOST_WIDE_INT); 27262587Sitojunstatic bool mips_valid_base_register_p (rtx, enum machine_mode, int); 27362587Sitojunstatic bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode); 27453541Sshinstatic bool mips_classify_address (struct mips_address_info *, rtx, 27553541Sshin enum machine_mode, int); 276120856Sumestatic bool mips_cannot_force_const_mem (rtx); 27753541Sshinstatic bool mips_use_blocks_for_constant_p (enum machine_mode, rtx); 27853541Sshinstatic int mips_symbol_insns (enum mips_symbol_type); 27953541Sshinstatic bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx); 28053541Sshinstatic rtx mips_force_temporary (rtx, rtx); 28153541Sshinstatic rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type); 28253541Sshinstatic rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT); 28353541Sshinstatic unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT); 28453541Sshinstatic unsigned int mips_build_lower (struct mips_integer_op *, 28553541Sshin unsigned HOST_WIDE_INT); 28653541Sshinstatic unsigned int mips_build_integer (struct mips_integer_op *, 28753541Sshin unsigned HOST_WIDE_INT); 28853541Sshinstatic void mips_legitimize_const_move (enum machine_mode, rtx, rtx); 28953541Sshinstatic int m16_check_op (rtx, int, int, int); 29053541Sshinstatic bool mips_rtx_costs (rtx, int, int, int *); 291171259Sdelphijstatic int mips_address_cost (rtx); 292194777Sbzstatic void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool); 29353541Sshinstatic void mips_load_call_address (rtx, rtx, int); 29453541Sshinstatic bool mips_function_ok_for_sibcall (tree, tree); 295148385Sumestatic void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT); 29653541Sshinstatic void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *); 297148385Sumestatic void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT); 298194777Sbzstatic void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode, 29953541Sshin tree, int, struct mips_arg_info *); 300158011Srwatsonstatic bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *); 301178285Srwatsonstatic void mips_set_architecture (const struct mips_cpu_info *); 302158011Srwatsonstatic void mips_set_tune (const struct mips_cpu_info *); 30353541Sshinstatic bool mips_handle_option (size_t, const char *, int); 30453541Sshinstatic struct machine_function *mips_init_machine_status (void); 30553541Sshinstatic void print_operand_reloc (FILE *, rtx, const char **); 30653541Sshin#if TARGET_IRIX 30753541Sshinstatic void irix_output_external_libcall (rtx); 30853541Sshin#endif 30953541Sshinstatic void mips_file_start (void); 310181803Sbzstatic void mips_file_end (void); 311148385Sumestatic bool mips_rewrite_small_data_p (rtx); 312181803Sbzstatic int mips_small_data_pattern_1 (rtx *, void *); 313148385Sumestatic int mips_rewrite_small_data_1 (rtx *, void *); 314148385Sumestatic bool mips_function_has_gp_insn (void); 315194907Srwatsonstatic unsigned int mips_global_pointer (void); 31653541Sshinstatic bool mips_save_reg_p (unsigned int); 31753541Sshinstatic void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT, 31853541Sshin mips_save_restore_fn); 31953541Sshinstatic void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn); 32053541Sshinstatic void mips_output_cplocal (void); 32153541Sshinstatic void mips_emit_loadgp (void); 32253541Sshinstatic void mips_output_function_prologue (FILE *, HOST_WIDE_INT); 323188144Sjamiestatic void mips_set_frame_expr (rtx); 324188144Sjamiestatic rtx mips_frame_set (rtx, rtx); 325148385Sumestatic void mips_save_reg (rtx, rtx); 326194777Sbzstatic void mips_output_function_epilogue (FILE *, HOST_WIDE_INT); 327194777Sbzstatic void mips_restore_reg (rtx, rtx); 328194777Sbzstatic void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, 329194777Sbz HOST_WIDE_INT, tree); 330194777Sbzstatic int symbolic_expression_p (rtx); 331148385Sumestatic section *mips_select_rtx_section (enum machine_mode, rtx, 332148385Sume unsigned HOST_WIDE_INT); 333148385Sumestatic section *mips_function_rodata_section (tree); 33453541Sshinstatic bool mips_in_small_data_p (tree); 335148385Sumestatic bool mips_use_anchors_for_symbol_p (rtx); 336148385Sumestatic int mips_fpr_return_fields (tree, tree *); 337194777Sbzstatic bool mips_return_in_msb (tree); 338194777Sbzstatic rtx mips_return_fpr_pair (enum machine_mode mode, 339194777Sbz enum machine_mode mode1, HOST_WIDE_INT, 340202915Sbz enum machine_mode mode2, HOST_WIDE_INT); 341194777Sbzstatic rtx mips16_gp_pseudo_reg (void); 342194777Sbzstatic void mips16_fp_args (FILE *, int, int); 343194777Sbzstatic void build_mips16_function_stub (FILE *); 344194777Sbzstatic rtx dump_constants_1 (enum machine_mode, rtx, rtx); 345194777Sbzstatic void dump_constants (struct mips16_constant *, rtx); 346148385Sumestatic int mips16_insn_length (rtx); 347148385Sumestatic int mips16_rewrite_pool_refs (rtx *, void *); 348148385Sumestatic void mips16_lay_out_constants (void); 349148385Sumestatic void mips_sim_reset (struct mips_sim *); 350148385Sumestatic void mips_sim_init (struct mips_sim *, state_t); 351120856Sumestatic void mips_sim_next_cycle (struct mips_sim *); 35253541Sshinstatic void mips_sim_wait_reg (struct mips_sim *, rtx, rtx); 35353541Sshinstatic int mips_sim_wait_regs_2 (rtx *, void *); 35453541Sshinstatic void mips_sim_wait_regs_1 (rtx *, void *); 35553541Sshinstatic void mips_sim_wait_regs (struct mips_sim *, rtx); 35653541Sshinstatic void mips_sim_wait_units (struct mips_sim *, rtx); 35753541Sshinstatic void mips_sim_wait_insn (struct mips_sim *, rtx); 35853541Sshinstatic void mips_sim_record_set (rtx, rtx, void *); 35953541Sshinstatic void mips_sim_issue_insn (struct mips_sim *, rtx); 36053541Sshinstatic void mips_sim_issue_nop (struct mips_sim *); 36153541Sshinstatic void mips_sim_finish_insn (struct mips_sim *, rtx); 362171259Sdelphijstatic void vr4130_avoid_branch_rt_conflict (rtx); 363171259Sdelphijstatic void vr4130_align_insns (void); 36453541Sshinstatic void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx); 36553541Sshinstatic void mips_avoid_hazards (void); 366194777Sbzstatic void mips_reorg (void); 36753541Sshinstatic bool mips_strict_matching_cpu_name_p (const char *, const char *); 36853541Sshinstatic bool mips_matching_cpu_name_p (const char *, const char *); 369132714Srwatsonstatic const struct mips_cpu_info *mips_parse_cpu (const char *); 370178285Srwatsonstatic const struct mips_cpu_info *mips_cpu_info_from_isa (int); 371132714Srwatsonstatic bool mips_return_in_memory (tree, tree); 37253541Sshinstatic bool mips_strict_argument_naming (CUMULATIVE_ARGS *); 37395023Ssuzstatic void mips_macc_chains_record (rtx); 37495023Ssuzstatic void mips_macc_chains_reorder (rtx *, int); 37553541Sshinstatic void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *); 37653541Sshinstatic bool vr4130_true_reg_dependence_p (rtx); 377120856Sumestatic bool vr4130_swap_insns_p (rtx, rtx); 37853541Sshinstatic void vr4130_reorder (rtx *, int); 37953541Sshinstatic void mips_promote_ready (rtx *, int, int); 38053541Sshinstatic int mips_sched_reorder (FILE *, int, rtx *, int *, int); 38153541Sshinstatic int mips_variable_issue (FILE *, int, rtx, int); 382194777Sbzstatic int mips_adjust_cost (rtx, rtx, rtx, int); 38353541Sshinstatic int mips_issue_rate (void); 38453541Sshinstatic int mips_multipass_dfa_lookahead (void); 38553541Sshinstatic void mips_init_libfuncs (void); 38653541Sshinstatic void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, 38753541Sshin tree, int *, int); 388127505Spjdstatic tree mips_build_builtin_va_list (void); 38953541Sshinstatic tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *); 39053541Sshinstatic bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode, 39153541Sshin tree, bool); 392194777Sbzstatic bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode, 39353541Sshin tree, bool); 39453541Sshinstatic int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode, 39553541Sshin tree, bool); 39678064Sumestatic bool mips_valid_pointer_mode (enum machine_mode); 397186141Sbzstatic bool mips_vector_mode_supported_p (enum machine_mode); 398186141Sbzstatic rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *); 399186141Sbzstatic rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx); 400120649Sumestatic rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int); 40153541Sshinstatic void mips_init_builtins (void); 40253541Sshinstatic rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool); 403171133Sgnnstatic rtx mips_expand_builtin_movtf (enum mips_builtin_type, 40453541Sshin enum insn_code, enum mips_fp_condition, 40553541Sshin rtx, tree); 40653541Sshinstatic rtx mips_expand_builtin_compare (enum mips_builtin_type, 40753541Sshin enum insn_code, enum mips_fp_condition, 408171259Sdelphij rtx, tree); 40953541Sshinstatic rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx); 410132714Srwatsonstatic void mips_encode_section_info (tree, rtx, int); 411132714Srwatsonstatic void mips_extra_live_on_entry (bitmap); 412178285Srwatsonstatic int mips_mode_rep_extended (enum machine_mode, enum machine_mode); 413132714Srwatson 41453541Sshin/* Structure to be filled in by compute_frame_size with register 41553541Sshin save masks, and offsets for the current function. */ 41678064Sume 417186141Sbzstruct mips_frame_info GTY(()) 41853541Sshin{ 41953541Sshin HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */ 42053541Sshin HOST_WIDE_INT var_size; /* # bytes that variables take up */ 421102218Struckman HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */ 422171259Sdelphij HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */ 423102218Struckman HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */ 424102218Struckman HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */ 425102218Struckman unsigned int mask; /* mask of saved gp registers */ 426184205Sdes unsigned int fmask; /* mask of saved fp registers */ 427102218Struckman HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */ 428102218Struckman HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */ 429102218Struckman HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */ 430102218Struckman HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */ 431102218Struckman bool initialized; /* true if frame size already calculated */ 432148385Sume int num_gp; /* number of gp registers saved */ 433102218Struckman int num_fp; /* number of fp registers saved */ 434102218Struckman}; 435102218Struckman 436102218Struckmanstruct machine_function GTY(()) { 437102218Struckman /* Pseudo-reg holding the value of $28 in a mips16 function which 438171259Sdelphij refers to GP relative global variables. */ 439102218Struckman rtx mips16_gp_pseudo_rtx; 440102218Struckman 441102218Struckman /* The number of extra stack bytes taken up by register varargs. 442102218Struckman This area is allocated by the callee at the very top of the frame. */ 443102218Struckman int varargs_size; 444102218Struckman 445102218Struckman /* Current frame information, calculated by compute_frame_size. */ 446102218Struckman struct mips_frame_info frame; 447102218Struckman 448102218Struckman /* The register to use as the global pointer within this function. */ 449184205Sdes unsigned int global_pointer; 450111119Simp 451102218Struckman /* True if mips_adjust_insn_length should ignore an instruction's 452102218Struckman hazard attribute. */ 453102218Struckman bool ignore_hazard_length_p; 454102218Struckman 455102218Struckman /* True if the whole function is suitable for .set noreorder and 45653541Sshin .set nomacro. */ 457171259Sdelphij bool all_noreorder_p; 45853541Sshin 45953541Sshin /* True if the function is known to have an instruction that needs $gp. */ 460102218Struckman bool has_gp_insn_p; 461102218Struckman}; 46253541Sshin 46353541Sshin/* Information about a single argument. */ 464169462Srwatsonstruct mips_arg_info 465157673Srwatson{ 466178320Srwatson /* True if the argument is passed in a floating-point register, or 467102218Struckman would have been if we hadn't run out of registers. */ 468102218Struckman bool fpr_p; 469178320Srwatson 47053541Sshin /* The number of words passed in registers, rounded up. */ 471102218Struckman unsigned int reg_words; 47253541Sshin 47353541Sshin /* For EABI, the offset of the first register from GP_ARG_FIRST or 47453541Sshin FP_ARG_FIRST. For other ABIs, the offset of the first register from 47553541Sshin the start of the ABI's argument structure (see the CUMULATIVE_ARGS 476171259Sdelphij comment for details). 47753541Sshin 47853541Sshin The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely 479102218Struckman on the stack. */ 480102218Struckman unsigned int reg_offset; 48153541Sshin 48253541Sshin /* The number of words that must be passed on the stack, rounded up. */ 483169462Srwatson unsigned int stack_words; 484157673Srwatson 485178320Srwatson /* The offset from the start of the stack overflow area of the argument's 486102218Struckman first stack word. Only meaningful when STACK_WORDS is nonzero. */ 487102218Struckman unsigned int stack_offset; 488178320Srwatson}; 48953541Sshin 490102218Struckman 49153541Sshin/* Information about an address described by mips_address_type. 49253541Sshin 49353541Sshin ADDRESS_CONST_INT 49453541Sshin No fields are used. 49553541Sshin 49653541Sshin ADDRESS_REG 497157673Srwatson REG is the base register and OFFSET is the constant offset. 49853541Sshin 49953541Sshin ADDRESS_LO_SUM 500157673Srwatson REG is the register that contains the high part of the address, 501157673Srwatson OFFSET is the symbolic address being referenced and SYMBOL_TYPE 502157673Srwatson is the type of OFFSET's symbol. 503221247Sbz 504124332Sume ADDRESS_SYMBOLIC 505169462Srwatson SYMBOL_TYPE is the type of symbol being referenced. */ 50654952Seivind 50753541Sshinstruct mips_address_info 508221247Sbz{ 509221247Sbz enum mips_address_type type; 510221247Sbz rtx reg; 511169462Srwatson rtx offset; 512169462Srwatson enum mips_symbol_type symbol_type; 513120913Sume}; 51453541Sshin 51553541Sshin 51653541Sshin/* One stage in a constant building sequence. These sequences have 51753541Sshin the form: 51853541Sshin 51953541Sshin A = VALUE[0] 52053541Sshin A = A CODE[1] VALUE[1] 521157673Srwatson A = A CODE[2] VALUE[2] 52253541Sshin ... 52353541Sshin 524157673Srwatson where A is an accumulator, each CODE[i] is a binary rtl operation 525157673Srwatson and each VALUE[i] is a constant integer. */ 526157673Srwatsonstruct mips_integer_op { 527221247Sbz enum rtx_code code; 528124332Sume unsigned HOST_WIDE_INT value; 529169462Srwatson}; 53054952Seivind 53153541Sshin 53253541Sshin/* The largest number of operations needed to load an integer constant. 533221247Sbz The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI. 534169462Srwatson When the lowest bit is clear, we can try, but reject a sequence with 535169462Srwatson an extra SLL at the end. */ 53653541Sshin#define MIPS_MAX_INTEGER_OPS 7 53753541Sshin 53853541Sshin 53953541Sshin/* Global variables for machine-dependent things. */ 54053541Sshin 54153541Sshin/* Threshold for data being put into the small data/bss area, instead 54253541Sshin of the normal data area. */ 54353541Sshinint mips_section_threshold = -1; 54453541Sshin 54553541Sshin/* Count the number of .file directives, so that .loc is up to date. */ 54653541Sshinint num_source_filenames = 0; 54753541Sshin 54853541Sshin/* Count the number of sdb related labels are generated (to find block 54953541Sshin start and end boundaries). */ 550171259Sdelphijint sdb_label_count = 0; 551171259Sdelphij 552171259Sdelphij/* Next label # for each statement for Silicon Graphics IRIS systems. */ 553175162Sobrienint sym_lineno = 0; 55453541Sshin 555177961Srwatson/* Linked list of all externals that are to be emitted when optimizing 55678064Sume for the global pointer if they haven't been declared by the end of 55753541Sshin the program with an appropriate .comm or initialization. */ 55878064Sume 559157673Srwatsonstruct extern_list GTY (()) 56053541Sshin{ 561119995Sru struct extern_list *next; /* next external */ 56253541Sshin const char *name; /* name of the external */ 56378064Sume int size; /* size in bytes */ 56478064Sume}; 56578064Sume 56653541Sshinstatic GTY (()) struct extern_list *extern_head = 0; 56753541Sshin 56853541Sshin/* Name of the file containing the current function. */ 56978064Sumeconst char *current_function_file = ""; 57078064Sume 57191346Salfred/* Number of nested .set noreorder, noat, nomacro, and volatile requests. */ 57278064Sumeint set_noreorder; 57378064Sumeint set_noat; 57478064Sumeint set_nomacro; 57553541Sshinint set_volatile; 57662587Sitojun 57762587Sitojun/* The next branch instruction is a branch likely, not branch normal. */ 57862587Sitojunint mips_branch_likely; 57953541Sshin 58053541Sshin/* The operands passed to the last cmpMM expander. */ 58153541Sshinrtx cmp_operands[2]; 58253541Sshin 58353541Sshin/* The target cpu for code generation. */ 58453541Sshinenum processor_type mips_arch; 58578064Sumeconst struct mips_cpu_info *mips_arch_info; 58662587Sitojun 58778064Sume/* The target cpu for optimization and scheduling. */ 58878064Sumeenum processor_type mips_tune; 58953541Sshinconst struct mips_cpu_info *mips_tune_info; 59053541Sshin 591133192Srwatson/* Which instruction set architecture to use. */ 592177961Srwatsonint mips_isa; 593178285Srwatson 594171260Sdelphij/* Which ABI to use. */ 595178285Srwatsonint mips_abi = MIPS_ABI_DEFAULT; 59653541Sshin 597133192Srwatson/* Cost information to use. */ 59862587Sitojunconst struct mips_rtx_cost_data *mips_cost; 59978064Sume 600125776Sume/* Whether we are generating mips16 hard float code. In mips16 mode 601125776Sume we always set TARGET_SOFT_FLOAT; this variable is nonzero if 602125776Sume -msoft-float was not specified by the user, which means that we 603125776Sume should arrange to call mips32 hard floating point code. */ 604125776Sumeint mips16_hard_float; 605125776Sume 606125776Sume/* The architecture selected by -mipsN. */ 607125776Sumestatic const struct mips_cpu_info *mips_isa_info; 608125776Sume 609125776Sume/* If TRUE, we split addresses into their high and low parts in the RTL. */ 610125776Sumeint mips_split_addresses; 611125776Sume 612125776Sume/* Mode used for saving/restoring general purpose registers. */ 613125776Sumestatic enum machine_mode gpr_mode; 614125776Sume 615125776Sume/* Array giving truth value on whether or not a given hard register 61678064Sume can support a given mode. */ 61778064Sumechar mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; 61878064Sume 61978064Sume/* List of all MIPS punctuation characters used by print_operand. */ 62078064Sumechar mips_print_operand_punct[256]; 62178064Sume 62278064Sume/* Map GCC register number to debugger register number. */ 62378064Sumeint mips_dbx_regno[FIRST_PSEUDO_REGISTER]; 62478064Sume 625186141Sbz/* A copy of the original flag_delayed_branch: see override_options. */ 62678064Sumestatic int mips_flag_delayed_branch; 62778064Sume 62878064Sumestatic GTY (()) int mips_output_filename_first_time = 1; 62978064Sume 63078064Sume/* mips_split_p[X] is true if symbols of type X can be split by 63178064Sume mips_split_symbol(). */ 63278064Sumebool mips_split_p[NUM_SYMBOL_TYPES]; 63378064Sume 63478064Sume/* mips_lo_relocs[X] is the relocation to use when a symbol of type X 635133192Srwatson appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or 636178285Srwatson if they are matched by a special .md file pattern. */ 63753541Sshinstatic const char *mips_lo_relocs[NUM_SYMBOL_TYPES]; 638133192Srwatson 63962587Sitojun/* Likewise for HIGHs. */ 64078064Sumestatic const char *mips_hi_relocs[NUM_SYMBOL_TYPES]; 641134121Srwatson 642134121Srwatson/* Map hard register number to register class */ 643178285Srwatsonconst enum reg_class mips_regno_to_class[] = 644134121Srwatson{ 645178285Srwatson LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG, 64653541Sshin M16_REGS, M16_REGS, M16_REGS, M16_REGS, 647133192Srwatson LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, 64853541Sshin LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, 64953541Sshin M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS, 65053541Sshin LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, 65153541Sshin T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS, 65253541Sshin LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, 65353541Sshin FP_REGS, FP_REGS, FP_REGS, FP_REGS, 654171259Sdelphij FP_REGS, FP_REGS, FP_REGS, FP_REGS, 655180427Sbz FP_REGS, FP_REGS, FP_REGS, FP_REGS, 65653541Sshin FP_REGS, FP_REGS, FP_REGS, FP_REGS, 65753541Sshin FP_REGS, FP_REGS, FP_REGS, FP_REGS, 65853541Sshin FP_REGS, FP_REGS, FP_REGS, FP_REGS, 65953541Sshin FP_REGS, FP_REGS, FP_REGS, FP_REGS, 660158011Srwatson FP_REGS, FP_REGS, FP_REGS, FP_REGS, 661158011Srwatson HI_REG, LO_REG, NO_REGS, ST_REGS, 66253541Sshin ST_REGS, ST_REGS, ST_REGS, ST_REGS, 66353541Sshin ST_REGS, ST_REGS, ST_REGS, NO_REGS, 66453541Sshin NO_REGS, ALL_REGS, ALL_REGS, NO_REGS, 66553541Sshin COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 66653541Sshin COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 66753541Sshin COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 668169154Srwatson COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 669169154Srwatson COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 67053541Sshin COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 671185435Sbz COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 67254952Seivind COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, 67353541Sshin COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 67453541Sshin COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 67553541Sshin COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 67653541Sshin COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 677185435Sbz COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 678185435Sbz COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 679192895Sjamie COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 680192895Sjamie COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, 681185435Sbz COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 68253541Sshin COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 68353541Sshin COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 68453541Sshin COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 68553541Sshin COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 68653541Sshin COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 68753541Sshin COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 68853541Sshin COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, 68953541Sshin DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, 69053541Sshin DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS, 69153541Sshin ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS 69253541Sshin}; 69353541Sshin 69453541Sshin/* Table of machine dependent attributes. */ 69553541Sshinconst struct attribute_spec mips_attribute_table[] = 69653541Sshin{ 69753541Sshin { "long_call", 0, 0, false, true, true, NULL }, 698169154Srwatson { NULL, 0, 0, false, false, false, NULL } 699169154Srwatson}; 70053541Sshin 70153541Sshin/* A table describing all the processors gcc knows about. Names are 70253541Sshin matched in the order listed. The first mention of an ISA level is 70353541Sshin taken as the canonical name for that ISA. 70453541Sshin 70553541Sshin To ease comparison, please keep this table in the same order as 70653541Sshin gas's mips_cpu_info_table[]. */ 70753541Sshinconst struct mips_cpu_info mips_cpu_info_table[] = { 70853541Sshin /* Entries for generic ISAs */ 70953541Sshin { "mips1", PROCESSOR_R3000, 1 }, 71053541Sshin { "mips2", PROCESSOR_R6000, 2 }, 711185435Sbz { "mips3", PROCESSOR_R4000, 3 }, 712192895Sjamie { "mips4", PROCESSOR_R8000, 4 }, 713192895Sjamie { "mips32", PROCESSOR_4KC, 32 }, 714185435Sbz { "mips32r2", PROCESSOR_M4K, 33 }, 715185435Sbz { "mips64", PROCESSOR_5KC, 64 }, 71654952Seivind 71753541Sshin /* MIPS I */ 71853541Sshin { "r3000", PROCESSOR_R3000, 1 }, 71953541Sshin { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */ 72053541Sshin { "r3900", PROCESSOR_R3900, 1 }, 72153541Sshin 72253541Sshin /* MIPS II */ 72353541Sshin { "r6000", PROCESSOR_R6000, 2 }, 72453541Sshin 725185435Sbz /* MIPS III */ 72653541Sshin { "r4000", PROCESSOR_R4000, 3 }, 72753541Sshin { "vr4100", PROCESSOR_R4100, 3 }, 72853541Sshin { "vr4111", PROCESSOR_R4111, 3 }, 72953541Sshin { "vr4120", PROCESSOR_R4120, 3 }, 73053541Sshin { "vr4130", PROCESSOR_R4130, 3 }, 73153541Sshin { "vr4300", PROCESSOR_R4300, 3 }, 73253541Sshin { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */ 73353541Sshin { "r4600", PROCESSOR_R4600, 3 }, 734185435Sbz { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */ 73553541Sshin { "r4650", PROCESSOR_R4650, 3 }, 73653541Sshin 73753541Sshin /* MIPS IV */ 73853541Sshin { "r8000", PROCESSOR_R8000, 4 }, 73953541Sshin { "vr5000", PROCESSOR_R5000, 4 }, 74053541Sshin { "vr5400", PROCESSOR_R5400, 4 }, 74153541Sshin { "vr5500", PROCESSOR_R5500, 4 }, 74253541Sshin { "rm7000", PROCESSOR_R7000, 4 }, 74381127Sume { "rm9000", PROCESSOR_R9000, 4 }, 744171259Sdelphij 74581127Sume /* MIPS32 */ 746186141Sbz { "4kc", PROCESSOR_4KC, 32 }, 74781127Sume { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */ 748191672Sbms { "4kp", PROCESSOR_4KP, 32 }, 74981127Sume 750157978Srwatson /* MIPS32 Release 2 */ 751169154Srwatson { "m4k", PROCESSOR_M4K, 33 }, 752178285Srwatson { "24k", PROCESSOR_24K, 33 }, 75381127Sume { "24kc", PROCESSOR_24K, 33 }, /* 24K no FPU */ 754191672Sbms { "24kf", PROCESSOR_24K, 33 }, /* 24K 1:2 FPU */ 75581127Sume { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */ 756191672Sbms 757191672Sbms /* MIPS64 */ 75881127Sume { "5kc", PROCESSOR_5KC, 64 }, 75981127Sume { "5kf", PROCESSOR_5KF, 64 }, 76081127Sume { "20kc", PROCESSOR_20KC, 64 }, 76181127Sume { "sb1", PROCESSOR_SB1, 64 }, 76281127Sume { "sb1a", PROCESSOR_SB1A, 64 }, 76381127Sume { "sr71000", PROCESSOR_SR71000, 64 }, 76481127Sume 765191672Sbms /* End marker */ 766191672Sbms { 0, 0, 0 } 767191672Sbms}; 768191672Sbms 769191672Sbms/* Default costs. If these are used for a processor we should look 770191672Sbms up the actual costs. */ 771191672Sbms#define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \ 772191672Sbms COSTS_N_INSNS (7), /* fp_mult_sf */ \ 773191672Sbms COSTS_N_INSNS (8), /* fp_mult_df */ \ 774191672Sbms COSTS_N_INSNS (23), /* fp_div_sf */ \ 77581127Sume COSTS_N_INSNS (36), /* fp_div_df */ \ 77681127Sume COSTS_N_INSNS (10), /* int_mult_si */ \ 777191672Sbms COSTS_N_INSNS (10), /* int_mult_di */ \ 77881127Sume COSTS_N_INSNS (69), /* int_div_si */ \ 779178285Srwatson COSTS_N_INSNS (69), /* int_div_di */ \ 78081127Sume 2, /* branch_cost */ \ 781157978Srwatson 4 /* memory_latency */ 78281127Sume 78381127Sume/* Need to replace these with the costs of calling the appropriate 78453541Sshin libgcc routine. */ 78553541Sshin#define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \ 78653541Sshin COSTS_N_INSNS (256), /* fp_mult_sf */ \ 78753541Sshin COSTS_N_INSNS (256), /* fp_mult_df */ \ 78853541Sshin COSTS_N_INSNS (256), /* fp_div_sf */ \ 78953541Sshin COSTS_N_INSNS (256) /* fp_div_df */ 79053541Sshin 791171259Sdelphijstatic struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] = 79253541Sshin { 793171259Sdelphij { /* R3000 */ 794122922Sandre COSTS_N_INSNS (2), /* fp_add */ 795122922Sandre COSTS_N_INSNS (4), /* fp_mult_sf */ 796122922Sandre COSTS_N_INSNS (5), /* fp_mult_df */ 797122922Sandre COSTS_N_INSNS (12), /* fp_div_sf */ 79853541Sshin COSTS_N_INSNS (19), /* fp_div_df */ 79953541Sshin COSTS_N_INSNS (12), /* int_mult_si */ 80053541Sshin COSTS_N_INSNS (12), /* int_mult_di */ 80153541Sshin COSTS_N_INSNS (35), /* int_div_si */ 80253541Sshin COSTS_N_INSNS (35), /* int_div_di */ 80353541Sshin 1, /* branch_cost */ 80498211Shsu 4 /* memory_latency */ 805171259Sdelphij 80653541Sshin }, 807122922Sandre { /* 4KC */ 808122922Sandre SOFT_FP_COSTS, 809122922Sandre COSTS_N_INSNS (6), /* int_mult_si */ 81098211Shsu COSTS_N_INSNS (6), /* int_mult_di */ 81153541Sshin COSTS_N_INSNS (36), /* int_div_si */ 81253541Sshin COSTS_N_INSNS (36), /* int_div_di */ 81353541Sshin 1, /* branch_cost */ 81453541Sshin 4 /* memory_latency */ 81553541Sshin }, 81653541Sshin { /* 4KP */ 817171259Sdelphij SOFT_FP_COSTS, 818185435Sbz COSTS_N_INSNS (36), /* int_mult_si */ 819185435Sbz COSTS_N_INSNS (36), /* int_mult_di */ 82053541Sshin COSTS_N_INSNS (37), /* int_div_si */ 82153541Sshin COSTS_N_INSNS (37), /* int_div_di */ 822185435Sbz 1, /* branch_cost */ 82353541Sshin 4 /* memory_latency */ 82478064Sume }, 82553541Sshin { /* 5KC */ 826178285Srwatson SOFT_FP_COSTS, 827158011Srwatson COSTS_N_INSNS (4), /* int_mult_si */ 82883934Sbrooks COSTS_N_INSNS (11), /* int_mult_di */ 82983934Sbrooks COSTS_N_INSNS (36), /* int_div_si */ 83083934Sbrooks COSTS_N_INSNS (68), /* int_div_di */ 83183934Sbrooks 1, /* branch_cost */ 83278064Sume 4 /* memory_latency */ 83353541Sshin }, 83453541Sshin { /* 5KF */ 83553541Sshin COSTS_N_INSNS (4), /* fp_add */ 836185435Sbz COSTS_N_INSNS (4), /* fp_mult_sf */ 837169154Srwatson COSTS_N_INSNS (5), /* fp_mult_df */ 838169154Srwatson COSTS_N_INSNS (17), /* fp_div_sf */ 839169154Srwatson COSTS_N_INSNS (32), /* fp_div_df */ 84054263Sshin COSTS_N_INSNS (4), /* int_mult_si */ 841185435Sbz COSTS_N_INSNS (11), /* int_mult_di */ 84254952Seivind COSTS_N_INSNS (36), /* int_div_si */ 84353541Sshin COSTS_N_INSNS (68), /* int_div_di */ 84453541Sshin 1, /* branch_cost */ 84553541Sshin 4 /* memory_latency */ 84653541Sshin }, 84753541Sshin { /* 20KC */ 84853541Sshin DEFAULT_COSTS 849185435Sbz }, 850185435Sbz { /* 24k */ 851185435Sbz COSTS_N_INSNS (8), /* fp_add */ 85253541Sshin COSTS_N_INSNS (8), /* fp_mult_sf */ 853192895Sjamie COSTS_N_INSNS (10), /* fp_mult_df */ 854185435Sbz COSTS_N_INSNS (34), /* fp_div_sf */ 855185435Sbz COSTS_N_INSNS (64), /* fp_div_df */ 856185435Sbz COSTS_N_INSNS (5), /* int_mult_si */ 85753541Sshin COSTS_N_INSNS (5), /* int_mult_di */ 85853541Sshin COSTS_N_INSNS (41), /* int_div_si */ 859185435Sbz COSTS_N_INSNS (41), /* int_div_di */ 860185435Sbz 1, /* branch_cost */ 86153541Sshin 4 /* memory_latency */ 862185435Sbz }, 863185435Sbz { /* 24kx */ 864185435Sbz COSTS_N_INSNS (4), /* fp_add */ 865185435Sbz COSTS_N_INSNS (4), /* fp_mult_sf */ 866185435Sbz COSTS_N_INSNS (5), /* fp_mult_df */ 867185435Sbz COSTS_N_INSNS (17), /* fp_div_sf */ 868185435Sbz COSTS_N_INSNS (32), /* fp_div_df */ 869185435Sbz COSTS_N_INSNS (5), /* int_mult_si */ 870185435Sbz COSTS_N_INSNS (5), /* int_mult_di */ 871185435Sbz COSTS_N_INSNS (41), /* int_div_si */ 872185435Sbz COSTS_N_INSNS (41), /* int_div_di */ 873185435Sbz 1, /* branch_cost */ 874185435Sbz 4 /* memory_latency */ 875185435Sbz }, 876185435Sbz { /* M4k */ 877169154Srwatson DEFAULT_COSTS 878169154Srwatson }, 87954263Sshin { /* R3900 */ 880185435Sbz COSTS_N_INSNS (2), /* fp_add */ 88154952Seivind COSTS_N_INSNS (4), /* fp_mult_sf */ 88253541Sshin COSTS_N_INSNS (5), /* fp_mult_df */ 883185435Sbz COSTS_N_INSNS (12), /* fp_div_sf */ 884185435Sbz COSTS_N_INSNS (19), /* fp_div_df */ 885185435Sbz COSTS_N_INSNS (2), /* int_mult_si */ 886185435Sbz COSTS_N_INSNS (2), /* int_mult_di */ 887185435Sbz COSTS_N_INSNS (35), /* int_div_si */ 888185435Sbz COSTS_N_INSNS (35), /* int_div_di */ 889185435Sbz 1, /* branch_cost */ 890185435Sbz 4 /* memory_latency */ 891185435Sbz }, 892185435Sbz { /* R6000 */ 893192895Sjamie COSTS_N_INSNS (3), /* fp_add */ 894185435Sbz COSTS_N_INSNS (5), /* fp_mult_sf */ 895188144Sjamie COSTS_N_INSNS (6), /* fp_mult_df */ 896188144Sjamie COSTS_N_INSNS (15), /* fp_div_sf */ 89753541Sshin COSTS_N_INSNS (16), /* fp_div_df */ 898185435Sbz COSTS_N_INSNS (17), /* int_mult_si */ 899185435Sbz COSTS_N_INSNS (17), /* int_mult_di */ 900185435Sbz COSTS_N_INSNS (38), /* int_div_si */ 901185435Sbz COSTS_N_INSNS (38), /* int_div_di */ 902185435Sbz 2, /* branch_cost */ 903185435Sbz 6 /* memory_latency */ 904185435Sbz }, 90553541Sshin { /* R4000 */ 906185435Sbz COSTS_N_INSNS (6), /* fp_add */ 907185435Sbz COSTS_N_INSNS (7), /* fp_mult_sf */ 908185435Sbz COSTS_N_INSNS (8), /* fp_mult_df */ 909185435Sbz COSTS_N_INSNS (23), /* fp_div_sf */ 910185435Sbz COSTS_N_INSNS (36), /* fp_div_df */ 911185435Sbz COSTS_N_INSNS (10), /* int_mult_si */ 91253541Sshin COSTS_N_INSNS (10), /* int_mult_di */ 91353541Sshin COSTS_N_INSNS (69), /* int_div_si */ 914185435Sbz COSTS_N_INSNS (69), /* int_div_di */ 91553541Sshin 2, /* branch_cost */ 916185435Sbz 6 /* memory_latency */ 917185435Sbz }, 918185435Sbz { /* R4100 */ 919185435Sbz DEFAULT_COSTS 920185435Sbz }, 921185435Sbz { /* R4111 */ 922185435Sbz DEFAULT_COSTS 923185435Sbz }, 92453541Sshin { /* R4120 */ 92553541Sshin DEFAULT_COSTS 92653541Sshin }, 92753541Sshin { /* R4130 */ 92853541Sshin /* The only costs that appear to be updated here are 92953541Sshin integer multiplication. */ 93053541Sshin SOFT_FP_COSTS, 93153541Sshin COSTS_N_INSNS (4), /* int_mult_si */ 93253541Sshin COSTS_N_INSNS (6), /* int_mult_di */ 93353541Sshin COSTS_N_INSNS (69), /* int_div_si */ 93453541Sshin COSTS_N_INSNS (69), /* int_div_di */ 93553541Sshin 1, /* branch_cost */ 93653541Sshin 4 /* memory_latency */ 93753541Sshin }, 93853541Sshin { /* R4300 */ 93953541Sshin DEFAULT_COSTS 94053541Sshin }, 941148385Sume { /* R4600 */ 942148385Sume DEFAULT_COSTS 94353541Sshin }, 94453541Sshin { /* R4650 */ 945 DEFAULT_COSTS 946 }, 947 { /* R5000 */ 948 COSTS_N_INSNS (6), /* fp_add */ 949 COSTS_N_INSNS (4), /* fp_mult_sf */ 950 COSTS_N_INSNS (5), /* fp_mult_df */ 951 COSTS_N_INSNS (23), /* fp_div_sf */ 952 COSTS_N_INSNS (36), /* fp_div_df */ 953 COSTS_N_INSNS (5), /* int_mult_si */ 954 COSTS_N_INSNS (5), /* int_mult_di */ 955 COSTS_N_INSNS (36), /* int_div_si */ 956 COSTS_N_INSNS (36), /* int_div_di */ 957 1, /* branch_cost */ 958 4 /* memory_latency */ 959 }, 960 { /* R5400 */ 961 COSTS_N_INSNS (6), /* fp_add */ 962 COSTS_N_INSNS (5), /* fp_mult_sf */ 963 COSTS_N_INSNS (6), /* fp_mult_df */ 964 COSTS_N_INSNS (30), /* fp_div_sf */ 965 COSTS_N_INSNS (59), /* fp_div_df */ 966 COSTS_N_INSNS (3), /* int_mult_si */ 967 COSTS_N_INSNS (4), /* int_mult_di */ 968 COSTS_N_INSNS (42), /* int_div_si */ 969 COSTS_N_INSNS (74), /* int_div_di */ 970 1, /* branch_cost */ 971 4 /* memory_latency */ 972 }, 973 { /* R5500 */ 974 COSTS_N_INSNS (6), /* fp_add */ 975 COSTS_N_INSNS (5), /* fp_mult_sf */ 976 COSTS_N_INSNS (6), /* fp_mult_df */ 977 COSTS_N_INSNS (30), /* fp_div_sf */ 978 COSTS_N_INSNS (59), /* fp_div_df */ 979 COSTS_N_INSNS (5), /* int_mult_si */ 980 COSTS_N_INSNS (9), /* int_mult_di */ 981 COSTS_N_INSNS (42), /* int_div_si */ 982 COSTS_N_INSNS (74), /* int_div_di */ 983 1, /* branch_cost */ 984 4 /* memory_latency */ 985 }, 986 { /* R7000 */ 987 /* The only costs that are changed here are 988 integer multiplication. */ 989 COSTS_N_INSNS (6), /* fp_add */ 990 COSTS_N_INSNS (7), /* fp_mult_sf */ 991 COSTS_N_INSNS (8), /* fp_mult_df */ 992 COSTS_N_INSNS (23), /* fp_div_sf */ 993 COSTS_N_INSNS (36), /* fp_div_df */ 994 COSTS_N_INSNS (5), /* int_mult_si */ 995 COSTS_N_INSNS (9), /* int_mult_di */ 996 COSTS_N_INSNS (69), /* int_div_si */ 997 COSTS_N_INSNS (69), /* int_div_di */ 998 1, /* branch_cost */ 999 4 /* memory_latency */ 1000 }, 1001 { /* R8000 */ 1002 DEFAULT_COSTS 1003 }, 1004 { /* R9000 */ 1005 /* The only costs that are changed here are 1006 integer multiplication. */ 1007 COSTS_N_INSNS (6), /* fp_add */ 1008 COSTS_N_INSNS (7), /* fp_mult_sf */ 1009 COSTS_N_INSNS (8), /* fp_mult_df */ 1010 COSTS_N_INSNS (23), /* fp_div_sf */ 1011 COSTS_N_INSNS (36), /* fp_div_df */ 1012 COSTS_N_INSNS (3), /* int_mult_si */ 1013 COSTS_N_INSNS (8), /* int_mult_di */ 1014 COSTS_N_INSNS (69), /* int_div_si */ 1015 COSTS_N_INSNS (69), /* int_div_di */ 1016 1, /* branch_cost */ 1017 4 /* memory_latency */ 1018 }, 1019 { /* SB1 */ 1020 /* These costs are the same as the SB-1A below. */ 1021 COSTS_N_INSNS (4), /* fp_add */ 1022 COSTS_N_INSNS (4), /* fp_mult_sf */ 1023 COSTS_N_INSNS (4), /* fp_mult_df */ 1024 COSTS_N_INSNS (24), /* fp_div_sf */ 1025 COSTS_N_INSNS (32), /* fp_div_df */ 1026 COSTS_N_INSNS (3), /* int_mult_si */ 1027 COSTS_N_INSNS (4), /* int_mult_di */ 1028 COSTS_N_INSNS (36), /* int_div_si */ 1029 COSTS_N_INSNS (68), /* int_div_di */ 1030 1, /* branch_cost */ 1031 4 /* memory_latency */ 1032 }, 1033 { /* SB1-A */ 1034 /* These costs are the same as the SB-1 above. */ 1035 COSTS_N_INSNS (4), /* fp_add */ 1036 COSTS_N_INSNS (4), /* fp_mult_sf */ 1037 COSTS_N_INSNS (4), /* fp_mult_df */ 1038 COSTS_N_INSNS (24), /* fp_div_sf */ 1039 COSTS_N_INSNS (32), /* fp_div_df */ 1040 COSTS_N_INSNS (3), /* int_mult_si */ 1041 COSTS_N_INSNS (4), /* int_mult_di */ 1042 COSTS_N_INSNS (36), /* int_div_si */ 1043 COSTS_N_INSNS (68), /* int_div_di */ 1044 1, /* branch_cost */ 1045 4 /* memory_latency */ 1046 }, 1047 { /* SR71000 */ 1048 DEFAULT_COSTS 1049 }, 1050 }; 1051 1052 1053/* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */ 1054#ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT 1055#define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0 1056#endif 1057 1058/* Initialize the GCC target structure. */ 1059#undef TARGET_ASM_ALIGNED_HI_OP 1060#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" 1061#undef TARGET_ASM_ALIGNED_SI_OP 1062#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 1063#undef TARGET_ASM_ALIGNED_DI_OP 1064#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" 1065 1066#undef TARGET_ASM_FUNCTION_PROLOGUE 1067#define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue 1068#undef TARGET_ASM_FUNCTION_EPILOGUE 1069#define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue 1070#undef TARGET_ASM_SELECT_RTX_SECTION 1071#define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section 1072#undef TARGET_ASM_FUNCTION_RODATA_SECTION 1073#define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section 1074 1075#undef TARGET_SCHED_REORDER 1076#define TARGET_SCHED_REORDER mips_sched_reorder 1077#undef TARGET_SCHED_VARIABLE_ISSUE 1078#define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue 1079#undef TARGET_SCHED_ADJUST_COST 1080#define TARGET_SCHED_ADJUST_COST mips_adjust_cost 1081#undef TARGET_SCHED_ISSUE_RATE 1082#define TARGET_SCHED_ISSUE_RATE mips_issue_rate 1083#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD 1084#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ 1085 mips_multipass_dfa_lookahead 1086 1087#undef TARGET_DEFAULT_TARGET_FLAGS 1088#define TARGET_DEFAULT_TARGET_FLAGS \ 1089 (TARGET_DEFAULT \ 1090 | TARGET_CPU_DEFAULT \ 1091 | TARGET_ENDIAN_DEFAULT \ 1092 | TARGET_FP_EXCEPTIONS_DEFAULT \ 1093 | MASK_CHECK_ZERO_DIV \ 1094 | MASK_FUSED_MADD) 1095#undef TARGET_HANDLE_OPTION 1096#define TARGET_HANDLE_OPTION mips_handle_option 1097 1098#undef TARGET_FUNCTION_OK_FOR_SIBCALL 1099#define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall 1100 1101#undef TARGET_VALID_POINTER_MODE 1102#define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode 1103#undef TARGET_RTX_COSTS 1104#define TARGET_RTX_COSTS mips_rtx_costs 1105#undef TARGET_ADDRESS_COST 1106#define TARGET_ADDRESS_COST mips_address_cost 1107 1108#undef TARGET_IN_SMALL_DATA_P 1109#define TARGET_IN_SMALL_DATA_P mips_in_small_data_p 1110 1111#undef TARGET_MACHINE_DEPENDENT_REORG 1112#define TARGET_MACHINE_DEPENDENT_REORG mips_reorg 1113 1114#undef TARGET_ASM_FILE_START 1115#undef TARGET_ASM_FILE_END 1116#define TARGET_ASM_FILE_START mips_file_start 1117#define TARGET_ASM_FILE_END mips_file_end 1118#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE 1119#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true 1120 1121#undef TARGET_INIT_LIBFUNCS 1122#define TARGET_INIT_LIBFUNCS mips_init_libfuncs 1123 1124#undef TARGET_BUILD_BUILTIN_VA_LIST 1125#define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list 1126#undef TARGET_GIMPLIFY_VA_ARG_EXPR 1127#define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr 1128 1129#undef TARGET_PROMOTE_FUNCTION_ARGS 1130#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true 1131#undef TARGET_PROMOTE_FUNCTION_RETURN 1132#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true 1133#undef TARGET_PROMOTE_PROTOTYPES 1134#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true 1135 1136#undef TARGET_RETURN_IN_MEMORY 1137#define TARGET_RETURN_IN_MEMORY mips_return_in_memory 1138#undef TARGET_RETURN_IN_MSB 1139#define TARGET_RETURN_IN_MSB mips_return_in_msb 1140 1141#undef TARGET_ASM_OUTPUT_MI_THUNK 1142#define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk 1143#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 1144#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true 1145 1146#undef TARGET_SETUP_INCOMING_VARARGS 1147#define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs 1148#undef TARGET_STRICT_ARGUMENT_NAMING 1149#define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming 1150#undef TARGET_MUST_PASS_IN_STACK 1151#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size 1152#undef TARGET_PASS_BY_REFERENCE 1153#define TARGET_PASS_BY_REFERENCE mips_pass_by_reference 1154#undef TARGET_CALLEE_COPIES 1155#define TARGET_CALLEE_COPIES mips_callee_copies 1156#undef TARGET_ARG_PARTIAL_BYTES 1157#define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes 1158 1159#undef TARGET_MODE_REP_EXTENDED 1160#define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended 1161 1162#undef TARGET_VECTOR_MODE_SUPPORTED_P 1163#define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p 1164 1165#undef TARGET_INIT_BUILTINS 1166#define TARGET_INIT_BUILTINS mips_init_builtins 1167#undef TARGET_EXPAND_BUILTIN 1168#define TARGET_EXPAND_BUILTIN mips_expand_builtin 1169 1170#undef TARGET_HAVE_TLS 1171#define TARGET_HAVE_TLS HAVE_AS_TLS 1172 1173#undef TARGET_CANNOT_FORCE_CONST_MEM 1174#define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem 1175 1176#undef TARGET_ENCODE_SECTION_INFO 1177#define TARGET_ENCODE_SECTION_INFO mips_encode_section_info 1178 1179#undef TARGET_ATTRIBUTE_TABLE 1180#define TARGET_ATTRIBUTE_TABLE mips_attribute_table 1181 1182#undef TARGET_EXTRA_LIVE_ON_ENTRY 1183#define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry 1184 1185#undef TARGET_MIN_ANCHOR_OFFSET 1186#define TARGET_MIN_ANCHOR_OFFSET -32768 1187#undef TARGET_MAX_ANCHOR_OFFSET 1188#define TARGET_MAX_ANCHOR_OFFSET 32767 1189#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P 1190#define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p 1191#undef TARGET_USE_ANCHORS_FOR_SYMBOL_P 1192#define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p 1193 1194struct gcc_target targetm = TARGET_INITIALIZER; 1195 1196/* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */ 1197 1198static enum mips_symbol_type 1199mips_classify_symbol (rtx x) 1200{ 1201 if (GET_CODE (x) == LABEL_REF) 1202 { 1203 if (TARGET_MIPS16) 1204 return SYMBOL_CONSTANT_POOL; 1205 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) 1206 return SYMBOL_GOT_LOCAL; 1207 return SYMBOL_GENERAL; 1208 } 1209 1210 gcc_assert (GET_CODE (x) == SYMBOL_REF); 1211 1212 if (SYMBOL_REF_TLS_MODEL (x)) 1213 return SYMBOL_TLS; 1214 1215 if (CONSTANT_POOL_ADDRESS_P (x)) 1216 { 1217 if (TARGET_MIPS16) 1218 return SYMBOL_CONSTANT_POOL; 1219 1220 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold) 1221 return SYMBOL_SMALL_DATA; 1222 } 1223 1224 /* Do not use small-data accesses for weak symbols; they may end up 1225 being zero. */ 1226 if (SYMBOL_REF_SMALL_P (x) 1227 && !SYMBOL_REF_WEAK (x)) 1228 return SYMBOL_SMALL_DATA; 1229 1230 if (TARGET_ABICALLS) 1231 { 1232 if (SYMBOL_REF_DECL (x) == 0) 1233 { 1234 if (!SYMBOL_REF_LOCAL_P (x)) 1235 return SYMBOL_GOT_GLOBAL; 1236 } 1237 else 1238 { 1239 /* Don't use GOT accesses for locally-binding symbols if 1240 TARGET_ABSOLUTE_ABICALLS. Otherwise, there are three 1241 cases to consider: 1242 1243 - o32 PIC (either with or without explicit relocs) 1244 - n32/n64 PIC without explicit relocs 1245 - n32/n64 PIC with explicit relocs 1246 1247 In the first case, both local and global accesses will use an 1248 R_MIPS_GOT16 relocation. We must correctly predict which of 1249 the two semantics (local or global) the assembler and linker 1250 will apply. The choice doesn't depend on the symbol's 1251 visibility, so we deliberately ignore decl_visibility and 1252 binds_local_p here. 1253 1254 In the second case, the assembler will not use R_MIPS_GOT16 1255 relocations, but it chooses between local and global accesses 1256 in the same way as for o32 PIC. 1257 1258 In the third case we have more freedom since both forms of 1259 access will work for any kind of symbol. However, there seems 1260 little point in doing things differently. */ 1261 if (DECL_P (SYMBOL_REF_DECL (x)) 1262 && TREE_PUBLIC (SYMBOL_REF_DECL (x)) 1263 && !(TARGET_ABSOLUTE_ABICALLS 1264 && targetm.binds_local_p (SYMBOL_REF_DECL (x)))) 1265 return SYMBOL_GOT_GLOBAL; 1266 } 1267 1268 if (!TARGET_ABSOLUTE_ABICALLS) 1269 return SYMBOL_GOT_LOCAL; 1270 } 1271 1272 return SYMBOL_GENERAL; 1273} 1274 1275 1276/* Split X into a base and a constant offset, storing them in *BASE 1277 and *OFFSET respectively. */ 1278 1279static void 1280mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset) 1281{ 1282 *offset = 0; 1283 1284 if (GET_CODE (x) == CONST) 1285 { 1286 x = XEXP (x, 0); 1287 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) 1288 { 1289 *offset += INTVAL (XEXP (x, 1)); 1290 x = XEXP (x, 0); 1291 } 1292 } 1293 *base = x; 1294} 1295 1296 1297/* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points 1298 to the same object as SYMBOL, or to the same object_block. */ 1299 1300static bool 1301mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset) 1302{ 1303 if (GET_CODE (symbol) != SYMBOL_REF) 1304 return false; 1305 1306 if (CONSTANT_POOL_ADDRESS_P (symbol) 1307 && offset >= 0 1308 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol))) 1309 return true; 1310 1311 if (SYMBOL_REF_DECL (symbol) != 0 1312 && offset >= 0 1313 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol)))) 1314 return true; 1315 1316 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol) 1317 && SYMBOL_REF_BLOCK (symbol) 1318 && SYMBOL_REF_BLOCK_OFFSET (symbol) >= 0 1319 && ((unsigned HOST_WIDE_INT) offset + SYMBOL_REF_BLOCK_OFFSET (symbol) 1320 < (unsigned HOST_WIDE_INT) SYMBOL_REF_BLOCK (symbol)->size)) 1321 return true; 1322 1323 return false; 1324} 1325 1326 1327/* Return true if X is a symbolic constant that can be calculated in 1328 the same way as a bare symbol. If it is, store the type of the 1329 symbol in *SYMBOL_TYPE. */ 1330 1331bool 1332mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type) 1333{ 1334 HOST_WIDE_INT offset; 1335 1336 mips_split_const (x, &x, &offset); 1337 if (UNSPEC_ADDRESS_P (x)) 1338 *symbol_type = UNSPEC_ADDRESS_TYPE (x); 1339 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) 1340 { 1341 *symbol_type = mips_classify_symbol (x); 1342 if (*symbol_type == SYMBOL_TLS) 1343 return false; 1344 } 1345 else 1346 return false; 1347 1348 if (offset == 0) 1349 return true; 1350 1351 /* Check whether a nonzero offset is valid for the underlying 1352 relocations. */ 1353 switch (*symbol_type) 1354 { 1355 case SYMBOL_GENERAL: 1356 case SYMBOL_64_HIGH: 1357 case SYMBOL_64_MID: 1358 case SYMBOL_64_LOW: 1359 /* If the target has 64-bit pointers and the object file only 1360 supports 32-bit symbols, the values of those symbols will be 1361 sign-extended. In this case we can't allow an arbitrary offset 1362 in case the 32-bit value X + OFFSET has a different sign from X. */ 1363 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS) 1364 return mips_offset_within_object_p (x, offset); 1365 1366 /* In other cases the relocations can handle any offset. */ 1367 return true; 1368 1369 case SYMBOL_CONSTANT_POOL: 1370 /* Allow constant pool references to be converted to LABEL+CONSTANT. 1371 In this case, we no longer have access to the underlying constant, 1372 but the original symbol-based access was known to be valid. */ 1373 if (GET_CODE (x) == LABEL_REF) 1374 return true; 1375 1376 /* Fall through. */ 1377 1378 case SYMBOL_SMALL_DATA: 1379 /* Make sure that the offset refers to something within the 1380 underlying object. This should guarantee that the final 1381 PC- or GP-relative offset is within the 16-bit limit. */ 1382 return mips_offset_within_object_p (x, offset); 1383 1384 case SYMBOL_GOT_LOCAL: 1385 case SYMBOL_GOTOFF_PAGE: 1386 /* The linker should provide enough local GOT entries for a 1387 16-bit offset. Larger offsets may lead to GOT overflow. */ 1388 return SMALL_OPERAND (offset); 1389 1390 case SYMBOL_GOT_GLOBAL: 1391 case SYMBOL_GOTOFF_GLOBAL: 1392 case SYMBOL_GOTOFF_CALL: 1393 case SYMBOL_GOTOFF_LOADGP: 1394 case SYMBOL_TLSGD: 1395 case SYMBOL_TLSLDM: 1396 case SYMBOL_DTPREL: 1397 case SYMBOL_TPREL: 1398 case SYMBOL_GOTTPREL: 1399 case SYMBOL_TLS: 1400 return false; 1401 } 1402 gcc_unreachable (); 1403} 1404 1405 1406/* This function is used to implement REG_MODE_OK_FOR_BASE_P. */ 1407 1408int 1409mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict) 1410{ 1411 if (regno >= FIRST_PSEUDO_REGISTER) 1412 { 1413 if (!strict) 1414 return true; 1415 regno = reg_renumber[regno]; 1416 } 1417 1418 /* These fake registers will be eliminated to either the stack or 1419 hard frame pointer, both of which are usually valid base registers. 1420 Reload deals with the cases where the eliminated form isn't valid. */ 1421 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM) 1422 return true; 1423 1424 /* In mips16 mode, the stack pointer can only address word and doubleword 1425 values, nothing smaller. There are two problems here: 1426 1427 (a) Instantiating virtual registers can introduce new uses of the 1428 stack pointer. If these virtual registers are valid addresses, 1429 the stack pointer should be too. 1430 1431 (b) Most uses of the stack pointer are not made explicit until 1432 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated. 1433 We don't know until that stage whether we'll be eliminating to the 1434 stack pointer (which needs the restriction) or the hard frame 1435 pointer (which doesn't). 1436 1437 All in all, it seems more consistent to only enforce this restriction 1438 during and after reload. */ 1439 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM) 1440 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8; 1441 1442 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno); 1443} 1444 1445 1446/* Return true if X is a valid base register for the given mode. 1447 Allow only hard registers if STRICT. */ 1448 1449static bool 1450mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict) 1451{ 1452 if (!strict && GET_CODE (x) == SUBREG) 1453 x = SUBREG_REG (x); 1454 1455 return (REG_P (x) 1456 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict)); 1457} 1458 1459 1460/* Return true if symbols of type SYMBOL_TYPE can directly address a value 1461 with mode MODE. This is used for both symbolic and LO_SUM addresses. */ 1462 1463static bool 1464mips_symbolic_address_p (enum mips_symbol_type symbol_type, 1465 enum machine_mode mode) 1466{ 1467 switch (symbol_type) 1468 { 1469 case SYMBOL_GENERAL: 1470 return !TARGET_MIPS16; 1471 1472 case SYMBOL_SMALL_DATA: 1473 return true; 1474 1475 case SYMBOL_CONSTANT_POOL: 1476 /* PC-relative addressing is only available for lw and ld. */ 1477 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8; 1478 1479 case SYMBOL_GOT_LOCAL: 1480 return true; 1481 1482 case SYMBOL_GOT_GLOBAL: 1483 /* The address will have to be loaded from the GOT first. */ 1484 return false; 1485 1486 case SYMBOL_GOTOFF_PAGE: 1487 case SYMBOL_GOTOFF_GLOBAL: 1488 case SYMBOL_GOTOFF_CALL: 1489 case SYMBOL_GOTOFF_LOADGP: 1490 case SYMBOL_TLS: 1491 case SYMBOL_TLSGD: 1492 case SYMBOL_TLSLDM: 1493 case SYMBOL_DTPREL: 1494 case SYMBOL_GOTTPREL: 1495 case SYMBOL_TPREL: 1496 case SYMBOL_64_HIGH: 1497 case SYMBOL_64_MID: 1498 case SYMBOL_64_LOW: 1499 return true; 1500 } 1501 gcc_unreachable (); 1502} 1503 1504 1505/* Return true if X is a valid address for machine mode MODE. If it is, 1506 fill in INFO appropriately. STRICT is true if we should only accept 1507 hard base registers. */ 1508 1509static bool 1510mips_classify_address (struct mips_address_info *info, rtx x, 1511 enum machine_mode mode, int strict) 1512{ 1513 switch (GET_CODE (x)) 1514 { 1515 case REG: 1516 case SUBREG: 1517 info->type = ADDRESS_REG; 1518 info->reg = x; 1519 info->offset = const0_rtx; 1520 return mips_valid_base_register_p (info->reg, mode, strict); 1521 1522 case PLUS: 1523 info->type = ADDRESS_REG; 1524 info->reg = XEXP (x, 0); 1525 info->offset = XEXP (x, 1); 1526 return (mips_valid_base_register_p (info->reg, mode, strict) 1527 && const_arith_operand (info->offset, VOIDmode)); 1528 1529 case LO_SUM: 1530 info->type = ADDRESS_LO_SUM; 1531 info->reg = XEXP (x, 0); 1532 info->offset = XEXP (x, 1); 1533 return (mips_valid_base_register_p (info->reg, mode, strict) 1534 && mips_symbolic_constant_p (info->offset, &info->symbol_type) 1535 && mips_symbolic_address_p (info->symbol_type, mode) 1536 && mips_lo_relocs[info->symbol_type] != 0); 1537 1538 case CONST_INT: 1539 /* Small-integer addresses don't occur very often, but they 1540 are legitimate if $0 is a valid base register. */ 1541 info->type = ADDRESS_CONST_INT; 1542 return !TARGET_MIPS16 && SMALL_INT (x); 1543 1544 case CONST: 1545 case LABEL_REF: 1546 case SYMBOL_REF: 1547 info->type = ADDRESS_SYMBOLIC; 1548 return (mips_symbolic_constant_p (x, &info->symbol_type) 1549 && mips_symbolic_address_p (info->symbol_type, mode) 1550 && !mips_split_p[info->symbol_type]); 1551 1552 default: 1553 return false; 1554 } 1555} 1556 1557/* Return true if X is a thread-local symbol. */ 1558 1559static bool 1560mips_tls_operand_p (rtx x) 1561{ 1562 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0; 1563} 1564 1565/* Return true if X can not be forced into a constant pool. */ 1566 1567static int 1568mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) 1569{ 1570 return mips_tls_operand_p (*x); 1571} 1572 1573/* Return true if X can not be forced into a constant pool. */ 1574 1575static bool 1576mips_cannot_force_const_mem (rtx x) 1577{ 1578 rtx base; 1579 HOST_WIDE_INT offset; 1580 1581 if (!TARGET_MIPS16) 1582 { 1583 /* As an optimization, reject constants that mips_legitimize_move 1584 can expand inline. 1585 1586 Suppose we have a multi-instruction sequence that loads constant C 1587 into register R. If R does not get allocated a hard register, and 1588 R is used in an operand that allows both registers and memory 1589 references, reload will consider forcing C into memory and using 1590 one of the instruction's memory alternatives. Returning false 1591 here will force it to use an input reload instead. */ 1592 if (GET_CODE (x) == CONST_INT) 1593 return true; 1594 1595 mips_split_const (x, &base, &offset); 1596 if (symbolic_operand (base, VOIDmode) && SMALL_OPERAND (offset)) 1597 return true; 1598 } 1599 1600 if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0)) 1601 return true; 1602 1603 return false; 1604} 1605 1606/* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. MIPS16 uses per-function 1607 constant pools, but normal-mode code doesn't need to. */ 1608 1609static bool 1610mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, 1611 rtx x ATTRIBUTE_UNUSED) 1612{ 1613 return !TARGET_MIPS16; 1614} 1615 1616/* Return the number of instructions needed to load a symbol of the 1617 given type into a register. If valid in an address, the same number 1618 of instructions are needed for loads and stores. Treat extended 1619 mips16 instructions as two instructions. */ 1620 1621static int 1622mips_symbol_insns (enum mips_symbol_type type) 1623{ 1624 switch (type) 1625 { 1626 case SYMBOL_GENERAL: 1627 /* In mips16 code, general symbols must be fetched from the 1628 constant pool. */ 1629 if (TARGET_MIPS16) 1630 return 0; 1631 1632 /* When using 64-bit symbols, we need 5 preparatory instructions, 1633 such as: 1634 1635 lui $at,%highest(symbol) 1636 daddiu $at,$at,%higher(symbol) 1637 dsll $at,$at,16 1638 daddiu $at,$at,%hi(symbol) 1639 dsll $at,$at,16 1640 1641 The final address is then $at + %lo(symbol). With 32-bit 1642 symbols we just need a preparatory lui. */ 1643 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2); 1644 1645 case SYMBOL_SMALL_DATA: 1646 return 1; 1647 1648 case SYMBOL_CONSTANT_POOL: 1649 /* This case is for mips16 only. Assume we'll need an 1650 extended instruction. */ 1651 return 2; 1652 1653 case SYMBOL_GOT_LOCAL: 1654 case SYMBOL_GOT_GLOBAL: 1655 /* Unless -funit-at-a-time is in effect, we can't be sure whether 1656 the local/global classification is accurate. See override_options 1657 for details. 1658 1659 The worst cases are: 1660 1661 (1) For local symbols when generating o32 or o64 code. The assembler 1662 will use: 1663 1664 lw $at,%got(symbol) 1665 nop 1666 1667 ...and the final address will be $at + %lo(symbol). 1668 1669 (2) For global symbols when -mxgot. The assembler will use: 1670 1671 lui $at,%got_hi(symbol) 1672 (d)addu $at,$at,$gp 1673 1674 ...and the final address will be $at + %got_lo(symbol). */ 1675 return 3; 1676 1677 case SYMBOL_GOTOFF_PAGE: 1678 case SYMBOL_GOTOFF_GLOBAL: 1679 case SYMBOL_GOTOFF_CALL: 1680 case SYMBOL_GOTOFF_LOADGP: 1681 case SYMBOL_64_HIGH: 1682 case SYMBOL_64_MID: 1683 case SYMBOL_64_LOW: 1684 case SYMBOL_TLSGD: 1685 case SYMBOL_TLSLDM: 1686 case SYMBOL_DTPREL: 1687 case SYMBOL_GOTTPREL: 1688 case SYMBOL_TPREL: 1689 /* Check whether the offset is a 16- or 32-bit value. */ 1690 return mips_split_p[type] ? 2 : 1; 1691 1692 case SYMBOL_TLS: 1693 /* We don't treat a bare TLS symbol as a constant. */ 1694 return 0; 1695 } 1696 gcc_unreachable (); 1697} 1698 1699/* Return true if X is a legitimate $sp-based address for mode MDOE. */ 1700 1701bool 1702mips_stack_address_p (rtx x, enum machine_mode mode) 1703{ 1704 struct mips_address_info addr; 1705 1706 return (mips_classify_address (&addr, x, mode, false) 1707 && addr.type == ADDRESS_REG 1708 && addr.reg == stack_pointer_rtx); 1709} 1710 1711/* Return true if a value at OFFSET bytes from BASE can be accessed 1712 using an unextended mips16 instruction. MODE is the mode of the 1713 value. 1714 1715 Usually the offset in an unextended instruction is a 5-bit field. 1716 The offset is unsigned and shifted left once for HIs, twice 1717 for SIs, and so on. An exception is SImode accesses off the 1718 stack pointer, which have an 8-bit immediate field. */ 1719 1720static bool 1721mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset) 1722{ 1723 if (TARGET_MIPS16 1724 && GET_CODE (offset) == CONST_INT 1725 && INTVAL (offset) >= 0 1726 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0) 1727 { 1728 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx) 1729 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode); 1730 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode); 1731 } 1732 return false; 1733} 1734 1735 1736/* Return the number of instructions needed to load or store a value 1737 of mode MODE at X. Return 0 if X isn't valid for MODE. 1738 1739 For mips16 code, count extended instructions as two instructions. */ 1740 1741int 1742mips_address_insns (rtx x, enum machine_mode mode) 1743{ 1744 struct mips_address_info addr; 1745 int factor; 1746 1747 if (mode == BLKmode) 1748 /* BLKmode is used for single unaligned loads and stores. */ 1749 factor = 1; 1750 else 1751 /* Each word of a multi-word value will be accessed individually. */ 1752 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 1753 1754 if (mips_classify_address (&addr, x, mode, false)) 1755 switch (addr.type) 1756 { 1757 case ADDRESS_REG: 1758 if (TARGET_MIPS16 1759 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset)) 1760 return factor * 2; 1761 return factor; 1762 1763 case ADDRESS_LO_SUM: 1764 return (TARGET_MIPS16 ? factor * 2 : factor); 1765 1766 case ADDRESS_CONST_INT: 1767 return factor; 1768 1769 case ADDRESS_SYMBOLIC: 1770 return factor * mips_symbol_insns (addr.symbol_type); 1771 } 1772 return 0; 1773} 1774 1775 1776/* Likewise for constant X. */ 1777 1778int 1779mips_const_insns (rtx x) 1780{ 1781 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS]; 1782 enum mips_symbol_type symbol_type; 1783 HOST_WIDE_INT offset; 1784 1785 switch (GET_CODE (x)) 1786 { 1787 case HIGH: 1788 if (TARGET_MIPS16 1789 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type) 1790 || !mips_split_p[symbol_type]) 1791 return 0; 1792 1793 return 1; 1794 1795 case CONST_INT: 1796 if (TARGET_MIPS16) 1797 /* Unsigned 8-bit constants can be loaded using an unextended 1798 LI instruction. Unsigned 16-bit constants can be loaded 1799 using an extended LI. Negative constants must be loaded 1800 using LI and then negated. */ 1801 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1 1802 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2 1803 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2 1804 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3 1805 : 0); 1806 1807 return mips_build_integer (codes, INTVAL (x)); 1808 1809 case CONST_DOUBLE: 1810 case CONST_VECTOR: 1811 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0); 1812 1813 case CONST: 1814 if (CONST_GP_P (x)) 1815 return 1; 1816 1817 /* See if we can refer to X directly. */ 1818 if (mips_symbolic_constant_p (x, &symbol_type)) 1819 return mips_symbol_insns (symbol_type); 1820 1821 /* Otherwise try splitting the constant into a base and offset. 1822 16-bit offsets can be added using an extra addiu. Larger offsets 1823 must be calculated separately and then added to the base. */ 1824 mips_split_const (x, &x, &offset); 1825 if (offset != 0) 1826 { 1827 int n = mips_const_insns (x); 1828 if (n != 0) 1829 { 1830 if (SMALL_OPERAND (offset)) 1831 return n + 1; 1832 else 1833 return n + 1 + mips_build_integer (codes, offset); 1834 } 1835 } 1836 return 0; 1837 1838 case SYMBOL_REF: 1839 case LABEL_REF: 1840 return mips_symbol_insns (mips_classify_symbol (x)); 1841 1842 default: 1843 return 0; 1844 } 1845} 1846 1847 1848/* Return the number of instructions needed for memory reference X. 1849 Count extended mips16 instructions as two instructions. */ 1850 1851int 1852mips_fetch_insns (rtx x) 1853{ 1854 gcc_assert (MEM_P (x)); 1855 return mips_address_insns (XEXP (x, 0), GET_MODE (x)); 1856} 1857 1858 1859/* Return the number of instructions needed for an integer division. */ 1860 1861int 1862mips_idiv_insns (void) 1863{ 1864 int count; 1865 1866 count = 1; 1867 if (TARGET_CHECK_ZERO_DIV) 1868 { 1869 if (GENERATE_DIVIDE_TRAPS) 1870 count++; 1871 else 1872 count += 2; 1873 } 1874 1875 if (TARGET_FIX_R4000 || TARGET_FIX_R4400) 1876 count++; 1877 return count; 1878} 1879 1880/* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It 1881 returns a nonzero value if X is a legitimate address for a memory 1882 operand of the indicated MODE. STRICT is nonzero if this function 1883 is called during reload. */ 1884 1885bool 1886mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict) 1887{ 1888 struct mips_address_info addr; 1889 1890 return mips_classify_address (&addr, x, mode, strict); 1891} 1892 1893 1894/* Copy VALUE to a register and return that register. If new psuedos 1895 are allowed, copy it into a new register, otherwise use DEST. */ 1896 1897static rtx 1898mips_force_temporary (rtx dest, rtx value) 1899{ 1900 if (!no_new_pseudos) 1901 return force_reg (Pmode, value); 1902 else 1903 { 1904 emit_move_insn (copy_rtx (dest), value); 1905 return dest; 1906 } 1907} 1908 1909 1910/* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary 1911 and is used to load the high part into a register. */ 1912 1913rtx 1914mips_split_symbol (rtx temp, rtx addr) 1915{ 1916 rtx high; 1917 1918 if (TARGET_MIPS16) 1919 high = mips16_gp_pseudo_reg (); 1920 else 1921 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr))); 1922 return gen_rtx_LO_SUM (Pmode, high, addr); 1923} 1924 1925 1926/* Return an UNSPEC address with underlying address ADDRESS and symbol 1927 type SYMBOL_TYPE. */ 1928 1929rtx 1930mips_unspec_address (rtx address, enum mips_symbol_type symbol_type) 1931{ 1932 rtx base; 1933 HOST_WIDE_INT offset; 1934 1935 mips_split_const (address, &base, &offset); 1936 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), 1937 UNSPEC_ADDRESS_FIRST + symbol_type); 1938 return plus_constant (gen_rtx_CONST (Pmode, base), offset); 1939} 1940 1941 1942/* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the 1943 high part to BASE and return the result. Just return BASE otherwise. 1944 TEMP is available as a temporary register if needed. 1945 1946 The returned expression can be used as the first operand to a LO_SUM. */ 1947 1948static rtx 1949mips_unspec_offset_high (rtx temp, rtx base, rtx addr, 1950 enum mips_symbol_type symbol_type) 1951{ 1952 if (mips_split_p[symbol_type]) 1953 { 1954 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type)); 1955 addr = mips_force_temporary (temp, addr); 1956 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base)); 1957 } 1958 return base; 1959} 1960 1961 1962/* Return a legitimate address for REG + OFFSET. TEMP is as for 1963 mips_force_temporary; it is only needed when OFFSET is not a 1964 SMALL_OPERAND. */ 1965 1966static rtx 1967mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) 1968{ 1969 if (!SMALL_OPERAND (offset)) 1970 { 1971 rtx high; 1972 if (TARGET_MIPS16) 1973 { 1974 /* Load the full offset into a register so that we can use 1975 an unextended instruction for the address itself. */ 1976 high = GEN_INT (offset); 1977 offset = 0; 1978 } 1979 else 1980 { 1981 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */ 1982 high = GEN_INT (CONST_HIGH_PART (offset)); 1983 offset = CONST_LOW_PART (offset); 1984 } 1985 high = mips_force_temporary (temp, high); 1986 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg)); 1987 } 1988 return plus_constant (reg, offset); 1989} 1990 1991/* Emit a call to __tls_get_addr. SYM is the TLS symbol we are 1992 referencing, and TYPE is the symbol type to use (either global 1993 dynamic or local dynamic). V0 is an RTX for the return value 1994 location. The entire insn sequence is returned. */ 1995 1996static GTY(()) rtx mips_tls_symbol; 1997 1998static rtx 1999mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0) 2000{ 2001 rtx insn, loc, tga, a0; 2002 2003 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST); 2004 2005 if (!mips_tls_symbol) 2006 mips_tls_symbol = init_one_libfunc ("__tls_get_addr"); 2007 2008 loc = mips_unspec_address (sym, type); 2009 2010 start_sequence (); 2011 2012 emit_insn (gen_rtx_SET (Pmode, a0, 2013 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc))); 2014 tga = gen_rtx_MEM (Pmode, mips_tls_symbol); 2015 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx)); 2016 CONST_OR_PURE_CALL_P (insn) = 1; 2017 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0); 2018 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0); 2019 insn = get_insns (); 2020 2021 end_sequence (); 2022 2023 return insn; 2024} 2025 2026/* Generate the code to access LOC, a thread local SYMBOL_REF. The 2027 return value will be a valid address and move_operand (either a REG 2028 or a LO_SUM). */ 2029 2030static rtx 2031mips_legitimize_tls_address (rtx loc) 2032{ 2033 rtx dest, insn, v0, v1, tmp1, tmp2, eqv; 2034 enum tls_model model; 2035 2036 v0 = gen_rtx_REG (Pmode, GP_RETURN); 2037 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1); 2038 2039 model = SYMBOL_REF_TLS_MODEL (loc); 2040 /* Only TARGET_ABICALLS code can have more than one module; other 2041 code must be be static and should not use a GOT. All TLS models 2042 reduce to local exec in this situation. */ 2043 if (!TARGET_ABICALLS) 2044 model = TLS_MODEL_LOCAL_EXEC; 2045 2046 switch (model) 2047 { 2048 case TLS_MODEL_GLOBAL_DYNAMIC: 2049 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0); 2050 dest = gen_reg_rtx (Pmode); 2051 emit_libcall_block (insn, dest, v0, loc); 2052 break; 2053 2054 case TLS_MODEL_LOCAL_DYNAMIC: 2055 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0); 2056 tmp1 = gen_reg_rtx (Pmode); 2057 2058 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to 2059 share the LDM result with other LD model accesses. */ 2060 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), 2061 UNSPEC_TLS_LDM); 2062 emit_libcall_block (insn, tmp1, v0, eqv); 2063 2064 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL); 2065 dest = gen_rtx_LO_SUM (Pmode, tmp2, 2066 mips_unspec_address (loc, SYMBOL_DTPREL)); 2067 break; 2068 2069 case TLS_MODEL_INITIAL_EXEC: 2070 tmp1 = gen_reg_rtx (Pmode); 2071 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL); 2072 if (Pmode == DImode) 2073 { 2074 emit_insn (gen_tls_get_tp_di (v1)); 2075 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2)); 2076 } 2077 else 2078 { 2079 emit_insn (gen_tls_get_tp_si (v1)); 2080 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2)); 2081 } 2082 dest = gen_reg_rtx (Pmode); 2083 emit_insn (gen_add3_insn (dest, tmp1, v1)); 2084 break; 2085 2086 case TLS_MODEL_LOCAL_EXEC: 2087 if (Pmode == DImode) 2088 emit_insn (gen_tls_get_tp_di (v1)); 2089 else 2090 emit_insn (gen_tls_get_tp_si (v1)); 2091 2092 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL); 2093 dest = gen_rtx_LO_SUM (Pmode, tmp1, 2094 mips_unspec_address (loc, SYMBOL_TPREL)); 2095 break; 2096 2097 default: 2098 gcc_unreachable (); 2099 } 2100 2101 return dest; 2102} 2103 2104/* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can 2105 be legitimized in a way that the generic machinery might not expect, 2106 put the new address in *XLOC and return true. MODE is the mode of 2107 the memory being accessed. */ 2108 2109bool 2110mips_legitimize_address (rtx *xloc, enum machine_mode mode) 2111{ 2112 enum mips_symbol_type symbol_type; 2113 2114 if (mips_tls_operand_p (*xloc)) 2115 { 2116 *xloc = mips_legitimize_tls_address (*xloc); 2117 return true; 2118 } 2119 2120 /* See if the address can split into a high part and a LO_SUM. */ 2121 if (mips_symbolic_constant_p (*xloc, &symbol_type) 2122 && mips_symbolic_address_p (symbol_type, mode) 2123 && mips_split_p[symbol_type]) 2124 { 2125 *xloc = mips_split_symbol (0, *xloc); 2126 return true; 2127 } 2128 2129 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT) 2130 { 2131 /* Handle REG + CONSTANT using mips_add_offset. */ 2132 rtx reg; 2133 2134 reg = XEXP (*xloc, 0); 2135 if (!mips_valid_base_register_p (reg, mode, 0)) 2136 reg = copy_to_mode_reg (Pmode, reg); 2137 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1))); 2138 return true; 2139 } 2140 2141 return false; 2142} 2143 2144 2145/* Subroutine of mips_build_integer (with the same interface). 2146 Assume that the final action in the sequence should be a left shift. */ 2147 2148static unsigned int 2149mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value) 2150{ 2151 unsigned int i, shift; 2152 2153 /* Shift VALUE right until its lowest bit is set. Shift arithmetically 2154 since signed numbers are easier to load than unsigned ones. */ 2155 shift = 0; 2156 while ((value & 1) == 0) 2157 value /= 2, shift++; 2158 2159 i = mips_build_integer (codes, value); 2160 codes[i].code = ASHIFT; 2161 codes[i].value = shift; 2162 return i + 1; 2163} 2164 2165 2166/* As for mips_build_shift, but assume that the final action will be 2167 an IOR or PLUS operation. */ 2168 2169static unsigned int 2170mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value) 2171{ 2172 unsigned HOST_WIDE_INT high; 2173 unsigned int i; 2174 2175 high = value & ~(unsigned HOST_WIDE_INT) 0xffff; 2176 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000) 2177 { 2178 /* The constant is too complex to load with a simple lui/ori pair 2179 so our goal is to clear as many trailing zeros as possible. 2180 In this case, we know bit 16 is set and that the low 16 bits 2181 form a negative number. If we subtract that number from VALUE, 2182 we will clear at least the lowest 17 bits, maybe more. */ 2183 i = mips_build_integer (codes, CONST_HIGH_PART (value)); 2184 codes[i].code = PLUS; 2185 codes[i].value = CONST_LOW_PART (value); 2186 } 2187 else 2188 { 2189 i = mips_build_integer (codes, high); 2190 codes[i].code = IOR; 2191 codes[i].value = value & 0xffff; 2192 } 2193 return i + 1; 2194} 2195 2196 2197/* Fill CODES with a sequence of rtl operations to load VALUE. 2198 Return the number of operations needed. */ 2199 2200static unsigned int 2201mips_build_integer (struct mips_integer_op *codes, 2202 unsigned HOST_WIDE_INT value) 2203{ 2204 if (SMALL_OPERAND (value) 2205 || SMALL_OPERAND_UNSIGNED (value) 2206 || LUI_OPERAND (value)) 2207 { 2208 /* The value can be loaded with a single instruction. */ 2209 codes[0].code = UNKNOWN; 2210 codes[0].value = value; 2211 return 1; 2212 } 2213 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value))) 2214 { 2215 /* Either the constant is a simple LUI/ORI combination or its 2216 lowest bit is set. We don't want to shift in this case. */ 2217 return mips_build_lower (codes, value); 2218 } 2219 else if ((value & 0xffff) == 0) 2220 { 2221 /* The constant will need at least three actions. The lowest 2222 16 bits are clear, so the final action will be a shift. */ 2223 return mips_build_shift (codes, value); 2224 } 2225 else 2226 { 2227 /* The final action could be a shift, add or inclusive OR. 2228 Rather than use a complex condition to select the best 2229 approach, try both mips_build_shift and mips_build_lower 2230 and pick the one that gives the shortest sequence. 2231 Note that this case is only used once per constant. */ 2232 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS]; 2233 unsigned int cost, alt_cost; 2234 2235 cost = mips_build_shift (codes, value); 2236 alt_cost = mips_build_lower (alt_codes, value); 2237 if (alt_cost < cost) 2238 { 2239 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0])); 2240 cost = alt_cost; 2241 } 2242 return cost; 2243 } 2244} 2245 2246 2247/* Load VALUE into DEST, using TEMP as a temporary register if need be. */ 2248 2249void 2250mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value) 2251{ 2252 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS]; 2253 enum machine_mode mode; 2254 unsigned int i, cost; 2255 rtx x; 2256 2257 mode = GET_MODE (dest); 2258 cost = mips_build_integer (codes, value); 2259 2260 /* Apply each binary operation to X. Invariant: X is a legitimate 2261 source operand for a SET pattern. */ 2262 x = GEN_INT (codes[0].value); 2263 for (i = 1; i < cost; i++) 2264 { 2265 if (no_new_pseudos) 2266 { 2267 emit_insn (gen_rtx_SET (VOIDmode, temp, x)); 2268 x = temp; 2269 } 2270 else 2271 x = force_reg (mode, x); 2272 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value)); 2273 } 2274 2275 emit_insn (gen_rtx_SET (VOIDmode, dest, x)); 2276} 2277 2278 2279/* Subroutine of mips_legitimize_move. Move constant SRC into register 2280 DEST given that SRC satisfies immediate_operand but doesn't satisfy 2281 move_operand. */ 2282 2283static void 2284mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src) 2285{ 2286 rtx base; 2287 HOST_WIDE_INT offset; 2288 2289 /* Split moves of big integers into smaller pieces. */ 2290 if (splittable_const_int_operand (src, mode)) 2291 { 2292 mips_move_integer (dest, dest, INTVAL (src)); 2293 return; 2294 } 2295 2296 /* Split moves of symbolic constants into high/low pairs. */ 2297 if (splittable_symbolic_operand (src, mode)) 2298 { 2299 emit_insn (gen_rtx_SET (VOIDmode, dest, mips_split_symbol (dest, src))); 2300 return; 2301 } 2302 2303 if (mips_tls_operand_p (src)) 2304 { 2305 emit_move_insn (dest, mips_legitimize_tls_address (src)); 2306 return; 2307 } 2308 2309 /* If we have (const (plus symbol offset)), load the symbol first 2310 and then add in the offset. This is usually better than forcing 2311 the constant into memory, at least in non-mips16 code. */ 2312 mips_split_const (src, &base, &offset); 2313 if (!TARGET_MIPS16 2314 && offset != 0 2315 && (!no_new_pseudos || SMALL_OPERAND (offset))) 2316 { 2317 base = mips_force_temporary (dest, base); 2318 emit_move_insn (dest, mips_add_offset (0, base, offset)); 2319 return; 2320 } 2321 2322 src = force_const_mem (mode, src); 2323 2324 /* When using explicit relocs, constant pool references are sometimes 2325 not legitimate addresses. */ 2326 if (!memory_operand (src, VOIDmode)) 2327 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0))); 2328 emit_move_insn (dest, src); 2329} 2330 2331 2332/* If (set DEST SRC) is not a valid instruction, emit an equivalent 2333 sequence that is valid. */ 2334 2335bool 2336mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src) 2337{ 2338 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) 2339 { 2340 emit_move_insn (dest, force_reg (mode, src)); 2341 return true; 2342 } 2343 2344 /* Check for individual, fully-reloaded mflo and mfhi instructions. */ 2345 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD 2346 && REG_P (src) && MD_REG_P (REGNO (src)) 2347 && REG_P (dest) && GP_REG_P (REGNO (dest))) 2348 { 2349 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM; 2350 if (GET_MODE_SIZE (mode) <= 4) 2351 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)), 2352 gen_rtx_REG (SImode, REGNO (src)), 2353 gen_rtx_REG (SImode, other_regno))); 2354 else 2355 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)), 2356 gen_rtx_REG (DImode, REGNO (src)), 2357 gen_rtx_REG (DImode, other_regno))); 2358 return true; 2359 } 2360 2361 /* We need to deal with constants that would be legitimate 2362 immediate_operands but not legitimate move_operands. */ 2363 if (CONSTANT_P (src) && !move_operand (src, mode)) 2364 { 2365 mips_legitimize_const_move (mode, dest, src); 2366 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src)); 2367 return true; 2368 } 2369 return false; 2370} 2371 2372/* We need a lot of little routines to check constant values on the 2373 mips16. These are used to figure out how long the instruction will 2374 be. It would be much better to do this using constraints, but 2375 there aren't nearly enough letters available. */ 2376 2377static int 2378m16_check_op (rtx op, int low, int high, int mask) 2379{ 2380 return (GET_CODE (op) == CONST_INT 2381 && INTVAL (op) >= low 2382 && INTVAL (op) <= high 2383 && (INTVAL (op) & mask) == 0); 2384} 2385 2386int 2387m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2388{ 2389 return m16_check_op (op, 0x1, 0x8, 0); 2390} 2391 2392int 2393m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2394{ 2395 return m16_check_op (op, - 0x8, 0x7, 0); 2396} 2397 2398int 2399m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2400{ 2401 return m16_check_op (op, - 0x7, 0x8, 0); 2402} 2403 2404int 2405m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2406{ 2407 return m16_check_op (op, - 0x10, 0xf, 0); 2408} 2409 2410int 2411m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2412{ 2413 return m16_check_op (op, - 0xf, 0x10, 0); 2414} 2415 2416int 2417m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2418{ 2419 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3); 2420} 2421 2422int 2423m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2424{ 2425 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3); 2426} 2427 2428int 2429m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2430{ 2431 return m16_check_op (op, - 0x80, 0x7f, 0); 2432} 2433 2434int 2435m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2436{ 2437 return m16_check_op (op, - 0x7f, 0x80, 0); 2438} 2439 2440int 2441m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2442{ 2443 return m16_check_op (op, 0x0, 0xff, 0); 2444} 2445 2446int 2447m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2448{ 2449 return m16_check_op (op, - 0xff, 0x0, 0); 2450} 2451 2452int 2453m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2454{ 2455 return m16_check_op (op, - 0x1, 0xfe, 0); 2456} 2457 2458int 2459m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2460{ 2461 return m16_check_op (op, 0x0, 0xff << 2, 3); 2462} 2463 2464int 2465m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2466{ 2467 return m16_check_op (op, (- 0xff) << 2, 0x0, 3); 2468} 2469 2470int 2471m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2472{ 2473 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7); 2474} 2475 2476int 2477m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 2478{ 2479 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7); 2480} 2481 2482static bool 2483mips_rtx_costs (rtx x, int code, int outer_code, int *total) 2484{ 2485 enum machine_mode mode = GET_MODE (x); 2486 bool float_mode_p = FLOAT_MODE_P (mode); 2487 2488 switch (code) 2489 { 2490 case CONST_INT: 2491 if (TARGET_MIPS16) 2492 { 2493 /* A number between 1 and 8 inclusive is efficient for a shift. 2494 Otherwise, we will need an extended instruction. */ 2495 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT 2496 || (outer_code) == LSHIFTRT) 2497 { 2498 if (INTVAL (x) >= 1 && INTVAL (x) <= 8) 2499 *total = 0; 2500 else 2501 *total = COSTS_N_INSNS (1); 2502 return true; 2503 } 2504 2505 /* We can use cmpi for an xor with an unsigned 16 bit value. */ 2506 if ((outer_code) == XOR 2507 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000) 2508 { 2509 *total = 0; 2510 return true; 2511 } 2512 2513 /* We may be able to use slt or sltu for a comparison with a 2514 signed 16 bit value. (The boundary conditions aren't quite 2515 right, but this is just a heuristic anyhow.) */ 2516 if (((outer_code) == LT || (outer_code) == LE 2517 || (outer_code) == GE || (outer_code) == GT 2518 || (outer_code) == LTU || (outer_code) == LEU 2519 || (outer_code) == GEU || (outer_code) == GTU) 2520 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000) 2521 { 2522 *total = 0; 2523 return true; 2524 } 2525 2526 /* Equality comparisons with 0 are cheap. */ 2527 if (((outer_code) == EQ || (outer_code) == NE) 2528 && INTVAL (x) == 0) 2529 { 2530 *total = 0; 2531 return true; 2532 } 2533 2534 /* Constants in the range 0...255 can be loaded with an unextended 2535 instruction. They are therefore as cheap as a register move. 2536 2537 Given the choice between "li R1,0...255" and "move R1,R2" 2538 (where R2 is a known constant), it is usually better to use "li", 2539 since we do not want to unnecessarily extend the lifetime 2540 of R2. */ 2541 if (outer_code == SET 2542 && INTVAL (x) >= 0 2543 && INTVAL (x) < 256) 2544 { 2545 *total = 0; 2546 return true; 2547 } 2548 } 2549 else 2550 { 2551 /* These can be used anywhere. */ 2552 *total = 0; 2553 return true; 2554 } 2555 2556 /* Otherwise fall through to the handling below because 2557 we'll need to construct the constant. */ 2558 2559 case CONST: 2560 case SYMBOL_REF: 2561 case LABEL_REF: 2562 case CONST_DOUBLE: 2563 if (LEGITIMATE_CONSTANT_P (x)) 2564 { 2565 *total = COSTS_N_INSNS (1); 2566 return true; 2567 } 2568 else 2569 { 2570 /* The value will need to be fetched from the constant pool. */ 2571 *total = CONSTANT_POOL_COST; 2572 return true; 2573 } 2574 2575 case MEM: 2576 { 2577 /* If the address is legitimate, return the number of 2578 instructions it needs, otherwise use the default handling. */ 2579 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x)); 2580 if (n > 0) 2581 { 2582 *total = COSTS_N_INSNS (n + 1); 2583 return true; 2584 } 2585 return false; 2586 } 2587 2588 case FFS: 2589 *total = COSTS_N_INSNS (6); 2590 return true; 2591 2592 case NOT: 2593 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1); 2594 return true; 2595 2596 case AND: 2597 case IOR: 2598 case XOR: 2599 if (mode == DImode && !TARGET_64BIT) 2600 { 2601 *total = COSTS_N_INSNS (2); 2602 return true; 2603 } 2604 return false; 2605 2606 case ASHIFT: 2607 case ASHIFTRT: 2608 case LSHIFTRT: 2609 if (mode == DImode && !TARGET_64BIT) 2610 { 2611 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT) 2612 ? 4 : 12); 2613 return true; 2614 } 2615 return false; 2616 2617 case ABS: 2618 if (float_mode_p) 2619 *total = COSTS_N_INSNS (1); 2620 else 2621 *total = COSTS_N_INSNS (4); 2622 return true; 2623 2624 case LO_SUM: 2625 *total = COSTS_N_INSNS (1); 2626 return true; 2627 2628 case PLUS: 2629 case MINUS: 2630 if (float_mode_p) 2631 { 2632 *total = mips_cost->fp_add; 2633 return true; 2634 } 2635 2636 else if (mode == DImode && !TARGET_64BIT) 2637 { 2638 *total = COSTS_N_INSNS (4); 2639 return true; 2640 } 2641 return false; 2642 2643 case NEG: 2644 if (mode == DImode && !TARGET_64BIT) 2645 { 2646 *total = COSTS_N_INSNS (4); 2647 return true; 2648 } 2649 return false; 2650 2651 case MULT: 2652 if (mode == SFmode) 2653 *total = mips_cost->fp_mult_sf; 2654 2655 else if (mode == DFmode) 2656 *total = mips_cost->fp_mult_df; 2657 2658 else if (mode == SImode) 2659 *total = mips_cost->int_mult_si; 2660 2661 else 2662 *total = mips_cost->int_mult_di; 2663 2664 return true; 2665 2666 case DIV: 2667 case MOD: 2668 if (float_mode_p) 2669 { 2670 if (mode == SFmode) 2671 *total = mips_cost->fp_div_sf; 2672 else 2673 *total = mips_cost->fp_div_df; 2674 2675 return true; 2676 } 2677 /* Fall through. */ 2678 2679 case UDIV: 2680 case UMOD: 2681 if (mode == DImode) 2682 *total = mips_cost->int_div_di; 2683 else 2684 *total = mips_cost->int_div_si; 2685 2686 return true; 2687 2688 case SIGN_EXTEND: 2689 /* A sign extend from SImode to DImode in 64 bit mode is often 2690 zero instructions, because the result can often be used 2691 directly by another instruction; we'll call it one. */ 2692 if (TARGET_64BIT && mode == DImode 2693 && GET_MODE (XEXP (x, 0)) == SImode) 2694 *total = COSTS_N_INSNS (1); 2695 else 2696 *total = COSTS_N_INSNS (2); 2697 return true; 2698 2699 case ZERO_EXTEND: 2700 if (TARGET_64BIT && mode == DImode 2701 && GET_MODE (XEXP (x, 0)) == SImode) 2702 *total = COSTS_N_INSNS (2); 2703 else 2704 *total = COSTS_N_INSNS (1); 2705 return true; 2706 2707 case FLOAT: 2708 case UNSIGNED_FLOAT: 2709 case FIX: 2710 case FLOAT_EXTEND: 2711 case FLOAT_TRUNCATE: 2712 case SQRT: 2713 *total = mips_cost->fp_add; 2714 return true; 2715 2716 default: 2717 return false; 2718 } 2719} 2720 2721/* Provide the costs of an addressing mode that contains ADDR. 2722 If ADDR is not a valid address, its cost is irrelevant. */ 2723 2724static int 2725mips_address_cost (rtx addr) 2726{ 2727 return mips_address_insns (addr, SImode); 2728} 2729 2730/* Return one word of double-word value OP, taking into account the fixed 2731 endianness of certain registers. HIGH_P is true to select the high part, 2732 false to select the low part. */ 2733 2734rtx 2735mips_subword (rtx op, int high_p) 2736{ 2737 unsigned int byte; 2738 enum machine_mode mode; 2739 2740 mode = GET_MODE (op); 2741 if (mode == VOIDmode) 2742 mode = DImode; 2743 2744 if (TARGET_BIG_ENDIAN ? !high_p : high_p) 2745 byte = UNITS_PER_WORD; 2746 else 2747 byte = 0; 2748 2749 if (REG_P (op)) 2750 { 2751 if (FP_REG_P (REGNO (op))) 2752 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op)); 2753 if (ACC_HI_REG_P (REGNO (op))) 2754 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1); 2755 } 2756 2757 if (MEM_P (op)) 2758 return mips_rewrite_small_data (adjust_address (op, word_mode, byte)); 2759 2760 return simplify_gen_subreg (word_mode, op, mode, byte); 2761} 2762 2763 2764/* Return true if a 64-bit move from SRC to DEST should be split into two. */ 2765 2766bool 2767mips_split_64bit_move_p (rtx dest, rtx src) 2768{ 2769 if (TARGET_64BIT) 2770 return false; 2771 2772 /* FP->FP moves can be done in a single instruction. */ 2773 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) 2774 return false; 2775 2776 /* Check for floating-point loads and stores. They can be done using 2777 ldc1 and sdc1 on MIPS II and above. */ 2778 if (mips_isa > 1) 2779 { 2780 if (FP_REG_RTX_P (dest) && MEM_P (src)) 2781 return false; 2782 if (FP_REG_RTX_P (src) && MEM_P (dest)) 2783 return false; 2784 } 2785 return true; 2786} 2787 2788 2789/* Split a 64-bit move from SRC to DEST assuming that 2790 mips_split_64bit_move_p holds. 2791 2792 Moves into and out of FPRs cause some difficulty here. Such moves 2793 will always be DFmode, since paired FPRs are not allowed to store 2794 DImode values. The most natural representation would be two separate 2795 32-bit moves, such as: 2796 2797 (set (reg:SI $f0) (mem:SI ...)) 2798 (set (reg:SI $f1) (mem:SI ...)) 2799 2800 However, the second insn is invalid because odd-numbered FPRs are 2801 not allowed to store independent values. Use the patterns load_df_low, 2802 load_df_high and store_df_high instead. */ 2803 2804void 2805mips_split_64bit_move (rtx dest, rtx src) 2806{ 2807 if (FP_REG_RTX_P (dest)) 2808 { 2809 /* Loading an FPR from memory or from GPRs. */ 2810 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0))); 2811 emit_insn (gen_load_df_high (dest, mips_subword (src, 1), 2812 copy_rtx (dest))); 2813 } 2814 else if (FP_REG_RTX_P (src)) 2815 { 2816 /* Storing an FPR into memory or GPRs. */ 2817 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0)); 2818 emit_insn (gen_store_df_high (mips_subword (dest, 1), src)); 2819 } 2820 else 2821 { 2822 /* The operation can be split into two normal moves. Decide in 2823 which order to do them. */ 2824 rtx low_dest; 2825 2826 low_dest = mips_subword (dest, 0); 2827 if (REG_P (low_dest) 2828 && reg_overlap_mentioned_p (low_dest, src)) 2829 { 2830 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1)); 2831 emit_move_insn (low_dest, mips_subword (src, 0)); 2832 } 2833 else 2834 { 2835 emit_move_insn (low_dest, mips_subword (src, 0)); 2836 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1)); 2837 } 2838 } 2839} 2840 2841/* Return the appropriate instructions to move SRC into DEST. Assume 2842 that SRC is operand 1 and DEST is operand 0. */ 2843 2844const char * 2845mips_output_move (rtx dest, rtx src) 2846{ 2847 enum rtx_code dest_code, src_code; 2848 bool dbl_p; 2849 2850 dest_code = GET_CODE (dest); 2851 src_code = GET_CODE (src); 2852 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8); 2853 2854 if (dbl_p && mips_split_64bit_move_p (dest, src)) 2855 return "#"; 2856 2857 if ((src_code == REG && GP_REG_P (REGNO (src))) 2858 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest)))) 2859 { 2860 if (dest_code == REG) 2861 { 2862 if (GP_REG_P (REGNO (dest))) 2863 return "move\t%0,%z1"; 2864 2865 if (MD_REG_P (REGNO (dest))) 2866 return "mt%0\t%z1"; 2867 2868 if (DSP_ACC_REG_P (REGNO (dest))) 2869 { 2870 static char retval[] = "mt__\t%z1,%q0"; 2871 retval[2] = reg_names[REGNO (dest)][4]; 2872 retval[3] = reg_names[REGNO (dest)][5]; 2873 return retval; 2874 } 2875 2876 if (FP_REG_P (REGNO (dest))) 2877 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0"); 2878 2879 if (ALL_COP_REG_P (REGNO (dest))) 2880 { 2881 static char retval[] = "dmtc_\t%z1,%0"; 2882 2883 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest)); 2884 return (dbl_p ? retval : retval + 1); 2885 } 2886 } 2887 if (dest_code == MEM) 2888 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0"); 2889 } 2890 if (dest_code == REG && GP_REG_P (REGNO (dest))) 2891 { 2892 if (src_code == REG) 2893 { 2894 if (DSP_ACC_REG_P (REGNO (src))) 2895 { 2896 static char retval[] = "mf__\t%0,%q1"; 2897 retval[2] = reg_names[REGNO (src)][4]; 2898 retval[3] = reg_names[REGNO (src)][5]; 2899 return retval; 2900 } 2901 2902 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC) 2903 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1"; 2904 2905 if (FP_REG_P (REGNO (src))) 2906 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1"); 2907 2908 if (ALL_COP_REG_P (REGNO (src))) 2909 { 2910 static char retval[] = "dmfc_\t%0,%1"; 2911 2912 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src)); 2913 return (dbl_p ? retval : retval + 1); 2914 } 2915 } 2916 2917 if (src_code == MEM) 2918 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1"); 2919 2920 if (src_code == CONST_INT) 2921 { 2922 /* Don't use the X format, because that will give out of 2923 range numbers for 64 bit hosts and 32 bit targets. */ 2924 if (!TARGET_MIPS16) 2925 return "li\t%0,%1\t\t\t# %X1"; 2926 2927 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff) 2928 return "li\t%0,%1"; 2929 2930 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff) 2931 return "#"; 2932 } 2933 2934 if (src_code == HIGH) 2935 return "lui\t%0,%h1"; 2936 2937 if (CONST_GP_P (src)) 2938 return "move\t%0,%1"; 2939 2940 if (symbolic_operand (src, VOIDmode)) 2941 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1"); 2942 } 2943 if (src_code == REG && FP_REG_P (REGNO (src))) 2944 { 2945 if (dest_code == REG && FP_REG_P (REGNO (dest))) 2946 { 2947 if (GET_MODE (dest) == V2SFmode) 2948 return "mov.ps\t%0,%1"; 2949 else 2950 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1"); 2951 } 2952 2953 if (dest_code == MEM) 2954 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0"); 2955 } 2956 if (dest_code == REG && FP_REG_P (REGNO (dest))) 2957 { 2958 if (src_code == MEM) 2959 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1"); 2960 } 2961 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM) 2962 { 2963 static char retval[] = "l_c_\t%0,%1"; 2964 2965 retval[1] = (dbl_p ? 'd' : 'w'); 2966 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest)); 2967 return retval; 2968 } 2969 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src))) 2970 { 2971 static char retval[] = "s_c_\t%1,%0"; 2972 2973 retval[1] = (dbl_p ? 'd' : 'w'); 2974 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src)); 2975 return retval; 2976 } 2977 gcc_unreachable (); 2978} 2979 2980/* Restore $gp from its save slot. Valid only when using o32 or 2981 o64 abicalls. */ 2982 2983void 2984mips_restore_gp (void) 2985{ 2986 rtx address, slot; 2987 2988 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI); 2989 2990 address = mips_add_offset (pic_offset_table_rtx, 2991 frame_pointer_needed 2992 ? hard_frame_pointer_rtx 2993 : stack_pointer_rtx, 2994 current_function_outgoing_args_size); 2995 slot = gen_rtx_MEM (Pmode, address); 2996 2997 emit_move_insn (pic_offset_table_rtx, slot); 2998 if (!TARGET_EXPLICIT_RELOCS) 2999 emit_insn (gen_blockage ()); 3000} 3001 3002/* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */ 3003 3004static void 3005mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1) 3006{ 3007 emit_insn (gen_rtx_SET (VOIDmode, target, 3008 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1))); 3009} 3010 3011/* Return true if CMP1 is a suitable second operand for relational 3012 operator CODE. See also the *sCC patterns in mips.md. */ 3013 3014static bool 3015mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1) 3016{ 3017 switch (code) 3018 { 3019 case GT: 3020 case GTU: 3021 return reg_or_0_operand (cmp1, VOIDmode); 3022 3023 case GE: 3024 case GEU: 3025 return !TARGET_MIPS16 && cmp1 == const1_rtx; 3026 3027 case LT: 3028 case LTU: 3029 return arith_operand (cmp1, VOIDmode); 3030 3031 case LE: 3032 return sle_operand (cmp1, VOIDmode); 3033 3034 case LEU: 3035 return sleu_operand (cmp1, VOIDmode); 3036 3037 default: 3038 gcc_unreachable (); 3039 } 3040} 3041 3042/* Canonicalize LE or LEU comparisons into LT comparisons when 3043 possible to avoid extra instructions or inverting the 3044 comparison. */ 3045 3046static bool 3047mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1, 3048 enum machine_mode mode) 3049{ 3050 HOST_WIDE_INT original, plus_one; 3051 3052 if (GET_CODE (*cmp1) != CONST_INT) 3053 return false; 3054 3055 original = INTVAL (*cmp1); 3056 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode); 3057 3058 switch (*code) 3059 { 3060 case LE: 3061 if (original < plus_one) 3062 { 3063 *code = LT; 3064 *cmp1 = force_reg (mode, GEN_INT (plus_one)); 3065 return true; 3066 } 3067 break; 3068 3069 case LEU: 3070 if (plus_one != 0) 3071 { 3072 *code = LTU; 3073 *cmp1 = force_reg (mode, GEN_INT (plus_one)); 3074 return true; 3075 } 3076 break; 3077 3078 default: 3079 return false; 3080 } 3081 3082 return false; 3083 3084} 3085 3086/* Compare CMP0 and CMP1 using relational operator CODE and store the 3087 result in TARGET. CMP0 and TARGET are register_operands that have 3088 the same integer mode. If INVERT_PTR is nonnull, it's OK to set 3089 TARGET to the inverse of the result and flip *INVERT_PTR instead. */ 3090 3091static void 3092mips_emit_int_relational (enum rtx_code code, bool *invert_ptr, 3093 rtx target, rtx cmp0, rtx cmp1) 3094{ 3095 /* First see if there is a MIPS instruction that can do this operation 3096 with CMP1 in its current form. If not, try to canonicalize the 3097 comparison to LT. If that fails, try doing the same for the 3098 inverse operation. If that also fails, force CMP1 into a register 3099 and try again. */ 3100 if (mips_relational_operand_ok_p (code, cmp1)) 3101 mips_emit_binary (code, target, cmp0, cmp1); 3102 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target))) 3103 mips_emit_binary (code, target, cmp0, cmp1); 3104 else 3105 { 3106 enum rtx_code inv_code = reverse_condition (code); 3107 if (!mips_relational_operand_ok_p (inv_code, cmp1)) 3108 { 3109 cmp1 = force_reg (GET_MODE (cmp0), cmp1); 3110 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1); 3111 } 3112 else if (invert_ptr == 0) 3113 { 3114 rtx inv_target = gen_reg_rtx (GET_MODE (target)); 3115 mips_emit_binary (inv_code, inv_target, cmp0, cmp1); 3116 mips_emit_binary (XOR, target, inv_target, const1_rtx); 3117 } 3118 else 3119 { 3120 *invert_ptr = !*invert_ptr; 3121 mips_emit_binary (inv_code, target, cmp0, cmp1); 3122 } 3123 } 3124} 3125 3126/* Return a register that is zero iff CMP0 and CMP1 are equal. 3127 The register will have the same mode as CMP0. */ 3128 3129static rtx 3130mips_zero_if_equal (rtx cmp0, rtx cmp1) 3131{ 3132 if (cmp1 == const0_rtx) 3133 return cmp0; 3134 3135 if (uns_arith_operand (cmp1, VOIDmode)) 3136 return expand_binop (GET_MODE (cmp0), xor_optab, 3137 cmp0, cmp1, 0, 0, OPTAB_DIRECT); 3138 3139 return expand_binop (GET_MODE (cmp0), sub_optab, 3140 cmp0, cmp1, 0, 0, OPTAB_DIRECT); 3141} 3142 3143/* Convert *CODE into a code that can be used in a floating-point 3144 scc instruction (c.<cond>.<fmt>). Return true if the values of 3145 the condition code registers will be inverted, with 0 indicating 3146 that the condition holds. */ 3147 3148static bool 3149mips_reverse_fp_cond_p (enum rtx_code *code) 3150{ 3151 switch (*code) 3152 { 3153 case NE: 3154 case LTGT: 3155 case ORDERED: 3156 *code = reverse_condition_maybe_unordered (*code); 3157 return true; 3158 3159 default: 3160 return false; 3161 } 3162} 3163 3164/* Convert a comparison into something that can be used in a branch or 3165 conditional move. cmp_operands[0] and cmp_operands[1] are the values 3166 being compared and *CODE is the code used to compare them. 3167 3168 Update *CODE, *OP0 and *OP1 so that they describe the final comparison. 3169 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible, 3170 otherwise any standard branch condition can be used. The standard branch 3171 conditions are: 3172 3173 - EQ/NE between two registers. 3174 - any comparison between a register and zero. */ 3175 3176static void 3177mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p) 3178{ 3179 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT) 3180 { 3181 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx) 3182 { 3183 *op0 = cmp_operands[0]; 3184 *op1 = cmp_operands[1]; 3185 } 3186 else if (*code == EQ || *code == NE) 3187 { 3188 if (need_eq_ne_p) 3189 { 3190 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]); 3191 *op1 = const0_rtx; 3192 } 3193 else 3194 { 3195 *op0 = cmp_operands[0]; 3196 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]); 3197 } 3198 } 3199 else 3200 { 3201 /* The comparison needs a separate scc instruction. Store the 3202 result of the scc in *OP0 and compare it against zero. */ 3203 bool invert = false; 3204 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0])); 3205 *op1 = const0_rtx; 3206 mips_emit_int_relational (*code, &invert, *op0, 3207 cmp_operands[0], cmp_operands[1]); 3208 *code = (invert ? EQ : NE); 3209 } 3210 } 3211 else 3212 { 3213 enum rtx_code cmp_code; 3214 3215 /* Floating-point tests use a separate c.cond.fmt comparison to 3216 set a condition code register. The branch or conditional move 3217 will then compare that register against zero. 3218 3219 Set CMP_CODE to the code of the comparison instruction and 3220 *CODE to the code that the branch or move should use. */ 3221 cmp_code = *code; 3222 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE; 3223 *op0 = (ISA_HAS_8CC 3224 ? gen_reg_rtx (CCmode) 3225 : gen_rtx_REG (CCmode, FPSW_REGNUM)); 3226 *op1 = const0_rtx; 3227 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]); 3228 } 3229} 3230 3231/* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE. 3232 Store the result in TARGET and return true if successful. 3233 3234 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */ 3235 3236bool 3237mips_emit_scc (enum rtx_code code, rtx target) 3238{ 3239 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT) 3240 return false; 3241 3242 target = gen_lowpart (GET_MODE (cmp_operands[0]), target); 3243 if (code == EQ || code == NE) 3244 { 3245 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]); 3246 mips_emit_binary (code, target, zie, const0_rtx); 3247 } 3248 else 3249 mips_emit_int_relational (code, 0, target, 3250 cmp_operands[0], cmp_operands[1]); 3251 return true; 3252} 3253 3254/* Emit the common code for doing conditional branches. 3255 operand[0] is the label to jump to. 3256 The comparison operands are saved away by cmp{si,di,sf,df}. */ 3257 3258void 3259gen_conditional_branch (rtx *operands, enum rtx_code code) 3260{ 3261 rtx op0, op1, condition; 3262 3263 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16); 3264 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1); 3265 emit_jump_insn (gen_condjump (condition, operands[0])); 3266} 3267 3268/* Implement: 3269 3270 (set temp (COND:CCV2 CMP_OP0 CMP_OP1)) 3271 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */ 3272 3273void 3274mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src, 3275 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1) 3276{ 3277 rtx cmp_result; 3278 bool reversed_p; 3279 3280 reversed_p = mips_reverse_fp_cond_p (&cond); 3281 cmp_result = gen_reg_rtx (CCV2mode); 3282 emit_insn (gen_scc_ps (cmp_result, 3283 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1))); 3284 if (reversed_p) 3285 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src, 3286 cmp_result)); 3287 else 3288 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src, 3289 cmp_result)); 3290} 3291 3292/* Emit the common code for conditional moves. OPERANDS is the array 3293 of operands passed to the conditional move define_expand. */ 3294 3295void 3296gen_conditional_move (rtx *operands) 3297{ 3298 enum rtx_code code; 3299 rtx op0, op1; 3300 3301 code = GET_CODE (operands[1]); 3302 mips_emit_compare (&code, &op0, &op1, true); 3303 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 3304 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), 3305 gen_rtx_fmt_ee (code, 3306 GET_MODE (op0), 3307 op0, op1), 3308 operands[2], operands[3]))); 3309} 3310 3311/* Emit a conditional trap. OPERANDS is the array of operands passed to 3312 the conditional_trap expander. */ 3313 3314void 3315mips_gen_conditional_trap (rtx *operands) 3316{ 3317 rtx op0, op1; 3318 enum rtx_code cmp_code = GET_CODE (operands[0]); 3319 enum machine_mode mode = GET_MODE (cmp_operands[0]); 3320 3321 /* MIPS conditional trap machine instructions don't have GT or LE 3322 flavors, so we must invert the comparison and convert to LT and 3323 GE, respectively. */ 3324 switch (cmp_code) 3325 { 3326 case GT: cmp_code = LT; break; 3327 case LE: cmp_code = GE; break; 3328 case GTU: cmp_code = LTU; break; 3329 case LEU: cmp_code = GEU; break; 3330 default: break; 3331 } 3332 if (cmp_code == GET_CODE (operands[0])) 3333 { 3334 op0 = cmp_operands[0]; 3335 op1 = cmp_operands[1]; 3336 } 3337 else 3338 { 3339 op0 = cmp_operands[1]; 3340 op1 = cmp_operands[0]; 3341 } 3342 op0 = force_reg (mode, op0); 3343 if (!arith_operand (op1, mode)) 3344 op1 = force_reg (mode, op1); 3345 3346 emit_insn (gen_rtx_TRAP_IF (VOIDmode, 3347 gen_rtx_fmt_ee (cmp_code, mode, op0, op1), 3348 operands[1])); 3349} 3350 3351/* Load function address ADDR into register DEST. SIBCALL_P is true 3352 if the address is needed for a sibling call. */ 3353 3354static void 3355mips_load_call_address (rtx dest, rtx addr, int sibcall_p) 3356{ 3357 /* If we're generating PIC, and this call is to a global function, 3358 try to allow its address to be resolved lazily. This isn't 3359 possible for NewABI sibcalls since the value of $gp on entry 3360 to the stub would be our caller's gp, not ours. */ 3361 if (TARGET_EXPLICIT_RELOCS 3362 && !(sibcall_p && TARGET_NEWABI) 3363 && global_got_operand (addr, VOIDmode)) 3364 { 3365 rtx high, lo_sum_symbol; 3366 3367 high = mips_unspec_offset_high (dest, pic_offset_table_rtx, 3368 addr, SYMBOL_GOTOFF_CALL); 3369 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL); 3370 if (Pmode == SImode) 3371 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol)); 3372 else 3373 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol)); 3374 } 3375 else 3376 emit_move_insn (dest, addr); 3377} 3378 3379 3380/* Expand a call or call_value instruction. RESULT is where the 3381 result will go (null for calls), ADDR is the address of the 3382 function, ARGS_SIZE is the size of the arguments and AUX is 3383 the value passed to us by mips_function_arg. SIBCALL_P is true 3384 if we are expanding a sibling call, false if we're expanding 3385 a normal call. */ 3386 3387void 3388mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p) 3389{ 3390 rtx orig_addr, pattern, insn; 3391 3392 orig_addr = addr; 3393 if (!call_insn_operand (addr, VOIDmode)) 3394 { 3395 addr = gen_reg_rtx (Pmode); 3396 mips_load_call_address (addr, orig_addr, sibcall_p); 3397 } 3398 3399 if (TARGET_MIPS16 3400 && mips16_hard_float 3401 && build_mips16_call_stub (result, addr, args_size, 3402 aux == 0 ? 0 : (int) GET_MODE (aux))) 3403 return; 3404 3405 if (result == 0) 3406 pattern = (sibcall_p 3407 ? gen_sibcall_internal (addr, args_size) 3408 : gen_call_internal (addr, args_size)); 3409 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2) 3410 { 3411 rtx reg1, reg2; 3412 3413 reg1 = XEXP (XVECEXP (result, 0, 0), 0); 3414 reg2 = XEXP (XVECEXP (result, 0, 1), 0); 3415 pattern = 3416 (sibcall_p 3417 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2) 3418 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2)); 3419 } 3420 else 3421 pattern = (sibcall_p 3422 ? gen_sibcall_value_internal (result, addr, args_size) 3423 : gen_call_value_internal (result, addr, args_size)); 3424 3425 insn = emit_call_insn (pattern); 3426 3427 /* Lazy-binding stubs require $gp to be valid on entry. */ 3428 if (global_got_operand (orig_addr, VOIDmode)) 3429 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); 3430} 3431 3432 3433/* We can handle any sibcall when TARGET_SIBCALLS is true. */ 3434 3435static bool 3436mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, 3437 tree exp ATTRIBUTE_UNUSED) 3438{ 3439 return TARGET_SIBCALLS; 3440} 3441 3442/* Emit code to move general operand SRC into condition-code 3443 register DEST. SCRATCH is a scratch TFmode float register. 3444 The sequence is: 3445 3446 FP1 = SRC 3447 FP2 = 0.0f 3448 DEST = FP2 < FP1 3449 3450 where FP1 and FP2 are single-precision float registers 3451 taken from SCRATCH. */ 3452 3453void 3454mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch) 3455{ 3456 rtx fp1, fp2; 3457 3458 /* Change the source to SFmode. */ 3459 if (MEM_P (src)) 3460 src = adjust_address (src, SFmode, 0); 3461 else if (REG_P (src) || GET_CODE (src) == SUBREG) 3462 src = gen_rtx_REG (SFmode, true_regnum (src)); 3463 3464 fp1 = gen_rtx_REG (SFmode, REGNO (scratch)); 3465 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC); 3466 3467 emit_move_insn (copy_rtx (fp1), src); 3468 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode)); 3469 emit_insn (gen_slt_sf (dest, fp2, fp1)); 3470} 3471 3472/* Emit code to change the current function's return address to 3473 ADDRESS. SCRATCH is available as a scratch register, if needed. 3474 ADDRESS and SCRATCH are both word-mode GPRs. */ 3475 3476void 3477mips_set_return_address (rtx address, rtx scratch) 3478{ 3479 rtx slot_address; 3480 3481 compute_frame_size (get_frame_size ()); 3482 gcc_assert ((cfun->machine->frame.mask >> 31) & 1); 3483 slot_address = mips_add_offset (scratch, stack_pointer_rtx, 3484 cfun->machine->frame.gp_sp_offset); 3485 3486 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address); 3487} 3488 3489/* Emit straight-line code to move LENGTH bytes from SRC to DEST. 3490 Assume that the areas do not overlap. */ 3491 3492static void 3493mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length) 3494{ 3495 HOST_WIDE_INT offset, delta; 3496 unsigned HOST_WIDE_INT bits; 3497 int i; 3498 enum machine_mode mode; 3499 rtx *regs; 3500 3501 /* Work out how many bits to move at a time. If both operands have 3502 half-word alignment, it is usually better to move in half words. 3503 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr 3504 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr. 3505 Otherwise move word-sized chunks. */ 3506 if (MEM_ALIGN (src) == BITS_PER_WORD / 2 3507 && MEM_ALIGN (dest) == BITS_PER_WORD / 2) 3508 bits = BITS_PER_WORD / 2; 3509 else 3510 bits = BITS_PER_WORD; 3511 3512 mode = mode_for_size (bits, MODE_INT, 0); 3513 delta = bits / BITS_PER_UNIT; 3514 3515 /* Allocate a buffer for the temporary registers. */ 3516 regs = alloca (sizeof (rtx) * length / delta); 3517 3518 /* Load as many BITS-sized chunks as possible. Use a normal load if 3519 the source has enough alignment, otherwise use left/right pairs. */ 3520 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) 3521 { 3522 regs[i] = gen_reg_rtx (mode); 3523 if (MEM_ALIGN (src) >= bits) 3524 emit_move_insn (regs[i], adjust_address (src, mode, offset)); 3525 else 3526 { 3527 rtx part = adjust_address (src, BLKmode, offset); 3528 if (!mips_expand_unaligned_load (regs[i], part, bits, 0)) 3529 gcc_unreachable (); 3530 } 3531 } 3532 3533 /* Copy the chunks to the destination. */ 3534 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) 3535 if (MEM_ALIGN (dest) >= bits) 3536 emit_move_insn (adjust_address (dest, mode, offset), regs[i]); 3537 else 3538 { 3539 rtx part = adjust_address (dest, BLKmode, offset); 3540 if (!mips_expand_unaligned_store (part, regs[i], bits, 0)) 3541 gcc_unreachable (); 3542 } 3543 3544 /* Mop up any left-over bytes. */ 3545 if (offset < length) 3546 { 3547 src = adjust_address (src, BLKmode, offset); 3548 dest = adjust_address (dest, BLKmode, offset); 3549 move_by_pieces (dest, src, length - offset, 3550 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0); 3551 } 3552} 3553 3554#define MAX_MOVE_REGS 4 3555#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD) 3556 3557 3558/* Helper function for doing a loop-based block operation on memory 3559 reference MEM. Each iteration of the loop will operate on LENGTH 3560 bytes of MEM. 3561 3562 Create a new base register for use within the loop and point it to 3563 the start of MEM. Create a new memory reference that uses this 3564 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */ 3565 3566static void 3567mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length, 3568 rtx *loop_reg, rtx *loop_mem) 3569{ 3570 *loop_reg = copy_addr_to_reg (XEXP (mem, 0)); 3571 3572 /* Although the new mem does not refer to a known location, 3573 it does keep up to LENGTH bytes of alignment. */ 3574 *loop_mem = change_address (mem, BLKmode, *loop_reg); 3575 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT)); 3576} 3577 3578 3579/* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES 3580 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the 3581 memory regions do not overlap. */ 3582 3583static void 3584mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length) 3585{ 3586 rtx label, src_reg, dest_reg, final_src; 3587 HOST_WIDE_INT leftover; 3588 3589 leftover = length % MAX_MOVE_BYTES; 3590 length -= leftover; 3591 3592 /* Create registers and memory references for use within the loop. */ 3593 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src); 3594 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest); 3595 3596 /* Calculate the value that SRC_REG should have after the last iteration 3597 of the loop. */ 3598 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length), 3599 0, 0, OPTAB_WIDEN); 3600 3601 /* Emit the start of the loop. */ 3602 label = gen_label_rtx (); 3603 emit_label (label); 3604 3605 /* Emit the loop body. */ 3606 mips_block_move_straight (dest, src, MAX_MOVE_BYTES); 3607 3608 /* Move on to the next block. */ 3609 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES)); 3610 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES)); 3611 3612 /* Emit the loop condition. */ 3613 if (Pmode == DImode) 3614 emit_insn (gen_cmpdi (src_reg, final_src)); 3615 else 3616 emit_insn (gen_cmpsi (src_reg, final_src)); 3617 emit_jump_insn (gen_bne (label)); 3618 3619 /* Mop up any left-over bytes. */ 3620 if (leftover) 3621 mips_block_move_straight (dest, src, leftover); 3622} 3623 3624/* Expand a movmemsi instruction. */ 3625 3626bool 3627mips_expand_block_move (rtx dest, rtx src, rtx length) 3628{ 3629 if (GET_CODE (length) == CONST_INT) 3630 { 3631 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES) 3632 { 3633 mips_block_move_straight (dest, src, INTVAL (length)); 3634 return true; 3635 } 3636 else if (optimize) 3637 { 3638 mips_block_move_loop (dest, src, INTVAL (length)); 3639 return true; 3640 } 3641 } 3642 return false; 3643} 3644 3645/* Argument support functions. */ 3646 3647/* Initialize CUMULATIVE_ARGS for a function. */ 3648 3649void 3650init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, 3651 rtx libname ATTRIBUTE_UNUSED) 3652{ 3653 static CUMULATIVE_ARGS zero_cum; 3654 tree param, next_param; 3655 3656 *cum = zero_cum; 3657 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); 3658 3659 /* Determine if this function has variable arguments. This is 3660 indicated by the last argument being 'void_type_mode' if there 3661 are no variable arguments. The standard MIPS calling sequence 3662 passes all arguments in the general purpose registers in this case. */ 3663 3664 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0; 3665 param != 0; param = next_param) 3666 { 3667 next_param = TREE_CHAIN (param); 3668 if (next_param == 0 && TREE_VALUE (param) != void_type_node) 3669 cum->gp_reg_found = 1; 3670 } 3671} 3672 3673 3674/* Fill INFO with information about a single argument. CUM is the 3675 cumulative state for earlier arguments. MODE is the mode of this 3676 argument and TYPE is its type (if known). NAMED is true if this 3677 is a named (fixed) argument rather than a variable one. */ 3678 3679static void 3680mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode, 3681 tree type, int named, struct mips_arg_info *info) 3682{ 3683 bool doubleword_aligned_p; 3684 unsigned int num_bytes, num_words, max_regs; 3685 3686 /* Work out the size of the argument. */ 3687 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); 3688 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 3689 3690 /* Decide whether it should go in a floating-point register, assuming 3691 one is free. Later code checks for availability. 3692 3693 The checks against UNITS_PER_FPVALUE handle the soft-float and 3694 single-float cases. */ 3695 switch (mips_abi) 3696 { 3697 case ABI_EABI: 3698 /* The EABI conventions have traditionally been defined in terms 3699 of TYPE_MODE, regardless of the actual type. */ 3700 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT 3701 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) 3702 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE); 3703 break; 3704 3705 case ABI_32: 3706 case ABI_O64: 3707 /* Only leading floating-point scalars are passed in 3708 floating-point registers. We also handle vector floats the same 3709 say, which is OK because they are not covered by the standard ABI. */ 3710 info->fpr_p = (!cum->gp_reg_found 3711 && cum->arg_number < 2 3712 && (type == 0 || SCALAR_FLOAT_TYPE_P (type) 3713 || VECTOR_FLOAT_TYPE_P (type)) 3714 && (GET_MODE_CLASS (mode) == MODE_FLOAT 3715 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) 3716 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE); 3717 break; 3718 3719 case ABI_N32: 3720 case ABI_64: 3721 /* Scalar and complex floating-point types are passed in 3722 floating-point registers. */ 3723 info->fpr_p = (named 3724 && (type == 0 || FLOAT_TYPE_P (type)) 3725 && (GET_MODE_CLASS (mode) == MODE_FLOAT 3726 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT 3727 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) 3728 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE); 3729 3730 /* ??? According to the ABI documentation, the real and imaginary 3731 parts of complex floats should be passed in individual registers. 3732 The real and imaginary parts of stack arguments are supposed 3733 to be contiguous and there should be an extra word of padding 3734 at the end. 3735 3736 This has two problems. First, it makes it impossible to use a 3737 single "void *" va_list type, since register and stack arguments 3738 are passed differently. (At the time of writing, MIPSpro cannot 3739 handle complex float varargs correctly.) Second, it's unclear 3740 what should happen when there is only one register free. 3741 3742 For now, we assume that named complex floats should go into FPRs 3743 if there are two FPRs free, otherwise they should be passed in the 3744 same way as a struct containing two floats. */ 3745 if (info->fpr_p 3746 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT 3747 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE) 3748 { 3749 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1) 3750 info->fpr_p = false; 3751 else 3752 num_words = 2; 3753 } 3754 break; 3755 3756 default: 3757 gcc_unreachable (); 3758 } 3759 3760 /* See whether the argument has doubleword alignment. */ 3761 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD; 3762 3763 /* Set REG_OFFSET to the register count we're interested in. 3764 The EABI allocates the floating-point registers separately, 3765 but the other ABIs allocate them like integer registers. */ 3766 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p 3767 ? cum->num_fprs 3768 : cum->num_gprs); 3769 3770 /* Advance to an even register if the argument is doubleword-aligned. */ 3771 if (doubleword_aligned_p) 3772 info->reg_offset += info->reg_offset & 1; 3773 3774 /* Work out the offset of a stack argument. */ 3775 info->stack_offset = cum->stack_words; 3776 if (doubleword_aligned_p) 3777 info->stack_offset += info->stack_offset & 1; 3778 3779 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset; 3780 3781 /* Partition the argument between registers and stack. */ 3782 info->reg_words = MIN (num_words, max_regs); 3783 info->stack_words = num_words - info->reg_words; 3784} 3785 3786 3787/* Implement FUNCTION_ARG_ADVANCE. */ 3788 3789void 3790function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, 3791 tree type, int named) 3792{ 3793 struct mips_arg_info info; 3794 3795 mips_arg_info (cum, mode, type, named, &info); 3796 3797 if (!info.fpr_p) 3798 cum->gp_reg_found = true; 3799 3800 /* See the comment above the cumulative args structure in mips.h 3801 for an explanation of what this code does. It assumes the O32 3802 ABI, which passes at most 2 arguments in float registers. */ 3803 if (cum->arg_number < 2 && info.fpr_p) 3804 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2); 3805 3806 if (mips_abi != ABI_EABI || !info.fpr_p) 3807 cum->num_gprs = info.reg_offset + info.reg_words; 3808 else if (info.reg_words > 0) 3809 cum->num_fprs += FP_INC; 3810 3811 if (info.stack_words > 0) 3812 cum->stack_words = info.stack_offset + info.stack_words; 3813 3814 cum->arg_number++; 3815} 3816 3817/* Implement FUNCTION_ARG. */ 3818 3819struct rtx_def * 3820function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode, 3821 tree type, int named) 3822{ 3823 struct mips_arg_info info; 3824 3825 /* We will be called with a mode of VOIDmode after the last argument 3826 has been seen. Whatever we return will be passed to the call 3827 insn. If we need a mips16 fp_code, return a REG with the code 3828 stored as the mode. */ 3829 if (mode == VOIDmode) 3830 { 3831 if (TARGET_MIPS16 && cum->fp_code != 0) 3832 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0); 3833 3834 else 3835 return 0; 3836 } 3837 3838 mips_arg_info (cum, mode, type, named, &info); 3839 3840 /* Return straight away if the whole argument is passed on the stack. */ 3841 if (info.reg_offset == MAX_ARGS_IN_REGISTERS) 3842 return 0; 3843 3844 if (type != 0 3845 && TREE_CODE (type) == RECORD_TYPE 3846 && TARGET_NEWABI 3847 && TYPE_SIZE_UNIT (type) 3848 && host_integerp (TYPE_SIZE_UNIT (type), 1) 3849 && named) 3850 { 3851 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the 3852 structure contains a double in its entirety, then that 64 bit 3853 chunk is passed in a floating point register. */ 3854 tree field; 3855 3856 /* First check to see if there is any such field. */ 3857 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 3858 if (TREE_CODE (field) == FIELD_DECL 3859 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE 3860 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD 3861 && host_integerp (bit_position (field), 0) 3862 && int_bit_position (field) % BITS_PER_WORD == 0) 3863 break; 3864 3865 if (field != 0) 3866 { 3867 /* Now handle the special case by returning a PARALLEL 3868 indicating where each 64 bit chunk goes. INFO.REG_WORDS 3869 chunks are passed in registers. */ 3870 unsigned int i; 3871 HOST_WIDE_INT bitpos; 3872 rtx ret; 3873 3874 /* assign_parms checks the mode of ENTRY_PARM, so we must 3875 use the actual mode here. */ 3876 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words)); 3877 3878 bitpos = 0; 3879 field = TYPE_FIELDS (type); 3880 for (i = 0; i < info.reg_words; i++) 3881 { 3882 rtx reg; 3883 3884 for (; field; field = TREE_CHAIN (field)) 3885 if (TREE_CODE (field) == FIELD_DECL 3886 && int_bit_position (field) >= bitpos) 3887 break; 3888 3889 if (field 3890 && int_bit_position (field) == bitpos 3891 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE 3892 && !TARGET_SOFT_FLOAT 3893 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD) 3894 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i); 3895 else 3896 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i); 3897 3898 XVECEXP (ret, 0, i) 3899 = gen_rtx_EXPR_LIST (VOIDmode, reg, 3900 GEN_INT (bitpos / BITS_PER_UNIT)); 3901 3902 bitpos += BITS_PER_WORD; 3903 } 3904 return ret; 3905 } 3906 } 3907 3908 /* Handle the n32/n64 conventions for passing complex floating-point 3909 arguments in FPR pairs. The real part goes in the lower register 3910 and the imaginary part goes in the upper register. */ 3911 if (TARGET_NEWABI 3912 && info.fpr_p 3913 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 3914 { 3915 rtx real, imag; 3916 enum machine_mode inner; 3917 int reg; 3918 3919 inner = GET_MODE_INNER (mode); 3920 reg = FP_ARG_FIRST + info.reg_offset; 3921 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner)) 3922 { 3923 /* Real part in registers, imaginary part on stack. */ 3924 gcc_assert (info.stack_words == info.reg_words); 3925 return gen_rtx_REG (inner, reg); 3926 } 3927 else 3928 { 3929 gcc_assert (info.stack_words == 0); 3930 real = gen_rtx_EXPR_LIST (VOIDmode, 3931 gen_rtx_REG (inner, reg), 3932 const0_rtx); 3933 imag = gen_rtx_EXPR_LIST (VOIDmode, 3934 gen_rtx_REG (inner, 3935 reg + info.reg_words / 2), 3936 GEN_INT (GET_MODE_SIZE (inner))); 3937 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag)); 3938 } 3939 } 3940 3941 if (!info.fpr_p) 3942 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset); 3943 else if (info.reg_offset == 1) 3944 /* This code handles the special o32 case in which the second word 3945 of the argument structure is passed in floating-point registers. */ 3946 return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC); 3947 else 3948 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset); 3949} 3950 3951 3952/* Implement TARGET_ARG_PARTIAL_BYTES. */ 3953 3954static int 3955mips_arg_partial_bytes (CUMULATIVE_ARGS *cum, 3956 enum machine_mode mode, tree type, bool named) 3957{ 3958 struct mips_arg_info info; 3959 3960 mips_arg_info (cum, mode, type, named, &info); 3961 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0; 3962} 3963 3964 3965/* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least 3966 PARM_BOUNDARY bits of alignment, but will be given anything up 3967 to STACK_BOUNDARY bits if the type requires it. */ 3968 3969int 3970function_arg_boundary (enum machine_mode mode, tree type) 3971{ 3972 unsigned int alignment; 3973 3974 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); 3975 if (alignment < PARM_BOUNDARY) 3976 alignment = PARM_BOUNDARY; 3977 if (alignment > STACK_BOUNDARY) 3978 alignment = STACK_BOUNDARY; 3979 return alignment; 3980} 3981 3982/* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return 3983 upward rather than downward. In other words, return true if the 3984 first byte of the stack slot has useful data, false if the last 3985 byte does. */ 3986 3987bool 3988mips_pad_arg_upward (enum machine_mode mode, tree type) 3989{ 3990 /* On little-endian targets, the first byte of every stack argument 3991 is passed in the first byte of the stack slot. */ 3992 if (!BYTES_BIG_ENDIAN) 3993 return true; 3994 3995 /* Otherwise, integral types are padded downward: the last byte of a 3996 stack argument is passed in the last byte of the stack slot. */ 3997 if (type != 0 3998 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type) 3999 : GET_MODE_CLASS (mode) == MODE_INT) 4000 return false; 4001 4002 /* Big-endian o64 pads floating-point arguments downward. */ 4003 if (mips_abi == ABI_O64) 4004 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT) 4005 return false; 4006 4007 /* Other types are padded upward for o32, o64, n32 and n64. */ 4008 if (mips_abi != ABI_EABI) 4009 return true; 4010 4011 /* Arguments smaller than a stack slot are padded downward. */ 4012 if (mode != BLKmode) 4013 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY); 4014 else 4015 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT)); 4016} 4017 4018 4019/* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN 4020 if the least significant byte of the register has useful data. Return 4021 the opposite if the most significant byte does. */ 4022 4023bool 4024mips_pad_reg_upward (enum machine_mode mode, tree type) 4025{ 4026 /* No shifting is required for floating-point arguments. */ 4027 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT) 4028 return !BYTES_BIG_ENDIAN; 4029 4030 /* Otherwise, apply the same padding to register arguments as we do 4031 to stack arguments. */ 4032 return mips_pad_arg_upward (mode, type); 4033} 4034 4035static void 4036mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, 4037 tree type, int *pretend_size ATTRIBUTE_UNUSED, 4038 int no_rtl) 4039{ 4040 CUMULATIVE_ARGS local_cum; 4041 int gp_saved, fp_saved; 4042 4043 /* The caller has advanced CUM up to, but not beyond, the last named 4044 argument. Advance a local copy of CUM past the last "real" named 4045 argument, to find out how many registers are left over. */ 4046 4047 local_cum = *cum; 4048 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1); 4049 4050 /* Found out how many registers we need to save. */ 4051 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs; 4052 fp_saved = (EABI_FLOAT_VARARGS_P 4053 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs 4054 : 0); 4055 4056 if (!no_rtl) 4057 { 4058 if (gp_saved > 0) 4059 { 4060 rtx ptr, mem; 4061 4062 ptr = plus_constant (virtual_incoming_args_rtx, 4063 REG_PARM_STACK_SPACE (cfun->decl) 4064 - gp_saved * UNITS_PER_WORD); 4065 mem = gen_rtx_MEM (BLKmode, ptr); 4066 set_mem_alias_set (mem, get_varargs_alias_set ()); 4067 4068 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, 4069 mem, gp_saved); 4070 } 4071 if (fp_saved > 0) 4072 { 4073 /* We can't use move_block_from_reg, because it will use 4074 the wrong mode. */ 4075 enum machine_mode mode; 4076 int off, i; 4077 4078 /* Set OFF to the offset from virtual_incoming_args_rtx of 4079 the first float register. The FP save area lies below 4080 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */ 4081 off = -gp_saved * UNITS_PER_WORD; 4082 off &= ~(UNITS_PER_FPVALUE - 1); 4083 off -= fp_saved * UNITS_PER_FPREG; 4084 4085 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode; 4086 4087 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC) 4088 { 4089 rtx ptr, mem; 4090 4091 ptr = plus_constant (virtual_incoming_args_rtx, off); 4092 mem = gen_rtx_MEM (mode, ptr); 4093 set_mem_alias_set (mem, get_varargs_alias_set ()); 4094 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i)); 4095 off += UNITS_PER_HWFPVALUE; 4096 } 4097 } 4098 } 4099 if (REG_PARM_STACK_SPACE (cfun->decl) == 0) 4100 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD 4101 + fp_saved * UNITS_PER_FPREG); 4102} 4103 4104/* Create the va_list data type. 4105 We keep 3 pointers, and two offsets. 4106 Two pointers are to the overflow area, which starts at the CFA. 4107 One of these is constant, for addressing into the GPR save area below it. 4108 The other is advanced up the stack through the overflow region. 4109 The third pointer is to the GPR save area. Since the FPR save area 4110 is just below it, we can address FPR slots off this pointer. 4111 We also keep two one-byte offsets, which are to be subtracted from the 4112 constant pointers to yield addresses in the GPR and FPR save areas. 4113 These are downcounted as float or non-float arguments are used, 4114 and when they get to zero, the argument must be obtained from the 4115 overflow region. 4116 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single 4117 pointer is enough. It's started at the GPR save area, and is 4118 advanced, period. 4119 Note that the GPR save area is not constant size, due to optimization 4120 in the prologue. Hence, we can't use a design with two pointers 4121 and two offsets, although we could have designed this with two pointers 4122 and three offsets. */ 4123 4124static tree 4125mips_build_builtin_va_list (void) 4126{ 4127 if (EABI_FLOAT_VARARGS_P) 4128 { 4129 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record; 4130 tree array, index; 4131 4132 record = (*lang_hooks.types.make_type) (RECORD_TYPE); 4133 4134 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"), 4135 ptr_type_node); 4136 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"), 4137 ptr_type_node); 4138 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"), 4139 ptr_type_node); 4140 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"), 4141 unsigned_char_type_node); 4142 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"), 4143 unsigned_char_type_node); 4144 /* Explicitly pad to the size of a pointer, so that -Wpadded won't 4145 warn on every user file. */ 4146 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1); 4147 array = build_array_type (unsigned_char_type_node, 4148 build_index_type (index)); 4149 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array); 4150 4151 DECL_FIELD_CONTEXT (f_ovfl) = record; 4152 DECL_FIELD_CONTEXT (f_gtop) = record; 4153 DECL_FIELD_CONTEXT (f_ftop) = record; 4154 DECL_FIELD_CONTEXT (f_goff) = record; 4155 DECL_FIELD_CONTEXT (f_foff) = record; 4156 DECL_FIELD_CONTEXT (f_res) = record; 4157 4158 TYPE_FIELDS (record) = f_ovfl; 4159 TREE_CHAIN (f_ovfl) = f_gtop; 4160 TREE_CHAIN (f_gtop) = f_ftop; 4161 TREE_CHAIN (f_ftop) = f_goff; 4162 TREE_CHAIN (f_goff) = f_foff; 4163 TREE_CHAIN (f_foff) = f_res; 4164 4165 layout_type (record); 4166 return record; 4167 } 4168 else if (TARGET_IRIX && TARGET_IRIX6) 4169 /* On IRIX 6, this type is 'char *'. */ 4170 return build_pointer_type (char_type_node); 4171 else 4172 /* Otherwise, we use 'void *'. */ 4173 return ptr_type_node; 4174} 4175 4176/* Implement va_start. */ 4177 4178void 4179mips_va_start (tree valist, rtx nextarg) 4180{ 4181 if (EABI_FLOAT_VARARGS_P) 4182 { 4183 const CUMULATIVE_ARGS *cum; 4184 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff; 4185 tree ovfl, gtop, ftop, goff, foff; 4186 tree t; 4187 int gpr_save_area_size; 4188 int fpr_save_area_size; 4189 int fpr_offset; 4190 4191 cum = ¤t_function_args_info; 4192 gpr_save_area_size 4193 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD; 4194 fpr_save_area_size 4195 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG; 4196 4197 f_ovfl = TYPE_FIELDS (va_list_type_node); 4198 f_gtop = TREE_CHAIN (f_ovfl); 4199 f_ftop = TREE_CHAIN (f_gtop); 4200 f_goff = TREE_CHAIN (f_ftop); 4201 f_foff = TREE_CHAIN (f_goff); 4202 4203 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl, 4204 NULL_TREE); 4205 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop, 4206 NULL_TREE); 4207 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop, 4208 NULL_TREE); 4209 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff, 4210 NULL_TREE); 4211 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff, 4212 NULL_TREE); 4213 4214 /* Emit code to initialize OVFL, which points to the next varargs 4215 stack argument. CUM->STACK_WORDS gives the number of stack 4216 words used by named arguments. */ 4217 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx); 4218 if (cum->stack_words > 0) 4219 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), t, 4220 build_int_cst (NULL_TREE, 4221 cum->stack_words * UNITS_PER_WORD)); 4222 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t); 4223 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 4224 4225 /* Emit code to initialize GTOP, the top of the GPR save area. */ 4226 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx); 4227 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t); 4228 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 4229 4230 /* Emit code to initialize FTOP, the top of the FPR save area. 4231 This address is gpr_save_area_bytes below GTOP, rounded 4232 down to the next fp-aligned boundary. */ 4233 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx); 4234 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1; 4235 fpr_offset &= ~(UNITS_PER_FPVALUE - 1); 4236 if (fpr_offset) 4237 t = build2 (PLUS_EXPR, TREE_TYPE (ftop), t, 4238 build_int_cst (NULL_TREE, -fpr_offset)); 4239 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t); 4240 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 4241 4242 /* Emit code to initialize GOFF, the offset from GTOP of the 4243 next GPR argument. */ 4244 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff, 4245 build_int_cst (NULL_TREE, gpr_save_area_size)); 4246 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 4247 4248 /* Likewise emit code to initialize FOFF, the offset from FTOP 4249 of the next FPR argument. */ 4250 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff, 4251 build_int_cst (NULL_TREE, fpr_save_area_size)); 4252 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 4253 } 4254 else 4255 { 4256 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size); 4257 std_expand_builtin_va_start (valist, nextarg); 4258 } 4259} 4260 4261/* Implement va_arg. */ 4262 4263static tree 4264mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p) 4265{ 4266 HOST_WIDE_INT size, rsize; 4267 tree addr; 4268 bool indirect; 4269 4270 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0); 4271 4272 if (indirect) 4273 type = build_pointer_type (type); 4274 4275 size = int_size_in_bytes (type); 4276 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; 4277 4278 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P) 4279 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p); 4280 else 4281 { 4282 /* Not a simple merged stack. */ 4283 4284 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff; 4285 tree ovfl, top, off, align; 4286 HOST_WIDE_INT osize; 4287 tree t, u; 4288 4289 f_ovfl = TYPE_FIELDS (va_list_type_node); 4290 f_gtop = TREE_CHAIN (f_ovfl); 4291 f_ftop = TREE_CHAIN (f_gtop); 4292 f_goff = TREE_CHAIN (f_ftop); 4293 f_foff = TREE_CHAIN (f_goff); 4294 4295 /* We maintain separate pointers and offsets for floating-point 4296 and integer arguments, but we need similar code in both cases. 4297 Let: 4298 4299 TOP be the top of the register save area; 4300 OFF be the offset from TOP of the next register; 4301 ADDR_RTX be the address of the argument; 4302 RSIZE be the number of bytes used to store the argument 4303 when it's in the register save area; 4304 OSIZE be the number of bytes used to store it when it's 4305 in the stack overflow area; and 4306 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0) 4307 4308 The code we want is: 4309 4310 1: off &= -rsize; // round down 4311 2: if (off != 0) 4312 3: { 4313 4: addr_rtx = top - off; 4314 5: off -= rsize; 4315 6: } 4316 7: else 4317 8: { 4318 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize; 4319 10: addr_rtx = ovfl + PADDING; 4320 11: ovfl += osize; 4321 14: } 4322 4323 [1] and [9] can sometimes be optimized away. */ 4324 4325 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl, 4326 NULL_TREE); 4327 4328 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT 4329 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE) 4330 { 4331 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop, 4332 NULL_TREE); 4333 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff, 4334 NULL_TREE); 4335 4336 /* When floating-point registers are saved to the stack, 4337 each one will take up UNITS_PER_HWFPVALUE bytes, regardless 4338 of the float's precision. */ 4339 rsize = UNITS_PER_HWFPVALUE; 4340 4341 /* Overflow arguments are padded to UNITS_PER_WORD bytes 4342 (= PARM_BOUNDARY bits). This can be different from RSIZE 4343 in two cases: 4344 4345 (1) On 32-bit targets when TYPE is a structure such as: 4346 4347 struct s { float f; }; 4348 4349 Such structures are passed in paired FPRs, so RSIZE 4350 will be 8 bytes. However, the structure only takes 4351 up 4 bytes of memory, so OSIZE will only be 4. 4352 4353 (2) In combinations such as -mgp64 -msingle-float 4354 -fshort-double. Doubles passed in registers 4355 will then take up 4 (UNITS_PER_HWFPVALUE) bytes, 4356 but those passed on the stack take up 4357 UNITS_PER_WORD bytes. */ 4358 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD); 4359 } 4360 else 4361 { 4362 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop, 4363 NULL_TREE); 4364 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff, 4365 NULL_TREE); 4366 if (rsize > UNITS_PER_WORD) 4367 { 4368 /* [1] Emit code for: off &= -rsize. */ 4369 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off, 4370 build_int_cst (NULL_TREE, -rsize)); 4371 t = build2 (MODIFY_EXPR, TREE_TYPE (off), off, t); 4372 gimplify_and_add (t, pre_p); 4373 } 4374 osize = rsize; 4375 } 4376 4377 /* [2] Emit code to branch if off == 0. */ 4378 t = build2 (NE_EXPR, boolean_type_node, off, 4379 build_int_cst (TREE_TYPE (off), 0)); 4380 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE); 4381 4382 /* [5] Emit code for: off -= rsize. We do this as a form of 4383 post-increment not available to C. Also widen for the 4384 coming pointer arithmetic. */ 4385 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize)); 4386 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t); 4387 t = fold_convert (sizetype, t); 4388 t = fold_convert (TREE_TYPE (top), t); 4389 4390 /* [4] Emit code for: addr_rtx = top - off. On big endian machines, 4391 the argument has RSIZE - SIZE bytes of leading padding. */ 4392 t = build2 (MINUS_EXPR, TREE_TYPE (top), top, t); 4393 if (BYTES_BIG_ENDIAN && rsize > size) 4394 { 4395 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE, 4396 rsize - size)); 4397 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u); 4398 } 4399 COND_EXPR_THEN (addr) = t; 4400 4401 if (osize > UNITS_PER_WORD) 4402 { 4403 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */ 4404 u = fold_convert (TREE_TYPE (ovfl), 4405 build_int_cst (NULL_TREE, osize - 1)); 4406 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u); 4407 u = fold_convert (TREE_TYPE (ovfl), 4408 build_int_cst (NULL_TREE, -osize)); 4409 t = build2 (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u); 4410 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t); 4411 } 4412 else 4413 align = NULL; 4414 4415 /* [10, 11]. Emit code to store ovfl in addr_rtx, then 4416 post-increment ovfl by osize. On big-endian machines, 4417 the argument has OSIZE - SIZE bytes of leading padding. */ 4418 u = fold_convert (TREE_TYPE (ovfl), 4419 build_int_cst (NULL_TREE, osize)); 4420 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u); 4421 if (BYTES_BIG_ENDIAN && osize > size) 4422 { 4423 u = fold_convert (TREE_TYPE (t), 4424 build_int_cst (NULL_TREE, osize - size)); 4425 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u); 4426 } 4427 4428 /* String [9] and [10,11] together. */ 4429 if (align) 4430 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t); 4431 COND_EXPR_ELSE (addr) = t; 4432 4433 addr = fold_convert (build_pointer_type (type), addr); 4434 addr = build_va_arg_indirect_ref (addr); 4435 } 4436 4437 if (indirect) 4438 addr = build_va_arg_indirect_ref (addr); 4439 4440 return addr; 4441} 4442 4443/* Return true if it is possible to use left/right accesses for a 4444 bitfield of WIDTH bits starting BITPOS bits into *OP. When 4445 returning true, update *OP, *LEFT and *RIGHT as follows: 4446 4447 *OP is a BLKmode reference to the whole field. 4448 4449 *LEFT is a QImode reference to the first byte if big endian or 4450 the last byte if little endian. This address can be used in the 4451 left-side instructions (lwl, swl, ldl, sdl). 4452 4453 *RIGHT is a QImode reference to the opposite end of the field and 4454 can be used in the patterning right-side instruction. */ 4455 4456static bool 4457mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos, 4458 rtx *left, rtx *right) 4459{ 4460 rtx first, last; 4461 4462 /* Check that the operand really is a MEM. Not all the extv and 4463 extzv predicates are checked. */ 4464 if (!MEM_P (*op)) 4465 return false; 4466 4467 /* Check that the size is valid. */ 4468 if (width != 32 && (!TARGET_64BIT || width != 64)) 4469 return false; 4470 4471 /* We can only access byte-aligned values. Since we are always passed 4472 a reference to the first byte of the field, it is not necessary to 4473 do anything with BITPOS after this check. */ 4474 if (bitpos % BITS_PER_UNIT != 0) 4475 return false; 4476 4477 /* Reject aligned bitfields: we want to use a normal load or store 4478 instead of a left/right pair. */ 4479 if (MEM_ALIGN (*op) >= width) 4480 return false; 4481 4482 /* Adjust *OP to refer to the whole field. This also has the effect 4483 of legitimizing *OP's address for BLKmode, possibly simplifying it. */ 4484 *op = adjust_address (*op, BLKmode, 0); 4485 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT)); 4486 4487 /* Get references to both ends of the field. We deliberately don't 4488 use the original QImode *OP for FIRST since the new BLKmode one 4489 might have a simpler address. */ 4490 first = adjust_address (*op, QImode, 0); 4491 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1); 4492 4493 /* Allocate to LEFT and RIGHT according to endianness. LEFT should 4494 be the upper word and RIGHT the lower word. */ 4495 if (TARGET_BIG_ENDIAN) 4496 *left = first, *right = last; 4497 else 4498 *left = last, *right = first; 4499 4500 return true; 4501} 4502 4503 4504/* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)). 4505 Return true on success. We only handle cases where zero_extract is 4506 equivalent to sign_extract. */ 4507 4508bool 4509mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos) 4510{ 4511 rtx left, right, temp; 4512 4513 /* If TARGET_64BIT, the destination of a 32-bit load will be a 4514 paradoxical word_mode subreg. This is the only case in which 4515 we allow the destination to be larger than the source. */ 4516 if (GET_CODE (dest) == SUBREG 4517 && GET_MODE (dest) == DImode 4518 && SUBREG_BYTE (dest) == 0 4519 && GET_MODE (SUBREG_REG (dest)) == SImode) 4520 dest = SUBREG_REG (dest); 4521 4522 /* After the above adjustment, the destination must be the same 4523 width as the source. */ 4524 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width) 4525 return false; 4526 4527 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right)) 4528 return false; 4529 4530 temp = gen_reg_rtx (GET_MODE (dest)); 4531 if (GET_MODE (dest) == DImode) 4532 { 4533 emit_insn (gen_mov_ldl (temp, src, left)); 4534 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp)); 4535 } 4536 else 4537 { 4538 emit_insn (gen_mov_lwl (temp, src, left)); 4539 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp)); 4540 } 4541 return true; 4542} 4543 4544 4545/* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return 4546 true on success. */ 4547 4548bool 4549mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos) 4550{ 4551 rtx left, right; 4552 enum machine_mode mode; 4553 4554 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right)) 4555 return false; 4556 4557 mode = mode_for_size (width, MODE_INT, 0); 4558 src = gen_lowpart (mode, src); 4559 4560 if (mode == DImode) 4561 { 4562 emit_insn (gen_mov_sdl (dest, src, left)); 4563 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right)); 4564 } 4565 else 4566 { 4567 emit_insn (gen_mov_swl (dest, src, left)); 4568 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right)); 4569 } 4570 return true; 4571} 4572 4573/* Return true if X is a MEM with the same size as MODE. */ 4574 4575bool 4576mips_mem_fits_mode_p (enum machine_mode mode, rtx x) 4577{ 4578 rtx size; 4579 4580 if (!MEM_P (x)) 4581 return false; 4582 4583 size = MEM_SIZE (x); 4584 return size && INTVAL (size) == GET_MODE_SIZE (mode); 4585} 4586 4587/* Return true if (zero_extract OP SIZE POSITION) can be used as the 4588 source of an "ext" instruction or the destination of an "ins" 4589 instruction. OP must be a register operand and the following 4590 conditions must hold: 4591 4592 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op)) 4593 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op)) 4594 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op)) 4595 4596 Also reject lengths equal to a word as they are better handled 4597 by the move patterns. */ 4598 4599bool 4600mips_use_ins_ext_p (rtx op, rtx size, rtx position) 4601{ 4602 HOST_WIDE_INT len, pos; 4603 4604 if (!ISA_HAS_EXT_INS 4605 || !register_operand (op, VOIDmode) 4606 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD) 4607 return false; 4608 4609 len = INTVAL (size); 4610 pos = INTVAL (position); 4611 4612 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op)) 4613 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op))) 4614 return false; 4615 4616 return true; 4617} 4618 4619/* Set up globals to generate code for the ISA or processor 4620 described by INFO. */ 4621 4622static void 4623mips_set_architecture (const struct mips_cpu_info *info) 4624{ 4625 if (info != 0) 4626 { 4627 mips_arch_info = info; 4628 mips_arch = info->cpu; 4629 mips_isa = info->isa; 4630 } 4631} 4632 4633 4634/* Likewise for tuning. */ 4635 4636static void 4637mips_set_tune (const struct mips_cpu_info *info) 4638{ 4639 if (info != 0) 4640 { 4641 mips_tune_info = info; 4642 mips_tune = info->cpu; 4643 } 4644} 4645 4646/* Implement TARGET_HANDLE_OPTION. */ 4647 4648static bool 4649mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) 4650{ 4651 switch (code) 4652 { 4653 case OPT_mabi_: 4654 if (strcmp (arg, "32") == 0) 4655 mips_abi = ABI_32; 4656 else if (strcmp (arg, "o64") == 0) 4657 mips_abi = ABI_O64; 4658 else if (strcmp (arg, "n32") == 0) 4659 mips_abi = ABI_N32; 4660 else if (strcmp (arg, "64") == 0) 4661 mips_abi = ABI_64; 4662 else if (strcmp (arg, "eabi") == 0) 4663 mips_abi = ABI_EABI; 4664 else 4665 return false; 4666 return true; 4667 4668 case OPT_march_: 4669 case OPT_mtune_: 4670 return mips_parse_cpu (arg) != 0; 4671 4672 case OPT_mips: 4673 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL))); 4674 return mips_isa_info != 0; 4675 4676 case OPT_mno_flush_func: 4677 mips_cache_flush_func = NULL; 4678 return true; 4679 4680 default: 4681 return true; 4682 } 4683} 4684 4685/* Set up the threshold for data to go into the small data area, instead 4686 of the normal data area, and detect any conflicts in the switches. */ 4687 4688void 4689override_options (void) 4690{ 4691 int i, start, regno; 4692 enum machine_mode mode; 4693 4694 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE; 4695 4696 /* The following code determines the architecture and register size. 4697 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()). 4698 The GAS and GCC code should be kept in sync as much as possible. */ 4699 4700 if (mips_arch_string != 0) 4701 mips_set_architecture (mips_parse_cpu (mips_arch_string)); 4702 4703 if (mips_isa_info != 0) 4704 { 4705 if (mips_arch_info == 0) 4706 mips_set_architecture (mips_isa_info); 4707 else if (mips_arch_info->isa != mips_isa_info->isa) 4708 error ("-%s conflicts with the other architecture options, " 4709 "which specify a %s processor", 4710 mips_isa_info->name, 4711 mips_cpu_info_from_isa (mips_arch_info->isa)->name); 4712 } 4713 4714 if (mips_arch_info == 0) 4715 { 4716#ifdef MIPS_CPU_STRING_DEFAULT 4717 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT)); 4718#else 4719 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT)); 4720#endif 4721 } 4722 4723 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS) 4724 error ("-march=%s is not compatible with the selected ABI", 4725 mips_arch_info->name); 4726 4727 /* Optimize for mips_arch, unless -mtune selects a different processor. */ 4728 if (mips_tune_string != 0) 4729 mips_set_tune (mips_parse_cpu (mips_tune_string)); 4730 4731 if (mips_tune_info == 0) 4732 mips_set_tune (mips_arch_info); 4733 4734 /* Set cost structure for the processor. */ 4735 mips_cost = &mips_rtx_cost_data[mips_tune]; 4736 4737 if ((target_flags_explicit & MASK_64BIT) != 0) 4738 { 4739 /* The user specified the size of the integer registers. Make sure 4740 it agrees with the ABI and ISA. */ 4741 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS) 4742 error ("-mgp64 used with a 32-bit processor"); 4743 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS) 4744 error ("-mgp32 used with a 64-bit ABI"); 4745 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS) 4746 error ("-mgp64 used with a 32-bit ABI"); 4747 } 4748 else 4749 { 4750 /* Infer the integer register size from the ABI and processor. 4751 Restrict ourselves to 32-bit registers if that's all the 4752 processor has, or if the ABI cannot handle 64-bit registers. */ 4753 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS) 4754 target_flags &= ~MASK_64BIT; 4755 else 4756 target_flags |= MASK_64BIT; 4757 } 4758 4759 if ((target_flags_explicit & MASK_FLOAT64) != 0) 4760 { 4761 /* Really, -mfp32 and -mfp64 are ornamental options. There's 4762 only one right answer here. */ 4763 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64) 4764 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float"); 4765 else if (!TARGET_64BIT && TARGET_FLOAT64) 4766 error ("unsupported combination: %s", "-mgp32 -mfp64"); 4767 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64) 4768 error ("unsupported combination: %s", "-mfp64 -msingle-float"); 4769 } 4770 else 4771 { 4772 /* -msingle-float selects 32-bit float registers. Otherwise the 4773 float registers should be the same size as the integer ones. */ 4774 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT) 4775 target_flags |= MASK_FLOAT64; 4776 else 4777 target_flags &= ~MASK_FLOAT64; 4778 } 4779 4780 /* End of code shared with GAS. */ 4781 4782 if ((target_flags_explicit & MASK_LONG64) == 0) 4783 { 4784 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64) 4785 target_flags |= MASK_LONG64; 4786 else 4787 target_flags &= ~MASK_LONG64; 4788 } 4789 4790 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT 4791 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0) 4792 { 4793 /* For some configurations, it is useful to have -march control 4794 the default setting of MASK_SOFT_FLOAT. */ 4795 switch ((int) mips_arch) 4796 { 4797 case PROCESSOR_R4100: 4798 case PROCESSOR_R4111: 4799 case PROCESSOR_R4120: 4800 case PROCESSOR_R4130: 4801 target_flags |= MASK_SOFT_FLOAT; 4802 break; 4803 4804 default: 4805 target_flags &= ~MASK_SOFT_FLOAT; 4806 break; 4807 } 4808 } 4809 4810 if (!TARGET_OLDABI) 4811 flag_pcc_struct_return = 0; 4812 4813 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0) 4814 { 4815 /* If neither -mbranch-likely nor -mno-branch-likely was given 4816 on the command line, set MASK_BRANCHLIKELY based on the target 4817 architecture. 4818 4819 By default, we enable use of Branch Likely instructions on 4820 all architectures which support them with the following 4821 exceptions: when creating MIPS32 or MIPS64 code, and when 4822 tuning for architectures where their use tends to hurt 4823 performance. 4824 4825 The MIPS32 and MIPS64 architecture specifications say "Software 4826 is strongly encouraged to avoid use of Branch Likely 4827 instructions, as they will be removed from a future revision 4828 of the [MIPS32 and MIPS64] architecture." Therefore, we do not 4829 issue those instructions unless instructed to do so by 4830 -mbranch-likely. */ 4831 if (ISA_HAS_BRANCHLIKELY 4832 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64) 4833 && !(TUNE_MIPS5500 || TUNE_SB1)) 4834 target_flags |= MASK_BRANCHLIKELY; 4835 else 4836 target_flags &= ~MASK_BRANCHLIKELY; 4837 } 4838 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY) 4839 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture"); 4840 4841 /* The effect of -mabicalls isn't defined for the EABI. */ 4842 if (mips_abi == ABI_EABI && TARGET_ABICALLS) 4843 { 4844 error ("unsupported combination: %s", "-mabicalls -mabi=eabi"); 4845 target_flags &= ~MASK_ABICALLS; 4846 } 4847 4848 if (TARGET_ABICALLS) 4849 { 4850 /* We need to set flag_pic for executables as well as DSOs 4851 because we may reference symbols that are not defined in 4852 the final executable. (MIPS does not use things like 4853 copy relocs, for example.) 4854 4855 Also, there is a body of code that uses __PIC__ to distinguish 4856 between -mabicalls and -mno-abicalls code. */ 4857 flag_pic = 1; 4858 if (mips_section_threshold > 0) 4859 warning (0, "%<-G%> is incompatible with %<-mabicalls%>"); 4860 } 4861 4862 /* mips_split_addresses is a half-way house between explicit 4863 relocations and the traditional assembler macros. It can 4864 split absolute 32-bit symbolic constants into a high/lo_sum 4865 pair but uses macros for other sorts of access. 4866 4867 Like explicit relocation support for REL targets, it relies 4868 on GNU extensions in the assembler and the linker. 4869 4870 Although this code should work for -O0, it has traditionally 4871 been treated as an optimization. */ 4872 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES 4873 && optimize && !flag_pic 4874 && !ABI_HAS_64BIT_SYMBOLS) 4875 mips_split_addresses = 1; 4876 else 4877 mips_split_addresses = 0; 4878 4879 /* -mvr4130-align is a "speed over size" optimization: it usually produces 4880 faster code, but at the expense of more nops. Enable it at -O3 and 4881 above. */ 4882 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0) 4883 target_flags |= MASK_VR4130_ALIGN; 4884 4885 /* When compiling for the mips16, we cannot use floating point. We 4886 record the original hard float value in mips16_hard_float. */ 4887 if (TARGET_MIPS16) 4888 { 4889 if (TARGET_SOFT_FLOAT) 4890 mips16_hard_float = 0; 4891 else 4892 mips16_hard_float = 1; 4893 target_flags |= MASK_SOFT_FLOAT; 4894 4895 /* Don't run the scheduler before reload, since it tends to 4896 increase register pressure. */ 4897 flag_schedule_insns = 0; 4898 4899 /* Don't do hot/cold partitioning. The constant layout code expects 4900 the whole function to be in a single section. */ 4901 flag_reorder_blocks_and_partition = 0; 4902 4903 /* Silently disable -mexplicit-relocs since it doesn't apply 4904 to mips16 code. Even so, it would overly pedantic to warn 4905 about "-mips16 -mexplicit-relocs", especially given that 4906 we use a %gprel() operator. */ 4907 target_flags &= ~MASK_EXPLICIT_RELOCS; 4908 } 4909 4910 /* When using explicit relocs, we call dbr_schedule from within 4911 mips_reorg. */ 4912 if (TARGET_EXPLICIT_RELOCS) 4913 { 4914 mips_flag_delayed_branch = flag_delayed_branch; 4915 flag_delayed_branch = 0; 4916 } 4917 4918#ifdef MIPS_TFMODE_FORMAT 4919 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT; 4920#endif 4921 4922 /* Make sure that the user didn't turn off paired single support when 4923 MIPS-3D support is requested. */ 4924 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT) 4925 && !TARGET_PAIRED_SINGLE_FLOAT) 4926 error ("-mips3d requires -mpaired-single"); 4927 4928 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */ 4929 if (TARGET_MIPS3D) 4930 target_flags |= MASK_PAIRED_SINGLE_FLOAT; 4931 4932 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64 4933 and TARGET_HARD_FLOAT are both true. */ 4934 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT)) 4935 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float"); 4936 4937 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is 4938 enabled. */ 4939 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64) 4940 error ("-mips3d/-mpaired-single must be used with -mips64"); 4941 4942 if (TARGET_MIPS16 && TARGET_DSP) 4943 error ("-mips16 and -mdsp cannot be used together"); 4944 4945 mips_print_operand_punct['?'] = 1; 4946 mips_print_operand_punct['#'] = 1; 4947 mips_print_operand_punct['/'] = 1; 4948 mips_print_operand_punct['&'] = 1; 4949 mips_print_operand_punct['!'] = 1; 4950 mips_print_operand_punct['*'] = 1; 4951 mips_print_operand_punct['@'] = 1; 4952 mips_print_operand_punct['.'] = 1; 4953 mips_print_operand_punct['('] = 1; 4954 mips_print_operand_punct[')'] = 1; 4955 mips_print_operand_punct['['] = 1; 4956 mips_print_operand_punct[']'] = 1; 4957 mips_print_operand_punct['<'] = 1; 4958 mips_print_operand_punct['>'] = 1; 4959 mips_print_operand_punct['{'] = 1; 4960 mips_print_operand_punct['}'] = 1; 4961 mips_print_operand_punct['^'] = 1; 4962 mips_print_operand_punct['$'] = 1; 4963 mips_print_operand_punct['+'] = 1; 4964 mips_print_operand_punct['~'] = 1; 4965 4966 /* Set up array to map GCC register number to debug register number. 4967 Ignore the special purpose register numbers. */ 4968 4969 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 4970 mips_dbx_regno[i] = -1; 4971 4972 start = GP_DBX_FIRST - GP_REG_FIRST; 4973 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++) 4974 mips_dbx_regno[i] = i + start; 4975 4976 start = FP_DBX_FIRST - FP_REG_FIRST; 4977 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) 4978 mips_dbx_regno[i] = i + start; 4979 4980 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0; 4981 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1; 4982 4983 /* Set up array giving whether a given register can hold a given mode. */ 4984 4985 for (mode = VOIDmode; 4986 mode != MAX_MACHINE_MODE; 4987 mode = (enum machine_mode) ((int)mode + 1)) 4988 { 4989 register int size = GET_MODE_SIZE (mode); 4990 register enum mode_class class = GET_MODE_CLASS (mode); 4991 4992 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 4993 { 4994 register int temp; 4995 4996 if (mode == CCV2mode) 4997 temp = (ISA_HAS_8CC 4998 && ST_REG_P (regno) 4999 && (regno - ST_REG_FIRST) % 2 == 0); 5000 5001 else if (mode == CCV4mode) 5002 temp = (ISA_HAS_8CC 5003 && ST_REG_P (regno) 5004 && (regno - ST_REG_FIRST) % 4 == 0); 5005 5006 else if (mode == CCmode) 5007 { 5008 if (! ISA_HAS_8CC) 5009 temp = (regno == FPSW_REGNUM); 5010 else 5011 temp = (ST_REG_P (regno) || GP_REG_P (regno) 5012 || FP_REG_P (regno)); 5013 } 5014 5015 else if (GP_REG_P (regno)) 5016 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD); 5017 5018 else if (FP_REG_P (regno)) 5019 temp = ((regno % FP_INC) == 0) 5020 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT 5021 || class == MODE_VECTOR_FLOAT) 5022 && size <= UNITS_PER_FPVALUE) 5023 /* Allow integer modes that fit into a single 5024 register. We need to put integers into FPRs 5025 when using instructions like cvt and trunc. 5026 We can't allow sizes smaller than a word, 5027 the FPU has no appropriate load/store 5028 instructions for those. */ 5029 || (class == MODE_INT 5030 && size >= MIN_UNITS_PER_WORD 5031 && size <= UNITS_PER_FPREG) 5032 /* Allow TFmode for CCmode reloads. */ 5033 || (ISA_HAS_8CC && mode == TFmode)); 5034 5035 else if (ACC_REG_P (regno)) 5036 temp = (INTEGRAL_MODE_P (mode) 5037 && (size <= UNITS_PER_WORD 5038 || (ACC_HI_REG_P (regno) 5039 && size == 2 * UNITS_PER_WORD))); 5040 5041 else if (ALL_COP_REG_P (regno)) 5042 temp = (class == MODE_INT && size <= UNITS_PER_WORD); 5043 else 5044 temp = 0; 5045 5046 mips_hard_regno_mode_ok[(int)mode][regno] = temp; 5047 } 5048 } 5049 5050 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been 5051 initialized yet, so we can't use that here. */ 5052 gpr_mode = TARGET_64BIT ? DImode : SImode; 5053 5054 /* Provide default values for align_* for 64-bit targets. */ 5055 if (TARGET_64BIT && !TARGET_MIPS16) 5056 { 5057 if (align_loops == 0) 5058 align_loops = 8; 5059 if (align_jumps == 0) 5060 align_jumps = 8; 5061 if (align_functions == 0) 5062 align_functions = 8; 5063 } 5064 5065 /* Function to allocate machine-dependent function status. */ 5066 init_machine_status = &mips_init_machine_status; 5067 5068 if (ABI_HAS_64BIT_SYMBOLS) 5069 { 5070 if (TARGET_EXPLICIT_RELOCS) 5071 { 5072 mips_split_p[SYMBOL_64_HIGH] = true; 5073 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest("; 5074 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher("; 5075 5076 mips_split_p[SYMBOL_64_MID] = true; 5077 mips_hi_relocs[SYMBOL_64_MID] = "%higher("; 5078 mips_lo_relocs[SYMBOL_64_MID] = "%hi("; 5079 5080 mips_split_p[SYMBOL_64_LOW] = true; 5081 mips_hi_relocs[SYMBOL_64_LOW] = "%hi("; 5082 mips_lo_relocs[SYMBOL_64_LOW] = "%lo("; 5083 5084 mips_split_p[SYMBOL_GENERAL] = true; 5085 mips_lo_relocs[SYMBOL_GENERAL] = "%lo("; 5086 } 5087 } 5088 else 5089 { 5090 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses) 5091 { 5092 mips_split_p[SYMBOL_GENERAL] = true; 5093 mips_hi_relocs[SYMBOL_GENERAL] = "%hi("; 5094 mips_lo_relocs[SYMBOL_GENERAL] = "%lo("; 5095 } 5096 } 5097 5098 if (TARGET_MIPS16) 5099 { 5100 /* The high part is provided by a pseudo copy of $gp. */ 5101 mips_split_p[SYMBOL_SMALL_DATA] = true; 5102 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel("; 5103 } 5104 5105 if (TARGET_EXPLICIT_RELOCS) 5106 { 5107 /* Small data constants are kept whole until after reload, 5108 then lowered by mips_rewrite_small_data. */ 5109 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel("; 5110 5111 mips_split_p[SYMBOL_GOT_LOCAL] = true; 5112 if (TARGET_NEWABI) 5113 { 5114 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page("; 5115 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst("; 5116 } 5117 else 5118 { 5119 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got("; 5120 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo("; 5121 } 5122 5123 if (TARGET_XGOT) 5124 { 5125 /* The HIGH and LO_SUM are matched by special .md patterns. */ 5126 mips_split_p[SYMBOL_GOT_GLOBAL] = true; 5127 5128 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true; 5129 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi("; 5130 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo("; 5131 5132 mips_split_p[SYMBOL_GOTOFF_CALL] = true; 5133 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi("; 5134 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo("; 5135 } 5136 else 5137 { 5138 if (TARGET_NEWABI) 5139 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp("; 5140 else 5141 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got("; 5142 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16("; 5143 } 5144 } 5145 5146 if (TARGET_NEWABI) 5147 { 5148 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true; 5149 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel("; 5150 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel("; 5151 } 5152 5153 /* Thread-local relocation operators. */ 5154 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd("; 5155 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm("; 5156 mips_split_p[SYMBOL_DTPREL] = 1; 5157 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi("; 5158 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo("; 5159 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel("; 5160 mips_split_p[SYMBOL_TPREL] = 1; 5161 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi("; 5162 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo("; 5163 5164 /* We don't have a thread pointer access instruction on MIPS16, or 5165 appropriate TLS relocations. */ 5166 if (TARGET_MIPS16) 5167 targetm.have_tls = false; 5168 5169 /* Default to working around R4000 errata only if the processor 5170 was selected explicitly. */ 5171 if ((target_flags_explicit & MASK_FIX_R4000) == 0 5172 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000")) 5173 target_flags |= MASK_FIX_R4000; 5174 5175 /* Default to working around R4400 errata only if the processor 5176 was selected explicitly. */ 5177 if ((target_flags_explicit & MASK_FIX_R4400) == 0 5178 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400")) 5179 target_flags |= MASK_FIX_R4400; 5180} 5181 5182/* Implement CONDITIONAL_REGISTER_USAGE. */ 5183 5184void 5185mips_conditional_register_usage (void) 5186{ 5187 if (!TARGET_DSP) 5188 { 5189 int regno; 5190 5191 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++) 5192 fixed_regs[regno] = call_used_regs[regno] = 1; 5193 } 5194 if (!TARGET_HARD_FLOAT) 5195 { 5196 int regno; 5197 5198 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 5199 fixed_regs[regno] = call_used_regs[regno] = 1; 5200 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) 5201 fixed_regs[regno] = call_used_regs[regno] = 1; 5202 } 5203 else if (! ISA_HAS_8CC) 5204 { 5205 int regno; 5206 5207 /* We only have a single condition code register. We 5208 implement this by hiding all the condition code registers, 5209 and generating RTL that refers directly to ST_REG_FIRST. */ 5210 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) 5211 fixed_regs[regno] = call_used_regs[regno] = 1; 5212 } 5213 /* In mips16 mode, we permit the $t temporary registers to be used 5214 for reload. We prohibit the unused $s registers, since they 5215 are caller saved, and saving them via a mips16 register would 5216 probably waste more time than just reloading the value. */ 5217 if (TARGET_MIPS16) 5218 { 5219 fixed_regs[18] = call_used_regs[18] = 1; 5220 fixed_regs[19] = call_used_regs[19] = 1; 5221 fixed_regs[20] = call_used_regs[20] = 1; 5222 fixed_regs[21] = call_used_regs[21] = 1; 5223 fixed_regs[22] = call_used_regs[22] = 1; 5224 fixed_regs[23] = call_used_regs[23] = 1; 5225 fixed_regs[26] = call_used_regs[26] = 1; 5226 fixed_regs[27] = call_used_regs[27] = 1; 5227 fixed_regs[30] = call_used_regs[30] = 1; 5228 } 5229 /* fp20-23 are now caller saved. */ 5230 if (mips_abi == ABI_64) 5231 { 5232 int regno; 5233 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++) 5234 call_really_used_regs[regno] = call_used_regs[regno] = 1; 5235 } 5236 /* Odd registers from fp21 to fp31 are now caller saved. */ 5237 if (mips_abi == ABI_N32) 5238 { 5239 int regno; 5240 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2) 5241 call_really_used_regs[regno] = call_used_regs[regno] = 1; 5242 } 5243} 5244 5245/* Allocate a chunk of memory for per-function machine-dependent data. */ 5246static struct machine_function * 5247mips_init_machine_status (void) 5248{ 5249 return ((struct machine_function *) 5250 ggc_alloc_cleared (sizeof (struct machine_function))); 5251} 5252 5253/* On the mips16, we want to allocate $24 (T_REG) before other 5254 registers for instructions for which it is possible. This helps 5255 avoid shuffling registers around in order to set up for an xor, 5256 encouraging the compiler to use a cmp instead. */ 5257 5258void 5259mips_order_regs_for_local_alloc (void) 5260{ 5261 register int i; 5262 5263 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 5264 reg_alloc_order[i] = i; 5265 5266 if (TARGET_MIPS16) 5267 { 5268 /* It really doesn't matter where we put register 0, since it is 5269 a fixed register anyhow. */ 5270 reg_alloc_order[0] = 24; 5271 reg_alloc_order[24] = 0; 5272 } 5273} 5274 5275 5276/* The MIPS debug format wants all automatic variables and arguments 5277 to be in terms of the virtual frame pointer (stack pointer before 5278 any adjustment in the function), while the MIPS 3.0 linker wants 5279 the frame pointer to be the stack pointer after the initial 5280 adjustment. So, we do the adjustment here. The arg pointer (which 5281 is eliminated) points to the virtual frame pointer, while the frame 5282 pointer (which may be eliminated) points to the stack pointer after 5283 the initial adjustments. */ 5284 5285HOST_WIDE_INT 5286mips_debugger_offset (rtx addr, HOST_WIDE_INT offset) 5287{ 5288 rtx offset2 = const0_rtx; 5289 rtx reg = eliminate_constant_term (addr, &offset2); 5290 5291 if (offset == 0) 5292 offset = INTVAL (offset2); 5293 5294 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx 5295 || reg == hard_frame_pointer_rtx) 5296 { 5297 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized) 5298 ? compute_frame_size (get_frame_size ()) 5299 : cfun->machine->frame.total_size; 5300 5301 /* MIPS16 frame is smaller */ 5302 if (frame_pointer_needed && TARGET_MIPS16) 5303 frame_size -= cfun->machine->frame.args_size; 5304 5305 offset = offset - frame_size; 5306 } 5307 5308 /* sdbout_parms does not want this to crash for unrecognized cases. */ 5309#if 0 5310 else if (reg != arg_pointer_rtx) 5311 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer", 5312 addr); 5313#endif 5314 5315 return offset; 5316} 5317 5318/* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are: 5319 5320 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x", 5321 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x", 5322 'h' OP is HIGH, prints %hi(X), 5323 'd' output integer constant in decimal, 5324 'z' if the operand is 0, use $0 instead of normal operand. 5325 'D' print second part of double-word register or memory operand. 5326 'L' print low-order register of double-word register operand. 5327 'M' print high-order register of double-word register operand. 5328 'C' print part of opcode for a branch condition. 5329 'F' print part of opcode for a floating-point branch condition. 5330 'N' print part of opcode for a branch condition, inverted. 5331 'W' print part of opcode for a floating-point branch condition, inverted. 5332 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...), 5333 'z' for (eq:?I ...), 'n' for (ne:?I ...). 5334 't' like 'T', but with the EQ/NE cases reversed 5335 'Y' for a CONST_INT X, print mips_fp_conditions[X] 5336 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing 5337 'R' print the reloc associated with LO_SUM 5338 'q' print DSP accumulator registers 5339 5340 The punctuation characters are: 5341 5342 '(' Turn on .set noreorder 5343 ')' Turn on .set reorder 5344 '[' Turn on .set noat 5345 ']' Turn on .set at 5346 '<' Turn on .set nomacro 5347 '>' Turn on .set macro 5348 '{' Turn on .set volatile (not GAS) 5349 '}' Turn on .set novolatile (not GAS) 5350 '&' Turn on .set noreorder if filling delay slots 5351 '*' Turn on both .set noreorder and .set nomacro if filling delay slots 5352 '!' Turn on .set nomacro if filling delay slots 5353 '#' Print nop if in a .set noreorder section. 5354 '/' Like '#', but does nothing within a delayed branch sequence 5355 '?' Print 'l' if we are to use a branch likely instead of normal branch. 5356 '@' Print the name of the assembler temporary register (at or $1). 5357 '.' Print the name of the register with a hard-wired zero (zero or $0). 5358 '^' Print the name of the pic call-through register (t9 or $25). 5359 '$' Print the name of the stack pointer register (sp or $29). 5360 '+' Print the name of the gp register (usually gp or $28). 5361 '~' Output a branch alignment to LABEL_ALIGN(NULL). */ 5362 5363void 5364print_operand (FILE *file, rtx op, int letter) 5365{ 5366 register enum rtx_code code; 5367 5368 if (PRINT_OPERAND_PUNCT_VALID_P (letter)) 5369 { 5370 switch (letter) 5371 { 5372 case '?': 5373 if (mips_branch_likely) 5374 putc ('l', file); 5375 break; 5376 5377 case '@': 5378 fputs (reg_names [GP_REG_FIRST + 1], file); 5379 break; 5380 5381 case '^': 5382 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file); 5383 break; 5384 5385 case '.': 5386 fputs (reg_names [GP_REG_FIRST + 0], file); 5387 break; 5388 5389 case '$': 5390 fputs (reg_names[STACK_POINTER_REGNUM], file); 5391 break; 5392 5393 case '+': 5394 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file); 5395 break; 5396 5397 case '&': 5398 if (final_sequence != 0 && set_noreorder++ == 0) 5399 fputs (".set\tnoreorder\n\t", file); 5400 break; 5401 5402 case '*': 5403 if (final_sequence != 0) 5404 { 5405 if (set_noreorder++ == 0) 5406 fputs (".set\tnoreorder\n\t", file); 5407 5408 if (set_nomacro++ == 0) 5409 fputs (".set\tnomacro\n\t", file); 5410 } 5411 break; 5412 5413 case '!': 5414 if (final_sequence != 0 && set_nomacro++ == 0) 5415 fputs ("\n\t.set\tnomacro", file); 5416 break; 5417 5418 case '#': 5419 if (set_noreorder != 0) 5420 fputs ("\n\tnop", file); 5421 break; 5422 5423 case '/': 5424 /* Print an extra newline so that the delayed insn is separated 5425 from the following ones. This looks neater and is consistent 5426 with non-nop delayed sequences. */ 5427 if (set_noreorder != 0 && final_sequence == 0) 5428 fputs ("\n\tnop\n", file); 5429 break; 5430 5431 case '(': 5432 if (set_noreorder++ == 0) 5433 fputs (".set\tnoreorder\n\t", file); 5434 break; 5435 5436 case ')': 5437 if (set_noreorder == 0) 5438 error ("internal error: %%) found without a %%( in assembler pattern"); 5439 5440 else if (--set_noreorder == 0) 5441 fputs ("\n\t.set\treorder", file); 5442 5443 break; 5444 5445 case '[': 5446 if (set_noat++ == 0) 5447 fputs (".set\tnoat\n\t", file); 5448 break; 5449 5450 case ']': 5451 if (set_noat == 0) 5452 error ("internal error: %%] found without a %%[ in assembler pattern"); 5453 else if (--set_noat == 0) 5454 fputs ("\n\t.set\tat", file); 5455 5456 break; 5457 5458 case '<': 5459 if (set_nomacro++ == 0) 5460 fputs (".set\tnomacro\n\t", file); 5461 break; 5462 5463 case '>': 5464 if (set_nomacro == 0) 5465 error ("internal error: %%> found without a %%< in assembler pattern"); 5466 else if (--set_nomacro == 0) 5467 fputs ("\n\t.set\tmacro", file); 5468 5469 break; 5470 5471 case '{': 5472 if (set_volatile++ == 0) 5473 fputs ("#.set\tvolatile\n\t", file); 5474 break; 5475 5476 case '}': 5477 if (set_volatile == 0) 5478 error ("internal error: %%} found without a %%{ in assembler pattern"); 5479 else if (--set_volatile == 0) 5480 fputs ("\n\t#.set\tnovolatile", file); 5481 5482 break; 5483 5484 case '~': 5485 { 5486 if (align_labels_log > 0) 5487 ASM_OUTPUT_ALIGN (file, align_labels_log); 5488 } 5489 break; 5490 5491 default: 5492 error ("PRINT_OPERAND: unknown punctuation '%c'", letter); 5493 break; 5494 } 5495 5496 return; 5497 } 5498 5499 if (! op) 5500 { 5501 error ("PRINT_OPERAND null pointer"); 5502 return; 5503 } 5504 5505 code = GET_CODE (op); 5506 5507 if (letter == 'C') 5508 switch (code) 5509 { 5510 case EQ: fputs ("eq", file); break; 5511 case NE: fputs ("ne", file); break; 5512 case GT: fputs ("gt", file); break; 5513 case GE: fputs ("ge", file); break; 5514 case LT: fputs ("lt", file); break; 5515 case LE: fputs ("le", file); break; 5516 case GTU: fputs ("gtu", file); break; 5517 case GEU: fputs ("geu", file); break; 5518 case LTU: fputs ("ltu", file); break; 5519 case LEU: fputs ("leu", file); break; 5520 default: 5521 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op); 5522 } 5523 5524 else if (letter == 'N') 5525 switch (code) 5526 { 5527 case EQ: fputs ("ne", file); break; 5528 case NE: fputs ("eq", file); break; 5529 case GT: fputs ("le", file); break; 5530 case GE: fputs ("lt", file); break; 5531 case LT: fputs ("ge", file); break; 5532 case LE: fputs ("gt", file); break; 5533 case GTU: fputs ("leu", file); break; 5534 case GEU: fputs ("ltu", file); break; 5535 case LTU: fputs ("geu", file); break; 5536 case LEU: fputs ("gtu", file); break; 5537 default: 5538 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op); 5539 } 5540 5541 else if (letter == 'F') 5542 switch (code) 5543 { 5544 case EQ: fputs ("c1f", file); break; 5545 case NE: fputs ("c1t", file); break; 5546 default: 5547 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op); 5548 } 5549 5550 else if (letter == 'W') 5551 switch (code) 5552 { 5553 case EQ: fputs ("c1t", file); break; 5554 case NE: fputs ("c1f", file); break; 5555 default: 5556 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op); 5557 } 5558 5559 else if (letter == 'h') 5560 { 5561 if (GET_CODE (op) == HIGH) 5562 op = XEXP (op, 0); 5563 5564 print_operand_reloc (file, op, mips_hi_relocs); 5565 } 5566 5567 else if (letter == 'R') 5568 print_operand_reloc (file, op, mips_lo_relocs); 5569 5570 else if (letter == 'Y') 5571 { 5572 if (GET_CODE (op) == CONST_INT 5573 && ((unsigned HOST_WIDE_INT) INTVAL (op) 5574 < ARRAY_SIZE (mips_fp_conditions))) 5575 fputs (mips_fp_conditions[INTVAL (op)], file); 5576 else 5577 output_operand_lossage ("invalid %%Y value"); 5578 } 5579 5580 else if (letter == 'Z') 5581 { 5582 if (ISA_HAS_8CC) 5583 { 5584 print_operand (file, op, 0); 5585 fputc (',', file); 5586 } 5587 } 5588 5589 else if (letter == 'q') 5590 { 5591 int regnum; 5592 5593 if (code != REG) 5594 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op); 5595 5596 regnum = REGNO (op); 5597 if (MD_REG_P (regnum)) 5598 fprintf (file, "$ac0"); 5599 else if (DSP_ACC_REG_P (regnum)) 5600 fprintf (file, "$ac%c", reg_names[regnum][3]); 5601 else 5602 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op); 5603 } 5604 5605 else if (code == REG || code == SUBREG) 5606 { 5607 register int regnum; 5608 5609 if (code == REG) 5610 regnum = REGNO (op); 5611 else 5612 regnum = true_regnum (op); 5613 5614 if ((letter == 'M' && ! WORDS_BIG_ENDIAN) 5615 || (letter == 'L' && WORDS_BIG_ENDIAN) 5616 || letter == 'D') 5617 regnum++; 5618 5619 fprintf (file, "%s", reg_names[regnum]); 5620 } 5621 5622 else if (code == MEM) 5623 { 5624 if (letter == 'D') 5625 output_address (plus_constant (XEXP (op, 0), 4)); 5626 else 5627 output_address (XEXP (op, 0)); 5628 } 5629 5630 else if (letter == 'x' && GET_CODE (op) == CONST_INT) 5631 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op)); 5632 5633 else if (letter == 'X' && GET_CODE(op) == CONST_INT) 5634 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op)); 5635 5636 else if (letter == 'd' && GET_CODE(op) == CONST_INT) 5637 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op))); 5638 5639 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op))) 5640 fputs (reg_names[GP_REG_FIRST], file); 5641 5642 else if (letter == 'd' || letter == 'x' || letter == 'X') 5643 output_operand_lossage ("invalid use of %%d, %%x, or %%X"); 5644 5645 else if (letter == 'T' || letter == 't') 5646 { 5647 int truth = (code == NE) == (letter == 'T'); 5648 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file); 5649 } 5650 5651 else if (CONST_GP_P (op)) 5652 fputs (reg_names[GLOBAL_POINTER_REGNUM], file); 5653 5654 else 5655 output_addr_const (file, op); 5656} 5657 5658 5659/* Print symbolic operand OP, which is part of a HIGH or LO_SUM. 5660 RELOCS is the array of relocations to use. */ 5661 5662static void 5663print_operand_reloc (FILE *file, rtx op, const char **relocs) 5664{ 5665 enum mips_symbol_type symbol_type; 5666 const char *p; 5667 rtx base; 5668 HOST_WIDE_INT offset; 5669 5670 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0) 5671 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op); 5672 5673 /* If OP uses an UNSPEC address, we want to print the inner symbol. */ 5674 mips_split_const (op, &base, &offset); 5675 if (UNSPEC_ADDRESS_P (base)) 5676 op = plus_constant (UNSPEC_ADDRESS (base), offset); 5677 5678 fputs (relocs[symbol_type], file); 5679 output_addr_const (file, op); 5680 for (p = relocs[symbol_type]; *p != 0; p++) 5681 if (*p == '(') 5682 fputc (')', file); 5683} 5684 5685/* Output address operand X to FILE. */ 5686 5687void 5688print_operand_address (FILE *file, rtx x) 5689{ 5690 struct mips_address_info addr; 5691 5692 if (mips_classify_address (&addr, x, word_mode, true)) 5693 switch (addr.type) 5694 { 5695 case ADDRESS_REG: 5696 print_operand (file, addr.offset, 0); 5697 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); 5698 return; 5699 5700 case ADDRESS_LO_SUM: 5701 print_operand (file, addr.offset, 'R'); 5702 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); 5703 return; 5704 5705 case ADDRESS_CONST_INT: 5706 output_addr_const (file, x); 5707 fprintf (file, "(%s)", reg_names[0]); 5708 return; 5709 5710 case ADDRESS_SYMBOLIC: 5711 output_addr_const (file, x); 5712 return; 5713 } 5714 gcc_unreachable (); 5715} 5716 5717/* When using assembler macros, keep track of all of small-data externs 5718 so that mips_file_end can emit the appropriate declarations for them. 5719 5720 In most cases it would be safe (though pointless) to emit .externs 5721 for other symbols too. One exception is when an object is within 5722 the -G limit but declared by the user to be in a section other 5723 than .sbss or .sdata. */ 5724 5725int 5726mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name) 5727{ 5728 register struct extern_list *p; 5729 5730 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl)) 5731 { 5732 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list)); 5733 p->next = extern_head; 5734 p->name = name; 5735 p->size = int_size_in_bytes (TREE_TYPE (decl)); 5736 extern_head = p; 5737 } 5738 5739 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL) 5740 { 5741 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list)); 5742 p->next = extern_head; 5743 p->name = name; 5744 p->size = -1; 5745 extern_head = p; 5746 } 5747 5748 return 0; 5749} 5750 5751#if TARGET_IRIX 5752static void 5753irix_output_external_libcall (rtx fun) 5754{ 5755 register struct extern_list *p; 5756 5757 if (mips_abi == ABI_32) 5758 { 5759 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list)); 5760 p->next = extern_head; 5761 p->name = XSTR (fun, 0); 5762 p->size = -1; 5763 extern_head = p; 5764 } 5765} 5766#endif 5767 5768/* Emit a new filename to a stream. If we are smuggling stabs, try to 5769 put out a MIPS ECOFF file and a stab. */ 5770 5771void 5772mips_output_filename (FILE *stream, const char *name) 5773{ 5774 5775 /* If we are emitting DWARF-2, let dwarf2out handle the ".file" 5776 directives. */ 5777 if (write_symbols == DWARF2_DEBUG) 5778 return; 5779 else if (mips_output_filename_first_time) 5780 { 5781 mips_output_filename_first_time = 0; 5782 num_source_filenames += 1; 5783 current_function_file = name; 5784 fprintf (stream, "\t.file\t%d ", num_source_filenames); 5785 output_quoted_string (stream, name); 5786 putc ('\n', stream); 5787 } 5788 5789 /* If we are emitting stabs, let dbxout.c handle this (except for 5790 the mips_output_filename_first_time case). */ 5791 else if (write_symbols == DBX_DEBUG) 5792 return; 5793 5794 else if (name != current_function_file 5795 && strcmp (name, current_function_file) != 0) 5796 { 5797 num_source_filenames += 1; 5798 current_function_file = name; 5799 fprintf (stream, "\t.file\t%d ", num_source_filenames); 5800 output_quoted_string (stream, name); 5801 putc ('\n', stream); 5802 } 5803} 5804 5805/* Output an ASCII string, in a space-saving way. PREFIX is the string 5806 that should be written before the opening quote, such as "\t.ascii\t" 5807 for real string data or "\t# " for a comment. */ 5808 5809void 5810mips_output_ascii (FILE *stream, const char *string_param, size_t len, 5811 const char *prefix) 5812{ 5813 size_t i; 5814 int cur_pos = 17; 5815 register const unsigned char *string = 5816 (const unsigned char *)string_param; 5817 5818 fprintf (stream, "%s\"", prefix); 5819 for (i = 0; i < len; i++) 5820 { 5821 register int c = string[i]; 5822 5823 if (ISPRINT (c)) 5824 { 5825 if (c == '\\' || c == '\"') 5826 { 5827 putc ('\\', stream); 5828 cur_pos++; 5829 } 5830 putc (c, stream); 5831 cur_pos++; 5832 } 5833 else 5834 { 5835 fprintf (stream, "\\%03o", c); 5836 cur_pos += 4; 5837 } 5838 5839 if (cur_pos > 72 && i+1 < len) 5840 { 5841 cur_pos = 17; 5842 fprintf (stream, "\"\n%s\"", prefix); 5843 } 5844 } 5845 fprintf (stream, "\"\n"); 5846} 5847 5848/* Implement TARGET_ASM_FILE_START. */ 5849 5850static void 5851mips_file_start (void) 5852{ 5853 default_file_start (); 5854 5855 if (!TARGET_IRIX) 5856 { 5857 /* Generate a special section to describe the ABI switches used to 5858 produce the resultant binary. This used to be done by the assembler 5859 setting bits in the ELF header's flags field, but we have run out of 5860 bits. GDB needs this information in order to be able to correctly 5861 debug these binaries. See the function mips_gdbarch_init() in 5862 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and 5863 causes unnecessary IRIX 6 ld warnings. */ 5864 const char * abi_string = NULL; 5865 5866 switch (mips_abi) 5867 { 5868 case ABI_32: abi_string = "abi32"; break; 5869 case ABI_N32: abi_string = "abiN32"; break; 5870 case ABI_64: abi_string = "abi64"; break; 5871 case ABI_O64: abi_string = "abiO64"; break; 5872 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break; 5873 default: 5874 gcc_unreachable (); 5875 } 5876 /* Note - we use fprintf directly rather than calling switch_to_section 5877 because in this way we can avoid creating an allocated section. We 5878 do not want this section to take up any space in the running 5879 executable. */ 5880 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string); 5881 5882 /* There is no ELF header flag to distinguish long32 forms of the 5883 EABI from long64 forms. Emit a special section to help tools 5884 such as GDB. Do the same for o64, which is sometimes used with 5885 -mlong64. */ 5886 if (mips_abi == ABI_EABI || mips_abi == ABI_O64) 5887 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n", 5888 TARGET_LONG64 ? 64 : 32); 5889 5890 /* Restore the default section. */ 5891 fprintf (asm_out_file, "\t.previous\n"); 5892 } 5893 5894 /* Generate the pseudo ops that System V.4 wants. */ 5895 if (TARGET_ABICALLS) 5896 fprintf (asm_out_file, "\t.abicalls\n"); 5897 5898 if (TARGET_MIPS16) 5899 fprintf (asm_out_file, "\t.set\tmips16\n"); 5900 5901 if (flag_verbose_asm) 5902 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n", 5903 ASM_COMMENT_START, 5904 mips_section_threshold, mips_arch_info->name, mips_isa); 5905} 5906 5907#ifdef BSS_SECTION_ASM_OP 5908/* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only 5909 in the use of sbss. */ 5910 5911void 5912mips_output_aligned_bss (FILE *stream, tree decl, const char *name, 5913 unsigned HOST_WIDE_INT size, int align) 5914{ 5915 extern tree last_assemble_variable_decl; 5916 5917 if (mips_in_small_data_p (decl)) 5918 switch_to_section (get_named_section (NULL, ".sbss", 0)); 5919 else 5920 switch_to_section (bss_section); 5921 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT)); 5922 last_assemble_variable_decl = decl; 5923 ASM_DECLARE_OBJECT_NAME (stream, name, decl); 5924 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1); 5925} 5926#endif 5927 5928/* Implement TARGET_ASM_FILE_END. When using assembler macros, emit 5929 .externs for any small-data variables that turned out to be external. */ 5930 5931static void 5932mips_file_end (void) 5933{ 5934 tree name_tree; 5935 struct extern_list *p; 5936 5937 if (extern_head) 5938 { 5939 fputs ("\n", asm_out_file); 5940 5941 for (p = extern_head; p != 0; p = p->next) 5942 { 5943 name_tree = get_identifier (p->name); 5944 5945 /* Positively ensure only one .extern for any given symbol. */ 5946 if (!TREE_ASM_WRITTEN (name_tree) 5947 && TREE_SYMBOL_REFERENCED (name_tree)) 5948 { 5949 TREE_ASM_WRITTEN (name_tree) = 1; 5950 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a 5951 `.global name .text' directive for every used but 5952 undefined function. If we don't, the linker may perform 5953 an optimization (skipping over the insns that set $gp) 5954 when it is unsafe. */ 5955 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1) 5956 { 5957 fputs ("\t.globl ", asm_out_file); 5958 assemble_name (asm_out_file, p->name); 5959 fputs (" .text\n", asm_out_file); 5960 } 5961 else 5962 { 5963 fputs ("\t.extern\t", asm_out_file); 5964 assemble_name (asm_out_file, p->name); 5965 fprintf (asm_out_file, ", %d\n", p->size); 5966 } 5967 } 5968 } 5969 } 5970} 5971 5972/* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the 5973 elfos.h version, but we also need to handle -muninit-const-in-rodata. */ 5974 5975void 5976mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name, 5977 unsigned HOST_WIDE_INT size, 5978 unsigned int align) 5979{ 5980 /* If the target wants uninitialized const declarations in 5981 .rdata then don't put them in .comm. */ 5982 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA 5983 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl) 5984 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node)) 5985 { 5986 if (TREE_PUBLIC (decl) && DECL_NAME (decl)) 5987 targetm.asm_out.globalize_label (stream, name); 5988 5989 switch_to_section (readonly_data_section); 5990 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT)); 5991 mips_declare_object (stream, name, "", 5992 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", 5993 size); 5994 } 5995 else 5996 mips_declare_common_object (stream, name, "\n\t.comm\t", 5997 size, align, true); 5998} 5999 6000/* Declare a common object of SIZE bytes using asm directive INIT_STRING. 6001 NAME is the name of the object and ALIGN is the required alignment 6002 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third 6003 alignment argument. */ 6004 6005void 6006mips_declare_common_object (FILE *stream, const char *name, 6007 const char *init_string, 6008 unsigned HOST_WIDE_INT size, 6009 unsigned int align, bool takes_alignment_p) 6010{ 6011 if (!takes_alignment_p) 6012 { 6013 size += (align / BITS_PER_UNIT) - 1; 6014 size -= size % (align / BITS_PER_UNIT); 6015 mips_declare_object (stream, name, init_string, 6016 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size); 6017 } 6018 else 6019 mips_declare_object (stream, name, init_string, 6020 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n", 6021 size, align / BITS_PER_UNIT); 6022} 6023 6024/* Emit either a label, .comm, or .lcomm directive. When using assembler 6025 macros, mark the symbol as written so that mips_file_end won't emit an 6026 .extern for it. STREAM is the output file, NAME is the name of the 6027 symbol, INIT_STRING is the string that should be written before the 6028 symbol and FINAL_STRING is the string that should be written after it. 6029 FINAL_STRING is a printf() format that consumes the remaining arguments. */ 6030 6031void 6032mips_declare_object (FILE *stream, const char *name, const char *init_string, 6033 const char *final_string, ...) 6034{ 6035 va_list ap; 6036 6037 fputs (init_string, stream); 6038 assemble_name (stream, name); 6039 va_start (ap, final_string); 6040 vfprintf (stream, final_string, ap); 6041 va_end (ap); 6042 6043 if (!TARGET_EXPLICIT_RELOCS) 6044 { 6045 tree name_tree = get_identifier (name); 6046 TREE_ASM_WRITTEN (name_tree) = 1; 6047 } 6048} 6049 6050#ifdef ASM_OUTPUT_SIZE_DIRECTIVE 6051extern int size_directive_output; 6052 6053/* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF 6054 definitions except that it uses mips_declare_object() to emit the label. */ 6055 6056void 6057mips_declare_object_name (FILE *stream, const char *name, 6058 tree decl ATTRIBUTE_UNUSED) 6059{ 6060#ifdef ASM_OUTPUT_TYPE_DIRECTIVE 6061 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object"); 6062#endif 6063 6064 size_directive_output = 0; 6065 if (!flag_inhibit_size_directive && DECL_SIZE (decl)) 6066 { 6067 HOST_WIDE_INT size; 6068 6069 size_directive_output = 1; 6070 size = int_size_in_bytes (TREE_TYPE (decl)); 6071 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); 6072 } 6073 6074 mips_declare_object (stream, name, "", ":\n"); 6075} 6076 6077/* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */ 6078 6079void 6080mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end) 6081{ 6082 const char *name; 6083 6084 name = XSTR (XEXP (DECL_RTL (decl), 0), 0); 6085 if (!flag_inhibit_size_directive 6086 && DECL_SIZE (decl) != 0 6087 && !at_end && top_level 6088 && DECL_INITIAL (decl) == error_mark_node 6089 && !size_directive_output) 6090 { 6091 HOST_WIDE_INT size; 6092 6093 size_directive_output = 1; 6094 size = int_size_in_bytes (TREE_TYPE (decl)); 6095 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); 6096 } 6097} 6098#endif 6099 6100/* Return true if X is a small data address that can be rewritten 6101 as a LO_SUM. */ 6102 6103static bool 6104mips_rewrite_small_data_p (rtx x) 6105{ 6106 enum mips_symbol_type symbol_type; 6107 6108 return (TARGET_EXPLICIT_RELOCS 6109 && mips_symbolic_constant_p (x, &symbol_type) 6110 && symbol_type == SYMBOL_SMALL_DATA); 6111} 6112 6113 6114/* A for_each_rtx callback for mips_small_data_pattern_p. */ 6115 6116static int 6117mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED) 6118{ 6119 if (GET_CODE (*loc) == LO_SUM) 6120 return -1; 6121 6122 return mips_rewrite_small_data_p (*loc); 6123} 6124 6125/* Return true if OP refers to small data symbols directly, not through 6126 a LO_SUM. */ 6127 6128bool 6129mips_small_data_pattern_p (rtx op) 6130{ 6131 return for_each_rtx (&op, mips_small_data_pattern_1, 0); 6132} 6133 6134/* A for_each_rtx callback, used by mips_rewrite_small_data. */ 6135 6136static int 6137mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED) 6138{ 6139 if (mips_rewrite_small_data_p (*loc)) 6140 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc); 6141 6142 if (GET_CODE (*loc) == LO_SUM) 6143 return -1; 6144 6145 return 0; 6146} 6147 6148/* If possible, rewrite OP so that it refers to small data using 6149 explicit relocations. */ 6150 6151rtx 6152mips_rewrite_small_data (rtx op) 6153{ 6154 op = copy_insn (op); 6155 for_each_rtx (&op, mips_rewrite_small_data_1, 0); 6156 return op; 6157} 6158 6159/* Return true if the current function has an insn that implicitly 6160 refers to $gp. */ 6161 6162static bool 6163mips_function_has_gp_insn (void) 6164{ 6165 /* Don't bother rechecking if we found one last time. */ 6166 if (!cfun->machine->has_gp_insn_p) 6167 { 6168 rtx insn; 6169 6170 push_topmost_sequence (); 6171 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 6172 if (INSN_P (insn) 6173 && GET_CODE (PATTERN (insn)) != USE 6174 && GET_CODE (PATTERN (insn)) != CLOBBER 6175 && (get_attr_got (insn) != GOT_UNSET 6176 || small_data_pattern (PATTERN (insn), VOIDmode))) 6177 break; 6178 pop_topmost_sequence (); 6179 6180 cfun->machine->has_gp_insn_p = (insn != 0); 6181 } 6182 return cfun->machine->has_gp_insn_p; 6183} 6184 6185 6186/* Return the register that should be used as the global pointer 6187 within this function. Return 0 if the function doesn't need 6188 a global pointer. */ 6189 6190static unsigned int 6191mips_global_pointer (void) 6192{ 6193 unsigned int regno; 6194 6195 /* $gp is always available in non-abicalls code. */ 6196 if (!TARGET_ABICALLS) 6197 return GLOBAL_POINTER_REGNUM; 6198 6199 /* We must always provide $gp when it is used implicitly. */ 6200 if (!TARGET_EXPLICIT_RELOCS) 6201 return GLOBAL_POINTER_REGNUM; 6202 6203 /* FUNCTION_PROFILER includes a jal macro, so we need to give it 6204 a valid gp. */ 6205 if (current_function_profile) 6206 return GLOBAL_POINTER_REGNUM; 6207 6208 /* If the function has a nonlocal goto, $gp must hold the correct 6209 global pointer for the target function. */ 6210 if (current_function_has_nonlocal_goto) 6211 return GLOBAL_POINTER_REGNUM; 6212 6213 /* If the gp is never referenced, there's no need to initialize it. 6214 Note that reload can sometimes introduce constant pool references 6215 into a function that otherwise didn't need them. For example, 6216 suppose we have an instruction like: 6217 6218 (set (reg:DF R1) (float:DF (reg:SI R2))) 6219 6220 If R2 turns out to be constant such as 1, the instruction may have a 6221 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of 6222 using this constant if R2 doesn't get allocated to a register. 6223 6224 In cases like these, reload will have added the constant to the pool 6225 but no instruction will yet refer to it. */ 6226 if (!regs_ever_live[GLOBAL_POINTER_REGNUM] 6227 && !current_function_uses_const_pool 6228 && !mips_function_has_gp_insn ()) 6229 return 0; 6230 6231 /* We need a global pointer, but perhaps we can use a call-clobbered 6232 register instead of $gp. */ 6233 if (TARGET_NEWABI && current_function_is_leaf) 6234 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 6235 if (!regs_ever_live[regno] 6236 && call_used_regs[regno] 6237 && !fixed_regs[regno] 6238 && regno != PIC_FUNCTION_ADDR_REGNUM) 6239 return regno; 6240 6241 return GLOBAL_POINTER_REGNUM; 6242} 6243 6244 6245/* Return true if the current function must save REGNO. */ 6246 6247static bool 6248mips_save_reg_p (unsigned int regno) 6249{ 6250 /* We only need to save $gp for NewABI PIC. */ 6251 if (regno == GLOBAL_POINTER_REGNUM) 6252 return (TARGET_ABICALLS && TARGET_NEWABI 6253 && cfun->machine->global_pointer == regno); 6254 6255 /* Check call-saved registers. */ 6256 if (regs_ever_live[regno] && !call_used_regs[regno]) 6257 return true; 6258 6259 /* We need to save the old frame pointer before setting up a new one. */ 6260 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) 6261 return true; 6262 6263 /* We need to save the incoming return address if it is ever clobbered 6264 within the function. */ 6265 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno]) 6266 return true; 6267 6268 if (TARGET_MIPS16) 6269 { 6270 tree return_type; 6271 6272 return_type = DECL_RESULT (current_function_decl); 6273 6274 /* $18 is a special case in mips16 code. It may be used to call 6275 a function which returns a floating point value, but it is 6276 marked in call_used_regs. */ 6277 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno]) 6278 return true; 6279 6280 /* $31 is also a special case. It will be used to copy a return 6281 value into the floating point registers if the return value is 6282 floating point. */ 6283 if (regno == GP_REG_FIRST + 31 6284 && mips16_hard_float 6285 && !aggregate_value_p (return_type, current_function_decl) 6286 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT 6287 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE) 6288 return true; 6289 } 6290 6291 return false; 6292} 6293 6294 6295/* Return the bytes needed to compute the frame pointer from the current 6296 stack pointer. SIZE is the size (in bytes) of the local variables. 6297 6298 MIPS stack frames look like: 6299 6300 Before call After call 6301 +-----------------------+ +-----------------------+ 6302 high | | | | 6303 mem. | | | | 6304 | caller's temps. | | caller's temps. | 6305 | | | | 6306 +-----------------------+ +-----------------------+ 6307 | | | | 6308 | arguments on stack. | | arguments on stack. | 6309 | | | | 6310 +-----------------------+ +-----------------------+ 6311 | 4 words to save | | 4 words to save | 6312 | arguments passed | | arguments passed | 6313 | in registers, even | | in registers, even | 6314 SP->| if not passed. | VFP->| if not passed. | 6315 +-----------------------+ +-----------------------+ 6316 | | 6317 | fp register save | 6318 | | 6319 +-----------------------+ 6320 | | 6321 | gp register save | 6322 | | 6323 +-----------------------+ 6324 | | 6325 | local variables | 6326 | | 6327 +-----------------------+ 6328 | | 6329 | alloca allocations | 6330 | | 6331 +-----------------------+ 6332 | | 6333 | GP save for V.4 abi | 6334 | | 6335 +-----------------------+ 6336 | | 6337 | arguments on stack | 6338 | | 6339 +-----------------------+ 6340 | 4 words to save | 6341 | arguments passed | 6342 | in registers, even | 6343 low SP->| if not passed. | 6344 memory +-----------------------+ 6345 6346*/ 6347 6348HOST_WIDE_INT 6349compute_frame_size (HOST_WIDE_INT size) 6350{ 6351 unsigned int regno; 6352 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */ 6353 HOST_WIDE_INT var_size; /* # bytes that variables take up */ 6354 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */ 6355 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */ 6356 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */ 6357 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */ 6358 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */ 6359 unsigned int mask; /* mask of saved gp registers */ 6360 unsigned int fmask; /* mask of saved fp registers */ 6361 6362 cfun->machine->global_pointer = mips_global_pointer (); 6363 6364 gp_reg_size = 0; 6365 fp_reg_size = 0; 6366 mask = 0; 6367 fmask = 0; 6368 var_size = MIPS_STACK_ALIGN (size); 6369 args_size = current_function_outgoing_args_size; 6370 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size; 6371 6372 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf 6373 functions. If the function has local variables, we're committed 6374 to allocating it anyway. Otherwise reclaim it here. */ 6375 if (var_size == 0 && current_function_is_leaf) 6376 cprestore_size = args_size = 0; 6377 6378 /* The MIPS 3.0 linker does not like functions that dynamically 6379 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it 6380 looks like we are trying to create a second frame pointer to the 6381 function, so allocate some stack space to make it happy. */ 6382 6383 if (args_size == 0 && current_function_calls_alloca) 6384 args_size = 4 * UNITS_PER_WORD; 6385 6386 total_size = var_size + args_size + cprestore_size; 6387 6388 /* Calculate space needed for gp registers. */ 6389 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 6390 if (mips_save_reg_p (regno)) 6391 { 6392 gp_reg_size += GET_MODE_SIZE (gpr_mode); 6393 mask |= 1 << (regno - GP_REG_FIRST); 6394 } 6395 6396 /* We need to restore these for the handler. */ 6397 if (current_function_calls_eh_return) 6398 { 6399 unsigned int i; 6400 for (i = 0; ; ++i) 6401 { 6402 regno = EH_RETURN_DATA_REGNO (i); 6403 if (regno == INVALID_REGNUM) 6404 break; 6405 gp_reg_size += GET_MODE_SIZE (gpr_mode); 6406 mask |= 1 << (regno - GP_REG_FIRST); 6407 } 6408 } 6409 6410 /* This loop must iterate over the same space as its companion in 6411 save_restore_insns. */ 6412 for (regno = (FP_REG_LAST - FP_INC + 1); 6413 regno >= FP_REG_FIRST; 6414 regno -= FP_INC) 6415 { 6416 if (mips_save_reg_p (regno)) 6417 { 6418 fp_reg_size += FP_INC * UNITS_PER_FPREG; 6419 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST); 6420 } 6421 } 6422 6423 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size); 6424 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size); 6425 6426 /* Add in the space required for saving incoming register arguments. */ 6427 total_size += current_function_pretend_args_size; 6428 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size); 6429 6430 /* Save other computed information. */ 6431 cfun->machine->frame.total_size = total_size; 6432 cfun->machine->frame.var_size = var_size; 6433 cfun->machine->frame.args_size = args_size; 6434 cfun->machine->frame.cprestore_size = cprestore_size; 6435 cfun->machine->frame.gp_reg_size = gp_reg_size; 6436 cfun->machine->frame.fp_reg_size = fp_reg_size; 6437 cfun->machine->frame.mask = mask; 6438 cfun->machine->frame.fmask = fmask; 6439 cfun->machine->frame.initialized = reload_completed; 6440 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD; 6441 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG); 6442 6443 if (mask) 6444 { 6445 HOST_WIDE_INT offset; 6446 6447 offset = (args_size + cprestore_size + var_size 6448 + gp_reg_size - GET_MODE_SIZE (gpr_mode)); 6449 cfun->machine->frame.gp_sp_offset = offset; 6450 cfun->machine->frame.gp_save_offset = offset - total_size; 6451 } 6452 else 6453 { 6454 cfun->machine->frame.gp_sp_offset = 0; 6455 cfun->machine->frame.gp_save_offset = 0; 6456 } 6457 6458 if (fmask) 6459 { 6460 HOST_WIDE_INT offset; 6461 6462 offset = (args_size + cprestore_size + var_size 6463 + gp_reg_rounded + fp_reg_size 6464 - FP_INC * UNITS_PER_FPREG); 6465 cfun->machine->frame.fp_sp_offset = offset; 6466 cfun->machine->frame.fp_save_offset = offset - total_size; 6467 } 6468 else 6469 { 6470 cfun->machine->frame.fp_sp_offset = 0; 6471 cfun->machine->frame.fp_save_offset = 0; 6472 } 6473 6474 /* Ok, we're done. */ 6475 return total_size; 6476} 6477 6478/* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame 6479 pointer or argument pointer. TO is either the stack pointer or 6480 hard frame pointer. */ 6481 6482HOST_WIDE_INT 6483mips_initial_elimination_offset (int from, int to) 6484{ 6485 HOST_WIDE_INT offset; 6486 6487 compute_frame_size (get_frame_size ()); 6488 6489 /* Set OFFSET to the offset from the stack pointer. */ 6490 switch (from) 6491 { 6492 case FRAME_POINTER_REGNUM: 6493 offset = 0; 6494 break; 6495 6496 case ARG_POINTER_REGNUM: 6497 offset = (cfun->machine->frame.total_size 6498 - current_function_pretend_args_size); 6499 break; 6500 6501 default: 6502 gcc_unreachable (); 6503 } 6504 6505 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM) 6506 offset -= cfun->machine->frame.args_size; 6507 6508 return offset; 6509} 6510 6511/* Implement RETURN_ADDR_RTX. Note, we do not support moving 6512 back to a previous frame. */ 6513rtx 6514mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) 6515{ 6516 if (count != 0) 6517 return const0_rtx; 6518 6519 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31); 6520} 6521 6522/* Use FN to save or restore register REGNO. MODE is the register's 6523 mode and OFFSET is the offset of its save slot from the current 6524 stack pointer. */ 6525 6526static void 6527mips_save_restore_reg (enum machine_mode mode, int regno, 6528 HOST_WIDE_INT offset, mips_save_restore_fn fn) 6529{ 6530 rtx mem; 6531 6532 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset)); 6533 6534 fn (gen_rtx_REG (mode, regno), mem); 6535} 6536 6537 6538/* Call FN for each register that is saved by the current function. 6539 SP_OFFSET is the offset of the current stack pointer from the start 6540 of the frame. */ 6541 6542static void 6543mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn) 6544{ 6545#define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0) 6546 6547 enum machine_mode fpr_mode; 6548 HOST_WIDE_INT offset; 6549 int regno; 6550 6551 /* Save registers starting from high to low. The debuggers prefer at least 6552 the return register be stored at func+4, and also it allows us not to 6553 need a nop in the epilog if at least one register is reloaded in 6554 addition to return address. */ 6555 offset = cfun->machine->frame.gp_sp_offset - sp_offset; 6556 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--) 6557 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) 6558 { 6559 mips_save_restore_reg (gpr_mode, regno, offset, fn); 6560 offset -= GET_MODE_SIZE (gpr_mode); 6561 } 6562 6563 /* This loop must iterate over the same space as its companion in 6564 compute_frame_size. */ 6565 offset = cfun->machine->frame.fp_sp_offset - sp_offset; 6566 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode); 6567 for (regno = (FP_REG_LAST - FP_INC + 1); 6568 regno >= FP_REG_FIRST; 6569 regno -= FP_INC) 6570 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) 6571 { 6572 mips_save_restore_reg (fpr_mode, regno, offset, fn); 6573 offset -= GET_MODE_SIZE (fpr_mode); 6574 } 6575#undef BITSET_P 6576} 6577 6578/* If we're generating n32 or n64 abicalls, and the current function 6579 does not use $28 as its global pointer, emit a cplocal directive. 6580 Use pic_offset_table_rtx as the argument to the directive. */ 6581 6582static void 6583mips_output_cplocal (void) 6584{ 6585 if (!TARGET_EXPLICIT_RELOCS 6586 && cfun->machine->global_pointer > 0 6587 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM) 6588 output_asm_insn (".cplocal %+", 0); 6589} 6590 6591/* Return the style of GP load sequence that is being used for the 6592 current function. */ 6593 6594enum mips_loadgp_style 6595mips_current_loadgp_style (void) 6596{ 6597 if (!TARGET_ABICALLS || cfun->machine->global_pointer == 0) 6598 return LOADGP_NONE; 6599 6600 if (TARGET_ABSOLUTE_ABICALLS) 6601 return LOADGP_ABSOLUTE; 6602 6603 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI; 6604} 6605 6606/* The __gnu_local_gp symbol. */ 6607 6608static GTY(()) rtx mips_gnu_local_gp; 6609 6610/* If we're generating n32 or n64 abicalls, emit instructions 6611 to set up the global pointer. */ 6612 6613static void 6614mips_emit_loadgp (void) 6615{ 6616 rtx addr, offset, incoming_address; 6617 6618 switch (mips_current_loadgp_style ()) 6619 { 6620 case LOADGP_ABSOLUTE: 6621 if (mips_gnu_local_gp == NULL) 6622 { 6623 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp"); 6624 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL; 6625 } 6626 emit_insn (gen_loadgp_noshared (mips_gnu_local_gp)); 6627 break; 6628 6629 case LOADGP_NEWABI: 6630 addr = XEXP (DECL_RTL (current_function_decl), 0); 6631 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP); 6632 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); 6633 emit_insn (gen_loadgp (offset, incoming_address)); 6634 if (!TARGET_EXPLICIT_RELOCS) 6635 emit_insn (gen_loadgp_blockage ()); 6636 break; 6637 6638 default: 6639 break; 6640 } 6641} 6642 6643/* Set up the stack and frame (if desired) for the function. */ 6644 6645static void 6646mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) 6647{ 6648 const char *fnname; 6649 HOST_WIDE_INT tsize = cfun->machine->frame.total_size; 6650 6651#ifdef SDB_DEBUGGING_INFO 6652 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG) 6653 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl)); 6654#endif 6655 6656 /* In mips16 mode, we may need to generate a 32 bit to handle 6657 floating point arguments. The linker will arrange for any 32 bit 6658 functions to call this stub, which will then jump to the 16 bit 6659 function proper. */ 6660 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT 6661 && current_function_args_info.fp_code != 0) 6662 build_mips16_function_stub (file); 6663 6664 if (!FUNCTION_NAME_ALREADY_DECLARED) 6665 { 6666 /* Get the function name the same way that toplev.c does before calling 6667 assemble_start_function. This is needed so that the name used here 6668 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ 6669 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); 6670 6671 if (!flag_inhibit_size_directive) 6672 { 6673 fputs ("\t.ent\t", file); 6674 assemble_name (file, fnname); 6675 fputs ("\n", file); 6676 } 6677 6678 assemble_name (file, fnname); 6679 fputs (":\n", file); 6680 } 6681 6682 /* Stop mips_file_end from treating this function as external. */ 6683 if (TARGET_IRIX && mips_abi == ABI_32) 6684 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1; 6685 6686 if (!flag_inhibit_size_directive) 6687 { 6688 /* .frame FRAMEREG, FRAMESIZE, RETREG */ 6689 fprintf (file, 6690 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t" 6691 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d" 6692 ", args= " HOST_WIDE_INT_PRINT_DEC 6693 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n", 6694 (reg_names[(frame_pointer_needed) 6695 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]), 6696 ((frame_pointer_needed && TARGET_MIPS16) 6697 ? tsize - cfun->machine->frame.args_size 6698 : tsize), 6699 reg_names[GP_REG_FIRST + 31], 6700 cfun->machine->frame.var_size, 6701 cfun->machine->frame.num_gp, 6702 cfun->machine->frame.num_fp, 6703 cfun->machine->frame.args_size, 6704 cfun->machine->frame.cprestore_size); 6705 6706 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */ 6707 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n", 6708 cfun->machine->frame.mask, 6709 cfun->machine->frame.gp_save_offset); 6710 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n", 6711 cfun->machine->frame.fmask, 6712 cfun->machine->frame.fp_save_offset); 6713 6714 /* Require: 6715 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg. 6716 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */ 6717 } 6718 6719 if (mips_current_loadgp_style () == LOADGP_OLDABI) 6720 { 6721 /* Handle the initialization of $gp for SVR4 PIC. */ 6722 if (!cfun->machine->all_noreorder_p) 6723 output_asm_insn ("%(.cpload\t%^%)", 0); 6724 else 6725 output_asm_insn ("%(.cpload\t%^\n\t%<", 0); 6726 } 6727 else if (cfun->machine->all_noreorder_p) 6728 output_asm_insn ("%(%<", 0); 6729 6730 /* Tell the assembler which register we're using as the global 6731 pointer. This is needed for thunks, since they can use either 6732 explicit relocs or assembler macros. */ 6733 mips_output_cplocal (); 6734} 6735 6736/* Make the last instruction frame related and note that it performs 6737 the operation described by FRAME_PATTERN. */ 6738 6739static void 6740mips_set_frame_expr (rtx frame_pattern) 6741{ 6742 rtx insn; 6743 6744 insn = get_last_insn (); 6745 RTX_FRAME_RELATED_P (insn) = 1; 6746 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, 6747 frame_pattern, 6748 REG_NOTES (insn)); 6749} 6750 6751 6752/* Return a frame-related rtx that stores REG at MEM. 6753 REG must be a single register. */ 6754 6755static rtx 6756mips_frame_set (rtx mem, rtx reg) 6757{ 6758 rtx set; 6759 6760 /* If we're saving the return address register and the dwarf return 6761 address column differs from the hard register number, adjust the 6762 note reg to refer to the former. */ 6763 if (REGNO (reg) == GP_REG_FIRST + 31 6764 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31) 6765 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN); 6766 6767 set = gen_rtx_SET (VOIDmode, mem, reg); 6768 RTX_FRAME_RELATED_P (set) = 1; 6769 6770 return set; 6771} 6772 6773 6774/* Save register REG to MEM. Make the instruction frame-related. */ 6775 6776static void 6777mips_save_reg (rtx reg, rtx mem) 6778{ 6779 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64) 6780 { 6781 rtx x1, x2; 6782 6783 if (mips_split_64bit_move_p (mem, reg)) 6784 mips_split_64bit_move (mem, reg); 6785 else 6786 emit_move_insn (mem, reg); 6787 6788 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0)); 6789 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1)); 6790 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2))); 6791 } 6792 else 6793 { 6794 if (TARGET_MIPS16 6795 && REGNO (reg) != GP_REG_FIRST + 31 6796 && !M16_REG_P (REGNO (reg))) 6797 { 6798 /* Save a non-mips16 register by moving it through a temporary. 6799 We don't need to do this for $31 since there's a special 6800 instruction for it. */ 6801 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg); 6802 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg))); 6803 } 6804 else 6805 emit_move_insn (mem, reg); 6806 6807 mips_set_frame_expr (mips_frame_set (mem, reg)); 6808 } 6809} 6810 6811 6812/* Expand the prologue into a bunch of separate insns. */ 6813 6814void 6815mips_expand_prologue (void) 6816{ 6817 HOST_WIDE_INT size; 6818 6819 if (cfun->machine->global_pointer > 0) 6820 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer; 6821 6822 size = compute_frame_size (get_frame_size ()); 6823 6824 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP 6825 bytes beforehand; this is enough to cover the register save area 6826 without going out of range. */ 6827 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0) 6828 { 6829 HOST_WIDE_INT step1; 6830 6831 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP); 6832 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx, 6833 stack_pointer_rtx, 6834 GEN_INT (-step1)))) = 1; 6835 size -= step1; 6836 mips_for_each_saved_reg (size, mips_save_reg); 6837 } 6838 6839 /* Allocate the rest of the frame. */ 6840 if (size > 0) 6841 { 6842 if (SMALL_OPERAND (-size)) 6843 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx, 6844 stack_pointer_rtx, 6845 GEN_INT (-size)))) = 1; 6846 else 6847 { 6848 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size)); 6849 if (TARGET_MIPS16) 6850 { 6851 /* There are no instructions to add or subtract registers 6852 from the stack pointer, so use the frame pointer as a 6853 temporary. We should always be using a frame pointer 6854 in this case anyway. */ 6855 gcc_assert (frame_pointer_needed); 6856 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); 6857 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx, 6858 hard_frame_pointer_rtx, 6859 MIPS_PROLOGUE_TEMP (Pmode))); 6860 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); 6861 } 6862 else 6863 emit_insn (gen_sub3_insn (stack_pointer_rtx, 6864 stack_pointer_rtx, 6865 MIPS_PROLOGUE_TEMP (Pmode))); 6866 6867 /* Describe the combined effect of the previous instructions. */ 6868 mips_set_frame_expr 6869 (gen_rtx_SET (VOIDmode, stack_pointer_rtx, 6870 plus_constant (stack_pointer_rtx, -size))); 6871 } 6872 } 6873 6874 /* Set up the frame pointer, if we're using one. In mips16 code, 6875 we point the frame pointer ahead of the outgoing argument area. 6876 This should allow more variables & incoming arguments to be 6877 accessed with unextended instructions. */ 6878 if (frame_pointer_needed) 6879 { 6880 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0) 6881 { 6882 rtx offset = GEN_INT (cfun->machine->frame.args_size); 6883 if (SMALL_OPERAND (cfun->machine->frame.args_size)) 6884 RTX_FRAME_RELATED_P 6885 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx, 6886 stack_pointer_rtx, 6887 offset))) = 1; 6888 else 6889 { 6890 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset); 6891 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); 6892 emit_insn (gen_add3_insn (hard_frame_pointer_rtx, 6893 hard_frame_pointer_rtx, 6894 MIPS_PROLOGUE_TEMP (Pmode))); 6895 mips_set_frame_expr 6896 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx, 6897 plus_constant (stack_pointer_rtx, 6898 cfun->machine->frame.args_size))); 6899 } 6900 } 6901 else 6902 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx, 6903 stack_pointer_rtx)) = 1; 6904 } 6905 6906 mips_emit_loadgp (); 6907 6908 /* If generating o32/o64 abicalls, save $gp on the stack. */ 6909 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf) 6910 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size))); 6911 6912 /* If we are profiling, make sure no instructions are scheduled before 6913 the call to mcount. */ 6914 6915 if (current_function_profile) 6916 emit_insn (gen_blockage ()); 6917} 6918 6919/* Do any necessary cleanup after a function to restore stack, frame, 6920 and regs. */ 6921 6922#define RA_MASK BITMASK_HIGH /* 1 << 31 */ 6923 6924static void 6925mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, 6926 HOST_WIDE_INT size ATTRIBUTE_UNUSED) 6927{ 6928 /* Reinstate the normal $gp. */ 6929 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM; 6930 mips_output_cplocal (); 6931 6932 if (cfun->machine->all_noreorder_p) 6933 { 6934 /* Avoid using %>%) since it adds excess whitespace. */ 6935 output_asm_insn (".set\tmacro", 0); 6936 output_asm_insn (".set\treorder", 0); 6937 set_noreorder = set_nomacro = 0; 6938 } 6939 6940 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive) 6941 { 6942 const char *fnname; 6943 6944 /* Get the function name the same way that toplev.c does before calling 6945 assemble_start_function. This is needed so that the name used here 6946 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ 6947 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); 6948 fputs ("\t.end\t", file); 6949 assemble_name (file, fnname); 6950 fputs ("\n", file); 6951 } 6952} 6953 6954/* Emit instructions to restore register REG from slot MEM. */ 6955 6956static void 6957mips_restore_reg (rtx reg, rtx mem) 6958{ 6959 /* There's no mips16 instruction to load $31 directly. Load into 6960 $7 instead and adjust the return insn appropriately. */ 6961 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31) 6962 reg = gen_rtx_REG (GET_MODE (reg), 7); 6963 6964 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg))) 6965 { 6966 /* Can't restore directly; move through a temporary. */ 6967 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem); 6968 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg))); 6969 } 6970 else 6971 emit_move_insn (reg, mem); 6972} 6973 6974 6975/* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true 6976 if this epilogue precedes a sibling call, false if it is for a normal 6977 "epilogue" pattern. */ 6978 6979void 6980mips_expand_epilogue (int sibcall_p) 6981{ 6982 HOST_WIDE_INT step1, step2; 6983 rtx base, target; 6984 6985 if (!sibcall_p && mips_can_use_return_insn ()) 6986 { 6987 emit_jump_insn (gen_return ()); 6988 return; 6989 } 6990 6991 /* Split the frame into two. STEP1 is the amount of stack we should 6992 deallocate before restoring the registers. STEP2 is the amount we 6993 should deallocate afterwards. 6994 6995 Start off by assuming that no registers need to be restored. */ 6996 step1 = cfun->machine->frame.total_size; 6997 step2 = 0; 6998 6999 /* Work out which register holds the frame address. Account for the 7000 frame pointer offset used by mips16 code. */ 7001 if (!frame_pointer_needed) 7002 base = stack_pointer_rtx; 7003 else 7004 { 7005 base = hard_frame_pointer_rtx; 7006 if (TARGET_MIPS16) 7007 step1 -= cfun->machine->frame.args_size; 7008 } 7009 7010 /* If we need to restore registers, deallocate as much stack as 7011 possible in the second step without going out of range. */ 7012 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0) 7013 { 7014 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP); 7015 step1 -= step2; 7016 } 7017 7018 /* Set TARGET to BASE + STEP1. */ 7019 target = base; 7020 if (step1 > 0) 7021 { 7022 rtx adjust; 7023 7024 /* Get an rtx for STEP1 that we can add to BASE. */ 7025 adjust = GEN_INT (step1); 7026 if (!SMALL_OPERAND (step1)) 7027 { 7028 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust); 7029 adjust = MIPS_EPILOGUE_TEMP (Pmode); 7030 } 7031 7032 /* Normal mode code can copy the result straight into $sp. */ 7033 if (!TARGET_MIPS16) 7034 target = stack_pointer_rtx; 7035 7036 emit_insn (gen_add3_insn (target, base, adjust)); 7037 } 7038 7039 /* Copy TARGET into the stack pointer. */ 7040 if (target != stack_pointer_rtx) 7041 emit_move_insn (stack_pointer_rtx, target); 7042 7043 /* If we're using addressing macros for n32/n64 abicalls, $gp is 7044 implicitly used by all SYMBOL_REFs. We must emit a blockage 7045 insn before restoring it. */ 7046 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS) 7047 emit_insn (gen_blockage ()); 7048 7049 /* Restore the registers. */ 7050 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2, 7051 mips_restore_reg); 7052 7053 /* Deallocate the final bit of the frame. */ 7054 if (step2 > 0) 7055 emit_insn (gen_add3_insn (stack_pointer_rtx, 7056 stack_pointer_rtx, 7057 GEN_INT (step2))); 7058 7059 /* Add in the __builtin_eh_return stack adjustment. We need to 7060 use a temporary in mips16 code. */ 7061 if (current_function_calls_eh_return) 7062 { 7063 if (TARGET_MIPS16) 7064 { 7065 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx); 7066 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode), 7067 MIPS_EPILOGUE_TEMP (Pmode), 7068 EH_RETURN_STACKADJ_RTX)); 7069 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode)); 7070 } 7071 else 7072 emit_insn (gen_add3_insn (stack_pointer_rtx, 7073 stack_pointer_rtx, 7074 EH_RETURN_STACKADJ_RTX)); 7075 } 7076 7077 if (!sibcall_p) 7078 { 7079 /* The mips16 loads the return address into $7, not $31. */ 7080 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0) 7081 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, 7082 GP_REG_FIRST + 7))); 7083 else 7084 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, 7085 GP_REG_FIRST + 31))); 7086 } 7087} 7088 7089/* Return nonzero if this function is known to have a null epilogue. 7090 This allows the optimizer to omit jumps to jumps if no stack 7091 was created. */ 7092 7093int 7094mips_can_use_return_insn (void) 7095{ 7096 tree return_type; 7097 7098 if (! reload_completed) 7099 return 0; 7100 7101 if (regs_ever_live[31] || current_function_profile) 7102 return 0; 7103 7104 return_type = DECL_RESULT (current_function_decl); 7105 7106 /* In mips16 mode, a function which returns a floating point value 7107 needs to arrange to copy the return value into the floating point 7108 registers. */ 7109 if (TARGET_MIPS16 7110 && mips16_hard_float 7111 && ! aggregate_value_p (return_type, current_function_decl) 7112 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT 7113 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE) 7114 return 0; 7115 7116 if (cfun->machine->frame.initialized) 7117 return cfun->machine->frame.total_size == 0; 7118 7119 return compute_frame_size (get_frame_size ()) == 0; 7120} 7121 7122/* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text 7123 in order to avoid duplicating too much logic from elsewhere. */ 7124 7125static void 7126mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 7127 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 7128 tree function) 7129{ 7130 rtx this, temp1, temp2, insn, fnaddr; 7131 7132 /* Pretend to be a post-reload pass while generating rtl. */ 7133 no_new_pseudos = 1; 7134 reload_completed = 1; 7135 reset_block_changes (); 7136 7137 /* Pick a global pointer for -mabicalls. Use $15 rather than $28 7138 for TARGET_NEWABI since the latter is a call-saved register. */ 7139 if (TARGET_ABICALLS) 7140 cfun->machine->global_pointer 7141 = REGNO (pic_offset_table_rtx) 7142 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM; 7143 7144 /* Set up the global pointer for n32 or n64 abicalls. */ 7145 mips_emit_loadgp (); 7146 7147 /* We need two temporary registers in some cases. */ 7148 temp1 = gen_rtx_REG (Pmode, 2); 7149 temp2 = gen_rtx_REG (Pmode, 3); 7150 7151 /* Find out which register contains the "this" pointer. */ 7152 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) 7153 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1); 7154 else 7155 this = gen_rtx_REG (Pmode, GP_ARG_FIRST); 7156 7157 /* Add DELTA to THIS. */ 7158 if (delta != 0) 7159 { 7160 rtx offset = GEN_INT (delta); 7161 if (!SMALL_OPERAND (delta)) 7162 { 7163 emit_move_insn (temp1, offset); 7164 offset = temp1; 7165 } 7166 emit_insn (gen_add3_insn (this, this, offset)); 7167 } 7168 7169 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */ 7170 if (vcall_offset != 0) 7171 { 7172 rtx addr; 7173 7174 /* Set TEMP1 to *THIS. */ 7175 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this)); 7176 7177 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */ 7178 addr = mips_add_offset (temp2, temp1, vcall_offset); 7179 7180 /* Load the offset and add it to THIS. */ 7181 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr)); 7182 emit_insn (gen_add3_insn (this, this, temp1)); 7183 } 7184 7185 /* Jump to the target function. Use a sibcall if direct jumps are 7186 allowed, otherwise load the address into a register first. */ 7187 fnaddr = XEXP (DECL_RTL (function), 0); 7188 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS) 7189 { 7190 /* This is messy. gas treats "la $25,foo" as part of a call 7191 sequence and may allow a global "foo" to be lazily bound. 7192 The general move patterns therefore reject this combination. 7193 7194 In this context, lazy binding would actually be OK for o32 and o64, 7195 but it's still wrong for n32 and n64; see mips_load_call_address. 7196 We must therefore load the address via a temporary register if 7197 mips_dangerous_for_la25_p. 7198 7199 If we jump to the temporary register rather than $25, the assembler 7200 can use the move insn to fill the jump's delay slot. */ 7201 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr)) 7202 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); 7203 mips_load_call_address (temp1, fnaddr, true); 7204 7205 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM) 7206 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1); 7207 emit_jump_insn (gen_indirect_jump (temp1)); 7208 } 7209 else 7210 { 7211 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx)); 7212 SIBLING_CALL_P (insn) = 1; 7213 } 7214 7215 /* Run just enough of rest_of_compilation. This sequence was 7216 "borrowed" from alpha.c. */ 7217 insn = get_insns (); 7218 insn_locators_initialize (); 7219 split_all_insns_noflow (); 7220 if (TARGET_MIPS16) 7221 mips16_lay_out_constants (); 7222 shorten_branches (insn); 7223 final_start_function (insn, file, 1); 7224 final (insn, file, 1); 7225 final_end_function (); 7226 7227 /* Clean up the vars set above. Note that final_end_function resets 7228 the global pointer for us. */ 7229 reload_completed = 0; 7230 no_new_pseudos = 0; 7231} 7232 7233/* Returns nonzero if X contains a SYMBOL_REF. */ 7234 7235static int 7236symbolic_expression_p (rtx x) 7237{ 7238 if (GET_CODE (x) == SYMBOL_REF) 7239 return 1; 7240 7241 if (GET_CODE (x) == CONST) 7242 return symbolic_expression_p (XEXP (x, 0)); 7243 7244 if (UNARY_P (x)) 7245 return symbolic_expression_p (XEXP (x, 0)); 7246 7247 if (ARITHMETIC_P (x)) 7248 return (symbolic_expression_p (XEXP (x, 0)) 7249 || symbolic_expression_p (XEXP (x, 1))); 7250 7251 return 0; 7252} 7253 7254/* Choose the section to use for the constant rtx expression X that has 7255 mode MODE. */ 7256 7257static section * 7258mips_select_rtx_section (enum machine_mode mode, rtx x, 7259 unsigned HOST_WIDE_INT align) 7260{ 7261 if (TARGET_MIPS16) 7262 { 7263 /* In mips16 mode, the constant table always goes in the same section 7264 as the function, so that constants can be loaded using PC relative 7265 addressing. */ 7266 return function_section (current_function_decl); 7267 } 7268 else if (TARGET_EMBEDDED_DATA) 7269 { 7270 /* For embedded applications, always put constants in read-only data, 7271 in order to reduce RAM usage. */ 7272 return mergeable_constant_section (mode, align, 0); 7273 } 7274 else 7275 { 7276 /* For hosted applications, always put constants in small data if 7277 possible, as this gives the best performance. */ 7278 /* ??? Consider using mergeable small data sections. */ 7279 7280 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold 7281 && mips_section_threshold > 0) 7282 return get_named_section (NULL, ".sdata", 0); 7283 else if (flag_pic && symbolic_expression_p (x)) 7284 return get_named_section (NULL, ".data.rel.ro", 3); 7285 else 7286 return mergeable_constant_section (mode, align, 0); 7287 } 7288} 7289 7290/* Implement TARGET_ASM_FUNCTION_RODATA_SECTION. 7291 7292 The complication here is that, with the combination TARGET_ABICALLS 7293 && !TARGET_GPWORD, jump tables will use absolute addresses, and should 7294 therefore not be included in the read-only part of a DSO. Handle such 7295 cases by selecting a normal data section instead of a read-only one. 7296 The logic apes that in default_function_rodata_section. */ 7297 7298static section * 7299mips_function_rodata_section (tree decl) 7300{ 7301 if (!TARGET_ABICALLS || TARGET_GPWORD) 7302 return default_function_rodata_section (decl); 7303 7304 if (decl && DECL_SECTION_NAME (decl)) 7305 { 7306 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); 7307 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0) 7308 { 7309 char *rname = ASTRDUP (name); 7310 rname[14] = 'd'; 7311 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl); 7312 } 7313 else if (flag_function_sections && flag_data_sections 7314 && strncmp (name, ".text.", 6) == 0) 7315 { 7316 char *rname = ASTRDUP (name); 7317 memcpy (rname + 1, "data", 4); 7318 return get_section (rname, SECTION_WRITE, decl); 7319 } 7320 } 7321 return data_section; 7322} 7323 7324/* Implement TARGET_IN_SMALL_DATA_P. This function controls whether 7325 locally-defined objects go in a small data section. It also controls 7326 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps 7327 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */ 7328 7329static bool 7330mips_in_small_data_p (tree decl) 7331{ 7332 HOST_WIDE_INT size; 7333 7334 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL) 7335 return false; 7336 7337 /* We don't yet generate small-data references for -mabicalls. See related 7338 -G handling in override_options. */ 7339 if (TARGET_ABICALLS) 7340 return false; 7341 7342 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0) 7343 { 7344 const char *name; 7345 7346 /* Reject anything that isn't in a known small-data section. */ 7347 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); 7348 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0) 7349 return false; 7350 7351 /* If a symbol is defined externally, the assembler will use the 7352 usual -G rules when deciding how to implement macros. */ 7353 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl)) 7354 return true; 7355 } 7356 else if (TARGET_EMBEDDED_DATA) 7357 { 7358 /* Don't put constants into the small data section: we want them 7359 to be in ROM rather than RAM. */ 7360 if (TREE_CODE (decl) != VAR_DECL) 7361 return false; 7362 7363 if (TREE_READONLY (decl) 7364 && !TREE_SIDE_EFFECTS (decl) 7365 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl)))) 7366 return false; 7367 } 7368 7369 size = int_size_in_bytes (TREE_TYPE (decl)); 7370 return (size > 0 && size <= mips_section_threshold); 7371} 7372 7373/* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use 7374 anchors for small data: the GP register acts as an anchor in that 7375 case. We also don't want to use them for PC-relative accesses, 7376 where the PC acts as an anchor. */ 7377 7378static bool 7379mips_use_anchors_for_symbol_p (rtx symbol) 7380{ 7381 switch (mips_classify_symbol (symbol)) 7382 { 7383 case SYMBOL_CONSTANT_POOL: 7384 case SYMBOL_SMALL_DATA: 7385 return false; 7386 7387 default: 7388 return true; 7389 } 7390} 7391 7392/* See whether VALTYPE is a record whose fields should be returned in 7393 floating-point registers. If so, return the number of fields and 7394 list them in FIELDS (which should have two elements). Return 0 7395 otherwise. 7396 7397 For n32 & n64, a structure with one or two fields is returned in 7398 floating-point registers as long as every field has a floating-point 7399 type. */ 7400 7401static int 7402mips_fpr_return_fields (tree valtype, tree *fields) 7403{ 7404 tree field; 7405 int i; 7406 7407 if (!TARGET_NEWABI) 7408 return 0; 7409 7410 if (TREE_CODE (valtype) != RECORD_TYPE) 7411 return 0; 7412 7413 i = 0; 7414 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field)) 7415 { 7416 if (TREE_CODE (field) != FIELD_DECL) 7417 continue; 7418 7419 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE) 7420 return 0; 7421 7422 if (i == 2) 7423 return 0; 7424 7425 fields[i++] = field; 7426 } 7427 return i; 7428} 7429 7430 7431/* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return 7432 a value in the most significant part of $2/$3 if: 7433 7434 - the target is big-endian; 7435 7436 - the value has a structure or union type (we generalize this to 7437 cover aggregates from other languages too); and 7438 7439 - the structure is not returned in floating-point registers. */ 7440 7441static bool 7442mips_return_in_msb (tree valtype) 7443{ 7444 tree fields[2]; 7445 7446 return (TARGET_NEWABI 7447 && TARGET_BIG_ENDIAN 7448 && AGGREGATE_TYPE_P (valtype) 7449 && mips_fpr_return_fields (valtype, fields) == 0); 7450} 7451 7452 7453/* Return a composite value in a pair of floating-point registers. 7454 MODE1 and OFFSET1 are the mode and byte offset for the first value, 7455 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the 7456 complete value. 7457 7458 For n32 & n64, $f0 always holds the first value and $f2 the second. 7459 Otherwise the values are packed together as closely as possible. */ 7460 7461static rtx 7462mips_return_fpr_pair (enum machine_mode mode, 7463 enum machine_mode mode1, HOST_WIDE_INT offset1, 7464 enum machine_mode mode2, HOST_WIDE_INT offset2) 7465{ 7466 int inc; 7467 7468 inc = (TARGET_NEWABI ? 2 : FP_INC); 7469 return gen_rtx_PARALLEL 7470 (mode, 7471 gen_rtvec (2, 7472 gen_rtx_EXPR_LIST (VOIDmode, 7473 gen_rtx_REG (mode1, FP_RETURN), 7474 GEN_INT (offset1)), 7475 gen_rtx_EXPR_LIST (VOIDmode, 7476 gen_rtx_REG (mode2, FP_RETURN + inc), 7477 GEN_INT (offset2)))); 7478 7479} 7480 7481 7482/* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls, 7483 VALTYPE is the return type and MODE is VOIDmode. For libcalls, 7484 VALTYPE is null and MODE is the mode of the return value. */ 7485 7486rtx 7487mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED, 7488 enum machine_mode mode) 7489{ 7490 if (valtype) 7491 { 7492 tree fields[2]; 7493 int unsignedp; 7494 7495 mode = TYPE_MODE (valtype); 7496 unsignedp = TYPE_UNSIGNED (valtype); 7497 7498 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns 7499 true, we must promote the mode just as PROMOTE_MODE does. */ 7500 mode = promote_mode (valtype, mode, &unsignedp, 1); 7501 7502 /* Handle structures whose fields are returned in $f0/$f2. */ 7503 switch (mips_fpr_return_fields (valtype, fields)) 7504 { 7505 case 1: 7506 return gen_rtx_REG (mode, FP_RETURN); 7507 7508 case 2: 7509 return mips_return_fpr_pair (mode, 7510 TYPE_MODE (TREE_TYPE (fields[0])), 7511 int_byte_position (fields[0]), 7512 TYPE_MODE (TREE_TYPE (fields[1])), 7513 int_byte_position (fields[1])); 7514 } 7515 7516 /* If a value is passed in the most significant part of a register, see 7517 whether we have to round the mode up to a whole number of words. */ 7518 if (mips_return_in_msb (valtype)) 7519 { 7520 HOST_WIDE_INT size = int_size_in_bytes (valtype); 7521 if (size % UNITS_PER_WORD != 0) 7522 { 7523 size += UNITS_PER_WORD - size % UNITS_PER_WORD; 7524 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); 7525 } 7526 } 7527 7528 /* For EABI, the class of return register depends entirely on MODE. 7529 For example, "struct { some_type x; }" and "union { some_type x; }" 7530 are returned in the same way as a bare "some_type" would be. 7531 Other ABIs only use FPRs for scalar, complex or vector types. */ 7532 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype)) 7533 return gen_rtx_REG (mode, GP_RETURN); 7534 } 7535 7536 if ((GET_MODE_CLASS (mode) == MODE_FLOAT 7537 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) 7538 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE) 7539 return gen_rtx_REG (mode, FP_RETURN); 7540 7541 /* Handle long doubles for n32 & n64. */ 7542 if (mode == TFmode) 7543 return mips_return_fpr_pair (mode, 7544 DImode, 0, 7545 DImode, GET_MODE_SIZE (mode) / 2); 7546 7547 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT 7548 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2) 7549 return mips_return_fpr_pair (mode, 7550 GET_MODE_INNER (mode), 0, 7551 GET_MODE_INNER (mode), 7552 GET_MODE_SIZE (mode) / 2); 7553 7554 return gen_rtx_REG (mode, GP_RETURN); 7555} 7556 7557/* Return nonzero when an argument must be passed by reference. */ 7558 7559static bool 7560mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, 7561 enum machine_mode mode, tree type, 7562 bool named ATTRIBUTE_UNUSED) 7563{ 7564 if (mips_abi == ABI_EABI) 7565 { 7566 int size; 7567 7568 /* ??? How should SCmode be handled? */ 7569 if (mode == DImode || mode == DFmode) 7570 return 0; 7571 7572 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); 7573 return size == -1 || size > UNITS_PER_WORD; 7574 } 7575 else 7576 { 7577 /* If we have a variable-sized parameter, we have no choice. */ 7578 return targetm.calls.must_pass_in_stack (mode, type); 7579 } 7580} 7581 7582static bool 7583mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, 7584 enum machine_mode mode ATTRIBUTE_UNUSED, 7585 tree type ATTRIBUTE_UNUSED, bool named) 7586{ 7587 return mips_abi == ABI_EABI && named; 7588} 7589 7590/* Return true if registers of class CLASS cannot change from mode FROM 7591 to mode TO. */ 7592 7593bool 7594mips_cannot_change_mode_class (enum machine_mode from, 7595 enum machine_mode to, enum reg_class class) 7596{ 7597 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD 7598 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD) 7599 { 7600 if (TARGET_BIG_ENDIAN) 7601 { 7602 /* When a multi-word value is stored in paired floating-point 7603 registers, the first register always holds the low word. 7604 We therefore can't allow FPRs to change between single-word 7605 and multi-word modes. */ 7606 if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class)) 7607 return true; 7608 } 7609 else 7610 { 7611 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored 7612 in LO and HI, the high word always comes first. We therefore 7613 can't allow values stored in HI to change between single-word 7614 and multi-word modes. 7615 This rule applies to both the original HI/LO pair and the new 7616 DSP accumulators. */ 7617 if (reg_classes_intersect_p (ACC_REGS, class)) 7618 return true; 7619 } 7620 } 7621 /* Loading a 32-bit value into a 64-bit floating-point register 7622 will not sign-extend the value, despite what LOAD_EXTEND_OP says. 7623 We can't allow 64-bit float registers to change from SImode to 7624 to a wider mode. */ 7625 if (TARGET_FLOAT64 7626 && from == SImode 7627 && GET_MODE_SIZE (to) >= UNITS_PER_WORD 7628 && reg_classes_intersect_p (FP_REGS, class)) 7629 return true; 7630 return false; 7631} 7632 7633/* Return true if X should not be moved directly into register $25. 7634 We need this because many versions of GAS will treat "la $25,foo" as 7635 part of a call sequence and so allow a global "foo" to be lazily bound. */ 7636 7637bool 7638mips_dangerous_for_la25_p (rtx x) 7639{ 7640 HOST_WIDE_INT offset; 7641 7642 if (TARGET_EXPLICIT_RELOCS) 7643 return false; 7644 7645 mips_split_const (x, &x, &offset); 7646 return global_got_operand (x, VOIDmode); 7647} 7648 7649/* Implement PREFERRED_RELOAD_CLASS. */ 7650 7651enum reg_class 7652mips_preferred_reload_class (rtx x, enum reg_class class) 7653{ 7654 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class)) 7655 return LEA_REGS; 7656 7657 if (TARGET_HARD_FLOAT 7658 && FLOAT_MODE_P (GET_MODE (x)) 7659 && reg_class_subset_p (FP_REGS, class)) 7660 return FP_REGS; 7661 7662 if (reg_class_subset_p (GR_REGS, class)) 7663 class = GR_REGS; 7664 7665 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class)) 7666 class = M16_REGS; 7667 7668 return class; 7669} 7670 7671/* This function returns the register class required for a secondary 7672 register when copying between one of the registers in CLASS, and X, 7673 using MODE. If IN_P is nonzero, the copy is going from X to the 7674 register, otherwise the register is the source. A return value of 7675 NO_REGS means that no secondary register is required. */ 7676 7677enum reg_class 7678mips_secondary_reload_class (enum reg_class class, 7679 enum machine_mode mode, rtx x, int in_p) 7680{ 7681 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS; 7682 int regno = -1; 7683 int gp_reg_p; 7684 7685 if (REG_P (x)|| GET_CODE (x) == SUBREG) 7686 regno = true_regnum (x); 7687 7688 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno); 7689 7690 if (mips_dangerous_for_la25_p (x)) 7691 { 7692 gr_regs = LEA_REGS; 7693 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25)) 7694 return gr_regs; 7695 } 7696 7697 /* Copying from HI or LO to anywhere other than a general register 7698 requires a general register. 7699 This rule applies to both the original HI/LO pair and the new 7700 DSP accumulators. */ 7701 if (reg_class_subset_p (class, ACC_REGS)) 7702 { 7703 if (TARGET_MIPS16 && in_p) 7704 { 7705 /* We can't really copy to HI or LO at all in mips16 mode. */ 7706 return M16_REGS; 7707 } 7708 return gp_reg_p ? NO_REGS : gr_regs; 7709 } 7710 if (ACC_REG_P (regno)) 7711 { 7712 if (TARGET_MIPS16 && ! in_p) 7713 { 7714 /* We can't really copy to HI or LO at all in mips16 mode. */ 7715 return M16_REGS; 7716 } 7717 return class == gr_regs ? NO_REGS : gr_regs; 7718 } 7719 7720 /* We can only copy a value to a condition code register from a 7721 floating point register, and even then we require a scratch 7722 floating point register. We can only copy a value out of a 7723 condition code register into a general register. */ 7724 if (class == ST_REGS) 7725 { 7726 if (in_p) 7727 return FP_REGS; 7728 return gp_reg_p ? NO_REGS : gr_regs; 7729 } 7730 if (ST_REG_P (regno)) 7731 { 7732 if (! in_p) 7733 return FP_REGS; 7734 return class == gr_regs ? NO_REGS : gr_regs; 7735 } 7736 7737 if (class == FP_REGS) 7738 { 7739 if (MEM_P (x)) 7740 { 7741 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */ 7742 return NO_REGS; 7743 } 7744 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT) 7745 { 7746 /* We can use the l.s and l.d macros to load floating-point 7747 constants. ??? For l.s, we could probably get better 7748 code by returning GR_REGS here. */ 7749 return NO_REGS; 7750 } 7751 else if (gp_reg_p || x == CONST0_RTX (mode)) 7752 { 7753 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */ 7754 return NO_REGS; 7755 } 7756 else if (FP_REG_P (regno)) 7757 { 7758 /* In this case we can use mov.s or mov.d. */ 7759 return NO_REGS; 7760 } 7761 else 7762 { 7763 /* Otherwise, we need to reload through an integer register. */ 7764 return gr_regs; 7765 } 7766 } 7767 7768 /* In mips16 mode, going between memory and anything but M16_REGS 7769 requires an M16_REG. */ 7770 if (TARGET_MIPS16) 7771 { 7772 if (class != M16_REGS && class != M16_NA_REGS) 7773 { 7774 if (gp_reg_p) 7775 return NO_REGS; 7776 return M16_REGS; 7777 } 7778 if (! gp_reg_p) 7779 { 7780 if (class == M16_REGS || class == M16_NA_REGS) 7781 return NO_REGS; 7782 return M16_REGS; 7783 } 7784 } 7785 7786 return NO_REGS; 7787} 7788 7789/* Implement CLASS_MAX_NREGS. 7790 7791 Usually all registers are word-sized. The only supported exception 7792 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float 7793 registers. A word-based calculation is correct even in that case, 7794 since -msingle-float disallows multi-FPR values. 7795 7796 The FP status registers are an exception to this rule. They are always 7797 4 bytes wide as they only hold condition code modes, and CCmode is always 7798 considered to be 4 bytes wide. */ 7799 7800int 7801mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED, 7802 enum machine_mode mode) 7803{ 7804 if (class == ST_REGS) 7805 return (GET_MODE_SIZE (mode) + 3) / 4; 7806 else 7807 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 7808} 7809 7810static bool 7811mips_valid_pointer_mode (enum machine_mode mode) 7812{ 7813 return (mode == SImode || (TARGET_64BIT && mode == DImode)); 7814} 7815 7816/* Target hook for vector_mode_supported_p. */ 7817 7818static bool 7819mips_vector_mode_supported_p (enum machine_mode mode) 7820{ 7821 switch (mode) 7822 { 7823 case V2SFmode: 7824 return TARGET_PAIRED_SINGLE_FLOAT; 7825 7826 case V2HImode: 7827 case V4QImode: 7828 return TARGET_DSP; 7829 7830 default: 7831 return false; 7832 } 7833} 7834 7835/* If we can access small data directly (using gp-relative relocation 7836 operators) return the small data pointer, otherwise return null. 7837 7838 For each mips16 function which refers to GP relative symbols, we 7839 use a pseudo register, initialized at the start of the function, to 7840 hold the $gp value. */ 7841 7842static rtx 7843mips16_gp_pseudo_reg (void) 7844{ 7845 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX) 7846 { 7847 rtx unspec; 7848 rtx insn, scan; 7849 7850 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode); 7851 7852 /* We want to initialize this to a value which gcc will believe 7853 is constant. */ 7854 start_sequence (); 7855 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP); 7856 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx, 7857 gen_rtx_CONST (Pmode, unspec)); 7858 insn = get_insns (); 7859 end_sequence (); 7860 7861 push_topmost_sequence (); 7862 /* We need to emit the initialization after the FUNCTION_BEG 7863 note, so that it will be integrated. */ 7864 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan)) 7865 if (NOTE_P (scan) 7866 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG) 7867 break; 7868 if (scan == NULL_RTX) 7869 scan = get_insns (); 7870 insn = emit_insn_after (insn, scan); 7871 pop_topmost_sequence (); 7872 } 7873 7874 return cfun->machine->mips16_gp_pseudo_rtx; 7875} 7876 7877/* Write out code to move floating point arguments in or out of 7878 general registers. Output the instructions to FILE. FP_CODE is 7879 the code describing which arguments are present (see the comment at 7880 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if 7881 we are copying from the floating point registers. */ 7882 7883static void 7884mips16_fp_args (FILE *file, int fp_code, int from_fp_p) 7885{ 7886 const char *s; 7887 int gparg, fparg; 7888 unsigned int f; 7889 7890 /* This code only works for the original 32 bit ABI and the O64 ABI. */ 7891 gcc_assert (TARGET_OLDABI); 7892 7893 if (from_fp_p) 7894 s = "mfc1"; 7895 else 7896 s = "mtc1"; 7897 gparg = GP_ARG_FIRST; 7898 fparg = FP_ARG_FIRST; 7899 for (f = (unsigned int) fp_code; f != 0; f >>= 2) 7900 { 7901 if ((f & 3) == 1) 7902 { 7903 if ((fparg & 1) != 0) 7904 ++fparg; 7905 fprintf (file, "\t%s\t%s,%s\n", s, 7906 reg_names[gparg], reg_names[fparg]); 7907 } 7908 else if ((f & 3) == 2) 7909 { 7910 if (TARGET_64BIT) 7911 fprintf (file, "\td%s\t%s,%s\n", s, 7912 reg_names[gparg], reg_names[fparg]); 7913 else 7914 { 7915 if ((fparg & 1) != 0) 7916 ++fparg; 7917 if (TARGET_BIG_ENDIAN) 7918 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s, 7919 reg_names[gparg], reg_names[fparg + 1], s, 7920 reg_names[gparg + 1], reg_names[fparg]); 7921 else 7922 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s, 7923 reg_names[gparg], reg_names[fparg], s, 7924 reg_names[gparg + 1], reg_names[fparg + 1]); 7925 ++gparg; 7926 ++fparg; 7927 } 7928 } 7929 else 7930 gcc_unreachable (); 7931 7932 ++gparg; 7933 ++fparg; 7934 } 7935} 7936 7937/* Build a mips16 function stub. This is used for functions which 7938 take arguments in the floating point registers. It is 32 bit code 7939 that moves the floating point args into the general registers, and 7940 then jumps to the 16 bit code. */ 7941 7942static void 7943build_mips16_function_stub (FILE *file) 7944{ 7945 const char *fnname; 7946 char *secname, *stubname; 7947 tree stubid, stubdecl; 7948 int need_comma; 7949 unsigned int f; 7950 7951 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); 7952 secname = (char *) alloca (strlen (fnname) + 20); 7953 sprintf (secname, ".mips16.fn.%s", fnname); 7954 stubname = (char *) alloca (strlen (fnname) + 20); 7955 sprintf (stubname, "__fn_stub_%s", fnname); 7956 stubid = get_identifier (stubname); 7957 stubdecl = build_decl (FUNCTION_DECL, stubid, 7958 build_function_type (void_type_node, NULL_TREE)); 7959 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname); 7960 7961 fprintf (file, "\t# Stub function for %s (", current_function_name ()); 7962 need_comma = 0; 7963 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2) 7964 { 7965 fprintf (file, "%s%s", 7966 need_comma ? ", " : "", 7967 (f & 3) == 1 ? "float" : "double"); 7968 need_comma = 1; 7969 } 7970 fprintf (file, ")\n"); 7971 7972 fprintf (file, "\t.set\tnomips16\n"); 7973 switch_to_section (function_section (stubdecl)); 7974 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT)); 7975 7976 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are 7977 within a .ent, and we cannot emit another .ent. */ 7978 if (!FUNCTION_NAME_ALREADY_DECLARED) 7979 { 7980 fputs ("\t.ent\t", file); 7981 assemble_name (file, stubname); 7982 fputs ("\n", file); 7983 } 7984 7985 assemble_name (file, stubname); 7986 fputs (":\n", file); 7987 7988 /* We don't want the assembler to insert any nops here. */ 7989 fprintf (file, "\t.set\tnoreorder\n"); 7990 7991 mips16_fp_args (file, current_function_args_info.fp_code, 1); 7992 7993 fprintf (asm_out_file, "\t.set\tnoat\n"); 7994 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]); 7995 assemble_name (file, fnname); 7996 fprintf (file, "\n"); 7997 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]); 7998 fprintf (asm_out_file, "\t.set\tat\n"); 7999 8000 /* Unfortunately, we can't fill the jump delay slot. We can't fill 8001 with one of the mfc1 instructions, because the result is not 8002 available for one instruction, so if the very first instruction 8003 in the function refers to the register, it will see the wrong 8004 value. */ 8005 fprintf (file, "\tnop\n"); 8006 8007 fprintf (file, "\t.set\treorder\n"); 8008 8009 if (!FUNCTION_NAME_ALREADY_DECLARED) 8010 { 8011 fputs ("\t.end\t", file); 8012 assemble_name (file, stubname); 8013 fputs ("\n", file); 8014 } 8015 8016 fprintf (file, "\t.set\tmips16\n"); 8017 8018 switch_to_section (function_section (current_function_decl)); 8019} 8020 8021/* We keep a list of functions for which we have already built stubs 8022 in build_mips16_call_stub. */ 8023 8024struct mips16_stub 8025{ 8026 struct mips16_stub *next; 8027 char *name; 8028 int fpret; 8029}; 8030 8031static struct mips16_stub *mips16_stubs; 8032 8033/* Build a call stub for a mips16 call. A stub is needed if we are 8034 passing any floating point values which should go into the floating 8035 point registers. If we are, and the call turns out to be to a 32 8036 bit function, the stub will be used to move the values into the 8037 floating point registers before calling the 32 bit function. The 8038 linker will magically adjust the function call to either the 16 bit 8039 function or the 32 bit stub, depending upon where the function call 8040 is actually defined. 8041 8042 Similarly, we need a stub if the return value might come back in a 8043 floating point register. 8044 8045 RETVAL is the location of the return value, or null if this is 8046 a call rather than a call_value. FN is the address of the 8047 function and ARG_SIZE is the size of the arguments. FP_CODE 8048 is the code built by function_arg. This function returns a nonzero 8049 value if it builds the call instruction itself. */ 8050 8051int 8052build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code) 8053{ 8054 int fpret; 8055 const char *fnname; 8056 char *secname, *stubname; 8057 struct mips16_stub *l; 8058 tree stubid, stubdecl; 8059 int need_comma; 8060 unsigned int f; 8061 8062 /* We don't need to do anything if we aren't in mips16 mode, or if 8063 we were invoked with the -msoft-float option. */ 8064 if (! TARGET_MIPS16 || ! mips16_hard_float) 8065 return 0; 8066 8067 /* Figure out whether the value might come back in a floating point 8068 register. */ 8069 fpret = (retval != 0 8070 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT 8071 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE); 8072 8073 /* We don't need to do anything if there were no floating point 8074 arguments and the value will not be returned in a floating point 8075 register. */ 8076 if (fp_code == 0 && ! fpret) 8077 return 0; 8078 8079 /* We don't need to do anything if this is a call to a special 8080 mips16 support function. */ 8081 if (GET_CODE (fn) == SYMBOL_REF 8082 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0) 8083 return 0; 8084 8085 /* This code will only work for o32 and o64 abis. The other ABI's 8086 require more sophisticated support. */ 8087 gcc_assert (TARGET_OLDABI); 8088 8089 /* We can only handle SFmode and DFmode floating point return 8090 values. */ 8091 if (fpret) 8092 gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode); 8093 8094 /* If we're calling via a function pointer, then we must always call 8095 via a stub. There are magic stubs provided in libgcc.a for each 8096 of the required cases. Each of them expects the function address 8097 to arrive in register $2. */ 8098 8099 if (GET_CODE (fn) != SYMBOL_REF) 8100 { 8101 char buf[30]; 8102 tree id; 8103 rtx stub_fn, insn; 8104 8105 /* ??? If this code is modified to support other ABI's, we need 8106 to handle PARALLEL return values here. */ 8107 8108 sprintf (buf, "__mips16_call_stub_%s%d", 8109 (fpret 8110 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_") 8111 : ""), 8112 fp_code); 8113 id = get_identifier (buf); 8114 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id)); 8115 8116 emit_move_insn (gen_rtx_REG (Pmode, 2), fn); 8117 8118 if (retval == NULL_RTX) 8119 insn = gen_call_internal (stub_fn, arg_size); 8120 else 8121 insn = gen_call_value_internal (retval, stub_fn, arg_size); 8122 insn = emit_call_insn (insn); 8123 8124 /* Put the register usage information on the CALL. */ 8125 CALL_INSN_FUNCTION_USAGE (insn) = 8126 gen_rtx_EXPR_LIST (VOIDmode, 8127 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)), 8128 CALL_INSN_FUNCTION_USAGE (insn)); 8129 8130 /* If we are handling a floating point return value, we need to 8131 save $18 in the function prologue. Putting a note on the 8132 call will mean that regs_ever_live[$18] will be true if the 8133 call is not eliminated, and we can check that in the prologue 8134 code. */ 8135 if (fpret) 8136 CALL_INSN_FUNCTION_USAGE (insn) = 8137 gen_rtx_EXPR_LIST (VOIDmode, 8138 gen_rtx_USE (VOIDmode, 8139 gen_rtx_REG (word_mode, 18)), 8140 CALL_INSN_FUNCTION_USAGE (insn)); 8141 8142 /* Return 1 to tell the caller that we've generated the call 8143 insn. */ 8144 return 1; 8145 } 8146 8147 /* We know the function we are going to call. If we have already 8148 built a stub, we don't need to do anything further. */ 8149 8150 fnname = XSTR (fn, 0); 8151 for (l = mips16_stubs; l != NULL; l = l->next) 8152 if (strcmp (l->name, fnname) == 0) 8153 break; 8154 8155 if (l == NULL) 8156 { 8157 /* Build a special purpose stub. When the linker sees a 8158 function call in mips16 code, it will check where the target 8159 is defined. If the target is a 32 bit call, the linker will 8160 search for the section defined here. It can tell which 8161 symbol this section is associated with by looking at the 8162 relocation information (the name is unreliable, since this 8163 might be a static function). If such a section is found, the 8164 linker will redirect the call to the start of the magic 8165 section. 8166 8167 If the function does not return a floating point value, the 8168 special stub section is named 8169 .mips16.call.FNNAME 8170 8171 If the function does return a floating point value, the stub 8172 section is named 8173 .mips16.call.fp.FNNAME 8174 */ 8175 8176 secname = (char *) alloca (strlen (fnname) + 40); 8177 sprintf (secname, ".mips16.call.%s%s", 8178 fpret ? "fp." : "", 8179 fnname); 8180 stubname = (char *) alloca (strlen (fnname) + 20); 8181 sprintf (stubname, "__call_stub_%s%s", 8182 fpret ? "fp_" : "", 8183 fnname); 8184 stubid = get_identifier (stubname); 8185 stubdecl = build_decl (FUNCTION_DECL, stubid, 8186 build_function_type (void_type_node, NULL_TREE)); 8187 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname); 8188 8189 fprintf (asm_out_file, "\t# Stub function to call %s%s (", 8190 (fpret 8191 ? (GET_MODE (retval) == SFmode ? "float " : "double ") 8192 : ""), 8193 fnname); 8194 need_comma = 0; 8195 for (f = (unsigned int) fp_code; f != 0; f >>= 2) 8196 { 8197 fprintf (asm_out_file, "%s%s", 8198 need_comma ? ", " : "", 8199 (f & 3) == 1 ? "float" : "double"); 8200 need_comma = 1; 8201 } 8202 fprintf (asm_out_file, ")\n"); 8203 8204 fprintf (asm_out_file, "\t.set\tnomips16\n"); 8205 assemble_start_function (stubdecl, stubname); 8206 8207 if (!FUNCTION_NAME_ALREADY_DECLARED) 8208 { 8209 fputs ("\t.ent\t", asm_out_file); 8210 assemble_name (asm_out_file, stubname); 8211 fputs ("\n", asm_out_file); 8212 8213 assemble_name (asm_out_file, stubname); 8214 fputs (":\n", asm_out_file); 8215 } 8216 8217 /* We build the stub code by hand. That's the only way we can 8218 do it, since we can't generate 32 bit code during a 16 bit 8219 compilation. */ 8220 8221 /* We don't want the assembler to insert any nops here. */ 8222 fprintf (asm_out_file, "\t.set\tnoreorder\n"); 8223 8224 mips16_fp_args (asm_out_file, fp_code, 0); 8225 8226 if (! fpret) 8227 { 8228 fprintf (asm_out_file, "\t.set\tnoat\n"); 8229 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1], 8230 fnname); 8231 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]); 8232 fprintf (asm_out_file, "\t.set\tat\n"); 8233 /* Unfortunately, we can't fill the jump delay slot. We 8234 can't fill with one of the mtc1 instructions, because the 8235 result is not available for one instruction, so if the 8236 very first instruction in the function refers to the 8237 register, it will see the wrong value. */ 8238 fprintf (asm_out_file, "\tnop\n"); 8239 } 8240 else 8241 { 8242 fprintf (asm_out_file, "\tmove\t%s,%s\n", 8243 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]); 8244 fprintf (asm_out_file, "\tjal\t%s\n", fnname); 8245 /* As above, we can't fill the delay slot. */ 8246 fprintf (asm_out_file, "\tnop\n"); 8247 if (GET_MODE (retval) == SFmode) 8248 fprintf (asm_out_file, "\tmfc1\t%s,%s\n", 8249 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]); 8250 else 8251 { 8252 if (TARGET_BIG_ENDIAN) 8253 { 8254 fprintf (asm_out_file, "\tmfc1\t%s,%s\n", 8255 reg_names[GP_REG_FIRST + 2], 8256 reg_names[FP_REG_FIRST + 1]); 8257 fprintf (asm_out_file, "\tmfc1\t%s,%s\n", 8258 reg_names[GP_REG_FIRST + 3], 8259 reg_names[FP_REG_FIRST + 0]); 8260 } 8261 else 8262 { 8263 fprintf (asm_out_file, "\tmfc1\t%s,%s\n", 8264 reg_names[GP_REG_FIRST + 2], 8265 reg_names[FP_REG_FIRST + 0]); 8266 fprintf (asm_out_file, "\tmfc1\t%s,%s\n", 8267 reg_names[GP_REG_FIRST + 3], 8268 reg_names[FP_REG_FIRST + 1]); 8269 } 8270 } 8271 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]); 8272 /* As above, we can't fill the delay slot. */ 8273 fprintf (asm_out_file, "\tnop\n"); 8274 } 8275 8276 fprintf (asm_out_file, "\t.set\treorder\n"); 8277 8278#ifdef ASM_DECLARE_FUNCTION_SIZE 8279 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl); 8280#endif 8281 8282 if (!FUNCTION_NAME_ALREADY_DECLARED) 8283 { 8284 fputs ("\t.end\t", asm_out_file); 8285 assemble_name (asm_out_file, stubname); 8286 fputs ("\n", asm_out_file); 8287 } 8288 8289 fprintf (asm_out_file, "\t.set\tmips16\n"); 8290 8291 /* Record this stub. */ 8292 l = (struct mips16_stub *) xmalloc (sizeof *l); 8293 l->name = xstrdup (fnname); 8294 l->fpret = fpret; 8295 l->next = mips16_stubs; 8296 mips16_stubs = l; 8297 } 8298 8299 /* If we expect a floating point return value, but we've built a 8300 stub which does not expect one, then we're in trouble. We can't 8301 use the existing stub, because it won't handle the floating point 8302 value. We can't build a new stub, because the linker won't know 8303 which stub to use for the various calls in this object file. 8304 Fortunately, this case is illegal, since it means that a function 8305 was declared in two different ways in a single compilation. */ 8306 if (fpret && ! l->fpret) 8307 error ("cannot handle inconsistent calls to %qs", fnname); 8308 8309 /* If we are calling a stub which handles a floating point return 8310 value, we need to arrange to save $18 in the prologue. We do 8311 this by marking the function call as using the register. The 8312 prologue will later see that it is used, and emit code to save 8313 it. */ 8314 8315 if (l->fpret) 8316 { 8317 rtx insn; 8318 8319 if (retval == NULL_RTX) 8320 insn = gen_call_internal (fn, arg_size); 8321 else 8322 insn = gen_call_value_internal (retval, fn, arg_size); 8323 insn = emit_call_insn (insn); 8324 8325 CALL_INSN_FUNCTION_USAGE (insn) = 8326 gen_rtx_EXPR_LIST (VOIDmode, 8327 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)), 8328 CALL_INSN_FUNCTION_USAGE (insn)); 8329 8330 /* Return 1 to tell the caller that we've generated the call 8331 insn. */ 8332 return 1; 8333 } 8334 8335 /* Return 0 to let the caller generate the call insn. */ 8336 return 0; 8337} 8338 8339/* An entry in the mips16 constant pool. VALUE is the pool constant, 8340 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */ 8341 8342struct mips16_constant { 8343 struct mips16_constant *next; 8344 rtx value; 8345 rtx label; 8346 enum machine_mode mode; 8347}; 8348 8349/* Information about an incomplete mips16 constant pool. FIRST is the 8350 first constant, HIGHEST_ADDRESS is the highest address that the first 8351 byte of the pool can have, and INSN_ADDRESS is the current instruction 8352 address. */ 8353 8354struct mips16_constant_pool { 8355 struct mips16_constant *first; 8356 int highest_address; 8357 int insn_address; 8358}; 8359 8360/* Add constant VALUE to POOL and return its label. MODE is the 8361 value's mode (used for CONST_INTs, etc.). */ 8362 8363static rtx 8364add_constant (struct mips16_constant_pool *pool, 8365 rtx value, enum machine_mode mode) 8366{ 8367 struct mips16_constant **p, *c; 8368 bool first_of_size_p; 8369 8370 /* See whether the constant is already in the pool. If so, return the 8371 existing label, otherwise leave P pointing to the place where the 8372 constant should be added. 8373 8374 Keep the pool sorted in increasing order of mode size so that we can 8375 reduce the number of alignments needed. */ 8376 first_of_size_p = true; 8377 for (p = &pool->first; *p != 0; p = &(*p)->next) 8378 { 8379 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value)) 8380 return (*p)->label; 8381 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode)) 8382 break; 8383 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode)) 8384 first_of_size_p = false; 8385 } 8386 8387 /* In the worst case, the constant needed by the earliest instruction 8388 will end up at the end of the pool. The entire pool must then be 8389 accessible from that instruction. 8390 8391 When adding the first constant, set the pool's highest address to 8392 the address of the first out-of-range byte. Adjust this address 8393 downwards each time a new constant is added. */ 8394 if (pool->first == 0) 8395 /* For pc-relative lw, addiu and daddiu instructions, the base PC value 8396 is the address of the instruction with the lowest two bits clear. 8397 The base PC value for ld has the lowest three bits clear. Assume 8398 the worst case here. */ 8399 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000; 8400 pool->highest_address -= GET_MODE_SIZE (mode); 8401 if (first_of_size_p) 8402 /* Take into account the worst possible padding due to alignment. */ 8403 pool->highest_address -= GET_MODE_SIZE (mode) - 1; 8404 8405 /* Create a new entry. */ 8406 c = (struct mips16_constant *) xmalloc (sizeof *c); 8407 c->value = value; 8408 c->mode = mode; 8409 c->label = gen_label_rtx (); 8410 c->next = *p; 8411 *p = c; 8412 8413 return c->label; 8414} 8415 8416/* Output constant VALUE after instruction INSN and return the last 8417 instruction emitted. MODE is the mode of the constant. */ 8418 8419static rtx 8420dump_constants_1 (enum machine_mode mode, rtx value, rtx insn) 8421{ 8422 switch (GET_MODE_CLASS (mode)) 8423 { 8424 case MODE_INT: 8425 { 8426 rtx size = GEN_INT (GET_MODE_SIZE (mode)); 8427 return emit_insn_after (gen_consttable_int (value, size), insn); 8428 } 8429 8430 case MODE_FLOAT: 8431 return emit_insn_after (gen_consttable_float (value), insn); 8432 8433 case MODE_VECTOR_FLOAT: 8434 case MODE_VECTOR_INT: 8435 { 8436 int i; 8437 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++) 8438 insn = dump_constants_1 (GET_MODE_INNER (mode), 8439 CONST_VECTOR_ELT (value, i), insn); 8440 return insn; 8441 } 8442 8443 default: 8444 gcc_unreachable (); 8445 } 8446} 8447 8448 8449/* Dump out the constants in CONSTANTS after INSN. */ 8450 8451static void 8452dump_constants (struct mips16_constant *constants, rtx insn) 8453{ 8454 struct mips16_constant *c, *next; 8455 int align; 8456 8457 align = 0; 8458 for (c = constants; c != NULL; c = next) 8459 { 8460 /* If necessary, increase the alignment of PC. */ 8461 if (align < GET_MODE_SIZE (c->mode)) 8462 { 8463 int align_log = floor_log2 (GET_MODE_SIZE (c->mode)); 8464 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn); 8465 } 8466 align = GET_MODE_SIZE (c->mode); 8467 8468 insn = emit_label_after (c->label, insn); 8469 insn = dump_constants_1 (c->mode, c->value, insn); 8470 8471 next = c->next; 8472 free (c); 8473 } 8474 8475 emit_barrier_after (insn); 8476} 8477 8478/* Return the length of instruction INSN. */ 8479 8480static int 8481mips16_insn_length (rtx insn) 8482{ 8483 if (JUMP_P (insn)) 8484 { 8485 rtx body = PATTERN (insn); 8486 if (GET_CODE (body) == ADDR_VEC) 8487 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0); 8488 if (GET_CODE (body) == ADDR_DIFF_VEC) 8489 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1); 8490 } 8491 return get_attr_length (insn); 8492} 8493 8494/* Rewrite *X so that constant pool references refer to the constant's 8495 label instead. DATA points to the constant pool structure. */ 8496 8497static int 8498mips16_rewrite_pool_refs (rtx *x, void *data) 8499{ 8500 struct mips16_constant_pool *pool = data; 8501 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x)) 8502 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool, 8503 get_pool_constant (*x), 8504 get_pool_mode (*x))); 8505 return 0; 8506} 8507 8508/* Build MIPS16 constant pools. */ 8509 8510static void 8511mips16_lay_out_constants (void) 8512{ 8513 struct mips16_constant_pool pool; 8514 rtx insn, barrier; 8515 8516 barrier = 0; 8517 memset (&pool, 0, sizeof (pool)); 8518 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 8519 { 8520 /* Rewrite constant pool references in INSN. */ 8521 if (INSN_P (insn)) 8522 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool); 8523 8524 pool.insn_address += mips16_insn_length (insn); 8525 8526 if (pool.first != NULL) 8527 { 8528 /* If there are no natural barriers between the first user of 8529 the pool and the highest acceptable address, we'll need to 8530 create a new instruction to jump around the constant pool. 8531 In the worst case, this instruction will be 4 bytes long. 8532 8533 If it's too late to do this transformation after INSN, 8534 do it immediately before INSN. */ 8535 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address) 8536 { 8537 rtx label, jump; 8538 8539 label = gen_label_rtx (); 8540 8541 jump = emit_jump_insn_before (gen_jump (label), insn); 8542 JUMP_LABEL (jump) = label; 8543 LABEL_NUSES (label) = 1; 8544 barrier = emit_barrier_after (jump); 8545 8546 emit_label_after (label, barrier); 8547 pool.insn_address += 4; 8548 } 8549 8550 /* See whether the constant pool is now out of range of the first 8551 user. If so, output the constants after the previous barrier. 8552 Note that any instructions between BARRIER and INSN (inclusive) 8553 will use negative offsets to refer to the pool. */ 8554 if (pool.insn_address > pool.highest_address) 8555 { 8556 dump_constants (pool.first, barrier); 8557 pool.first = NULL; 8558 barrier = 0; 8559 } 8560 else if (BARRIER_P (insn)) 8561 barrier = insn; 8562 } 8563 } 8564 dump_constants (pool.first, get_last_insn ()); 8565} 8566 8567/* A temporary variable used by for_each_rtx callbacks, etc. */ 8568static rtx mips_sim_insn; 8569 8570/* A structure representing the state of the processor pipeline. 8571 Used by the mips_sim_* family of functions. */ 8572struct mips_sim { 8573 /* The maximum number of instructions that can be issued in a cycle. 8574 (Caches mips_issue_rate.) */ 8575 unsigned int issue_rate; 8576 8577 /* The current simulation time. */ 8578 unsigned int time; 8579 8580 /* How many more instructions can be issued in the current cycle. */ 8581 unsigned int insns_left; 8582 8583 /* LAST_SET[X].INSN is the last instruction to set register X. 8584 LAST_SET[X].TIME is the time at which that instruction was issued. 8585 INSN is null if no instruction has yet set register X. */ 8586 struct { 8587 rtx insn; 8588 unsigned int time; 8589 } last_set[FIRST_PSEUDO_REGISTER]; 8590 8591 /* The pipeline's current DFA state. */ 8592 state_t dfa_state; 8593}; 8594 8595/* Reset STATE to the initial simulation state. */ 8596 8597static void 8598mips_sim_reset (struct mips_sim *state) 8599{ 8600 state->time = 0; 8601 state->insns_left = state->issue_rate; 8602 memset (&state->last_set, 0, sizeof (state->last_set)); 8603 state_reset (state->dfa_state); 8604} 8605 8606/* Initialize STATE before its first use. DFA_STATE points to an 8607 allocated but uninitialized DFA state. */ 8608 8609static void 8610mips_sim_init (struct mips_sim *state, state_t dfa_state) 8611{ 8612 state->issue_rate = mips_issue_rate (); 8613 state->dfa_state = dfa_state; 8614 mips_sim_reset (state); 8615} 8616 8617/* Advance STATE by one clock cycle. */ 8618 8619static void 8620mips_sim_next_cycle (struct mips_sim *state) 8621{ 8622 state->time++; 8623 state->insns_left = state->issue_rate; 8624 state_transition (state->dfa_state, 0); 8625} 8626 8627/* Advance simulation state STATE until instruction INSN can read 8628 register REG. */ 8629 8630static void 8631mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg) 8632{ 8633 unsigned int i; 8634 8635 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++) 8636 if (state->last_set[REGNO (reg) + i].insn != 0) 8637 { 8638 unsigned int t; 8639 8640 t = state->last_set[REGNO (reg) + i].time; 8641 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn); 8642 while (state->time < t) 8643 mips_sim_next_cycle (state); 8644 } 8645} 8646 8647/* A for_each_rtx callback. If *X is a register, advance simulation state 8648 DATA until mips_sim_insn can read the register's value. */ 8649 8650static int 8651mips_sim_wait_regs_2 (rtx *x, void *data) 8652{ 8653 if (REG_P (*x)) 8654 mips_sim_wait_reg (data, mips_sim_insn, *x); 8655 return 0; 8656} 8657 8658/* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */ 8659 8660static void 8661mips_sim_wait_regs_1 (rtx *x, void *data) 8662{ 8663 for_each_rtx (x, mips_sim_wait_regs_2, data); 8664} 8665 8666/* Advance simulation state STATE until all of INSN's register 8667 dependencies are satisfied. */ 8668 8669static void 8670mips_sim_wait_regs (struct mips_sim *state, rtx insn) 8671{ 8672 mips_sim_insn = insn; 8673 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state); 8674} 8675 8676/* Advance simulation state STATE until the units required by 8677 instruction INSN are available. */ 8678 8679static void 8680mips_sim_wait_units (struct mips_sim *state, rtx insn) 8681{ 8682 state_t tmp_state; 8683 8684 tmp_state = alloca (state_size ()); 8685 while (state->insns_left == 0 8686 || (memcpy (tmp_state, state->dfa_state, state_size ()), 8687 state_transition (tmp_state, insn) >= 0)) 8688 mips_sim_next_cycle (state); 8689} 8690 8691/* Advance simulation state STATE until INSN is ready to issue. */ 8692 8693static void 8694mips_sim_wait_insn (struct mips_sim *state, rtx insn) 8695{ 8696 mips_sim_wait_regs (state, insn); 8697 mips_sim_wait_units (state, insn); 8698} 8699 8700/* mips_sim_insn has just set X. Update the LAST_SET array 8701 in simulation state DATA. */ 8702 8703static void 8704mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data) 8705{ 8706 struct mips_sim *state; 8707 unsigned int i; 8708 8709 state = data; 8710 if (REG_P (x)) 8711 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++) 8712 { 8713 state->last_set[REGNO (x) + i].insn = mips_sim_insn; 8714 state->last_set[REGNO (x) + i].time = state->time; 8715 } 8716} 8717 8718/* Issue instruction INSN in scheduler state STATE. Assume that INSN 8719 can issue immediately (i.e., that mips_sim_wait_insn has already 8720 been called). */ 8721 8722static void 8723mips_sim_issue_insn (struct mips_sim *state, rtx insn) 8724{ 8725 state_transition (state->dfa_state, insn); 8726 state->insns_left--; 8727 8728 mips_sim_insn = insn; 8729 note_stores (PATTERN (insn), mips_sim_record_set, state); 8730} 8731 8732/* Simulate issuing a NOP in state STATE. */ 8733 8734static void 8735mips_sim_issue_nop (struct mips_sim *state) 8736{ 8737 if (state->insns_left == 0) 8738 mips_sim_next_cycle (state); 8739 state->insns_left--; 8740} 8741 8742/* Update simulation state STATE so that it's ready to accept the instruction 8743 after INSN. INSN should be part of the main rtl chain, not a member of a 8744 SEQUENCE. */ 8745 8746static void 8747mips_sim_finish_insn (struct mips_sim *state, rtx insn) 8748{ 8749 /* If INSN is a jump with an implicit delay slot, simulate a nop. */ 8750 if (JUMP_P (insn)) 8751 mips_sim_issue_nop (state); 8752 8753 switch (GET_CODE (SEQ_BEGIN (insn))) 8754 { 8755 case CODE_LABEL: 8756 case CALL_INSN: 8757 /* We can't predict the processor state after a call or label. */ 8758 mips_sim_reset (state); 8759 break; 8760 8761 case JUMP_INSN: 8762 /* The delay slots of branch likely instructions are only executed 8763 when the branch is taken. Therefore, if the caller has simulated 8764 the delay slot instruction, STATE does not really reflect the state 8765 of the pipeline for the instruction after the delay slot. Also, 8766 branch likely instructions tend to incur a penalty when not taken, 8767 so there will probably be an extra delay between the branch and 8768 the instruction after the delay slot. */ 8769 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn))) 8770 mips_sim_reset (state); 8771 break; 8772 8773 default: 8774 break; 8775 } 8776} 8777 8778/* The VR4130 pipeline issues aligned pairs of instructions together, 8779 but it stalls the second instruction if it depends on the first. 8780 In order to cut down the amount of logic required, this dependence 8781 check is not based on a full instruction decode. Instead, any non-SPECIAL 8782 instruction is assumed to modify the register specified by bits 20-16 8783 (which is usually the "rt" field). 8784 8785 In beq, beql, bne and bnel instructions, the rt field is actually an 8786 input, so we can end up with a false dependence between the branch 8787 and its delay slot. If this situation occurs in instruction INSN, 8788 try to avoid it by swapping rs and rt. */ 8789 8790static void 8791vr4130_avoid_branch_rt_conflict (rtx insn) 8792{ 8793 rtx first, second; 8794 8795 first = SEQ_BEGIN (insn); 8796 second = SEQ_END (insn); 8797 if (JUMP_P (first) 8798 && NONJUMP_INSN_P (second) 8799 && GET_CODE (PATTERN (first)) == SET 8800 && GET_CODE (SET_DEST (PATTERN (first))) == PC 8801 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE) 8802 { 8803 /* Check for the right kind of condition. */ 8804 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0); 8805 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) 8806 && REG_P (XEXP (cond, 0)) 8807 && REG_P (XEXP (cond, 1)) 8808 && reg_referenced_p (XEXP (cond, 1), PATTERN (second)) 8809 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second))) 8810 { 8811 /* SECOND mentions the rt register but not the rs register. */ 8812 rtx tmp = XEXP (cond, 0); 8813 XEXP (cond, 0) = XEXP (cond, 1); 8814 XEXP (cond, 1) = tmp; 8815 } 8816 } 8817} 8818 8819/* Implement -mvr4130-align. Go through each basic block and simulate the 8820 processor pipeline. If we find that a pair of instructions could execute 8821 in parallel, and the first of those instruction is not 8-byte aligned, 8822 insert a nop to make it aligned. */ 8823 8824static void 8825vr4130_align_insns (void) 8826{ 8827 struct mips_sim state; 8828 rtx insn, subinsn, last, last2, next; 8829 bool aligned_p; 8830 8831 dfa_start (); 8832 8833 /* LAST is the last instruction before INSN to have a nonzero length. 8834 LAST2 is the last such instruction before LAST. */ 8835 last = 0; 8836 last2 = 0; 8837 8838 /* ALIGNED_P is true if INSN is known to be at an aligned address. */ 8839 aligned_p = true; 8840 8841 mips_sim_init (&state, alloca (state_size ())); 8842 for (insn = get_insns (); insn != 0; insn = next) 8843 { 8844 unsigned int length; 8845 8846 next = NEXT_INSN (insn); 8847 8848 /* See the comment above vr4130_avoid_branch_rt_conflict for details. 8849 This isn't really related to the alignment pass, but we do it on 8850 the fly to avoid a separate instruction walk. */ 8851 vr4130_avoid_branch_rt_conflict (insn); 8852 8853 if (USEFUL_INSN_P (insn)) 8854 FOR_EACH_SUBINSN (subinsn, insn) 8855 { 8856 mips_sim_wait_insn (&state, subinsn); 8857 8858 /* If we want this instruction to issue in parallel with the 8859 previous one, make sure that the previous instruction is 8860 aligned. There are several reasons why this isn't worthwhile 8861 when the second instruction is a call: 8862 8863 - Calls are less likely to be performance critical, 8864 - There's a good chance that the delay slot can execute 8865 in parallel with the call. 8866 - The return address would then be unaligned. 8867 8868 In general, if we're going to insert a nop between instructions 8869 X and Y, it's better to insert it immediately after X. That 8870 way, if the nop makes Y aligned, it will also align any labels 8871 between X and Y. */ 8872 if (state.insns_left != state.issue_rate 8873 && !CALL_P (subinsn)) 8874 { 8875 if (subinsn == SEQ_BEGIN (insn) && aligned_p) 8876 { 8877 /* SUBINSN is the first instruction in INSN and INSN is 8878 aligned. We want to align the previous instruction 8879 instead, so insert a nop between LAST2 and LAST. 8880 8881 Note that LAST could be either a single instruction 8882 or a branch with a delay slot. In the latter case, 8883 LAST, like INSN, is already aligned, but the delay 8884 slot must have some extra delay that stops it from 8885 issuing at the same time as the branch. We therefore 8886 insert a nop before the branch in order to align its 8887 delay slot. */ 8888 emit_insn_after (gen_nop (), last2); 8889 aligned_p = false; 8890 } 8891 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p) 8892 { 8893 /* SUBINSN is the delay slot of INSN, but INSN is 8894 currently unaligned. Insert a nop between 8895 LAST and INSN to align it. */ 8896 emit_insn_after (gen_nop (), last); 8897 aligned_p = true; 8898 } 8899 } 8900 mips_sim_issue_insn (&state, subinsn); 8901 } 8902 mips_sim_finish_insn (&state, insn); 8903 8904 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */ 8905 length = get_attr_length (insn); 8906 if (length > 0) 8907 { 8908 /* If the instruction is an asm statement or multi-instruction 8909 mips.md patern, the length is only an estimate. Insert an 8910 8 byte alignment after it so that the following instructions 8911 can be handled correctly. */ 8912 if (NONJUMP_INSN_P (SEQ_BEGIN (insn)) 8913 && (recog_memoized (insn) < 0 || length >= 8)) 8914 { 8915 next = emit_insn_after (gen_align (GEN_INT (3)), insn); 8916 next = NEXT_INSN (next); 8917 mips_sim_next_cycle (&state); 8918 aligned_p = true; 8919 } 8920 else if (length & 4) 8921 aligned_p = !aligned_p; 8922 last2 = last; 8923 last = insn; 8924 } 8925 8926 /* See whether INSN is an aligned label. */ 8927 if (LABEL_P (insn) && label_to_alignment (insn) >= 3) 8928 aligned_p = true; 8929 } 8930 dfa_finish (); 8931} 8932 8933/* Subroutine of mips_reorg. If there is a hazard between INSN 8934 and a previous instruction, avoid it by inserting nops after 8935 instruction AFTER. 8936 8937 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at 8938 this point. If *DELAYED_REG is non-null, INSN must wait a cycle 8939 before using the value of that register. *HILO_DELAY counts the 8940 number of instructions since the last hilo hazard (that is, 8941 the number of instructions since the last mflo or mfhi). 8942 8943 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY 8944 for the next instruction. 8945 8946 LO_REG is an rtx for the LO register, used in dependence checking. */ 8947 8948static void 8949mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay, 8950 rtx *delayed_reg, rtx lo_reg) 8951{ 8952 rtx pattern, set; 8953 int nops, ninsns; 8954 8955 if (!INSN_P (insn)) 8956 return; 8957 8958 pattern = PATTERN (insn); 8959 8960 /* Do not put the whole function in .set noreorder if it contains 8961 an asm statement. We don't know whether there will be hazards 8962 between the asm statement and the gcc-generated code. */ 8963 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0) 8964 cfun->machine->all_noreorder_p = false; 8965 8966 /* Ignore zero-length instructions (barriers and the like). */ 8967 ninsns = get_attr_length (insn) / 4; 8968 if (ninsns == 0) 8969 return; 8970 8971 /* Work out how many nops are needed. Note that we only care about 8972 registers that are explicitly mentioned in the instruction's pattern. 8973 It doesn't matter that calls use the argument registers or that they 8974 clobber hi and lo. */ 8975 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern)) 8976 nops = 2 - *hilo_delay; 8977 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern)) 8978 nops = 1; 8979 else 8980 nops = 0; 8981 8982 /* Insert the nops between this instruction and the previous one. 8983 Each new nop takes us further from the last hilo hazard. */ 8984 *hilo_delay += nops; 8985 while (nops-- > 0) 8986 emit_insn_after (gen_hazard_nop (), after); 8987 8988 /* Set up the state for the next instruction. */ 8989 *hilo_delay += ninsns; 8990 *delayed_reg = 0; 8991 if (INSN_CODE (insn) >= 0) 8992 switch (get_attr_hazard (insn)) 8993 { 8994 case HAZARD_NONE: 8995 break; 8996 8997 case HAZARD_HILO: 8998 *hilo_delay = 0; 8999 break; 9000 9001 case HAZARD_DELAY: 9002 set = single_set (insn); 9003 gcc_assert (set != 0); 9004 *delayed_reg = SET_DEST (set); 9005 break; 9006 } 9007} 9008 9009 9010/* Go through the instruction stream and insert nops where necessary. 9011 See if the whole function can then be put into .set noreorder & 9012 .set nomacro. */ 9013 9014static void 9015mips_avoid_hazards (void) 9016{ 9017 rtx insn, last_insn, lo_reg, delayed_reg; 9018 int hilo_delay, i; 9019 9020 /* Force all instructions to be split into their final form. */ 9021 split_all_insns_noflow (); 9022 9023 /* Recalculate instruction lengths without taking nops into account. */ 9024 cfun->machine->ignore_hazard_length_p = true; 9025 shorten_branches (get_insns ()); 9026 9027 cfun->machine->all_noreorder_p = true; 9028 9029 /* Profiled functions can't be all noreorder because the profiler 9030 support uses assembler macros. */ 9031 if (current_function_profile) 9032 cfun->machine->all_noreorder_p = false; 9033 9034 /* Code compiled with -mfix-vr4120 can't be all noreorder because 9035 we rely on the assembler to work around some errata. */ 9036 if (TARGET_FIX_VR4120) 9037 cfun->machine->all_noreorder_p = false; 9038 9039 /* The same is true for -mfix-vr4130 if we might generate mflo or 9040 mfhi instructions. Note that we avoid using mflo and mfhi if 9041 the VR4130 macc and dmacc instructions are available instead; 9042 see the *mfhilo_{si,di}_macc patterns. */ 9043 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI) 9044 cfun->machine->all_noreorder_p = false; 9045 9046 last_insn = 0; 9047 hilo_delay = 2; 9048 delayed_reg = 0; 9049 lo_reg = gen_rtx_REG (SImode, LO_REGNUM); 9050 9051 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) 9052 if (INSN_P (insn)) 9053 { 9054 if (GET_CODE (PATTERN (insn)) == SEQUENCE) 9055 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) 9056 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i), 9057 &hilo_delay, &delayed_reg, lo_reg); 9058 else 9059 mips_avoid_hazard (last_insn, insn, &hilo_delay, 9060 &delayed_reg, lo_reg); 9061 9062 last_insn = insn; 9063 } 9064} 9065 9066 9067/* Implement TARGET_MACHINE_DEPENDENT_REORG. */ 9068 9069static void 9070mips_reorg (void) 9071{ 9072 if (TARGET_MIPS16) 9073 mips16_lay_out_constants (); 9074 else if (TARGET_EXPLICIT_RELOCS) 9075 { 9076 if (mips_flag_delayed_branch) 9077 dbr_schedule (get_insns ()); 9078 mips_avoid_hazards (); 9079 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN) 9080 vr4130_align_insns (); 9081 } 9082} 9083 9084/* This function does three things: 9085 9086 - Register the special divsi3 and modsi3 functions if -mfix-vr4120. 9087 - Register the mips16 hardware floating point stubs. 9088 - Register the gofast functions if selected using --enable-gofast. */ 9089 9090#include "config/gofast.h" 9091 9092static void 9093mips_init_libfuncs (void) 9094{ 9095 if (TARGET_FIX_VR4120) 9096 { 9097 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3"); 9098 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3"); 9099 } 9100 9101 if (TARGET_MIPS16 && mips16_hard_float) 9102 { 9103 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3"); 9104 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3"); 9105 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3"); 9106 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3"); 9107 9108 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2"); 9109 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2"); 9110 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2"); 9111 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2"); 9112 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2"); 9113 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2"); 9114 9115 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi"); 9116 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf"); 9117 9118 if (TARGET_DOUBLE_FLOAT) 9119 { 9120 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3"); 9121 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3"); 9122 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3"); 9123 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3"); 9124 9125 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2"); 9126 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2"); 9127 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2"); 9128 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2"); 9129 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2"); 9130 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2"); 9131 9132 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2"); 9133 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2"); 9134 9135 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi"); 9136 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf"); 9137 } 9138 } 9139 else 9140 gofast_maybe_init_libfuncs (); 9141} 9142 9143/* Return a number assessing the cost of moving a register in class 9144 FROM to class TO. The classes are expressed using the enumeration 9145 values such as `GENERAL_REGS'. A value of 2 is the default; other 9146 values are interpreted relative to that. 9147 9148 It is not required that the cost always equal 2 when FROM is the 9149 same as TO; on some machines it is expensive to move between 9150 registers if they are not general registers. 9151 9152 If reload sees an insn consisting of a single `set' between two 9153 hard registers, and if `REGISTER_MOVE_COST' applied to their 9154 classes returns a value of 2, reload does not check to ensure that 9155 the constraints of the insn are met. Setting a cost of other than 9156 2 will allow reload to verify that the constraints are met. You 9157 should do this if the `movM' pattern's constraints do not allow 9158 such copying. 9159 9160 ??? We make the cost of moving from HI/LO into general 9161 registers the same as for one of moving general registers to 9162 HI/LO for TARGET_MIPS16 in order to prevent allocating a 9163 pseudo to HI/LO. This might hurt optimizations though, it 9164 isn't clear if it is wise. And it might not work in all cases. We 9165 could solve the DImode LO reg problem by using a multiply, just 9166 like reload_{in,out}si. We could solve the SImode/HImode HI reg 9167 problem by using divide instructions. divu puts the remainder in 9168 the HI reg, so doing a divide by -1 will move the value in the HI 9169 reg for all values except -1. We could handle that case by using a 9170 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit 9171 a compare/branch to test the input value to see which instruction 9172 we need to use. This gets pretty messy, but it is feasible. */ 9173 9174int 9175mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, 9176 enum reg_class to, enum reg_class from) 9177{ 9178 if (from == M16_REGS && GR_REG_CLASS_P (to)) 9179 return 2; 9180 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to)) 9181 return 2; 9182 else if (GR_REG_CLASS_P (from)) 9183 { 9184 if (to == M16_REGS) 9185 return 2; 9186 else if (to == M16_NA_REGS) 9187 return 2; 9188 else if (GR_REG_CLASS_P (to)) 9189 { 9190 if (TARGET_MIPS16) 9191 return 4; 9192 else 9193 return 2; 9194 } 9195 else if (to == FP_REGS) 9196 return 4; 9197 else if (reg_class_subset_p (to, ACC_REGS)) 9198 { 9199 if (TARGET_MIPS16) 9200 return 12; 9201 else 9202 return 6; 9203 } 9204 else if (COP_REG_CLASS_P (to)) 9205 { 9206 return 5; 9207 } 9208 } 9209 else if (from == FP_REGS) 9210 { 9211 if (GR_REG_CLASS_P (to)) 9212 return 4; 9213 else if (to == FP_REGS) 9214 return 2; 9215 else if (to == ST_REGS) 9216 return 8; 9217 } 9218 else if (reg_class_subset_p (from, ACC_REGS)) 9219 { 9220 if (GR_REG_CLASS_P (to)) 9221 { 9222 if (TARGET_MIPS16) 9223 return 12; 9224 else 9225 return 6; 9226 } 9227 } 9228 else if (from == ST_REGS && GR_REG_CLASS_P (to)) 9229 return 4; 9230 else if (COP_REG_CLASS_P (from)) 9231 { 9232 return 5; 9233 } 9234 9235 /* Fall through. 9236 ??? What cases are these? Shouldn't we return 2 here? */ 9237 9238 return 12; 9239} 9240 9241/* Return the length of INSN. LENGTH is the initial length computed by 9242 attributes in the machine-description file. */ 9243 9244int 9245mips_adjust_insn_length (rtx insn, int length) 9246{ 9247 /* A unconditional jump has an unfilled delay slot if it is not part 9248 of a sequence. A conditional jump normally has a delay slot, but 9249 does not on MIPS16. */ 9250 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn))) 9251 length += 4; 9252 9253 /* See how many nops might be needed to avoid hardware hazards. */ 9254 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0) 9255 switch (get_attr_hazard (insn)) 9256 { 9257 case HAZARD_NONE: 9258 break; 9259 9260 case HAZARD_DELAY: 9261 length += 4; 9262 break; 9263 9264 case HAZARD_HILO: 9265 length += 8; 9266 break; 9267 } 9268 9269 /* All MIPS16 instructions are a measly two bytes. */ 9270 if (TARGET_MIPS16) 9271 length /= 2; 9272 9273 return length; 9274} 9275 9276 9277/* Return an asm sequence to start a noat block and load the address 9278 of a label into $1. */ 9279 9280const char * 9281mips_output_load_label (void) 9282{ 9283 if (TARGET_EXPLICIT_RELOCS) 9284 switch (mips_abi) 9285 { 9286 case ABI_N32: 9287 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)"; 9288 9289 case ABI_64: 9290 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)"; 9291 9292 default: 9293 if (ISA_HAS_LOAD_DELAY) 9294 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)"; 9295 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)"; 9296 } 9297 else 9298 { 9299 if (Pmode == DImode) 9300 return "%[dla\t%@,%0"; 9301 else 9302 return "%[la\t%@,%0"; 9303 } 9304} 9305 9306/* Return the assembly code for INSN, which has the operands given by 9307 OPERANDS, and which branches to OPERANDS[1] if some condition is true. 9308 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1] 9309 is in range of a direct branch. BRANCH_IF_FALSE is an inverted 9310 version of BRANCH_IF_TRUE. */ 9311 9312const char * 9313mips_output_conditional_branch (rtx insn, rtx *operands, 9314 const char *branch_if_true, 9315 const char *branch_if_false) 9316{ 9317 unsigned int length; 9318 rtx taken, not_taken; 9319 9320 length = get_attr_length (insn); 9321 if (length <= 8) 9322 { 9323 /* Just a simple conditional branch. */ 9324 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); 9325 return branch_if_true; 9326 } 9327 9328 /* Generate a reversed branch around a direct jump. This fallback does 9329 not use branch-likely instructions. */ 9330 mips_branch_likely = false; 9331 not_taken = gen_label_rtx (); 9332 taken = operands[1]; 9333 9334 /* Generate the reversed branch to NOT_TAKEN. */ 9335 operands[1] = not_taken; 9336 output_asm_insn (branch_if_false, operands); 9337 9338 /* If INSN has a delay slot, we must provide delay slots for both the 9339 branch to NOT_TAKEN and the conditional jump. We must also ensure 9340 that INSN's delay slot is executed in the appropriate cases. */ 9341 if (final_sequence) 9342 { 9343 /* This first delay slot will always be executed, so use INSN's 9344 delay slot if is not annulled. */ 9345 if (!INSN_ANNULLED_BRANCH_P (insn)) 9346 { 9347 final_scan_insn (XVECEXP (final_sequence, 0, 1), 9348 asm_out_file, optimize, 1, NULL); 9349 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1; 9350 } 9351 else 9352 output_asm_insn ("nop", 0); 9353 fprintf (asm_out_file, "\n"); 9354 } 9355 9356 /* Output the unconditional branch to TAKEN. */ 9357 if (length <= 16) 9358 output_asm_insn ("j\t%0%/", &taken); 9359 else 9360 { 9361 output_asm_insn (mips_output_load_label (), &taken); 9362 output_asm_insn ("jr\t%@%]%/", 0); 9363 } 9364 9365 /* Now deal with its delay slot; see above. */ 9366 if (final_sequence) 9367 { 9368 /* This delay slot will only be executed if the branch is taken. 9369 Use INSN's delay slot if is annulled. */ 9370 if (INSN_ANNULLED_BRANCH_P (insn)) 9371 { 9372 final_scan_insn (XVECEXP (final_sequence, 0, 1), 9373 asm_out_file, optimize, 1, NULL); 9374 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1; 9375 } 9376 else 9377 output_asm_insn ("nop", 0); 9378 fprintf (asm_out_file, "\n"); 9379 } 9380 9381 /* Output NOT_TAKEN. */ 9382 (*targetm.asm_out.internal_label) (asm_out_file, "L", 9383 CODE_LABEL_NUMBER (not_taken)); 9384 return ""; 9385} 9386 9387/* Return the assembly code for INSN, which branches to OPERANDS[1] 9388 if some ordered condition is true. The condition is given by 9389 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of 9390 OPERANDS[0]. OPERANDS[2] is the comparison's first operand; 9391 its second is always zero. */ 9392 9393const char * 9394mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p) 9395{ 9396 const char *branch[2]; 9397 9398 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true. 9399 Make BRANCH[0] branch on the inverse condition. */ 9400 switch (GET_CODE (operands[0])) 9401 { 9402 /* These cases are equivalent to comparisons against zero. */ 9403 case LEU: 9404 inverted_p = !inverted_p; 9405 /* Fall through. */ 9406 case GTU: 9407 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1"); 9408 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1"); 9409 break; 9410 9411 /* These cases are always true or always false. */ 9412 case LTU: 9413 inverted_p = !inverted_p; 9414 /* Fall through. */ 9415 case GEU: 9416 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1"); 9417 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1"); 9418 break; 9419 9420 default: 9421 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1"); 9422 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1"); 9423 break; 9424 } 9425 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]); 9426} 9427 9428/* Used to output div or ddiv instruction DIVISION, which has the operands 9429 given by OPERANDS. Add in a divide-by-zero check if needed. 9430 9431 When working around R4000 and R4400 errata, we need to make sure that 9432 the division is not immediately followed by a shift[1][2]. We also 9433 need to stop the division from being put into a branch delay slot[3]. 9434 The easiest way to avoid both problems is to add a nop after the 9435 division. When a divide-by-zero check is needed, this nop can be 9436 used to fill the branch delay slot. 9437 9438 [1] If a double-word or a variable shift executes immediately 9439 after starting an integer division, the shift may give an 9440 incorrect result. See quotations of errata #16 and #28 from 9441 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" 9442 in mips.md for details. 9443 9444 [2] A similar bug to [1] exists for all revisions of the 9445 R4000 and the R4400 when run in an MC configuration. 9446 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0": 9447 9448 "19. In this following sequence: 9449 9450 ddiv (or ddivu or div or divu) 9451 dsll32 (or dsrl32, dsra32) 9452 9453 if an MPT stall occurs, while the divide is slipping the cpu 9454 pipeline, then the following double shift would end up with an 9455 incorrect result. 9456 9457 Workaround: The compiler needs to avoid generating any 9458 sequence with divide followed by extended double shift." 9459 9460 This erratum is also present in "MIPS R4400MC Errata, Processor 9461 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0 9462 & 3.0" as errata #10 and #4, respectively. 9463 9464 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" 9465 (also valid for MIPS R4000MC processors): 9466 9467 "52. R4000SC: This bug does not apply for the R4000PC. 9468 9469 There are two flavors of this bug: 9470 9471 1) If the instruction just after divide takes an RF exception 9472 (tlb-refill, tlb-invalid) and gets an instruction cache 9473 miss (both primary and secondary) and the line which is 9474 currently in secondary cache at this index had the first 9475 data word, where the bits 5..2 are set, then R4000 would 9476 get a wrong result for the div. 9477 9478 ##1 9479 nop 9480 div r8, r9 9481 ------------------- # end-of page. -tlb-refill 9482 nop 9483 ##2 9484 nop 9485 div r8, r9 9486 ------------------- # end-of page. -tlb-invalid 9487 nop 9488 9489 2) If the divide is in the taken branch delay slot, where the 9490 target takes RF exception and gets an I-cache miss for the 9491 exception vector or where I-cache miss occurs for the 9492 target address, under the above mentioned scenarios, the 9493 div would get wrong results. 9494 9495 ##1 9496 j r2 # to next page mapped or unmapped 9497 div r8,r9 # this bug would be there as long 9498 # as there is an ICache miss and 9499 nop # the "data pattern" is present 9500 9501 ##2 9502 beq r0, r0, NextPage # to Next page 9503 div r8,r9 9504 nop 9505 9506 This bug is present for div, divu, ddiv, and ddivu 9507 instructions. 9508 9509 Workaround: For item 1), OS could make sure that the next page 9510 after the divide instruction is also mapped. For item 2), the 9511 compiler could make sure that the divide instruction is not in 9512 the branch delay slot." 9513 9514 These processors have PRId values of 0x00004220 and 0x00004300 for 9515 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */ 9516 9517const char * 9518mips_output_division (const char *division, rtx *operands) 9519{ 9520 const char *s; 9521 9522 s = division; 9523 if (TARGET_FIX_R4000 || TARGET_FIX_R4400) 9524 { 9525 output_asm_insn (s, operands); 9526 s = "nop"; 9527 } 9528 if (TARGET_CHECK_ZERO_DIV) 9529 { 9530 if (TARGET_MIPS16) 9531 { 9532 output_asm_insn (s, operands); 9533 s = "bnez\t%2,1f\n\tbreak\t7\n1:"; 9534 } 9535 else if (GENERATE_DIVIDE_TRAPS) 9536 { 9537 output_asm_insn (s, operands); 9538 s = "teq\t%2,%.,7"; 9539 } 9540 else 9541 { 9542 output_asm_insn ("%(bne\t%2,%.,1f", operands); 9543 output_asm_insn (s, operands); 9544 s = "break\t7%)\n1:"; 9545 } 9546 } 9547 return s; 9548} 9549 9550/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL 9551 with a final "000" replaced by "k". Ignore case. 9552 9553 Note: this function is shared between GCC and GAS. */ 9554 9555static bool 9556mips_strict_matching_cpu_name_p (const char *canonical, const char *given) 9557{ 9558 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) 9559 given++, canonical++; 9560 9561 return ((*given == 0 && *canonical == 0) 9562 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); 9563} 9564 9565 9566/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied 9567 CPU name. We've traditionally allowed a lot of variation here. 9568 9569 Note: this function is shared between GCC and GAS. */ 9570 9571static bool 9572mips_matching_cpu_name_p (const char *canonical, const char *given) 9573{ 9574 /* First see if the name matches exactly, or with a final "000" 9575 turned into "k". */ 9576 if (mips_strict_matching_cpu_name_p (canonical, given)) 9577 return true; 9578 9579 /* If not, try comparing based on numerical designation alone. 9580 See if GIVEN is an unadorned number, or 'r' followed by a number. */ 9581 if (TOLOWER (*given) == 'r') 9582 given++; 9583 if (!ISDIGIT (*given)) 9584 return false; 9585 9586 /* Skip over some well-known prefixes in the canonical name, 9587 hoping to find a number there too. */ 9588 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') 9589 canonical += 2; 9590 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') 9591 canonical += 2; 9592 else if (TOLOWER (canonical[0]) == 'r') 9593 canonical += 1; 9594 9595 return mips_strict_matching_cpu_name_p (canonical, given); 9596} 9597 9598 9599/* Return the mips_cpu_info entry for the processor or ISA given 9600 by CPU_STRING. Return null if the string isn't recognized. 9601 9602 A similar function exists in GAS. */ 9603 9604static const struct mips_cpu_info * 9605mips_parse_cpu (const char *cpu_string) 9606{ 9607 const struct mips_cpu_info *p; 9608 const char *s; 9609 9610 /* In the past, we allowed upper-case CPU names, but it doesn't 9611 work well with the multilib machinery. */ 9612 for (s = cpu_string; *s != 0; s++) 9613 if (ISUPPER (*s)) 9614 { 9615 warning (0, "the cpu name must be lower case"); 9616 break; 9617 } 9618 9619 /* 'from-abi' selects the most compatible architecture for the given 9620 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the 9621 EABIs, we have to decide whether we're using the 32-bit or 64-bit 9622 version. Look first at the -mgp options, if given, otherwise base 9623 the choice on MASK_64BIT in TARGET_DEFAULT. */ 9624 if (strcasecmp (cpu_string, "from-abi") == 0) 9625 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1 9626 : ABI_NEEDS_64BIT_REGS ? 3 9627 : (TARGET_64BIT ? 3 : 1)); 9628 9629 /* 'default' has traditionally been a no-op. Probably not very useful. */ 9630 if (strcasecmp (cpu_string, "default") == 0) 9631 return 0; 9632 9633 for (p = mips_cpu_info_table; p->name != 0; p++) 9634 if (mips_matching_cpu_name_p (p->name, cpu_string)) 9635 return p; 9636 9637 return 0; 9638} 9639 9640 9641/* Return the processor associated with the given ISA level, or null 9642 if the ISA isn't valid. */ 9643 9644static const struct mips_cpu_info * 9645mips_cpu_info_from_isa (int isa) 9646{ 9647 const struct mips_cpu_info *p; 9648 9649 for (p = mips_cpu_info_table; p->name != 0; p++) 9650 if (p->isa == isa) 9651 return p; 9652 9653 return 0; 9654} 9655 9656/* Implement HARD_REGNO_NREGS. The size of FP registers is controlled 9657 by UNITS_PER_FPREG. The size of FP status registers is always 4, because 9658 they only hold condition code modes, and CCmode is always considered to 9659 be 4 bytes wide. All other registers are word sized. */ 9660 9661unsigned int 9662mips_hard_regno_nregs (int regno, enum machine_mode mode) 9663{ 9664 if (ST_REG_P (regno)) 9665 return ((GET_MODE_SIZE (mode) + 3) / 4); 9666 else if (! FP_REG_P (regno)) 9667 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD); 9668 else 9669 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG); 9670} 9671 9672/* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs) 9673 all BLKmode objects are returned in memory. Under the new (N32 and 9674 64-bit MIPS ABIs) small structures are returned in a register. 9675 Objects with varying size must still be returned in memory, of 9676 course. */ 9677 9678static bool 9679mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED) 9680{ 9681 if (TARGET_OLDABI) 9682 return (TYPE_MODE (type) == BLKmode); 9683 else 9684 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD)) 9685 || (int_size_in_bytes (type) == -1)); 9686} 9687 9688static bool 9689mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED) 9690{ 9691 return !TARGET_OLDABI; 9692} 9693 9694/* Return true if INSN is a multiply-add or multiply-subtract 9695 instruction and PREV assigns to the accumulator operand. */ 9696 9697bool 9698mips_linked_madd_p (rtx prev, rtx insn) 9699{ 9700 rtx x; 9701 9702 x = single_set (insn); 9703 if (x == 0) 9704 return false; 9705 9706 x = SET_SRC (x); 9707 9708 if (GET_CODE (x) == PLUS 9709 && GET_CODE (XEXP (x, 0)) == MULT 9710 && reg_set_p (XEXP (x, 1), prev)) 9711 return true; 9712 9713 if (GET_CODE (x) == MINUS 9714 && GET_CODE (XEXP (x, 1)) == MULT 9715 && reg_set_p (XEXP (x, 0), prev)) 9716 return true; 9717 9718 return false; 9719} 9720 9721/* Used by TUNE_MACC_CHAINS to record the last scheduled instruction 9722 that may clobber hi or lo. */ 9723 9724static rtx mips_macc_chains_last_hilo; 9725 9726/* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has 9727 been scheduled, updating mips_macc_chains_last_hilo appropriately. */ 9728 9729static void 9730mips_macc_chains_record (rtx insn) 9731{ 9732 if (get_attr_may_clobber_hilo (insn)) 9733 mips_macc_chains_last_hilo = insn; 9734} 9735 9736/* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which 9737 has NREADY elements, looking for a multiply-add or multiply-subtract 9738 instruction that is cumulative with mips_macc_chains_last_hilo. 9739 If there is one, promote it ahead of anything else that might 9740 clobber hi or lo. */ 9741 9742static void 9743mips_macc_chains_reorder (rtx *ready, int nready) 9744{ 9745 int i, j; 9746 9747 if (mips_macc_chains_last_hilo != 0) 9748 for (i = nready - 1; i >= 0; i--) 9749 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i])) 9750 { 9751 for (j = nready - 1; j > i; j--) 9752 if (recog_memoized (ready[j]) >= 0 9753 && get_attr_may_clobber_hilo (ready[j])) 9754 { 9755 mips_promote_ready (ready, i, j); 9756 break; 9757 } 9758 break; 9759 } 9760} 9761 9762/* The last instruction to be scheduled. */ 9763 9764static rtx vr4130_last_insn; 9765 9766/* A note_stores callback used by vr4130_true_reg_dependence_p. DATA 9767 points to an rtx that is initially an instruction. Nullify the rtx 9768 if the instruction uses the value of register X. */ 9769 9770static void 9771vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data) 9772{ 9773 rtx *insn_ptr = data; 9774 if (REG_P (x) 9775 && *insn_ptr != 0 9776 && reg_referenced_p (x, PATTERN (*insn_ptr))) 9777 *insn_ptr = 0; 9778} 9779 9780/* Return true if there is true register dependence between vr4130_last_insn 9781 and INSN. */ 9782 9783static bool 9784vr4130_true_reg_dependence_p (rtx insn) 9785{ 9786 note_stores (PATTERN (vr4130_last_insn), 9787 vr4130_true_reg_dependence_p_1, &insn); 9788 return insn == 0; 9789} 9790 9791/* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of 9792 the ready queue and that INSN2 is the instruction after it, return 9793 true if it is worth promoting INSN2 ahead of INSN1. Look for cases 9794 in which INSN1 and INSN2 can probably issue in parallel, but for 9795 which (INSN2, INSN1) should be less sensitive to instruction 9796 alignment than (INSN1, INSN2). See 4130.md for more details. */ 9797 9798static bool 9799vr4130_swap_insns_p (rtx insn1, rtx insn2) 9800{ 9801 rtx dep; 9802 9803 /* Check for the following case: 9804 9805 1) there is some other instruction X with an anti dependence on INSN1; 9806 2) X has a higher priority than INSN2; and 9807 3) X is an arithmetic instruction (and thus has no unit restrictions). 9808 9809 If INSN1 is the last instruction blocking X, it would better to 9810 choose (INSN1, X) over (INSN2, INSN1). */ 9811 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1)) 9812 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI 9813 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2) 9814 && recog_memoized (XEXP (dep, 0)) >= 0 9815 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU) 9816 return false; 9817 9818 if (vr4130_last_insn != 0 9819 && recog_memoized (insn1) >= 0 9820 && recog_memoized (insn2) >= 0) 9821 { 9822 /* See whether INSN1 and INSN2 use different execution units, 9823 or if they are both ALU-type instructions. If so, they can 9824 probably execute in parallel. */ 9825 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1); 9826 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2); 9827 if (class1 != class2 || class1 == VR4130_CLASS_ALU) 9828 { 9829 /* If only one of the instructions has a dependence on 9830 vr4130_last_insn, prefer to schedule the other one first. */ 9831 bool dep1 = vr4130_true_reg_dependence_p (insn1); 9832 bool dep2 = vr4130_true_reg_dependence_p (insn2); 9833 if (dep1 != dep2) 9834 return dep1; 9835 9836 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn 9837 is not an ALU-type instruction and if INSN1 uses the same 9838 execution unit. (Note that if this condition holds, we already 9839 know that INSN2 uses a different execution unit.) */ 9840 if (class1 != VR4130_CLASS_ALU 9841 && recog_memoized (vr4130_last_insn) >= 0 9842 && class1 == get_attr_vr4130_class (vr4130_last_insn)) 9843 return true; 9844 } 9845 } 9846 return false; 9847} 9848 9849/* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready 9850 queue with at least two instructions. Swap the first two if 9851 vr4130_swap_insns_p says that it could be worthwhile. */ 9852 9853static void 9854vr4130_reorder (rtx *ready, int nready) 9855{ 9856 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2])) 9857 mips_promote_ready (ready, nready - 2, nready - 1); 9858} 9859 9860/* Remove the instruction at index LOWER from ready queue READY and 9861 reinsert it in front of the instruction at index HIGHER. LOWER must 9862 be <= HIGHER. */ 9863 9864static void 9865mips_promote_ready (rtx *ready, int lower, int higher) 9866{ 9867 rtx new_head; 9868 int i; 9869 9870 new_head = ready[lower]; 9871 for (i = lower; i < higher; i++) 9872 ready[i] = ready[i + 1]; 9873 ready[i] = new_head; 9874} 9875 9876/* Implement TARGET_SCHED_REORDER. */ 9877 9878static int 9879mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, 9880 rtx *ready, int *nreadyp, int cycle) 9881{ 9882 if (!reload_completed && TUNE_MACC_CHAINS) 9883 { 9884 if (cycle == 0) 9885 mips_macc_chains_last_hilo = 0; 9886 if (*nreadyp > 0) 9887 mips_macc_chains_reorder (ready, *nreadyp); 9888 } 9889 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN) 9890 { 9891 if (cycle == 0) 9892 vr4130_last_insn = 0; 9893 if (*nreadyp > 1) 9894 vr4130_reorder (ready, *nreadyp); 9895 } 9896 return mips_issue_rate (); 9897} 9898 9899/* Implement TARGET_SCHED_VARIABLE_ISSUE. */ 9900 9901static int 9902mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, 9903 rtx insn, int more) 9904{ 9905 switch (GET_CODE (PATTERN (insn))) 9906 { 9907 case USE: 9908 case CLOBBER: 9909 /* Don't count USEs and CLOBBERs against the issue rate. */ 9910 break; 9911 9912 default: 9913 more--; 9914 if (!reload_completed && TUNE_MACC_CHAINS) 9915 mips_macc_chains_record (insn); 9916 vr4130_last_insn = insn; 9917 break; 9918 } 9919 return more; 9920} 9921 9922/* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output 9923 dependencies have no cost. */ 9924 9925static int 9926mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link, 9927 rtx dep ATTRIBUTE_UNUSED, int cost) 9928{ 9929 if (REG_NOTE_KIND (link) != 0) 9930 return 0; 9931 return cost; 9932} 9933 9934/* Return the number of instructions that can be issued per cycle. */ 9935 9936static int 9937mips_issue_rate (void) 9938{ 9939 switch (mips_tune) 9940 { 9941 case PROCESSOR_R4130: 9942 case PROCESSOR_R5400: 9943 case PROCESSOR_R5500: 9944 case PROCESSOR_R7000: 9945 case PROCESSOR_R9000: 9946 return 2; 9947 9948 case PROCESSOR_SB1: 9949 case PROCESSOR_SB1A: 9950 /* This is actually 4, but we get better performance if we claim 3. 9951 This is partly because of unwanted speculative code motion with the 9952 larger number, and partly because in most common cases we can't 9953 reach the theoretical max of 4. */ 9954 return 3; 9955 9956 default: 9957 return 1; 9958 } 9959} 9960 9961/* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should 9962 be as wide as the scheduling freedom in the DFA. */ 9963 9964static int 9965mips_multipass_dfa_lookahead (void) 9966{ 9967 /* Can schedule up to 4 of the 6 function units in any one cycle. */ 9968 if (TUNE_SB1) 9969 return 4; 9970 9971 return 0; 9972} 9973 9974/* Implements a store data bypass check. We need this because the cprestore 9975 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the 9976 default routine to abort. We just return false for that case. */ 9977/* ??? Should try to give a better result here than assuming false. */ 9978 9979int 9980mips_store_data_bypass_p (rtx out_insn, rtx in_insn) 9981{ 9982 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE) 9983 return false; 9984 9985 return ! store_data_bypass_p (out_insn, in_insn); 9986} 9987 9988/* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY), 9989 return the first operand of the associated "pref" or "prefx" insn. */ 9990 9991rtx 9992mips_prefetch_cookie (rtx write, rtx locality) 9993{ 9994 /* store_streamed / load_streamed. */ 9995 if (INTVAL (locality) <= 0) 9996 return GEN_INT (INTVAL (write) + 4); 9997 9998 /* store / load. */ 9999 if (INTVAL (locality) <= 2) 10000 return write; 10001 10002 /* store_retained / load_retained. */ 10003 return GEN_INT (INTVAL (write) + 6); 10004} 10005 10006/* MIPS builtin function support. */ 10007 10008struct builtin_description 10009{ 10010 /* The code of the main .md file instruction. See mips_builtin_type 10011 for more information. */ 10012 enum insn_code icode; 10013 10014 /* The floating-point comparison code to use with ICODE, if any. */ 10015 enum mips_fp_condition cond; 10016 10017 /* The name of the builtin function. */ 10018 const char *name; 10019 10020 /* Specifies how the function should be expanded. */ 10021 enum mips_builtin_type builtin_type; 10022 10023 /* The function's prototype. */ 10024 enum mips_function_type function_type; 10025 10026 /* The target flags required for this function. */ 10027 int target_flags; 10028}; 10029 10030/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>. 10031 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */ 10032#define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \ 10033 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \ 10034 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS } 10035 10036/* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require 10037 TARGET_FLAGS. */ 10038#define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \ 10039 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \ 10040 "__builtin_mips_" #INSN "_" #COND "_s", \ 10041 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \ 10042 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \ 10043 "__builtin_mips_" #INSN "_" #COND "_d", \ 10044 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS } 10045 10046/* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps. 10047 The lower and upper forms require TARGET_FLAGS while the any and all 10048 forms require MASK_MIPS3D. */ 10049#define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \ 10050 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \ 10051 "__builtin_mips_any_" #INSN "_" #COND "_ps", \ 10052 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \ 10053 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \ 10054 "__builtin_mips_all_" #INSN "_" #COND "_ps", \ 10055 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \ 10056 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \ 10057 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \ 10058 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \ 10059 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \ 10060 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \ 10061 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS } 10062 10063/* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions 10064 require MASK_MIPS3D. */ 10065#define CMP_4S_BUILTINS(INSN, COND) \ 10066 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \ 10067 "__builtin_mips_any_" #INSN "_" #COND "_4s", \ 10068 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \ 10069 MASK_MIPS3D }, \ 10070 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \ 10071 "__builtin_mips_all_" #INSN "_" #COND "_4s", \ 10072 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \ 10073 MASK_MIPS3D } 10074 10075/* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison 10076 instruction requires TARGET_FLAGS. */ 10077#define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \ 10078 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \ 10079 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \ 10080 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \ 10081 TARGET_FLAGS }, \ 10082 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \ 10083 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \ 10084 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \ 10085 TARGET_FLAGS } 10086 10087/* Define all the builtins related to c.cond.fmt condition COND. */ 10088#define CMP_BUILTINS(COND) \ 10089 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \ 10090 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \ 10091 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \ 10092 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \ 10093 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \ 10094 CMP_4S_BUILTINS (c, COND), \ 10095 CMP_4S_BUILTINS (cabs, COND) 10096 10097static const struct builtin_description mips_bdesc[] = 10098{ 10099 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT), 10100 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT), 10101 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT), 10102 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT), 10103 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT), 10104 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT), 10105 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT), 10106 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT), 10107 10108 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, 10109 MASK_PAIRED_SINGLE_FLOAT), 10110 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D), 10111 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D), 10112 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D), 10113 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D), 10114 10115 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D), 10116 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D), 10117 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D), 10118 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D), 10119 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D), 10120 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D), 10121 10122 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D), 10123 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D), 10124 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D), 10125 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D), 10126 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D), 10127 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D), 10128 10129 MIPS_FP_CONDITIONS (CMP_BUILTINS) 10130}; 10131 10132/* Builtin functions for the SB-1 processor. */ 10133 10134#define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2 10135 10136static const struct builtin_description sb1_bdesc[] = 10137{ 10138 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT) 10139}; 10140 10141/* Builtin functions for DSP ASE. */ 10142 10143#define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3 10144#define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3 10145#define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3 10146#define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3 10147 10148/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction 10149 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are 10150 builtin_description fields. */ 10151#define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \ 10152 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \ 10153 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS } 10154 10155/* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP 10156 branch instruction. TARGET_FLAGS is a builtin_description field. */ 10157#define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \ 10158 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \ 10159 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS } 10160 10161static const struct builtin_description dsp_bdesc[] = 10162{ 10163 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP), 10164 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP), 10165 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP), 10166 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP), 10167 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP), 10168 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP), 10169 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP), 10170 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP), 10171 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP), 10172 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP), 10173 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP), 10174 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP), 10175 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP), 10176 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP), 10177 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP), 10178 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP), 10179 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP), 10180 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP), 10181 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP), 10182 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP), 10183 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP), 10184 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP), 10185 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP), 10186 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP), 10187 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP), 10188 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP), 10189 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP), 10190 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP), 10191 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP), 10192 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP), 10193 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP), 10194 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP), 10195 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP), 10196 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP), 10197 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP), 10198 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP), 10199 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP), 10200 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP), 10201 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP), 10202 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP), 10203 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP), 10204 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP), 10205 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP), 10206 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP), 10207 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP), 10208 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP), 10209 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP), 10210 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP), 10211 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP), 10212 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP), 10213 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP), 10214 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP), 10215 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP), 10216 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP), 10217 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP), 10218 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP), 10219 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP), 10220 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP), 10221 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP), 10222 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP), 10223 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP), 10224 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP), 10225 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP), 10226 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP), 10227 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP), 10228 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP), 10229 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP), 10230 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP), 10231 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP), 10232 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP), 10233 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP), 10234 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP), 10235 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP), 10236 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP), 10237 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP), 10238 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP), 10239 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP), 10240 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP), 10241 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP), 10242 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP), 10243 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP), 10244 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP), 10245 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP), 10246 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP), 10247 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP), 10248 BPOSGE_BUILTIN (32, MASK_DSP) 10249}; 10250 10251/* This helps provide a mapping from builtin function codes to bdesc 10252 arrays. */ 10253 10254struct bdesc_map 10255{ 10256 /* The builtin function table that this entry describes. */ 10257 const struct builtin_description *bdesc; 10258 10259 /* The number of entries in the builtin function table. */ 10260 unsigned int size; 10261 10262 /* The target processor that supports these builtin functions. 10263 PROCESSOR_MAX means we enable them for all processors. */ 10264 enum processor_type proc; 10265}; 10266 10267static const struct bdesc_map bdesc_arrays[] = 10268{ 10269 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX }, 10270 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 }, 10271 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX } 10272}; 10273 10274/* Take the head of argument list *ARGLIST and convert it into a form 10275 suitable for input operand OP of instruction ICODE. Return the value 10276 and point *ARGLIST at the next element of the list. */ 10277 10278static rtx 10279mips_prepare_builtin_arg (enum insn_code icode, 10280 unsigned int op, tree *arglist) 10281{ 10282 rtx value; 10283 enum machine_mode mode; 10284 10285 value = expand_normal (TREE_VALUE (*arglist)); 10286 mode = insn_data[icode].operand[op].mode; 10287 if (!insn_data[icode].operand[op].predicate (value, mode)) 10288 { 10289 value = copy_to_mode_reg (mode, value); 10290 /* Check the predicate again. */ 10291 if (!insn_data[icode].operand[op].predicate (value, mode)) 10292 { 10293 error ("invalid argument to builtin function"); 10294 return const0_rtx; 10295 } 10296 } 10297 10298 *arglist = TREE_CHAIN (*arglist); 10299 return value; 10300} 10301 10302/* Return an rtx suitable for output operand OP of instruction ICODE. 10303 If TARGET is non-null, try to use it where possible. */ 10304 10305static rtx 10306mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target) 10307{ 10308 enum machine_mode mode; 10309 10310 mode = insn_data[icode].operand[op].mode; 10311 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode)) 10312 target = gen_reg_rtx (mode); 10313 10314 return target; 10315} 10316 10317/* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */ 10318 10319rtx 10320mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, 10321 enum machine_mode mode ATTRIBUTE_UNUSED, 10322 int ignore ATTRIBUTE_UNUSED) 10323{ 10324 enum insn_code icode; 10325 enum mips_builtin_type type; 10326 tree fndecl, arglist; 10327 unsigned int fcode; 10328 const struct builtin_description *bdesc; 10329 const struct bdesc_map *m; 10330 10331 fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); 10332 arglist = TREE_OPERAND (exp, 1); 10333 fcode = DECL_FUNCTION_CODE (fndecl); 10334 10335 bdesc = NULL; 10336 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++) 10337 { 10338 if (fcode < m->size) 10339 { 10340 bdesc = m->bdesc; 10341 icode = bdesc[fcode].icode; 10342 type = bdesc[fcode].builtin_type; 10343 break; 10344 } 10345 fcode -= m->size; 10346 } 10347 if (bdesc == NULL) 10348 return 0; 10349 10350 switch (type) 10351 { 10352 case MIPS_BUILTIN_DIRECT: 10353 return mips_expand_builtin_direct (icode, target, arglist, true); 10354 10355 case MIPS_BUILTIN_DIRECT_NO_TARGET: 10356 return mips_expand_builtin_direct (icode, target, arglist, false); 10357 10358 case MIPS_BUILTIN_MOVT: 10359 case MIPS_BUILTIN_MOVF: 10360 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond, 10361 target, arglist); 10362 10363 case MIPS_BUILTIN_CMP_ANY: 10364 case MIPS_BUILTIN_CMP_ALL: 10365 case MIPS_BUILTIN_CMP_UPPER: 10366 case MIPS_BUILTIN_CMP_LOWER: 10367 case MIPS_BUILTIN_CMP_SINGLE: 10368 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond, 10369 target, arglist); 10370 10371 case MIPS_BUILTIN_BPOSGE32: 10372 return mips_expand_builtin_bposge (type, target); 10373 10374 default: 10375 return 0; 10376 } 10377} 10378 10379/* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */ 10380 10381void 10382mips_init_builtins (void) 10383{ 10384 const struct builtin_description *d; 10385 const struct bdesc_map *m; 10386 tree types[(int) MIPS_MAX_FTYPE_MAX]; 10387 tree V2SF_type_node; 10388 tree V2HI_type_node; 10389 tree V4QI_type_node; 10390 unsigned int offset; 10391 10392 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */ 10393 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP) 10394 return; 10395 10396 if (TARGET_PAIRED_SINGLE_FLOAT) 10397 { 10398 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode); 10399 10400 types[MIPS_V2SF_FTYPE_V2SF] 10401 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE); 10402 10403 types[MIPS_V2SF_FTYPE_V2SF_V2SF] 10404 = build_function_type_list (V2SF_type_node, 10405 V2SF_type_node, V2SF_type_node, NULL_TREE); 10406 10407 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT] 10408 = build_function_type_list (V2SF_type_node, 10409 V2SF_type_node, V2SF_type_node, 10410 integer_type_node, NULL_TREE); 10411 10412 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF] 10413 = build_function_type_list (V2SF_type_node, 10414 V2SF_type_node, V2SF_type_node, 10415 V2SF_type_node, V2SF_type_node, NULL_TREE); 10416 10417 types[MIPS_V2SF_FTYPE_SF_SF] 10418 = build_function_type_list (V2SF_type_node, 10419 float_type_node, float_type_node, NULL_TREE); 10420 10421 types[MIPS_INT_FTYPE_V2SF_V2SF] 10422 = build_function_type_list (integer_type_node, 10423 V2SF_type_node, V2SF_type_node, NULL_TREE); 10424 10425 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF] 10426 = build_function_type_list (integer_type_node, 10427 V2SF_type_node, V2SF_type_node, 10428 V2SF_type_node, V2SF_type_node, NULL_TREE); 10429 10430 types[MIPS_INT_FTYPE_SF_SF] 10431 = build_function_type_list (integer_type_node, 10432 float_type_node, float_type_node, NULL_TREE); 10433 10434 types[MIPS_INT_FTYPE_DF_DF] 10435 = build_function_type_list (integer_type_node, 10436 double_type_node, double_type_node, NULL_TREE); 10437 10438 types[MIPS_SF_FTYPE_V2SF] 10439 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE); 10440 10441 types[MIPS_SF_FTYPE_SF] 10442 = build_function_type_list (float_type_node, 10443 float_type_node, NULL_TREE); 10444 10445 types[MIPS_SF_FTYPE_SF_SF] 10446 = build_function_type_list (float_type_node, 10447 float_type_node, float_type_node, NULL_TREE); 10448 10449 types[MIPS_DF_FTYPE_DF] 10450 = build_function_type_list (double_type_node, 10451 double_type_node, NULL_TREE); 10452 10453 types[MIPS_DF_FTYPE_DF_DF] 10454 = build_function_type_list (double_type_node, 10455 double_type_node, double_type_node, NULL_TREE); 10456 } 10457 10458 if (TARGET_DSP) 10459 { 10460 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode); 10461 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode); 10462 10463 types[MIPS_V2HI_FTYPE_V2HI_V2HI] 10464 = build_function_type_list (V2HI_type_node, 10465 V2HI_type_node, V2HI_type_node, 10466 NULL_TREE); 10467 10468 types[MIPS_SI_FTYPE_SI_SI] 10469 = build_function_type_list (intSI_type_node, 10470 intSI_type_node, intSI_type_node, 10471 NULL_TREE); 10472 10473 types[MIPS_V4QI_FTYPE_V4QI_V4QI] 10474 = build_function_type_list (V4QI_type_node, 10475 V4QI_type_node, V4QI_type_node, 10476 NULL_TREE); 10477 10478 types[MIPS_SI_FTYPE_V4QI] 10479 = build_function_type_list (intSI_type_node, 10480 V4QI_type_node, 10481 NULL_TREE); 10482 10483 types[MIPS_V2HI_FTYPE_V2HI] 10484 = build_function_type_list (V2HI_type_node, 10485 V2HI_type_node, 10486 NULL_TREE); 10487 10488 types[MIPS_SI_FTYPE_SI] 10489 = build_function_type_list (intSI_type_node, 10490 intSI_type_node, 10491 NULL_TREE); 10492 10493 types[MIPS_V4QI_FTYPE_V2HI_V2HI] 10494 = build_function_type_list (V4QI_type_node, 10495 V2HI_type_node, V2HI_type_node, 10496 NULL_TREE); 10497 10498 types[MIPS_V2HI_FTYPE_SI_SI] 10499 = build_function_type_list (V2HI_type_node, 10500 intSI_type_node, intSI_type_node, 10501 NULL_TREE); 10502 10503 types[MIPS_SI_FTYPE_V2HI] 10504 = build_function_type_list (intSI_type_node, 10505 V2HI_type_node, 10506 NULL_TREE); 10507 10508 types[MIPS_V2HI_FTYPE_V4QI] 10509 = build_function_type_list (V2HI_type_node, 10510 V4QI_type_node, 10511 NULL_TREE); 10512 10513 types[MIPS_V4QI_FTYPE_V4QI_SI] 10514 = build_function_type_list (V4QI_type_node, 10515 V4QI_type_node, intSI_type_node, 10516 NULL_TREE); 10517 10518 types[MIPS_V2HI_FTYPE_V2HI_SI] 10519 = build_function_type_list (V2HI_type_node, 10520 V2HI_type_node, intSI_type_node, 10521 NULL_TREE); 10522 10523 types[MIPS_V2HI_FTYPE_V4QI_V2HI] 10524 = build_function_type_list (V2HI_type_node, 10525 V4QI_type_node, V2HI_type_node, 10526 NULL_TREE); 10527 10528 types[MIPS_SI_FTYPE_V2HI_V2HI] 10529 = build_function_type_list (intSI_type_node, 10530 V2HI_type_node, V2HI_type_node, 10531 NULL_TREE); 10532 10533 types[MIPS_DI_FTYPE_DI_V4QI_V4QI] 10534 = build_function_type_list (intDI_type_node, 10535 intDI_type_node, V4QI_type_node, V4QI_type_node, 10536 NULL_TREE); 10537 10538 types[MIPS_DI_FTYPE_DI_V2HI_V2HI] 10539 = build_function_type_list (intDI_type_node, 10540 intDI_type_node, V2HI_type_node, V2HI_type_node, 10541 NULL_TREE); 10542 10543 types[MIPS_DI_FTYPE_DI_SI_SI] 10544 = build_function_type_list (intDI_type_node, 10545 intDI_type_node, intSI_type_node, intSI_type_node, 10546 NULL_TREE); 10547 10548 types[MIPS_V4QI_FTYPE_SI] 10549 = build_function_type_list (V4QI_type_node, 10550 intSI_type_node, 10551 NULL_TREE); 10552 10553 types[MIPS_V2HI_FTYPE_SI] 10554 = build_function_type_list (V2HI_type_node, 10555 intSI_type_node, 10556 NULL_TREE); 10557 10558 types[MIPS_VOID_FTYPE_V4QI_V4QI] 10559 = build_function_type_list (void_type_node, 10560 V4QI_type_node, V4QI_type_node, 10561 NULL_TREE); 10562 10563 types[MIPS_SI_FTYPE_V4QI_V4QI] 10564 = build_function_type_list (intSI_type_node, 10565 V4QI_type_node, V4QI_type_node, 10566 NULL_TREE); 10567 10568 types[MIPS_VOID_FTYPE_V2HI_V2HI] 10569 = build_function_type_list (void_type_node, 10570 V2HI_type_node, V2HI_type_node, 10571 NULL_TREE); 10572 10573 types[MIPS_SI_FTYPE_DI_SI] 10574 = build_function_type_list (intSI_type_node, 10575 intDI_type_node, intSI_type_node, 10576 NULL_TREE); 10577 10578 types[MIPS_DI_FTYPE_DI_SI] 10579 = build_function_type_list (intDI_type_node, 10580 intDI_type_node, intSI_type_node, 10581 NULL_TREE); 10582 10583 types[MIPS_VOID_FTYPE_SI_SI] 10584 = build_function_type_list (void_type_node, 10585 intSI_type_node, intSI_type_node, 10586 NULL_TREE); 10587 10588 types[MIPS_SI_FTYPE_PTR_SI] 10589 = build_function_type_list (intSI_type_node, 10590 ptr_type_node, intSI_type_node, 10591 NULL_TREE); 10592 10593 types[MIPS_SI_FTYPE_VOID] 10594 = build_function_type (intSI_type_node, void_list_node); 10595 } 10596 10597 /* Iterate through all of the bdesc arrays, initializing all of the 10598 builtin functions. */ 10599 10600 offset = 0; 10601 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++) 10602 { 10603 if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch)) 10604 for (d = m->bdesc; d < &m->bdesc[m->size]; d++) 10605 if ((d->target_flags & target_flags) == d->target_flags) 10606 lang_hooks.builtin_function (d->name, types[d->function_type], 10607 d - m->bdesc + offset, 10608 BUILT_IN_MD, NULL, NULL); 10609 offset += m->size; 10610 } 10611} 10612 10613/* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the 10614 .md pattern and ARGLIST is the list of function arguments. TARGET, 10615 if nonnull, suggests a good place to put the result. 10616 HAS_TARGET indicates the function must return something. */ 10617 10618static rtx 10619mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist, 10620 bool has_target) 10621{ 10622 rtx ops[MAX_RECOG_OPERANDS]; 10623 int i = 0; 10624 10625 if (has_target) 10626 { 10627 /* We save target to ops[0]. */ 10628 ops[0] = mips_prepare_builtin_target (icode, 0, target); 10629 i = 1; 10630 } 10631 10632 /* We need to test if arglist is not zero. Some instructions have extra 10633 clobber registers. */ 10634 for (; i < insn_data[icode].n_operands && arglist != 0; i++) 10635 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist); 10636 10637 switch (i) 10638 { 10639 case 2: 10640 emit_insn (GEN_FCN (icode) (ops[0], ops[1])); 10641 break; 10642 10643 case 3: 10644 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2])); 10645 break; 10646 10647 case 4: 10648 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3])); 10649 break; 10650 10651 default: 10652 gcc_unreachable (); 10653 } 10654 return target; 10655} 10656 10657/* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps() 10658 function (TYPE says which). ARGLIST is the list of arguments to the 10659 function, ICODE is the instruction that should be used to compare 10660 the first two arguments, and COND is the condition it should test. 10661 TARGET, if nonnull, suggests a good place to put the result. */ 10662 10663static rtx 10664mips_expand_builtin_movtf (enum mips_builtin_type type, 10665 enum insn_code icode, enum mips_fp_condition cond, 10666 rtx target, tree arglist) 10667{ 10668 rtx cmp_result, op0, op1; 10669 10670 cmp_result = mips_prepare_builtin_target (icode, 0, 0); 10671 op0 = mips_prepare_builtin_arg (icode, 1, &arglist); 10672 op1 = mips_prepare_builtin_arg (icode, 2, &arglist); 10673 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond))); 10674 10675 icode = CODE_FOR_mips_cond_move_tf_ps; 10676 target = mips_prepare_builtin_target (icode, 0, target); 10677 if (type == MIPS_BUILTIN_MOVT) 10678 { 10679 op1 = mips_prepare_builtin_arg (icode, 2, &arglist); 10680 op0 = mips_prepare_builtin_arg (icode, 1, &arglist); 10681 } 10682 else 10683 { 10684 op0 = mips_prepare_builtin_arg (icode, 1, &arglist); 10685 op1 = mips_prepare_builtin_arg (icode, 2, &arglist); 10686 } 10687 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result)); 10688 return target; 10689} 10690 10691/* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE 10692 into TARGET otherwise. Return TARGET. */ 10693 10694static rtx 10695mips_builtin_branch_and_move (rtx condition, rtx target, 10696 rtx value_if_true, rtx value_if_false) 10697{ 10698 rtx true_label, done_label; 10699 10700 true_label = gen_label_rtx (); 10701 done_label = gen_label_rtx (); 10702 10703 /* First assume that CONDITION is false. */ 10704 emit_move_insn (target, value_if_false); 10705 10706 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */ 10707 emit_jump_insn (gen_condjump (condition, true_label)); 10708 emit_jump_insn (gen_jump (done_label)); 10709 emit_barrier (); 10710 10711 /* Fix TARGET if CONDITION is true. */ 10712 emit_label (true_label); 10713 emit_move_insn (target, value_if_true); 10714 10715 emit_label (done_label); 10716 return target; 10717} 10718 10719/* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code 10720 of the comparison instruction and COND is the condition it should test. 10721 ARGLIST is the list of function arguments and TARGET, if nonnull, 10722 suggests a good place to put the boolean result. */ 10723 10724static rtx 10725mips_expand_builtin_compare (enum mips_builtin_type builtin_type, 10726 enum insn_code icode, enum mips_fp_condition cond, 10727 rtx target, tree arglist) 10728{ 10729 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS]; 10730 int i; 10731 10732 if (target == 0 || GET_MODE (target) != SImode) 10733 target = gen_reg_rtx (SImode); 10734 10735 /* Prepare the operands to the comparison. */ 10736 cmp_result = mips_prepare_builtin_target (icode, 0, 0); 10737 for (i = 1; i < insn_data[icode].n_operands - 1; i++) 10738 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist); 10739 10740 switch (insn_data[icode].n_operands) 10741 { 10742 case 4: 10743 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond))); 10744 break; 10745 10746 case 6: 10747 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], 10748 ops[3], ops[4], GEN_INT (cond))); 10749 break; 10750 10751 default: 10752 gcc_unreachable (); 10753 } 10754 10755 /* If the comparison sets more than one register, we define the result 10756 to be 0 if all registers are false and -1 if all registers are true. 10757 The value of the complete result is indeterminate otherwise. */ 10758 switch (builtin_type) 10759 { 10760 case MIPS_BUILTIN_CMP_ALL: 10761 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx); 10762 return mips_builtin_branch_and_move (condition, target, 10763 const0_rtx, const1_rtx); 10764 10765 case MIPS_BUILTIN_CMP_UPPER: 10766 case MIPS_BUILTIN_CMP_LOWER: 10767 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER); 10768 condition = gen_single_cc (cmp_result, offset); 10769 return mips_builtin_branch_and_move (condition, target, 10770 const1_rtx, const0_rtx); 10771 10772 default: 10773 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx); 10774 return mips_builtin_branch_and_move (condition, target, 10775 const1_rtx, const0_rtx); 10776 } 10777} 10778 10779/* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull, 10780 suggests a good place to put the boolean result. */ 10781 10782static rtx 10783mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target) 10784{ 10785 rtx condition, cmp_result; 10786 int cmp_value; 10787 10788 if (target == 0 || GET_MODE (target) != SImode) 10789 target = gen_reg_rtx (SImode); 10790 10791 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM); 10792 10793 if (builtin_type == MIPS_BUILTIN_BPOSGE32) 10794 cmp_value = 32; 10795 else 10796 gcc_assert (0); 10797 10798 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value)); 10799 return mips_builtin_branch_and_move (condition, target, 10800 const1_rtx, const0_rtx); 10801} 10802 10803/* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL. 10804 FIRST is true if this is the first time handling this decl. */ 10805 10806static void 10807mips_encode_section_info (tree decl, rtx rtl, int first) 10808{ 10809 default_encode_section_info (decl, rtl, first); 10810 10811 if (TREE_CODE (decl) == FUNCTION_DECL 10812 && lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) 10813 { 10814 rtx symbol = XEXP (rtl, 0); 10815 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL; 10816 } 10817} 10818 10819/* Implement TARGET_EXTRA_LIVE_ON_ENTRY. PIC_FUNCTION_ADDR_REGNUM is live 10820 on entry to a function when generating -mshared abicalls code. */ 10821 10822static void 10823mips_extra_live_on_entry (bitmap regs) 10824{ 10825 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) 10826 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM); 10827} 10828 10829/* SImode values are represented as sign-extended to DImode. */ 10830 10831int 10832mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep) 10833{ 10834 if (TARGET_64BIT && mode == SImode && mode_rep == DImode) 10835 return SIGN_EXTEND; 10836 10837 return UNKNOWN; 10838} 10839 10840#include "gt-mips.h" 10841