vect.md revision 267654
1;; IA-64 machine description for vector operations. 2;; Copyright (C) 2004, 2005 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 2, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING. If not, write to 18;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 19;; Boston, MA 02110-1301, USA. 20 21 22;; Integer vector operations 23 24(define_mode_macro VECINT [V8QI V4HI V2SI]) 25(define_mode_macro VECINT12 [V8QI V4HI]) 26(define_mode_macro VECINT24 [V4HI V2SI]) 27(define_mode_attr vecsize [(V8QI "1") (V4HI "2") (V2SI "4")]) 28 29(define_expand "mov<mode>" 30 [(set (match_operand:VECINT 0 "general_operand" "") 31 (match_operand:VECINT 1 "general_operand" ""))] 32 "" 33{ 34 rtx op1 = ia64_expand_move (operands[0], operands[1]); 35 if (!op1) 36 DONE; 37 operands[1] = op1; 38}) 39 40(define_insn "*mov<mode>_internal" 41 [(set (match_operand:VECINT 0 "destination_operand" 42 "=r,r,r,r,m ,*f ,*f,Q ,r ,*f") 43 (match_operand:VECINT 1 "move_operand" 44 "rU,W,i,m,rU,U*f,Q ,*f,*f,r "))] 45 "ia64_move_ok (operands[0], operands[1])" 46 "@ 47 mov %0 = %r1 48 addl %0 = %v1, r0 49 movl %0 = %v1 50 ld8%O1 %0 = %1%P1 51 st8%Q0 %0 = %r1%P0 52 mov %0 = %F1 53 ldf8 %0 = %1%P1 54 stf8 %0 = %1%P0 55 getf.sig %0 = %1 56 setf.sig %0 = %1" 57 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,fmisc,fld,stf,frfr,tofr")]) 58 59(define_insn "one_cmpl<mode>2" 60 [(set (match_operand:VECINT 0 "gr_register_operand" "=r") 61 (not:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")))] 62 "" 63 "andcm %0 = -1, %1" 64 [(set_attr "itanium_class" "ilog")]) 65 66(define_insn "and<mode>3" 67 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f") 68 (and:VECINT 69 (match_operand:VECINT 1 "grfr_register_operand" "r,*f") 70 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))] 71 "" 72 "@ 73 and %0 = %2, %1 74 fand %0 = %2, %1" 75 [(set_attr "itanium_class" "ilog,fmisc")]) 76 77(define_insn "*andnot<mode>" 78 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f") 79 (and:VECINT 80 (not:VECINT (match_operand:VECINT 1 "grfr_register_operand" "r,*f")) 81 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))] 82 "" 83 "@ 84 andcm %0 = %2, %1 85 fandcm %0 = %2, %1" 86 [(set_attr "itanium_class" "ilog,fmisc")]) 87 88(define_insn "ior<mode>3" 89 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f") 90 (ior:VECINT 91 (match_operand:VECINT 1 "grfr_register_operand" "r,*f") 92 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))] 93 "" 94 "@ 95 or %0 = %2, %1 96 for %0 = %2, %1" 97 [(set_attr "itanium_class" "ilog,fmisc")]) 98 99(define_insn "xor<mode>3" 100 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f") 101 (xor:VECINT 102 (match_operand:VECINT 1 "grfr_register_operand" "r,*f") 103 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))] 104 "" 105 "@ 106 xor %0 = %2, %1 107 fxor %0 = %2, %1" 108 [(set_attr "itanium_class" "ilog,fmisc")]) 109 110(define_insn "neg<mode>2" 111 [(set (match_operand:VECINT 0 "gr_register_operand" "=r") 112 (neg:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")))] 113 "" 114 "psub<vecsize> %0 = r0, %1" 115 [(set_attr "itanium_class" "mmalua")]) 116 117(define_insn "add<mode>3" 118 [(set (match_operand:VECINT 0 "gr_register_operand" "=r") 119 (plus:VECINT (match_operand:VECINT 1 "gr_register_operand" "r") 120 (match_operand:VECINT 2 "gr_register_operand" "r")))] 121 "" 122 "padd<vecsize> %0 = %1, %2" 123 [(set_attr "itanium_class" "mmalua")]) 124 125(define_insn "*ssadd<mode>3" 126 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r") 127 (ss_plus:VECINT12 128 (match_operand:VECINT12 1 "gr_register_operand" "r") 129 (match_operand:VECINT12 2 "gr_register_operand" "r")))] 130 "" 131 "padd<vecsize>.sss %0 = %1, %2" 132 [(set_attr "itanium_class" "mmalua")]) 133 134(define_insn "*usadd<mode>3" 135 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r") 136 (us_plus:VECINT12 137 (match_operand:VECINT12 1 "gr_register_operand" "r") 138 (match_operand:VECINT12 2 "gr_register_operand" "r")))] 139 "" 140 "padd<vecsize>.uuu %0 = %1, %2" 141 [(set_attr "itanium_class" "mmalua")]) 142 143(define_insn "sub<mode>3" 144 [(set (match_operand:VECINT 0 "gr_register_operand" "=r") 145 (minus:VECINT (match_operand:VECINT 1 "gr_register_operand" "r") 146 (match_operand:VECINT 2 "gr_register_operand" "r")))] 147 "" 148 "psub<vecsize> %0 = %1, %2" 149 [(set_attr "itanium_class" "mmalua")]) 150 151(define_insn "*sssub<mode>3" 152 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r") 153 (ss_minus:VECINT12 154 (match_operand:VECINT12 1 "gr_register_operand" "r") 155 (match_operand:VECINT12 2 "gr_register_operand" "r")))] 156 "" 157 "psub<vecsize>.sss %0 = %1, %2" 158 [(set_attr "itanium_class" "mmalua")]) 159 160(define_insn "*ussub<mode>3" 161 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r") 162 (us_minus:VECINT12 163 (match_operand:VECINT12 1 "gr_register_operand" "r") 164 (match_operand:VECINT12 2 "gr_register_operand" "r")))] 165 "" 166 "psub<vecsize>.uuu %0 = %1, %2" 167 [(set_attr "itanium_class" "mmalua")]) 168 169(define_expand "mulv8qi3" 170 [(set (match_operand:V8QI 0 "gr_register_operand" "") 171 (mult:V8QI (match_operand:V8QI 1 "gr_register_operand" "r") 172 (match_operand:V8QI 2 "gr_register_operand" "r")))] 173 "" 174{ 175 rtx r1, l1, r2, l2, rm, lm; 176 177 r1 = gen_reg_rtx (V4HImode); 178 l1 = gen_reg_rtx (V4HImode); 179 r2 = gen_reg_rtx (V4HImode); 180 l2 = gen_reg_rtx (V4HImode); 181 182 /* Zero-extend the QImode elements into two words of HImode elements 183 by interleaving them with zero bytes. */ 184 emit_insn (gen_mix1_r (gen_lowpart (V8QImode, r1), 185 operands[1], CONST0_RTX (V8QImode))); 186 emit_insn (gen_mix1_r (gen_lowpart (V8QImode, r2), 187 operands[2], CONST0_RTX (V8QImode))); 188 emit_insn (gen_mix1_l (gen_lowpart (V8QImode, l1), 189 operands[1], CONST0_RTX (V8QImode))); 190 emit_insn (gen_mix1_l (gen_lowpart (V8QImode, l2), 191 operands[2], CONST0_RTX (V8QImode))); 192 193 /* Multiply. */ 194 rm = gen_reg_rtx (V4HImode); 195 lm = gen_reg_rtx (V4HImode); 196 emit_insn (gen_mulv4hi3 (rm, r1, r2)); 197 emit_insn (gen_mulv4hi3 (lm, l1, l2)); 198 199 /* Zap the high order bytes of the HImode elements by overwriting those 200 in one part with the low order bytes of the other. */ 201 emit_insn (gen_mix1_r (operands[0], 202 gen_lowpart (V8QImode, rm), 203 gen_lowpart (V8QImode, lm))); 204 DONE; 205}) 206 207(define_insn "mulv4hi3" 208 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") 209 (mult:V4HI (match_operand:V4HI 1 "gr_register_operand" "r") 210 (match_operand:V4HI 2 "gr_register_operand" "r")))] 211 "" 212 "pmpyshr2 %0 = %1, %2, 0" 213 [(set_attr "itanium_class" "mmmul")]) 214 215(define_insn "pmpy2_r" 216 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") 217 (mult:V2SI 218 (vec_select:V2SI 219 (sign_extend:V4SI 220 (match_operand:V4HI 1 "gr_register_operand" "r")) 221 (parallel [(const_int 0) (const_int 2)])) 222 (vec_select:V2SI 223 (sign_extend:V4SI 224 (match_operand:V4HI 2 "gr_register_operand" "r")) 225 (parallel [(const_int 0) (const_int 2)]))))] 226 "" 227 "pmpy2.r %0 = %1, %2" 228 [(set_attr "itanium_class" "mmshf")]) 229 230(define_insn "pmpy2_l" 231 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") 232 (mult:V2SI 233 (vec_select:V2SI 234 (sign_extend:V4SI 235 (match_operand:V4HI 1 "gr_register_operand" "r")) 236 (parallel [(const_int 1) (const_int 3)])) 237 (vec_select:V2SI 238 (sign_extend:V4SI 239 (match_operand:V4HI 2 "gr_register_operand" "r")) 240 (parallel [(const_int 1) (const_int 3)]))))] 241 "" 242 "pmpy2.l %0 = %1, %2" 243 [(set_attr "itanium_class" "mmshf")]) 244 245(define_expand "umax<mode>3" 246 [(set (match_operand:VECINT 0 "gr_register_operand" "") 247 (umax:VECINT (match_operand:VECINT 1 "gr_register_operand" "") 248 (match_operand:VECINT 2 "gr_register_operand" "")))] 249 "" 250{ 251 if (ia64_expand_vecint_minmax (UMAX, <MODE>mode, operands)) 252 DONE; 253}) 254 255(define_expand "smax<mode>3" 256 [(set (match_operand:VECINT 0 "gr_register_operand" "") 257 (smax:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "") 258 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))] 259 "" 260{ 261 if (ia64_expand_vecint_minmax (SMAX, <MODE>mode, operands)) 262 DONE; 263}) 264 265(define_expand "umin<mode>3" 266 [(set (match_operand:VECINT 0 "gr_register_operand" "") 267 (umin:VECINT (match_operand:VECINT 1 "gr_register_operand" "") 268 (match_operand:VECINT 2 "gr_register_operand" "")))] 269 "" 270{ 271 if (ia64_expand_vecint_minmax (UMIN, <MODE>mode, operands)) 272 DONE; 273}) 274 275(define_expand "smin<mode>3" 276 [(set (match_operand:VECINT 0 "gr_register_operand" "") 277 (smin:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "") 278 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))] 279 "" 280{ 281 if (ia64_expand_vecint_minmax (SMIN, <MODE>mode, operands)) 282 DONE; 283}) 284 285(define_insn "*umaxv8qi3" 286 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 287 (umax:V8QI (match_operand:V8QI 1 "gr_register_operand" "r") 288 (match_operand:V8QI 2 "gr_register_operand" "r")))] 289 "" 290 "pmax1.u %0 = %1, %2" 291 [(set_attr "itanium_class" "mmshf")]) 292 293(define_insn "*smaxv4hi3" 294 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") 295 (smax:V4HI (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") 296 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")))] 297 "" 298 "pmax2 %0 = %r1, %r2" 299 [(set_attr "itanium_class" "mmshf")]) 300 301(define_insn "*uminv8qi3" 302 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 303 (umin:V8QI (match_operand:V8QI 1 "gr_register_operand" "r") 304 (match_operand:V8QI 2 "gr_register_operand" "r")))] 305 "" 306 "pmin1.u %0 = %1, %2" 307 [(set_attr "itanium_class" "mmshf")]) 308 309(define_insn "*sminv4hi3" 310 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") 311 (smin:V4HI (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") 312 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")))] 313 "" 314 "pmin2 %0 = %r1, %r2" 315 [(set_attr "itanium_class" "mmshf")]) 316 317(define_insn "ashl<mode>3" 318 [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") 319 (ashift:VECINT24 320 (match_operand:VECINT24 1 "gr_register_operand" "r") 321 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] 322 "" 323 "pshl<vecsize> %0 = %1, %2" 324 [(set_attr "itanium_class" "mmshf")]) 325 326(define_insn "ashr<mode>3" 327 [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") 328 (ashiftrt:VECINT24 329 (match_operand:VECINT24 1 "gr_register_operand" "r") 330 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] 331 "" 332 "pshr<vecsize> %0 = %1, %2" 333 [(set_attr "itanium_class" "mmshf")]) 334 335(define_insn "lshr<mode>3" 336 [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") 337 (lshiftrt:VECINT24 338 (match_operand:VECINT24 1 "gr_register_operand" "r") 339 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] 340 "" 341 "pshr<vecsize>.u %0 = %1, %2" 342 [(set_attr "itanium_class" "mmshf")]) 343 344(define_expand "vec_shl_<mode>" 345 [(set (match_operand:VECINT 0 "gr_register_operand" "") 346 (ashift:DI (match_operand:VECINT 1 "gr_register_operand" "") 347 (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))] 348 "" 349{ 350 operands[0] = gen_lowpart (DImode, operands[0]); 351 operands[1] = gen_lowpart (DImode, operands[1]); 352}) 353 354(define_expand "vec_shr_<mode>" 355 [(set (match_operand:VECINT 0 "gr_register_operand" "") 356 (lshiftrt:DI (match_operand:VECINT 1 "gr_register_operand" "") 357 (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))] 358 "" 359{ 360 operands[0] = gen_lowpart (DImode, operands[0]); 361 operands[1] = gen_lowpart (DImode, operands[1]); 362}) 363 364(define_expand "widen_usumv8qi3" 365 [(match_operand:V4HI 0 "gr_register_operand" "") 366 (match_operand:V8QI 1 "gr_register_operand" "") 367 (match_operand:V4HI 2 "gr_register_operand" "")] 368 "" 369{ 370 ia64_expand_widen_sum (operands, true); 371 DONE; 372}) 373 374(define_expand "widen_usumv4hi3" 375 [(match_operand:V2SI 0 "gr_register_operand" "") 376 (match_operand:V4HI 1 "gr_register_operand" "") 377 (match_operand:V2SI 2 "gr_register_operand" "")] 378 "" 379{ 380 ia64_expand_widen_sum (operands, true); 381 DONE; 382}) 383 384(define_expand "widen_ssumv8qi3" 385 [(match_operand:V4HI 0 "gr_register_operand" "") 386 (match_operand:V8QI 1 "gr_register_operand" "") 387 (match_operand:V4HI 2 "gr_register_operand" "")] 388 "" 389{ 390 ia64_expand_widen_sum (operands, false); 391 DONE; 392}) 393 394(define_expand "widen_ssumv4hi3" 395 [(match_operand:V2SI 0 "gr_register_operand" "") 396 (match_operand:V4HI 1 "gr_register_operand" "") 397 (match_operand:V2SI 2 "gr_register_operand" "")] 398 "" 399{ 400 ia64_expand_widen_sum (operands, false); 401 DONE; 402}) 403 404(define_expand "udot_prodv8qi" 405 [(match_operand:V2SI 0 "gr_register_operand" "") 406 (match_operand:V8QI 1 "gr_register_operand" "") 407 (match_operand:V8QI 2 "gr_register_operand" "") 408 (match_operand:V2SI 3 "gr_register_operand" "")] 409 "" 410{ 411 ia64_expand_dot_prod_v8qi (operands, true); 412 DONE; 413}) 414 415(define_expand "sdot_prodv8qi" 416 [(match_operand:V2SI 0 "gr_register_operand" "") 417 (match_operand:V8QI 1 "gr_register_operand" "") 418 (match_operand:V8QI 2 "gr_register_operand" "") 419 (match_operand:V2SI 3 "gr_register_operand" "")] 420 "" 421{ 422 ia64_expand_dot_prod_v8qi (operands, false); 423 DONE; 424}) 425 426(define_expand "sdot_prodv4hi" 427 [(match_operand:V2SI 0 "gr_register_operand" "") 428 (match_operand:V4HI 1 "gr_register_operand" "") 429 (match_operand:V4HI 2 "gr_register_operand" "") 430 (match_operand:V2SI 3 "gr_register_operand" "")] 431 "" 432{ 433 rtx l, r, t; 434 435 r = gen_reg_rtx (V2SImode); 436 l = gen_reg_rtx (V2SImode); 437 t = gen_reg_rtx (V2SImode); 438 439 emit_insn (gen_pmpy2_r (r, operands[1], operands[2])); 440 emit_insn (gen_pmpy2_l (l, operands[1], operands[2])); 441 emit_insn (gen_addv2si3 (t, r, operands[3])); 442 emit_insn (gen_addv2si3 (operands[0], t, l)); 443 DONE; 444}) 445 446(define_expand "vcond<mode>" 447 [(set (match_operand:VECINT 0 "gr_register_operand" "") 448 (if_then_else:VECINT 449 (match_operator 3 "" 450 [(match_operand:VECINT 4 "gr_reg_or_0_operand" "") 451 (match_operand:VECINT 5 "gr_reg_or_0_operand" "")]) 452 (match_operand:VECINT 1 "gr_reg_or_0_operand" "") 453 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))] 454 "" 455{ 456 ia64_expand_vecint_cmov (operands); 457 DONE; 458}) 459 460(define_expand "vcondu<mode>" 461 [(set (match_operand:VECINT 0 "gr_register_operand" "") 462 (if_then_else:VECINT 463 (match_operator 3 "" 464 [(match_operand:VECINT 4 "gr_reg_or_0_operand" "") 465 (match_operand:VECINT 5 "gr_reg_or_0_operand" "")]) 466 (match_operand:VECINT 1 "gr_reg_or_0_operand" "") 467 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))] 468 "" 469{ 470 ia64_expand_vecint_cmov (operands); 471 DONE; 472}) 473 474(define_insn "*cmpeq_<mode>" 475 [(set (match_operand:VECINT 0 "gr_register_operand" "=r") 476 (eq:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "rU") 477 (match_operand:VECINT 2 "gr_reg_or_0_operand" "rU")))] 478 "" 479 "pcmp<vecsize>.eq %0 = %r1, %r2" 480 [(set_attr "itanium_class" "mmalua")]) 481 482(define_insn "*cmpgt_<mode>" 483 [(set (match_operand:VECINT 0 "gr_register_operand" "=r") 484 (gt:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "rU") 485 (match_operand:VECINT 2 "gr_reg_or_0_operand" "rU")))] 486 "" 487 "pcmp<vecsize>.gt %0 = %r1, %r2" 488 [(set_attr "itanium_class" "mmalua")]) 489 490(define_insn "pack2_sss" 491 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 492 (vec_concat:V8QI 493 (ss_truncate:V4QI 494 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")) 495 (ss_truncate:V4QI 496 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))))] 497 "" 498 "pack2.sss %0 = %r1, %r2" 499 [(set_attr "itanium_class" "mmshf")]) 500 501(define_insn "*pack2_uss" 502 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 503 (vec_concat:V8QI 504 (us_truncate:V4QI 505 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")) 506 (us_truncate:V4QI 507 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))))] 508 "" 509 "pack2.uss %0 = %r1, %r2" 510 [(set_attr "itanium_class" "mmshf")]) 511 512(define_insn "pack4_sss" 513 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") 514 (vec_concat:V4HI 515 (ss_truncate:V2HI 516 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU")) 517 (ss_truncate:V2HI 518 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU"))))] 519 "" 520 "pack4.sss %0 = %r1, %r2" 521 [(set_attr "itanium_class" "mmshf")]) 522 523(define_insn "unpack1_l" 524 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 525 (vec_select:V8QI 526 (vec_concat:V16QI 527 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") 528 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) 529 (parallel [(const_int 0) 530 (const_int 1) 531 (const_int 2) 532 (const_int 3) 533 (const_int 8) 534 (const_int 9) 535 (const_int 10) 536 (const_int 11)])))] 537 "" 538 "unpack1.l %0 = %r2, %r1" 539 [(set_attr "itanium_class" "mmshf")]) 540 541(define_insn "unpack1_h" 542 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 543 (vec_select:V8QI 544 (vec_concat:V16QI 545 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") 546 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) 547 (parallel [(const_int 4) 548 (const_int 5) 549 (const_int 6) 550 (const_int 7) 551 (const_int 12) 552 (const_int 13) 553 (const_int 14) 554 (const_int 15)])))] 555 "" 556 "unpack1.h %0 = %r2, %r1" 557 [(set_attr "itanium_class" "mmshf")]) 558 559(define_insn "mix1_r" 560 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 561 (vec_select:V8QI 562 (vec_concat:V16QI 563 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") 564 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) 565 (parallel [(const_int 0) 566 (const_int 8) 567 (const_int 2) 568 (const_int 10) 569 (const_int 4) 570 (const_int 12) 571 (const_int 6) 572 (const_int 14)])))] 573 "" 574 "mix1.r %0 = %r2, %r1" 575 [(set_attr "itanium_class" "mmshf")]) 576 577(define_insn "mix1_l" 578 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 579 (vec_select:V8QI 580 (vec_concat:V16QI 581 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") 582 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) 583 (parallel [(const_int 1) 584 (const_int 9) 585 (const_int 3) 586 (const_int 11) 587 (const_int 5) 588 (const_int 13) 589 (const_int 7) 590 (const_int 15)])))] 591 "" 592 "mix1.l %0 = %r2, %r1" 593 [(set_attr "itanium_class" "mmshf")]) 594 595(define_insn "*mux1_rev" 596 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 597 (vec_select:V8QI 598 (match_operand:V8QI 1 "gr_register_operand" "r") 599 (parallel [(const_int 7) 600 (const_int 6) 601 (const_int 5) 602 (const_int 4) 603 (const_int 3) 604 (const_int 2) 605 (const_int 1) 606 (const_int 0)])))] 607 "" 608 "mux1 %0 = %1, @rev" 609 [(set_attr "itanium_class" "mmshf")]) 610 611(define_insn "*mux1_mix" 612 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 613 (vec_select:V8QI 614 (match_operand:V8QI 1 "gr_register_operand" "r") 615 (parallel [(const_int 0) 616 (const_int 4) 617 (const_int 2) 618 (const_int 6) 619 (const_int 1) 620 (const_int 5) 621 (const_int 3) 622 (const_int 7)])))] 623 "" 624 "mux1 %0 = %1, @mix" 625 [(set_attr "itanium_class" "mmshf")]) 626 627(define_insn "*mux1_shuf" 628 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 629 (vec_select:V8QI 630 (match_operand:V8QI 1 "gr_register_operand" "r") 631 (parallel [(const_int 0) 632 (const_int 4) 633 (const_int 1) 634 (const_int 5) 635 (const_int 2) 636 (const_int 6) 637 (const_int 3) 638 (const_int 7)])))] 639 "" 640 "mux1 %0 = %1, @shuf" 641 [(set_attr "itanium_class" "mmshf")]) 642 643(define_insn "*mux1_alt" 644 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 645 (vec_select:V8QI 646 (match_operand:V8QI 1 "gr_register_operand" "r") 647 (parallel [(const_int 0) 648 (const_int 2) 649 (const_int 4) 650 (const_int 6) 651 (const_int 1) 652 (const_int 3) 653 (const_int 5) 654 (const_int 7)])))] 655 "" 656 "mux1 %0 = %1, @alt" 657 [(set_attr "itanium_class" "mmshf")]) 658 659(define_insn "*mux1_brcst_v8qi" 660 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 661 (vec_select:V8QI 662 (match_operand:V8QI 1 "gr_register_operand" "r") 663 (parallel [(const_int 0) 664 (const_int 0) 665 (const_int 0) 666 (const_int 0) 667 (const_int 0) 668 (const_int 0) 669 (const_int 0) 670 (const_int 0)])))] 671 "" 672 "mux1 %0 = %1, @brcst" 673 [(set_attr "itanium_class" "mmshf")]) 674 675(define_insn "*mux1_brcst_qi" 676 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") 677 (vec_duplicate:V8QI 678 (match_operand:QI 1 "gr_register_operand" "r")))] 679 "" 680 "mux1 %0 = %1, @brcst" 681 [(set_attr "itanium_class" "mmshf")]) 682 683(define_insn "unpack2_l" 684 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") 685 (vec_select:V4HI 686 (vec_concat:V8HI 687 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") 688 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")) 689 (parallel [(const_int 0) 690 (const_int 4) 691 (const_int 1) 692 (const_int 5)])))] 693 "" 694 "unpack2.l %0 = %r2, %r1" 695 [(set_attr "itanium_class" "mmshf")]) 696 697(define_insn "unpack2_h" 698 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") 699 (vec_select:V4HI 700 (vec_concat:V8HI 701 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") 702 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")) 703 (parallel [(const_int 2) 704 (const_int 6) 705 (const_int 3) 706 (const_int 7)])))] 707 "" 708 "unpack2.h %0 = %r2, %r1" 709 [(set_attr "itanium_class" "mmshf")]) 710 711(define_insn "*mix2_r" 712 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") 713 (vec_select:V4HI 714 (vec_concat:V8HI 715 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") 716 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")) 717 (parallel [(const_int 0) 718 (const_int 4) 719 (const_int 2) 720 (const_int 6)])))] 721 "" 722 "mix2.r %0 = %r2, %r1" 723 [(set_attr "itanium_class" "mmshf")]) 724 725(define_insn "*mix2_l" 726 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") 727 (vec_select:V4HI 728 (vec_concat:V8HI 729 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") 730 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")) 731 (parallel [(const_int 1) 732 (const_int 5) 733 (const_int 3) 734 (const_int 7)])))] 735 "" 736 "mix2.l %0 = %r2, %r1" 737 [(set_attr "itanium_class" "mmshf")]) 738 739(define_insn "*mux2" 740 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") 741 (vec_select:V4HI 742 (match_operand:V4HI 1 "gr_register_operand" "r") 743 (parallel [(match_operand 2 "const_int_2bit_operand" "") 744 (match_operand 3 "const_int_2bit_operand" "") 745 (match_operand 4 "const_int_2bit_operand" "") 746 (match_operand 5 "const_int_2bit_operand" "")])))] 747 "" 748{ 749 int mask; 750 mask = INTVAL (operands[2]); 751 mask |= INTVAL (operands[3]) << 2; 752 mask |= INTVAL (operands[4]) << 4; 753 mask |= INTVAL (operands[5]) << 6; 754 operands[2] = GEN_INT (mask); 755 return "%,mux2 %0 = %1, %2"; 756} 757 [(set_attr "itanium_class" "mmshf")]) 758 759(define_insn "*mux2_brcst_hi" 760 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") 761 (vec_duplicate:V4HI 762 (match_operand:HI 1 "gr_register_operand" "r")))] 763 "" 764 "mux2 %0 = %1, 0" 765 [(set_attr "itanium_class" "mmshf")]) 766 767;; Note that mix4.r performs the exact same operation. 768(define_insn "*unpack4_l" 769 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") 770 (vec_select:V2SI 771 (vec_concat:V4SI 772 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU") 773 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU")) 774 (parallel [(const_int 0) 775 (const_int 2)])))] 776 "" 777 "unpack4.l %0 = %r2, %r1" 778 [(set_attr "itanium_class" "mmshf")]) 779 780;; Note that mix4.l performs the exact same operation. 781(define_insn "*unpack4_h" 782 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") 783 (vec_select:V2SI 784 (vec_concat:V4SI 785 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU") 786 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU")) 787 (parallel [(const_int 1) 788 (const_int 3)])))] 789 "" 790 "unpack4.h %0 = %r2, %r1" 791 [(set_attr "itanium_class" "mmshf")]) 792 793(define_expand "vec_initv2si" 794 [(match_operand:V2SI 0 "gr_register_operand" "") 795 (match_operand 1 "" "")] 796 "" 797{ 798 rtx op1 = XVECEXP (operands[1], 0, 0); 799 rtx op2 = XVECEXP (operands[1], 0, 1); 800 rtx x; 801 802 if (GET_CODE (op1) == CONST_INT && GET_CODE (op2) == CONST_INT) 803 { 804 rtvec v = rtvec_alloc (2); 805 RTVEC_ELT (v, 0) = TARGET_BIG_ENDIAN ? op2 : op1; 806 RTVEC_ELT (v, 1) = TARGET_BIG_ENDIAN ? op1 : op2;; 807 x = gen_rtx_CONST_VECTOR (V2SImode, v); 808 emit_move_insn (operands[0], x); 809 DONE; 810 } 811 812 if (!gr_reg_or_0_operand (op1, SImode)) 813 op1 = force_reg (SImode, op1); 814 if (!gr_reg_or_0_operand (op2, SImode)) 815 op2 = force_reg (SImode, op2); 816 817 if (TARGET_BIG_ENDIAN) 818 x = gen_rtx_VEC_CONCAT (V2SImode, op2, op1); 819 else 820 x = gen_rtx_VEC_CONCAT (V2SImode, op1, op2); 821 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); 822 DONE; 823}) 824 825(define_insn "*vecinit_v2si" 826 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") 827 (vec_concat:V2SI 828 (match_operand:SI 1 "gr_reg_or_0_operand" "rO") 829 (match_operand:SI 2 "gr_reg_or_0_operand" "rO")))] 830 "" 831 "unpack4.l %0 = %r2, %r1" 832 [(set_attr "itanium_class" "mmshf")]) 833 834;; Missing operations 835;; padd.uus 836;; pavg 837;; pavgsub 838;; pmpyshr, general form 839;; psad 840;; pshladd 841;; pshradd 842;; psub.uus 843 844;; Floating point vector operations 845 846(define_expand "movv2sf" 847 [(set (match_operand:V2SF 0 "general_operand" "") 848 (match_operand:V2SF 1 "general_operand" ""))] 849 "" 850{ 851 rtx op1 = ia64_expand_move (operands[0], operands[1]); 852 if (!op1) 853 DONE; 854 operands[1] = op1; 855}) 856 857(define_insn "*movv2sf_internal" 858 [(set (match_operand:V2SF 0 "destination_operand" 859 "=f,f,f,Q,*r ,*r,*r,*r,m ,f ,*r") 860 (match_operand:V2SF 1 "move_operand" 861 "fU,Y,Q,f,U*r,W ,i ,m ,*r,*r,f "))] 862 "ia64_move_ok (operands[0], operands[1])" 863{ 864 static const char * const alt[] = { 865 "%,mov %0 = %F1", 866 "%,fpack %0 = %F2, %F1", 867 "%,ldf8 %0 = %1%P1", 868 "%,stf8 %0 = %1%P0", 869 "%,mov %0 = %r1", 870 "%,addl %0 = %v1, r0", 871 "%,movl %0 = %v1", 872 "%,ld8%O1 %0 = %1%P1", 873 "%,st8%Q0 %0 = %r1%P0", 874 "%,setf.sig %0 = %1", 875 "%,getf.sig %0 = %1" 876 }; 877 878 if (which_alternative == 1) 879 { 880 operands[2] = XVECEXP (operands[1], 0, 1); 881 operands[1] = XVECEXP (operands[1], 0, 0); 882 } 883 884 return alt[which_alternative]; 885} 886 [(set_attr "itanium_class" "fmisc,fmisc,fld,stf,ialu,ialu,long_i,ld,st,tofr,frfr")]) 887 888(define_insn "absv2sf2" 889 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 890 (abs:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")))] 891 "" 892 "fpabs %0 = %1" 893 [(set_attr "itanium_class" "fmisc")]) 894 895(define_insn "negv2sf2" 896 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 897 (neg:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")))] 898 "" 899 "fpneg %0 = %1" 900 [(set_attr "itanium_class" "fmisc")]) 901 902(define_insn "*negabsv2sf2" 903 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 904 (neg:V2SF 905 (abs:V2SF (match_operand:V2SF 1 "fr_register_operand" "f"))))] 906 "" 907 "fpnegabs %0 = %1" 908 [(set_attr "itanium_class" "fmisc")]) 909 910;; In order to convince combine to merge plus and mult to a useful fpma, 911;; we need a couple of extra patterns. 912(define_expand "addv2sf3" 913 [(parallel 914 [(set (match_operand:V2SF 0 "fr_register_operand" "") 915 (plus:V2SF (match_operand:V2SF 1 "fr_register_operand" "") 916 (match_operand:V2SF 2 "fr_register_operand" ""))) 917 (use (match_dup 3))])] 918 "" 919{ 920 rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode)); 921 operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v)); 922}) 923 924;; The split condition here could be combine_completed, if we had such. 925(define_insn_and_split "*addv2sf3_1" 926 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 927 (plus:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") 928 (match_operand:V2SF 2 "fr_register_operand" "f"))) 929 (use (match_operand:V2SF 3 "fr_register_operand" "f"))] 930 "" 931 "#" 932 "reload_completed" 933 [(set (match_dup 0) 934 (plus:V2SF 935 (mult:V2SF (match_dup 1) (match_dup 3)) 936 (match_dup 2)))] 937 "") 938 939(define_insn_and_split "*addv2sf3_2" 940 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 941 (plus:V2SF 942 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") 943 (match_operand:V2SF 2 "fr_register_operand" "f")) 944 (match_operand:V2SF 3 "fr_register_operand" "f"))) 945 (use (match_operand:V2SF 4 "" "X"))] 946 "" 947 "#" 948 "" 949 [(set (match_dup 0) 950 (plus:V2SF 951 (mult:V2SF (match_dup 1) (match_dup 2)) 952 (match_dup 3)))] 953 "") 954 955;; In order to convince combine to merge minus and mult to a useful fpms, 956;; we need a couple of extra patterns. 957(define_expand "subv2sf3" 958 [(parallel 959 [(set (match_operand:V2SF 0 "fr_register_operand" "") 960 (minus:V2SF (match_operand:V2SF 1 "fr_register_operand" "") 961 (match_operand:V2SF 2 "fr_register_operand" ""))) 962 (use (match_dup 3))])] 963 "" 964{ 965 rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode)); 966 operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v)); 967}) 968 969;; The split condition here could be combine_completed, if we had such. 970(define_insn_and_split "*subv2sf3_1" 971 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 972 (minus:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") 973 (match_operand:V2SF 2 "fr_register_operand" "f"))) 974 (use (match_operand:V2SF 3 "fr_register_operand" "f"))] 975 "" 976 "#" 977 "reload_completed" 978 [(set (match_dup 0) 979 (minus:V2SF 980 (mult:V2SF (match_dup 1) (match_dup 3)) 981 (match_dup 2)))] 982 "") 983 984(define_insn_and_split "*subv2sf3_2" 985 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 986 (minus:V2SF 987 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") 988 (match_operand:V2SF 2 "fr_register_operand" "f")) 989 (match_operand:V2SF 3 "fr_register_operand" "f"))) 990 (use (match_operand:V2SF 4 "" "X"))] 991 "" 992 "#" 993 "" 994 [(set (match_dup 0) 995 (minus:V2SF 996 (mult:V2SF (match_dup 1) (match_dup 2)) 997 (match_dup 3)))] 998 "") 999 1000(define_insn "mulv2sf3" 1001 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1002 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") 1003 (match_operand:V2SF 2 "fr_register_operand" "f")))] 1004 "" 1005 "fpmpy %0 = %1, %2" 1006 [(set_attr "itanium_class" "fmac")]) 1007 1008(define_insn "*fpma" 1009 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1010 (plus:V2SF 1011 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") 1012 (match_operand:V2SF 2 "fr_register_operand" "f")) 1013 (match_operand:V2SF 3 "fr_register_operand" "f")))] 1014 "" 1015 "fpma %0 = %1, %2, %3" 1016 [(set_attr "itanium_class" "fmac")]) 1017 1018(define_insn "*fpms" 1019 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1020 (minus:V2SF 1021 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") 1022 (match_operand:V2SF 2 "fr_register_operand" "f")) 1023 (match_operand:V2SF 3 "fr_register_operand" "f")))] 1024 "" 1025 "fpms %0 = %1, %2, %3" 1026 [(set_attr "itanium_class" "fmac")]) 1027 1028(define_insn "*fpnmpy" 1029 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1030 (neg:V2SF 1031 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") 1032 (match_operand:V2SF 2 "fr_register_operand" "f"))))] 1033 "" 1034 "fpnmpy %0 = %1, %2" 1035 [(set_attr "itanium_class" "fmac")]) 1036 1037(define_insn "*fpnma" 1038 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1039 (plus:V2SF 1040 (neg:V2SF 1041 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") 1042 (match_operand:V2SF 2 "fr_register_operand" "f"))) 1043 (match_operand:V2SF 3 "fr_register_operand" "f")))] 1044 "" 1045 "fpnma %0 = %1, %2, %3" 1046 [(set_attr "itanium_class" "fmac")]) 1047 1048(define_insn "smaxv2sf3" 1049 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1050 (smax:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") 1051 (match_operand:V2SF 2 "fr_register_operand" "f")))] 1052 "" 1053 "fpmax %0 = %1, %2" 1054 [(set_attr "itanium_class" "fmisc")]) 1055 1056(define_insn "sminv2sf3" 1057 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1058 (smin:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") 1059 (match_operand:V2SF 2 "fr_register_operand" "f")))] 1060 "" 1061 "fpmin %0 = %1, %2" 1062 [(set_attr "itanium_class" "fmisc")]) 1063 1064(define_expand "reduc_splus_v2sf" 1065 [(match_operand:V2SF 0 "fr_register_operand" "") 1066 (match_operand:V2SF 1 "fr_register_operand" "")] 1067 "" 1068{ 1069 rtx tmp = gen_reg_rtx (V2SFmode); 1070 emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode))); 1071 emit_insn (gen_addv2sf3 (operands[0], operands[1], tmp)); 1072 DONE; 1073}) 1074 1075(define_expand "reduc_smax_v2sf" 1076 [(match_operand:V2SF 0 "fr_register_operand" "") 1077 (match_operand:V2SF 1 "fr_register_operand" "")] 1078 "" 1079{ 1080 rtx tmp = gen_reg_rtx (V2SFmode); 1081 emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode))); 1082 emit_insn (gen_smaxv2sf3 (operands[0], operands[1], tmp)); 1083 DONE; 1084}) 1085 1086(define_expand "reduc_smin_v2sf" 1087 [(match_operand:V2SF 0 "fr_register_operand" "") 1088 (match_operand:V2SF 1 "fr_register_operand" "")] 1089 "" 1090{ 1091 rtx tmp = gen_reg_rtx (V2SFmode); 1092 emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode))); 1093 emit_insn (gen_sminv2sf3 (operands[0], operands[1], tmp)); 1094 DONE; 1095}) 1096 1097(define_expand "vcondv2sf" 1098 [(set (match_operand:V2SF 0 "fr_register_operand" "") 1099 (if_then_else:V2SF 1100 (match_operator 3 "" 1101 [(match_operand:V2SF 4 "fr_reg_or_0_operand" "") 1102 (match_operand:V2SF 5 "fr_reg_or_0_operand" "")]) 1103 (match_operand:V2SF 1 "fr_reg_or_0_operand" "") 1104 (match_operand:V2SF 2 "fr_reg_or_0_operand" "")))] 1105 "" 1106{ 1107 rtx x, cmp; 1108 1109 cmp = gen_reg_rtx (V2SFmode); 1110 PUT_MODE (operands[3], V2SFmode); 1111 emit_insn (gen_rtx_SET (VOIDmode, cmp, operands[3])); 1112 1113 x = gen_rtx_IF_THEN_ELSE (V2SFmode, cmp, operands[1], operands[2]); 1114 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); 1115 DONE; 1116}) 1117 1118(define_insn "*fpcmp" 1119 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1120 (match_operator:V2SF 3 "comparison_operator" 1121 [(match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") 1122 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")]))] 1123 "" 1124 "fpcmp.%D3 %0 = %F1, %F2" 1125 [(set_attr "itanium_class" "fmisc")]) 1126 1127(define_insn "*fselect" 1128 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1129 (if_then_else:V2SF 1130 (match_operand:V2SF 1 "fr_register_operand" "f") 1131 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU") 1132 (match_operand:V2SF 3 "fr_reg_or_0_operand" "fU")))] 1133 "" 1134 "fselect %0 = %F2, %F3, %1" 1135 [(set_attr "itanium_class" "fmisc")]) 1136 1137(define_expand "vec_initv2sf" 1138 [(match_operand:V2SF 0 "fr_register_operand" "") 1139 (match_operand 1 "" "")] 1140 "" 1141{ 1142 rtx op1 = XVECEXP (operands[1], 0, 0); 1143 rtx op2 = XVECEXP (operands[1], 0, 1); 1144 rtx x; 1145 1146 if (GET_CODE (op1) == CONST_DOUBLE && GET_CODE (op2) == CONST_DOUBLE) 1147 { 1148 x = gen_rtx_CONST_VECTOR (V2SFmode, XVEC (operands[1], 0)); 1149 emit_move_insn (operands[0], x); 1150 DONE; 1151 } 1152 1153 if (!fr_reg_or_fp01_operand (op1, SFmode)) 1154 op1 = force_reg (SFmode, op1); 1155 if (!fr_reg_or_fp01_operand (op2, SFmode)) 1156 op2 = force_reg (SFmode, op2); 1157 1158 if (TARGET_BIG_ENDIAN) 1159 emit_insn (gen_fpack (operands[0], op2, op1)); 1160 else 1161 emit_insn (gen_fpack (operands[0], op1, op2)); 1162 DONE; 1163}) 1164 1165(define_insn "fpack" 1166 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1167 (vec_concat:V2SF 1168 (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") 1169 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] 1170 "" 1171 "fpack %0 = %F2, %F1" 1172 [(set_attr "itanium_class" "fmisc")]) 1173 1174(define_insn "fswap" 1175 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1176 (vec_select:V2SF 1177 (vec_concat:V4SF 1178 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") 1179 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")) 1180 (parallel [(const_int 1) (const_int 2)])))] 1181 "" 1182 "fswap %0 = %F1, %F2" 1183 [(set_attr "itanium_class" "fmisc")]) 1184 1185(define_insn "*fmix_l" 1186 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1187 (vec_select:V2SF 1188 (vec_concat:V4SF 1189 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") 1190 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")) 1191 (parallel [(const_int 1) (const_int 3)])))] 1192 "" 1193 "fmix.l %0 = %F2, %F1" 1194 [(set_attr "itanium_class" "fmisc")]) 1195 1196(define_insn "fmix_r" 1197 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1198 (vec_select:V2SF 1199 (vec_concat:V4SF 1200 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") 1201 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")) 1202 (parallel [(const_int 0) (const_int 2)])))] 1203 "" 1204 "fmix.r %0 = %F2, %F1" 1205 [(set_attr "itanium_class" "fmisc")]) 1206 1207(define_insn "fmix_lr" 1208 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") 1209 (vec_select:V2SF 1210 (vec_concat:V4SF 1211 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") 1212 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")) 1213 (parallel [(const_int 0) (const_int 3)])))] 1214 "" 1215 "fmix.lr %0 = %F2, %F1" 1216 [(set_attr "itanium_class" "fmisc")]) 1217 1218(define_expand "vec_setv2sf" 1219 [(match_operand:V2SF 0 "fr_register_operand" "") 1220 (match_operand:SF 1 "fr_register_operand" "") 1221 (match_operand 2 "const_int_operand" "")] 1222 "" 1223{ 1224 rtx tmp = gen_reg_rtx (V2SFmode); 1225 emit_insn (gen_fpack (tmp, operands[1], CONST0_RTX (SFmode))); 1226 1227 switch (INTVAL (operands[2])) 1228 { 1229 case 0: 1230 emit_insn (gen_fmix_lr (operands[0], tmp, operands[0])); 1231 break; 1232 case 1: 1233 emit_insn (gen_fmix_r (operands[0], operands[0], tmp)); 1234 break; 1235 default: 1236 gcc_unreachable (); 1237 } 1238 DONE; 1239}) 1240 1241(define_insn_and_split "*vec_extractv2sf_0_le" 1242 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,f,m") 1243 (unspec:SF [(match_operand:V2SF 1 "nonimmediate_operand" "rfm,rm,r") 1244 (const_int 0)] 1245 UNSPEC_VECT_EXTR))] 1246 "!TARGET_BIG_ENDIAN" 1247 "#" 1248 "reload_completed" 1249 [(set (match_dup 0) (match_dup 1))] 1250{ 1251 if (REG_P (operands[1]) && FR_REGNO_P (REGNO (operands[1]))) 1252 operands[0] = gen_rtx_REG (V2SFmode, REGNO (operands[0])); 1253 else if (MEM_P (operands[1])) 1254 operands[1] = adjust_address (operands[1], SFmode, 0); 1255 else 1256 operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1])); 1257}) 1258 1259(define_insn_and_split "*vec_extractv2sf_0_be" 1260 [(set (match_operand:SF 0 "register_operand" "=r,f") 1261 (unspec:SF [(match_operand:V2SF 1 "register_operand" "rf,r") 1262 (const_int 0)] 1263 UNSPEC_VECT_EXTR))] 1264 "TARGET_BIG_ENDIAN" 1265 "#" 1266 "reload_completed" 1267 [(set (match_dup 0) (match_dup 1))] 1268{ 1269 if (REG_P (operands[1]) && FR_REGNO_P (REGNO (operands[1]))) 1270 operands[0] = gen_rtx_REG (V2SFmode, REGNO (operands[0])); 1271 else 1272 operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1])); 1273}) 1274 1275(define_insn_and_split "*vec_extractv2sf_1" 1276 [(set (match_operand:SF 0 "register_operand" "=r") 1277 (unspec:SF [(match_operand:V2SF 1 "register_operand" "r") 1278 (const_int 1)] 1279 UNSPEC_VECT_EXTR))] 1280 "" 1281 "#" 1282 "reload_completed" 1283 [(const_int 0)] 1284{ 1285 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); 1286 operands[1] = gen_rtx_REG (DImode, REGNO (operands[1])); 1287 if (TARGET_BIG_ENDIAN) 1288 emit_move_insn (operands[0], operands[1]); 1289 else 1290 emit_insn (gen_lshrdi3 (operands[0], operands[1], GEN_INT (32))); 1291 DONE; 1292}) 1293 1294(define_expand "vec_extractv2sf" 1295 [(set (match_operand:SF 0 "register_operand" "") 1296 (unspec:SF [(match_operand:V2SF 1 "register_operand" "") 1297 (match_operand:DI 2 "const_int_operand" "")] 1298 UNSPEC_VECT_EXTR))] 1299 "" 1300 "") 1301 1302;; Missing operations 1303;; fprcpa 1304;; fpsqrta 1305