1132718Skan;; Itanium1 (original Itanium) DFA descriptions for insn scheduling 2132718Skan;; and bundling. 3169689Skan;; Copyright (C) 2002, 2004, 2005 Free Software Foundation, Inc. 4132718Skan;; Contributed by Vladimir Makarov <vmakarov@redhat.com>. 5132718Skan;; 6132718Skan;; This file is part of GCC. 7132718Skan;; 8132718Skan;; GCC is free software; you can redistribute it and/or modify 9132718Skan;; it under the terms of the GNU General Public License as published by 10132718Skan;; the Free Software Foundation; either version 2, or (at your option) 11132718Skan;; any later version. 12132718Skan;; 13132718Skan;; GCC is distributed in the hope that it will be useful, 14132718Skan;; but WITHOUT ANY WARRANTY; without even the implied warranty of 15132718Skan;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16132718Skan;; GNU General Public License for more details. 17132718Skan;; 18132718Skan;; You should have received a copy of the GNU General Public License 19132718Skan;; along with GCC; see the file COPYING. If not, write to 20169689Skan;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 21169689Skan;; Boston, MA 02110-1301, USA. */ 22132718Skan;; 23132718Skan 24132718Skan 25132718Skan/* This is description of pipeline hazards based on DFA. The 26132718Skan following constructions can be used for this: 27132718Skan 28132718Skan o define_cpu_unit string [string]) describes a cpu functional unit 29132718Skan (separated by comma). 30132718Skan 31132718Skan 1st operand: Names of cpu function units. 32132718Skan 2nd operand: Name of automaton (see comments for 33132718Skan DEFINE_AUTOMATON). 34132718Skan 35132718Skan All define_reservations and define_cpu_units should have unique 36169689Skan names which cannot be "nothing". 37132718Skan 38132718Skan o (exclusion_set string string) means that each CPU function unit 39169689Skan in the first string cannot be reserved simultaneously with each 40132718Skan unit whose name is in the second string and vise versa. CPU 41132718Skan units in the string are separated by commas. For example, it is 42132718Skan useful for description CPU with fully pipelined floating point 43132718Skan functional unit which can execute simultaneously only single 44132718Skan floating point insns or only double floating point insns. 45132718Skan 46132718Skan o (presence_set string string) means that each CPU function unit in 47169689Skan the first string cannot be reserved unless at least one of 48132718Skan pattern of units whose names are in the second string is 49132718Skan reserved. This is an asymmetric relation. CPU units or unit 50132718Skan patterns in the strings are separated by commas. Pattern is one 51132718Skan unit name or unit names separated by white-spaces. 52132718Skan 53132718Skan For example, it is useful for description that slot1 is reserved 54132718Skan after slot0 reservation for a VLIW processor. We could describe 55132718Skan it by the following construction 56132718Skan 57132718Skan (presence_set "slot1" "slot0") 58132718Skan 59132718Skan Or slot1 is reserved only after slot0 and unit b0 reservation. 60132718Skan In this case we could write 61132718Skan 62132718Skan (presence_set "slot1" "slot0 b0") 63132718Skan 64132718Skan All CPU functional units in a set should belong to the same 65132718Skan automaton. 66132718Skan 67132718Skan o (final_presence_set string string) is analogous to 68132718Skan `presence_set'. The difference between them is when checking is 69132718Skan done. When an instruction is issued in given automaton state 70132718Skan reflecting all current and planned unit reservations, the 71132718Skan automaton state is changed. The first state is a source state, 72132718Skan the second one is a result state. Checking for `presence_set' is 73132718Skan done on the source state reservation, checking for 74132718Skan `final_presence_set' is done on the result reservation. This 75132718Skan construction is useful to describe a reservation which is 76132718Skan actually two subsequent reservations. For example, if we use 77132718Skan 78132718Skan (presence_set "slot1" "slot0") 79132718Skan 80132718Skan the following insn will be never issued (because slot1 requires 81132718Skan slot0 which is absent in the source state). 82132718Skan 83132718Skan (define_reservation "insn_and_nop" "slot0 + slot1") 84132718Skan 85132718Skan but it can be issued if we use analogous `final_presence_set'. 86132718Skan 87132718Skan o (absence_set string string) means that each CPU function unit in 88132718Skan the first string can be reserved only if each pattern of units 89132718Skan whose names are in the second string is not reserved. This is an 90132718Skan asymmetric relation (actually exclusion set is analogous to this 91132718Skan one but it is symmetric). CPU units or unit patterns in the 92132718Skan string are separated by commas. Pattern is one unit name or unit 93132718Skan names separated by white-spaces. 94132718Skan 95169689Skan For example, it is useful for description that slot0 cannot be 96132718Skan reserved after slot1 or slot2 reservation for a VLIW processor. 97132718Skan We could describe it by the following construction 98132718Skan 99132718Skan (absence_set "slot2" "slot0, slot1") 100132718Skan 101169689Skan Or slot2 cannot be reserved if slot0 and unit b0 are reserved or 102132718Skan slot1 and unit b1 are reserved . In this case we could write 103132718Skan 104132718Skan (absence_set "slot2" "slot0 b0, slot1 b1") 105132718Skan 106132718Skan All CPU functional units in a set should to belong the same 107132718Skan automaton. 108132718Skan 109132718Skan o (final_absence_set string string) is analogous to `absence_set' but 110132718Skan checking is done on the result (state) reservation. See comments 111132718Skan for final_presence_set. 112132718Skan 113132718Skan o (define_bypass number out_insn_names in_insn_names) names bypass with 114132718Skan given latency (the first number) from insns given by the first 115132718Skan string (see define_insn_reservation) into insns given by the 116132718Skan second string. Insn names in the strings are separated by 117132718Skan commas. 118132718Skan 119132718Skan o (define_automaton string) describes names of an automaton 120132718Skan generated and used for pipeline hazards recognition. The names 121132718Skan are separated by comma. Actually it is possibly to generate the 122132718Skan single automaton but unfortunately it can be very large. If we 123132718Skan use more one automata, the summary size of the automata usually 124132718Skan is less than the single one. The automaton name is used in 125132718Skan define_cpu_unit. All automata should have unique names. 126132718Skan 127132718Skan o (automata_option string) describes option for generation of 128132718Skan automata. Currently there are the following options: 129132718Skan 130132718Skan o "no-minimization" which makes no minimization of automata. 131132718Skan This is only worth to do when we are debugging the description 132132718Skan and need to look more accurately at reservations of states. 133132718Skan 134132718Skan o "ndfa" which makes automata with nondetermenistic reservation 135132718Skan by insns. 136132718Skan 137132718Skan o (define_reservation string string) names reservation (the first 138132718Skan string) of cpu functional units (the 2nd string). Sometimes unit 139132718Skan reservations for different insns contain common parts. In such 140132718Skan case, you describe common part and use one its name (the 1st 141132718Skan parameter) in regular expression in define_insn_reservation. All 142132718Skan define_reservations, define results and define_cpu_units should 143169689Skan have unique names which cannot be "nothing". 144132718Skan 145132718Skan o (define_insn_reservation name default_latency condition regexpr) 146132718Skan describes reservation of cpu functional units (the 3nd operand) 147132718Skan for instruction which is selected by the condition (the 2nd 148132718Skan parameter). The first parameter is used for output of debugging 149132718Skan information. The reservations are described by a regular 150132718Skan expression according the following syntax: 151132718Skan 152132718Skan regexp = regexp "," oneof 153132718Skan | oneof 154132718Skan 155132718Skan oneof = oneof "|" allof 156132718Skan | allof 157132718Skan 158132718Skan allof = allof "+" repeat 159132718Skan | repeat 160132718Skan 161132718Skan repeat = element "*" number 162132718Skan | element 163132718Skan 164132718Skan element = cpu_function_name 165132718Skan | reservation_name 166132718Skan | result_name 167132718Skan | "nothing" 168132718Skan | "(" regexp ")" 169132718Skan 170132718Skan 1. "," is used for describing start of the next cycle in 171132718Skan reservation. 172132718Skan 173132718Skan 2. "|" is used for describing the reservation described by the 174132718Skan first regular expression *or* the reservation described by 175132718Skan the second regular expression *or* etc. 176132718Skan 177132718Skan 3. "+" is used for describing the reservation described by the 178132718Skan first regular expression *and* the reservation described by 179132718Skan the second regular expression *and* etc. 180132718Skan 181132718Skan 4. "*" is used for convenience and simply means sequence in 182132718Skan which the regular expression are repeated NUMBER times with 183132718Skan cycle advancing (see ","). 184132718Skan 185132718Skan 5. cpu function unit name which means reservation. 186132718Skan 187132718Skan 6. reservation name -- see define_reservation. 188132718Skan 189132718Skan 7. string "nothing" means no units reservation. 190132718Skan 191132718Skan*/ 192132718Skan 193132718Skan(define_automaton "one") 194132718Skan 195132718Skan;; All possible combinations of bundles/syllables 196132718Skan(define_cpu_unit "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\ 197132718Skan 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx" "one") 198132718Skan(define_cpu_unit "1_0mi.i, 1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0bb.b, 1_0mb.b,\ 199132718Skan 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx." "one") 200132718Skan(define_cpu_unit "1_0mii., 1_0mmi., 1_0mfi., 1_0mmf., 1_0bbb., 1_0mbb.,\ 201132718Skan 1_0mib., 1_0mmb., 1_0mfb." "one") 202132718Skan 203132718Skan(define_cpu_unit "1_1m.ii, 1_1m.mi, 1_1m.fi, 1_1b.bb, 1_1m.bb,\ 204132718Skan 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx" "one") 205132718Skan(define_cpu_unit "1_1mi.i, 1_1mm.i, 1_1mf.i, 1_1bb.b, 1_1mb.b,\ 206132718Skan 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx." "one") 207132718Skan(define_cpu_unit "1_1mii., 1_1mmi., 1_1mfi., 1_1bbb., 1_1mbb.,\ 208132718Skan 1_1mib., 1_1mmb., 1_1mfb." "one") 209132718Skan 210132718Skan;; Slot 1 211132718Skan(exclusion_set "1_0m.ii" 212132718Skan "1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb,\ 213132718Skan 1_0m.lx") 214132718Skan(exclusion_set "1_0m.mi" 215132718Skan "1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 216132718Skan(exclusion_set "1_0m.fi" 217132718Skan "1_0m.mf, 1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 218132718Skan(exclusion_set "1_0m.mf" 219132718Skan "1_0b.bb, 1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 220132718Skan(exclusion_set "1_0b.bb" "1_0m.bb, 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 221132718Skan(exclusion_set "1_0m.bb" "1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 222132718Skan(exclusion_set "1_0m.ib" "1_0m.mb, 1_0m.fb, 1_0m.lx") 223132718Skan(exclusion_set "1_0m.mb" "1_0m.fb, 1_0m.lx") 224132718Skan(exclusion_set "1_0m.fb" "1_0m.lx") 225132718Skan 226132718Skan;; Slot 2 227132718Skan(exclusion_set "1_0mi.i" 228132718Skan "1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b,\ 229132718Skan 1_0mlx.") 230132718Skan(exclusion_set "1_0mm.i" 231132718Skan "1_0mf.i, 1_0mm.f, 1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 232132718Skan(exclusion_set "1_0mf.i" 233132718Skan "1_0mm.f, 1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 234132718Skan(exclusion_set "1_0mm.f" 235132718Skan "1_0bb.b, 1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 236132718Skan(exclusion_set "1_0bb.b" "1_0mb.b, 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 237132718Skan(exclusion_set "1_0mb.b" "1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 238132718Skan(exclusion_set "1_0mi.b" "1_0mm.b, 1_0mf.b, 1_0mlx.") 239132718Skan(exclusion_set "1_0mm.b" "1_0mf.b, 1_0mlx.") 240132718Skan(exclusion_set "1_0mf.b" "1_0mlx.") 241132718Skan 242132718Skan;; Slot 3 243132718Skan(exclusion_set "1_0mii." 244132718Skan "1_0mmi., 1_0mfi., 1_0mmf., 1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb.,\ 245132718Skan 1_0mlx.") 246132718Skan(exclusion_set "1_0mmi." 247132718Skan "1_0mfi., 1_0mmf., 1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 248132718Skan(exclusion_set "1_0mfi." 249132718Skan "1_0mmf., 1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 250132718Skan(exclusion_set "1_0mmf." 251132718Skan "1_0bbb., 1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 252132718Skan(exclusion_set "1_0bbb." "1_0mbb., 1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 253132718Skan(exclusion_set "1_0mbb." "1_0mib., 1_0mmb., 1_0mfb., 1_0mlx.") 254132718Skan(exclusion_set "1_0mib." "1_0mmb., 1_0mfb., 1_0mlx.") 255132718Skan(exclusion_set "1_0mmb." "1_0mfb., 1_0mlx.") 256132718Skan(exclusion_set "1_0mfb." "1_0mlx.") 257132718Skan 258132718Skan;; Slot 4 259132718Skan(exclusion_set "1_1m.ii" 260132718Skan "1_1m.mi, 1_1m.fi, 1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 261132718Skan(exclusion_set "1_1m.mi" 262132718Skan "1_1m.fi, 1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 263132718Skan(exclusion_set "1_1m.fi" 264132718Skan "1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 265132718Skan(exclusion_set "1_1b.bb" "1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 266132718Skan(exclusion_set "1_1m.bb" "1_1m.ib, 1_1m.mb, 1_1m.fb, 1_1m.lx") 267132718Skan(exclusion_set "1_1m.ib" "1_1m.mb, 1_1m.fb, 1_1m.lx") 268132718Skan(exclusion_set "1_1m.mb" "1_1m.fb, 1_1m.lx") 269132718Skan(exclusion_set "1_1m.fb" "1_1m.lx") 270132718Skan 271132718Skan;; Slot 5 272132718Skan(exclusion_set "1_1mi.i" 273132718Skan "1_1mm.i, 1_1mf.i, 1_1bb.b, 1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 274132718Skan(exclusion_set "1_1mm.i" 275132718Skan "1_1mf.i, 1_1bb.b, 1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 276132718Skan(exclusion_set "1_1mf.i" 277132718Skan "1_1bb.b, 1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 278132718Skan(exclusion_set "1_1bb.b" "1_1mb.b, 1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 279132718Skan(exclusion_set "1_1mb.b" "1_1mi.b, 1_1mm.b, 1_1mf.b, 1_1mlx.") 280132718Skan(exclusion_set "1_1mi.b" "1_1mm.b, 1_1mf.b, 1_1mlx.") 281132718Skan(exclusion_set "1_1mm.b" "1_1mf.b, 1_1mlx.") 282132718Skan(exclusion_set "1_1mf.b" "1_1mlx.") 283132718Skan 284132718Skan;; Slot 6 285132718Skan(exclusion_set "1_1mii." 286132718Skan "1_1mmi., 1_1mfi., 1_1bbb., 1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 287132718Skan(exclusion_set "1_1mmi." 288132718Skan "1_1mfi., 1_1bbb., 1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 289132718Skan(exclusion_set "1_1mfi." 290132718Skan "1_1bbb., 1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 291132718Skan(exclusion_set "1_1bbb." "1_1mbb., 1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 292132718Skan(exclusion_set "1_1mbb." "1_1mib., 1_1mmb., 1_1mfb., 1_1mlx.") 293132718Skan(exclusion_set "1_1mib." "1_1mmb., 1_1mfb., 1_1mlx.") 294132718Skan(exclusion_set "1_1mmb." "1_1mfb., 1_1mlx.") 295132718Skan(exclusion_set "1_1mfb." "1_1mlx.") 296132718Skan 297132718Skan(final_presence_set "1_0mi.i" "1_0m.ii") 298132718Skan(final_presence_set "1_0mii." "1_0mi.i") 299132718Skan(final_presence_set "1_1mi.i" "1_1m.ii") 300132718Skan(final_presence_set "1_1mii." "1_1mi.i") 301132718Skan 302132718Skan(final_presence_set "1_0mm.i" "1_0m.mi") 303132718Skan(final_presence_set "1_0mmi." "1_0mm.i") 304132718Skan(final_presence_set "1_1mm.i" "1_1m.mi") 305132718Skan(final_presence_set "1_1mmi." "1_1mm.i") 306132718Skan 307132718Skan(final_presence_set "1_0mf.i" "1_0m.fi") 308132718Skan(final_presence_set "1_0mfi." "1_0mf.i") 309132718Skan(final_presence_set "1_1mf.i" "1_1m.fi") 310132718Skan(final_presence_set "1_1mfi." "1_1mf.i") 311132718Skan 312132718Skan(final_presence_set "1_0mm.f" "1_0m.mf") 313132718Skan(final_presence_set "1_0mmf." "1_0mm.f") 314132718Skan 315132718Skan(final_presence_set "1_0bb.b" "1_0b.bb") 316132718Skan(final_presence_set "1_0bbb." "1_0bb.b") 317132718Skan(final_presence_set "1_1bb.b" "1_1b.bb") 318132718Skan(final_presence_set "1_1bbb." "1_1bb.b") 319132718Skan 320132718Skan(final_presence_set "1_0mb.b" "1_0m.bb") 321132718Skan(final_presence_set "1_0mbb." "1_0mb.b") 322132718Skan(final_presence_set "1_1mb.b" "1_1m.bb") 323132718Skan(final_presence_set "1_1mbb." "1_1mb.b") 324132718Skan 325132718Skan(final_presence_set "1_0mi.b" "1_0m.ib") 326132718Skan(final_presence_set "1_0mib." "1_0mi.b") 327132718Skan(final_presence_set "1_1mi.b" "1_1m.ib") 328132718Skan(final_presence_set "1_1mib." "1_1mi.b") 329132718Skan 330132718Skan(final_presence_set "1_0mm.b" "1_0m.mb") 331132718Skan(final_presence_set "1_0mmb." "1_0mm.b") 332132718Skan(final_presence_set "1_1mm.b" "1_1m.mb") 333132718Skan(final_presence_set "1_1mmb." "1_1mm.b") 334132718Skan 335132718Skan(final_presence_set "1_0mf.b" "1_0m.fb") 336132718Skan(final_presence_set "1_0mfb." "1_0mf.b") 337132718Skan(final_presence_set "1_1mf.b" "1_1m.fb") 338132718Skan(final_presence_set "1_1mfb." "1_1mf.b") 339132718Skan 340132718Skan(final_presence_set "1_0mlx." "1_0m.lx") 341132718Skan(final_presence_set "1_1mlx." "1_1m.lx") 342132718Skan 343132718Skan(final_presence_set 344132718Skan "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx" 345132718Skan "1_0mii.,1_0mmi.,1_0mfi.,1_0mmf.,1_0bbb.,1_0mbb.,1_0mib.,1_0mmb.,1_0mfb.,\ 346132718Skan 1_0mlx.") 347132718Skan 348132718Skan;; Microarchitecture units: 349132718Skan(define_cpu_unit 350132718Skan "1_um0, 1_um1, 1_ui0, 1_ui1, 1_uf0, 1_uf1, 1_ub0, 1_ub1, 1_ub2,\ 351132718Skan 1_unb0, 1_unb1, 1_unb2" "one") 352132718Skan 353132718Skan(exclusion_set "1_ub0" "1_unb0") 354132718Skan(exclusion_set "1_ub1" "1_unb1") 355132718Skan(exclusion_set "1_ub2" "1_unb2") 356132718Skan 357132718Skan;; The following rules are used to decrease number of alternatives. 358132718Skan;; They are consequences of Itanium microarchitecture. They also 359132718Skan;; describe the following rules mentioned in Itanium 360132718Skan;; microarchitecture: rules mentioned in Itanium microarchitecture: 361132718Skan;; o "MMF: Always splits issue before the first M and after F regardless 362132718Skan;; of surrounding bundles and stops". 363132718Skan;; o "BBB/MBB: Always splits issue after either of these bundles". 364132718Skan;; o "MIB BBB: Split issue after the first bundle in this pair". 365132718Skan 366132718Skan(exclusion_set "1_0m.mf,1_0mm.f,1_0mmf." 367132718Skan "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx") 368132718Skan(exclusion_set "1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb." 369132718Skan "1_1m.ii,1_1m.mi,1_1m.fi,1_1b.bb,1_1m.bb,1_1m.ib,1_1m.mb,1_1m.fb,1_1m.lx") 370132718Skan(exclusion_set "1_0m.ib,1_0mi.b,1_0mib." "1_1b.bb") 371132718Skan 372132718Skan;; For exceptions of M, I, B, F insns: 373132718Skan(define_cpu_unit "1_not_um1, 1_not_ui1, 1_not_uf1" "one") 374132718Skan 375132718Skan(final_absence_set "1_not_um1" "1_um1") 376132718Skan(final_absence_set "1_not_ui1" "1_ui1") 377132718Skan(final_absence_set "1_not_uf1" "1_uf1") 378132718Skan 379132718Skan;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the 380132718Skan;;; B-slot contains a nop.b or a brp instruction". 381132718Skan;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or 382132718Skan;;; nop.b, otherwise it disperses to B2". 383132718Skan(final_absence_set 384132718Skan "1_1m.ii, 1_1m.mi, 1_1m.fi, 1_1b.bb, 1_1m.bb, 1_1m.ib, 1_1m.mb, 1_1m.fb,\ 385132718Skan 1_1m.lx" 386132718Skan "1_0mib. 1_ub2, 1_0mfb. 1_ub2, 1_0mmb. 1_ub2") 387132718Skan 388132718Skan;; This is necessary to start new processor cycle when we meet stop bit. 389132718Skan(define_cpu_unit "1_stop" "one") 390132718Skan(final_absence_set 391132718Skan "1_0m.ii,1_0mi.i,1_0mii.,1_0m.mi,1_0mm.i,1_0mmi.,1_0m.fi,1_0mf.i,1_0mfi.,\ 392132718Skan 1_0m.mf,1_0mm.f,1_0mmf.,1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb.,\ 393132718Skan 1_0m.ib,1_0mi.b,1_0mib.,1_0m.mb,1_0mm.b,1_0mmb.,1_0m.fb,1_0mf.b,1_0mfb.,\ 394132718Skan 1_0m.lx,1_0mlx., \ 395132718Skan 1_1m.ii,1_1mi.i,1_1mii.,1_1m.mi,1_1mm.i,1_1mmi.,1_1m.fi,1_1mf.i,1_1mfi.,\ 396132718Skan 1_1b.bb,1_1bb.b,1_1bbb.,1_1m.bb,1_1mb.b,1_1mbb.,1_1m.ib,1_1mi.b,1_1mib.,\ 397132718Skan 1_1m.mb,1_1mm.b,1_1mmb.,1_1m.fb,1_1mf.b,1_1mfb.,1_1m.lx,1_1mlx." 398132718Skan "1_stop") 399132718Skan 400132718Skan;; M and I instruction is dispersed to the lowest numbered M or I unit 401132718Skan;; not already in use. An I slot in the 3rd position of 2nd bundle is 402132718Skan;; always dispersed to I1 403132718Skan(final_presence_set "1_um1" "1_um0") 404132718Skan(final_presence_set "1_ui1" "1_ui0, 1_1mii., 1_1mmi., 1_1mfi.") 405132718Skan 406132718Skan;; Insns 407132718Skan 408132718Skan;; M and I instruction is dispersed to the lowest numbered M or I unit 409132718Skan;; not already in use. An I slot in the 3rd position of 2nd bundle is 410132718Skan;; always dispersed to I1 411132718Skan(define_reservation "1_M0" 412132718Skan "1_0m.ii+1_um0|1_0m.mi+1_um0|1_0mm.i+(1_um0|1_um1)\ 413132718Skan |1_0m.fi+1_um0|1_0m.mf+1_um0|1_0mm.f+1_um1\ 414132718Skan |1_0m.bb+1_um0|1_0m.ib+1_um0|1_0m.mb+1_um0\ 415132718Skan |1_0mm.b+1_um1|1_0m.fb+1_um0|1_0m.lx+1_um0\ 416132718Skan |1_1mm.i+1_um1|1_1mm.b+1_um1\ 417132718Skan |(1_1m.ii|1_1m.mi|1_1m.fi|1_1m.bb|1_1m.ib|1_1m.mb|1_1m.fb|1_1m.lx)\ 418132718Skan +(1_um0|1_um1)") 419132718Skan 420132718Skan(define_reservation "1_M1" 421132718Skan "(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\ 422132718Skan |1_0mib.+1_unb0|1_0mfb.+1_unb0|1_0mmb.+1_unb0)\ 423132718Skan +(1_1m.ii|1_1m.mi|1_1m.fi|1_1m.bb|1_1m.ib|1_1m.mb|1_1m.fb|1_1m.lx)\ 424132718Skan +(1_um0|1_um1)") 425132718Skan 426132718Skan(define_reservation "1_M" "1_M0|1_M1") 427132718Skan 428132718Skan;; Exceptions for dispersal rules. 429132718Skan;; "An I slot in the 3rd position of 2nd bundle is always dispersed to I1". 430132718Skan(define_reservation "1_I0" 431132718Skan "1_0mi.i+1_ui0|1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\ 432132718Skan |1_0mi.b+1_ui0|(1_1mi.i|1_1mi.b)+(1_ui0|1_ui1)\ 433132718Skan |1_1mii.+1_ui1|1_1mmi.+1_ui1|1_1mfi.+1_ui1") 434132718Skan 435132718Skan(define_reservation "1_I1" 436132718Skan "1_0m.ii+1_um0+1_0mi.i+1_ui0|1_0mm.i+(1_um0|1_um1)+1_0mmi.+1_ui0\ 437132718Skan |1_0mf.i+1_uf0+1_0mfi.+1_ui0|1_0m.ib+1_um0+1_0mi.b+1_ui0\ 438132718Skan |(1_1m.ii+(1_um0|1_um1)+1_1mi.i\ 439132718Skan |1_1m.ib+(1_um0|1_um1)+1_1mi.b)+(1_ui0|1_ui1)\ 440132718Skan |1_1mm.i+1_um1+1_1mmi.+1_ui1|1_1mf.i+1_uf1+1_1mfi.+1_ui1") 441132718Skan 442132718Skan(define_reservation "1_I" "1_I0|1_I1") 443132718Skan 444132718Skan;; "An F slot in the 1st bundle disperses to F0". 445132718Skan;; "An F slot in the 2st bundle disperses to F1". 446132718Skan(define_reservation "1_F0" 447132718Skan "1_0mf.i+1_uf0|1_0mmf.+1_uf0|1_0mf.b+1_uf0|1_1mf.i+1_uf1|1_1mf.b+1_uf1") 448132718Skan 449132718Skan(define_reservation "1_F1" 450132718Skan "1_0m.fi+1_um0+1_0mf.i+1_uf0|1_0mm.f+(1_um0|1_um1)+1_0mmf.+1_uf0\ 451132718Skan |1_0m.fb+1_um0+1_0mf.b+1_uf0|1_1m.fi+(1_um0|1_um1)+1_1mf.i+1_uf1\ 452132718Skan |1_1m.fb+(1_um0|1_um1)+1_1mf.b+1_uf1") 453132718Skan 454132718Skan(define_reservation "1_F2" 455132718Skan "1_0m.mf+1_um0+1_0mm.f+1_um1+1_0mmf.+1_uf0\ 456132718Skan |(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\ 457132718Skan |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0)\ 458132718Skan +(1_1m.fi+(1_um0|1_um1)+1_1mf.i+1_uf1\ 459132718Skan |1_1m.fb+(1_um0|1_um1)+1_1mf.b+1_uf1)") 460132718Skan 461132718Skan(define_reservation "1_F" "1_F0|1_F1|1_F2") 462132718Skan 463132718Skan;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B 464132718Skan;;; unit. That is, a B slot in 1st position is dispersed to B0. In the 465132718Skan;;; 2nd position it is dispersed to B2". 466132718Skan(define_reservation "1_NB" 467132718Skan "1_0b.bb+1_unb0|1_0bb.b+1_unb1|1_0bbb.+1_unb2\ 468132718Skan |1_0mb.b+1_unb1|1_0mbb.+1_unb2\ 469132718Skan |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0\ 470132718Skan |1_1b.bb+1_unb0|1_1bb.b+1_unb1\ 471132718Skan |1_1bbb.+1_unb2|1_1mb.b+1_unb1|1_1mbb.+1_unb2|1_1mib.+1_unb0\ 472132718Skan |1_1mmb.+1_unb0|1_1mfb.+1_unb0") 473132718Skan 474132718Skan(define_reservation "1_B0" 475132718Skan "1_0b.bb+1_ub0|1_0bb.b+1_ub1|1_0bbb.+1_ub2\ 476132718Skan |1_0mb.b+1_ub1|1_0mbb.+1_ub2|1_0mib.+1_ub2\ 477132718Skan |1_0mfb.+1_ub2|1_1b.bb+1_ub0|1_1bb.b+1_ub1\ 478132718Skan |1_1bbb.+1_ub2|1_1mb.b+1_ub1\ 479132718Skan |1_1mib.+1_ub2|1_1mmb.+1_ub2|1_1mfb.+1_ub2") 480132718Skan 481132718Skan(define_reservation "1_B1" 482132718Skan "1_0m.bb+1_um0+1_0mb.b+1_ub1|1_0mi.b+1_ui0+1_0mib.+1_ub2\ 483132718Skan |1_0mf.b+1_uf0+1_0mfb.+1_ub2\ 484132718Skan |(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0)+1_1b.bb+1_ub0\ 485132718Skan |1_1m.bb+(1_um0|1_um1)+1_1mb.b+1_ub1\ 486132718Skan |1_1mi.b+(1_ui0|1_ui1)+1_1mib.+1_ub2\ 487132718Skan |1_1mm.b+1_um1+1_1mmb.+1_ub2\ 488132718Skan |1_1mf.b+1_uf1+1_1mfb.+1_ub2") 489132718Skan 490132718Skan(define_reservation "1_B" "1_B0|1_B1") 491132718Skan 492132718Skan;; MLX bunlde uses ports equivalent to MFI bundles. 493132718Skan(define_reservation "1_L0" "1_0mlx.+1_ui0+1_uf0|1_1mlx.+(1_ui0|1_ui1)+1_uf1") 494132718Skan(define_reservation "1_L1" 495132718Skan "1_0m.lx+1_um0+1_0mlx.+1_ui0+1_uf0\ 496132718Skan |1_1m.lx+(1_um0|1_um1)+1_1mlx.+(1_ui0|1_ui1)+1_uf1") 497132718Skan(define_reservation "1_L2" 498132718Skan "(1_0mii.+(1_ui0|1_ui1)|1_0mmi.+1_ui0|1_0mfi.+1_ui0\ 499132718Skan |1_0mib.+1_unb0|1_0mmb.+1_unb0|1_0mfb.+1_unb0) 500132718Skan +1_1m.lx+(1_um0|1_um1)+1_1mlx.+1_ui1+1_uf1") 501132718Skan(define_reservation "1_L" "1_L0|1_L1|1_L2") 502132718Skan 503132718Skan(define_reservation "1_A" "1_M|1_I") 504132718Skan 505132718Skan(define_insn_reservation "1_stop_bit" 0 506132718Skan (and (and (eq_attr "cpu" "itanium") 507132718Skan (eq_attr "itanium_class" "stop_bit")) 508132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 509132718Skan "1_stop|1_m0_stop|1_m1_stop|1_mi0_stop|1_mi1_stop") 510132718Skan 511132718Skan(define_insn_reservation "1_br" 0 512132718Skan (and (and (eq_attr "cpu" "itanium") 513132718Skan (eq_attr "itanium_class" "br")) 514132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_B") 515132718Skan(define_insn_reservation "1_scall" 0 516132718Skan (and (and (eq_attr "cpu" "itanium") 517132718Skan (eq_attr "itanium_class" "scall")) 518132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_B") 519132718Skan(define_insn_reservation "1_fcmp" 2 520132718Skan (and (and (eq_attr "cpu" "itanium") 521132718Skan (eq_attr "itanium_class" "fcmp")) 522132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 523132718Skan "1_F+1_not_uf1") 524132718Skan(define_insn_reservation "1_fcvtfx" 7 525132718Skan (and (and (eq_attr "cpu" "itanium") 526132718Skan (eq_attr "itanium_class" "fcvtfx")) 527132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_F") 528169689Skan 529132718Skan(define_insn_reservation "1_fld" 9 530169689Skan (and (and (and (eq_attr "cpu" "itanium") 531169689Skan (eq_attr "itanium_class" "fld")) 532169689Skan (eq_attr "check_load" "no")) 533132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 534169689Skan(define_insn_reservation "1_fldc" 0 535169689Skan (and (and (and (eq_attr "cpu" "itanium") 536169689Skan (eq_attr "itanium_class" "fld")) 537169689Skan (eq_attr "check_load" "yes")) 538169689Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 539169689Skan 540169689Skan(define_insn_reservation "1_fldp" 9 541169689Skan (and (and (and (eq_attr "cpu" "itanium") 542169689Skan (eq_attr "itanium_class" "fldp")) 543169689Skan (eq_attr "check_load" "no")) 544169689Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 545169689Skan(define_insn_reservation "1_fldpc" 0 546169689Skan (and (and (and (eq_attr "cpu" "itanium") 547169689Skan (eq_attr "itanium_class" "fldp")) 548169689Skan (eq_attr "check_load" "yes")) 549169689Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 550169689Skan 551132718Skan(define_insn_reservation "1_fmac" 5 552132718Skan (and (and (eq_attr "cpu" "itanium") 553132718Skan (eq_attr "itanium_class" "fmac")) 554132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_F") 555132718Skan(define_insn_reservation "1_fmisc" 5 556132718Skan (and (and (eq_attr "cpu" "itanium") 557132718Skan (eq_attr "itanium_class" "fmisc")) 558132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 559132718Skan "1_F+1_not_uf1") 560132718Skan 561132718Skan;; There is only one insn `mov = ar.bsp' for frar_i: 562132718Skan(define_insn_reservation "1_frar_i" 13 563132718Skan (and (and (eq_attr "cpu" "itanium") 564132718Skan (eq_attr "itanium_class" "frar_i")) 565132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 566132718Skan "1_I+1_not_ui1") 567132718Skan;; There is only two insns `mov = ar.unat' or `mov = ar.ccv' for frar_m: 568132718Skan(define_insn_reservation "1_frar_m" 6 569132718Skan (and (and (eq_attr "cpu" "itanium") 570132718Skan (eq_attr "itanium_class" "frar_m")) 571132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 572132718Skan "1_M+1_not_um1") 573132718Skan(define_insn_reservation "1_frbr" 2 574132718Skan (and (and (eq_attr "cpu" "itanium") 575132718Skan (eq_attr "itanium_class" "frbr")) 576132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 577132718Skan "1_I+1_not_ui1") 578132718Skan(define_insn_reservation "1_frfr" 2 579132718Skan (and (and (eq_attr "cpu" "itanium") 580132718Skan (eq_attr "itanium_class" "frfr")) 581132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 582132718Skan "1_M+1_not_um1") 583132718Skan(define_insn_reservation "1_frpr" 2 584132718Skan (and (and (eq_attr "cpu" "itanium") 585132718Skan (eq_attr "itanium_class" "frpr")) 586132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 587132718Skan "1_I+1_not_ui1") 588132718Skan 589132718Skan(define_insn_reservation "1_ialu" 1 590132718Skan (and (and (eq_attr "cpu" "itanium") 591132718Skan (eq_attr "itanium_class" "ialu")) 592132718Skan (eq (symbol_ref 593132718Skan "bundling_p || ia64_produce_address_p (insn)") 594132718Skan (const_int 0))) 595132718Skan "1_A") 596132718Skan(define_insn_reservation "1_ialu_addr" 1 597132718Skan (and (and (eq_attr "cpu" "itanium") 598132718Skan (eq_attr "itanium_class" "ialu")) 599132718Skan (eq (symbol_ref 600132718Skan "!bundling_p && ia64_produce_address_p (insn)") 601132718Skan (const_int 1))) 602132718Skan "1_M") 603132718Skan(define_insn_reservation "1_icmp" 1 604132718Skan (and (and (eq_attr "cpu" "itanium") 605132718Skan (eq_attr "itanium_class" "icmp")) 606132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_A") 607132718Skan(define_insn_reservation "1_ilog" 1 608132718Skan (and (and (eq_attr "cpu" "itanium") 609132718Skan (eq_attr "itanium_class" "ilog")) 610132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_A") 611169689Skan(define_insn_reservation "1_mmalua" 2 612169689Skan (and (and (eq_attr "cpu" "itanium") 613169689Skan (eq_attr "itanium_class" "mmalua")) 614169689Skan (eq (symbol_ref "bundling_p") (const_int 0))) 615169689Skan "1_A") 616132718Skan(define_insn_reservation "1_ishf" 1 617132718Skan (and (and (eq_attr "cpu" "itanium") 618132718Skan (eq_attr "itanium_class" "ishf")) 619132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 620132718Skan "1_I+1_not_ui1") 621132718Skan(define_insn_reservation "1_ld" 2 622169689Skan (and (and (and (eq_attr "cpu" "itanium") 623169689Skan (eq_attr "itanium_class" "ld")) 624169689Skan (eq_attr "check_load" "no")) 625132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 626169689Skan(define_insn_reservation "1_ldc" 0 627169689Skan (and (and (and (eq_attr "cpu" "itanium") 628169689Skan (eq_attr "itanium_class" "ld")) 629169689Skan (eq_attr "check_load" "yes")) 630169689Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 631132718Skan(define_insn_reservation "1_long_i" 1 632132718Skan (and (and (eq_attr "cpu" "itanium") 633132718Skan (eq_attr "itanium_class" "long_i")) 634132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_L") 635132718Skan(define_insn_reservation "1_mmmul" 2 636132718Skan (and (and (eq_attr "cpu" "itanium") 637132718Skan (eq_attr "itanium_class" "mmmul")) 638132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 639132718Skan "1_I+1_not_ui1") 640132718Skan(define_insn_reservation "1_mmshf" 2 641132718Skan (and (and (eq_attr "cpu" "itanium") 642132718Skan (eq_attr "itanium_class" "mmshf")) 643132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_I") 644132718Skan(define_insn_reservation "1_mmshfi" 1 645132718Skan (and (and (eq_attr "cpu" "itanium") 646132718Skan (eq_attr "itanium_class" "mmshfi")) 647132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_I") 648132718Skan 649132718Skan;; Now we have only one insn (flushrs) of such class. We assume that flushrs 650132718Skan;; is the 1st syllable of the bundle after stop bit. 651132718Skan(define_insn_reservation "1_rse_m" 0 652132718Skan (and (and (eq_attr "cpu" "itanium") 653132718Skan (eq_attr "itanium_class" "rse_m")) 654132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 655132718Skan "(1_0m.ii|1_0m.mi|1_0m.fi|1_0m.mf|1_0b.bb|1_0m.bb\ 656132718Skan |1_0m.ib|1_0m.mb|1_0m.fb|1_0m.lx)+1_um0") 657132718Skan(define_insn_reservation "1_sem" 0 658132718Skan (and (and (eq_attr "cpu" "itanium") 659132718Skan (eq_attr "itanium_class" "sem")) 660132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 661132718Skan "1_M+1_not_um1") 662132718Skan(define_insn_reservation "1_stf" 1 663132718Skan (and (and (eq_attr "cpu" "itanium") 664132718Skan (eq_attr "itanium_class" "stf")) 665132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 666132718Skan(define_insn_reservation "1_st" 1 667132718Skan (and (and (eq_attr "cpu" "itanium") 668132718Skan (eq_attr "itanium_class" "st")) 669132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 670132718Skan(define_insn_reservation "1_syst_m0" 0 671132718Skan (and (and (eq_attr "cpu" "itanium") 672132718Skan (eq_attr "itanium_class" "syst_m0")) 673132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 674132718Skan "1_M+1_not_um1") 675132718Skan(define_insn_reservation "1_syst_m" 0 676132718Skan (and (and (eq_attr "cpu" "itanium") 677132718Skan (eq_attr "itanium_class" "syst_m")) 678132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 679132718Skan(define_insn_reservation "1_tbit" 1 680132718Skan (and (and (eq_attr "cpu" "itanium") 681132718Skan (eq_attr "itanium_class" "tbit")) 682132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 683132718Skan "1_I+1_not_ui1") 684132718Skan 685132718Skan;; There is only ony insn `mov ar.pfs =' for toar_i: 686132718Skan(define_insn_reservation "1_toar_i" 0 687132718Skan (and (and (eq_attr "cpu" "itanium") 688132718Skan (eq_attr "itanium_class" "toar_i")) 689132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 690132718Skan "1_I+1_not_ui1") 691132718Skan;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m: 692132718Skan(define_insn_reservation "1_toar_m" 5 693132718Skan (and (and (eq_attr "cpu" "itanium") 694132718Skan (eq_attr "itanium_class" "toar_m")) 695132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 696132718Skan "1_M+1_not_um1") 697132718Skan(define_insn_reservation "1_tobr" 1 698132718Skan (and (and (eq_attr "cpu" "itanium") 699132718Skan (eq_attr "itanium_class" "tobr")) 700132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 701132718Skan "1_I+1_not_ui1") 702132718Skan(define_insn_reservation "1_tofr" 9 703132718Skan (and (and (eq_attr "cpu" "itanium") 704132718Skan (eq_attr "itanium_class" "tofr")) 705132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 706132718Skan(define_insn_reservation "1_topr" 1 707132718Skan (and (and (eq_attr "cpu" "itanium") 708132718Skan (eq_attr "itanium_class" "topr")) 709132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 710132718Skan "1_I+1_not_ui1") 711132718Skan(define_insn_reservation "1_xmpy" 7 712132718Skan (and (and (eq_attr "cpu" "itanium") 713132718Skan (eq_attr "itanium_class" "xmpy")) 714132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_F") 715132718Skan(define_insn_reservation "1_xtd" 1 716132718Skan (and (and (eq_attr "cpu" "itanium") 717132718Skan (eq_attr "itanium_class" "xtd")) 718132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_I") 719132718Skan 720169689Skan(define_insn_reservation "1_chk_s_i" 0 721132718Skan (and (and (eq_attr "cpu" "itanium") 722169689Skan (eq_attr "itanium_class" "chk_s_i")) 723132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_A") 724169689Skan(define_insn_reservation "1_chk_s_f" 0 725169689Skan (and (and (eq_attr "cpu" "itanium") 726169689Skan (eq_attr "itanium_class" "chk_s_f")) 727169689Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 728169689Skan(define_insn_reservation "1_chk_a" 0 729169689Skan (and (and (eq_attr "cpu" "itanium") 730169689Skan (eq_attr "itanium_class" "chk_a")) 731169689Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 732169689Skan 733132718Skan(define_insn_reservation "1_lfetch" 0 734132718Skan (and (and (eq_attr "cpu" "itanium") 735132718Skan (eq_attr "itanium_class" "lfetch")) 736132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_M") 737132718Skan 738132718Skan(define_insn_reservation "1_nop_m" 0 739132718Skan (and (and (eq_attr "cpu" "itanium") 740132718Skan (eq_attr "itanium_class" "nop_m")) 741132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_M0") 742132718Skan(define_insn_reservation "1_nop_b" 0 743132718Skan (and (and (eq_attr "cpu" "itanium") 744132718Skan (eq_attr "itanium_class" "nop_b")) 745132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_NB") 746132718Skan(define_insn_reservation "1_nop_i" 0 747132718Skan (and (and (eq_attr "cpu" "itanium") 748132718Skan (eq_attr "itanium_class" "nop_i")) 749132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_I0") 750132718Skan(define_insn_reservation "1_nop_f" 0 751132718Skan (and (and (eq_attr "cpu" "itanium") 752132718Skan (eq_attr "itanium_class" "nop_f")) 753132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_F0") 754132718Skan(define_insn_reservation "1_nop_x" 0 755132718Skan (and (and (eq_attr "cpu" "itanium") 756132718Skan (eq_attr "itanium_class" "nop_x")) 757132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_L0") 758132718Skan 759132718Skan;; We assume that there is no insn issued on the same cycle as unknown insn. 760132718Skan(define_cpu_unit "1_empty" "one") 761132718Skan(exclusion_set "1_empty" 762132718Skan "1_0m.ii,1_0m.mi,1_0m.fi,1_0m.mf,1_0b.bb,1_0m.bb,1_0m.ib,1_0m.mb,1_0m.fb,\ 763132718Skan 1_0m.lx") 764132718Skan 765132718Skan(define_insn_reservation "1_unknown" 1 766132718Skan (and (and (eq_attr "cpu" "itanium") 767132718Skan (eq_attr "itanium_class" "unknown")) 768132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "1_empty") 769132718Skan 770132718Skan(define_insn_reservation "1_nop" 1 771132718Skan (and (and (eq_attr "cpu" "itanium") 772132718Skan (eq_attr "itanium_class" "nop")) 773132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 774132718Skan "1_M0|1_NB|1_I0|1_F0") 775132718Skan 776132718Skan(define_insn_reservation "1_ignore" 0 777132718Skan (and (and (eq_attr "cpu" "itanium") 778132718Skan (eq_attr "itanium_class" "ignore")) 779132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) "nothing") 780132718Skan 781132718Skan 782132718Skan(define_cpu_unit 783132718Skan "1_0m_bs, 1_0mi_bs, 1_0mm_bs, 1_0mf_bs, 1_0b_bs, 1_0bb_bs, 1_0mb_bs" 784132718Skan "one") 785132718Skan(define_cpu_unit 786132718Skan "1_1m_bs, 1_1mi_bs, 1_1mm_bs, 1_1mf_bs, 1_1b_bs, 1_1bb_bs, 1_1mb_bs" 787132718Skan "one") 788132718Skan 789132718Skan(define_cpu_unit "1_m_cont, 1_mi_cont, 1_mm_cont, 1_mf_cont, 1_mb_cont,\ 790132718Skan 1_b_cont, 1_bb_cont" "one") 791132718Skan 792132718Skan;; For stop in the middle of the bundles. 793132718Skan(define_cpu_unit "1_m_stop, 1_m0_stop, 1_m1_stop, 1_0mmi_cont" "one") 794132718Skan(define_cpu_unit "1_mi_stop, 1_mi0_stop, 1_mi1_stop, 1_0mii_cont" "one") 795132718Skan 796132718Skan(final_presence_set "1_0m_bs" 797132718Skan "1_0m.ii, 1_0m.mi, 1_0m.mf, 1_0m.fi, 1_0m.bb,\ 798132718Skan 1_0m.ib, 1_0m.fb, 1_0m.mb, 1_0m.lx") 799132718Skan(final_presence_set "1_1m_bs" 800132718Skan "1_1m.ii, 1_1m.mi, 1_1m.fi, 1_1m.bb, 1_1m.ib, 1_1m.fb, 1_1m.mb,\ 801132718Skan 1_1m.lx") 802132718Skan(final_presence_set "1_0mi_bs" "1_0mi.i, 1_0mi.i") 803132718Skan(final_presence_set "1_1mi_bs" "1_1mi.i, 1_1mi.i") 804132718Skan(final_presence_set "1_0mm_bs" "1_0mm.i, 1_0mm.f, 1_0mm.b") 805132718Skan(final_presence_set "1_1mm_bs" "1_1mm.i, 1_1mm.b") 806132718Skan(final_presence_set "1_0mf_bs" "1_0mf.i, 1_0mf.b") 807132718Skan(final_presence_set "1_1mf_bs" "1_1mf.i, 1_1mf.b") 808132718Skan(final_presence_set "1_0b_bs" "1_0b.bb") 809132718Skan(final_presence_set "1_1b_bs" "1_1b.bb") 810132718Skan(final_presence_set "1_0bb_bs" "1_0bb.b") 811132718Skan(final_presence_set "1_1bb_bs" "1_1bb.b") 812132718Skan(final_presence_set "1_0mb_bs" "1_0mb.b") 813132718Skan(final_presence_set "1_1mb_bs" "1_1mb.b") 814132718Skan 815132718Skan(exclusion_set "1_0m_bs" 816132718Skan "1_0mi.i, 1_0mm.i, 1_0mm.f, 1_0mf.i, 1_0mb.b,\ 817132718Skan 1_0mi.b, 1_0mf.b, 1_0mm.b, 1_0mlx., 1_m0_stop") 818132718Skan(exclusion_set "1_1m_bs" 819132718Skan "1_1mi.i, 1_1mm.i, 1_1mf.i, 1_1mb.b, 1_1mi.b, 1_1mf.b, 1_1mm.b,\ 820132718Skan 1_1mlx., 1_m1_stop") 821132718Skan(exclusion_set "1_0mi_bs" "1_0mii., 1_0mib., 1_mi0_stop") 822132718Skan(exclusion_set "1_1mi_bs" "1_1mii., 1_1mib., 1_mi1_stop") 823132718Skan(exclusion_set "1_0mm_bs" "1_0mmi., 1_0mmf., 1_0mmb.") 824132718Skan(exclusion_set "1_1mm_bs" "1_1mmi., 1_1mmb.") 825132718Skan(exclusion_set "1_0mf_bs" "1_0mfi., 1_0mfb.") 826132718Skan(exclusion_set "1_1mf_bs" "1_1mfi., 1_1mfb.") 827132718Skan(exclusion_set "1_0b_bs" "1_0bb.b") 828132718Skan(exclusion_set "1_1b_bs" "1_1bb.b") 829132718Skan(exclusion_set "1_0bb_bs" "1_0bbb.") 830132718Skan(exclusion_set "1_1bb_bs" "1_1bbb.") 831132718Skan(exclusion_set "1_0mb_bs" "1_0mbb.") 832132718Skan(exclusion_set "1_1mb_bs" "1_1mbb.") 833132718Skan 834132718Skan(exclusion_set 835132718Skan "1_0m_bs, 1_0mi_bs, 1_0mm_bs, 1_0mf_bs, 1_0b_bs, 1_0bb_bs, 1_0mb_bs, 836132718Skan 1_1m_bs, 1_1mi_bs, 1_1mm_bs, 1_1mf_bs, 1_1b_bs, 1_1bb_bs, 1_1mb_bs" 837132718Skan "1_stop") 838132718Skan 839132718Skan(final_presence_set 840132718Skan "1_0mi.i, 1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0mb.b,\ 841132718Skan 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx." 842132718Skan "1_m_cont") 843132718Skan(final_presence_set "1_0mii., 1_0mib." "1_mi_cont") 844132718Skan(final_presence_set "1_0mmi., 1_0mmf., 1_0mmb." "1_mm_cont") 845132718Skan(final_presence_set "1_0mfi., 1_0mfb." "1_mf_cont") 846132718Skan(final_presence_set "1_0bb.b" "1_b_cont") 847132718Skan(final_presence_set "1_0bbb." "1_bb_cont") 848132718Skan(final_presence_set "1_0mbb." "1_mb_cont") 849132718Skan 850132718Skan(exclusion_set 851132718Skan "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\ 852132718Skan 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx" 853132718Skan "1_m_cont, 1_mi_cont, 1_mm_cont, 1_mf_cont,\ 854132718Skan 1_mb_cont, 1_b_cont, 1_bb_cont") 855132718Skan 856132718Skan(exclusion_set "1_empty" 857132718Skan "1_m_cont,1_mi_cont,1_mm_cont,1_mf_cont,\ 858132718Skan 1_mb_cont,1_b_cont,1_bb_cont") 859132718Skan 860132718Skan;; For m;mi bundle 861132718Skan(final_presence_set "1_m0_stop" "1_0m.mi") 862132718Skan(final_presence_set "1_0mm.i" "1_0mmi_cont") 863132718Skan(exclusion_set "1_0mmi_cont" 864132718Skan "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\ 865132718Skan 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 866132718Skan(exclusion_set "1_m0_stop" "1_0mm.i") 867132718Skan(final_presence_set "1_m1_stop" "1_1m.mi") 868132718Skan(exclusion_set "1_m1_stop" "1_1mm.i") 869132718Skan(final_presence_set "1_m_stop" "1_m0_stop, 1_m1_stop") 870132718Skan 871132718Skan;; For mi;i bundle 872132718Skan(final_presence_set "1_mi0_stop" "1_0mi.i") 873132718Skan(final_presence_set "1_0mii." "1_0mii_cont") 874132718Skan(exclusion_set "1_0mii_cont" 875132718Skan "1_0m.ii, 1_0m.mi, 1_0m.fi, 1_0m.mf, 1_0b.bb, 1_0m.bb,\ 876132718Skan 1_0m.ib, 1_0m.mb, 1_0m.fb, 1_0m.lx") 877132718Skan(exclusion_set "1_mi0_stop" "1_0mii.") 878132718Skan(final_presence_set "1_mi1_stop" "1_1mi.i") 879132718Skan(exclusion_set "1_mi1_stop" "1_1mii.") 880132718Skan(final_presence_set "1_mi_stop" "1_mi0_stop, 1_mi1_stop") 881132718Skan 882132718Skan(final_absence_set 883132718Skan "1_0m.ii,1_0mi.i,1_0mii.,1_0m.mi,1_0mm.i,1_0mmi.,1_0m.fi,1_0mf.i,1_0mfi.,\ 884132718Skan 1_0m.mf,1_0mm.f,1_0mmf.,1_0b.bb,1_0bb.b,1_0bbb.,1_0m.bb,1_0mb.b,1_0mbb.,\ 885132718Skan 1_0m.ib,1_0mi.b,1_0mib.,1_0m.mb,1_0mm.b,1_0mmb.,1_0m.fb,1_0mf.b,1_0mfb.,\ 886132718Skan 1_0m.lx,1_0mlx., \ 887132718Skan 1_1m.ii,1_1mi.i,1_1mii.,1_1m.mi,1_1mm.i,1_1mmi.,1_1m.fi,1_1mf.i,1_1mfi.,\ 888132718Skan 1_1b.bb,1_1bb.b,1_1bbb.,1_1m.bb,1_1mb.b,1_1mbb.,\ 889132718Skan 1_1m.ib,1_1mi.b,1_1mib.,1_1m.mb,1_1mm.b,1_1mmb.,1_1m.fb,1_1mf.b,1_1mfb.,\ 890132718Skan 1_1m.lx,1_1mlx." 891132718Skan "1_m0_stop,1_m1_stop,1_mi0_stop,1_mi1_stop") 892132718Skan 893132718Skan(define_cpu_unit "1_m_cont_only, 1_b_cont_only" "one") 894132718Skan(define_cpu_unit "1_mi_cont_only, 1_mm_cont_only, 1_mf_cont_only" "one") 895132718Skan(define_cpu_unit "1_mb_cont_only, 1_bb_cont_only" "one") 896132718Skan 897132718Skan(final_presence_set "1_m_cont_only" "1_m_cont") 898132718Skan(exclusion_set "1_m_cont_only" 899132718Skan "1_0mi.i, 1_0mm.i, 1_0mf.i, 1_0mm.f, 1_0mb.b,\ 900132718Skan 1_0mi.b, 1_0mm.b, 1_0mf.b, 1_0mlx.") 901132718Skan 902132718Skan(final_presence_set "1_b_cont_only" "1_b_cont") 903132718Skan(exclusion_set "1_b_cont_only" "1_0bb.b") 904132718Skan 905132718Skan(final_presence_set "1_mi_cont_only" "1_mi_cont") 906132718Skan(exclusion_set "1_mi_cont_only" "1_0mii., 1_0mib.") 907132718Skan 908132718Skan(final_presence_set "1_mm_cont_only" "1_mm_cont") 909132718Skan(exclusion_set "1_mm_cont_only" "1_0mmi., 1_0mmf., 1_0mmb.") 910132718Skan 911132718Skan(final_presence_set "1_mf_cont_only" "1_mf_cont") 912132718Skan(exclusion_set "1_mf_cont_only" "1_0mfi., 1_0mfb.") 913132718Skan 914132718Skan(final_presence_set "1_mb_cont_only" "1_mb_cont") 915132718Skan(exclusion_set "1_mb_cont_only" "1_0mbb.") 916132718Skan 917132718Skan(final_presence_set "1_bb_cont_only" "1_bb_cont") 918132718Skan(exclusion_set "1_bb_cont_only" "1_0bbb.") 919132718Skan 920132718Skan(define_insn_reservation "1_pre_cycle" 0 921132718Skan (and (and (eq_attr "cpu" "itanium") 922132718Skan (eq_attr "itanium_class" "pre_cycle")) 923132718Skan (eq (symbol_ref "bundling_p") (const_int 0))) 924132718Skan "(1_0m_bs, 1_m_cont) \ 925132718Skan | (1_0mi_bs, (1_mi_cont|nothing)) \ 926132718Skan | (1_0mm_bs, 1_mm_cont) \ 927132718Skan | (1_0mf_bs, (1_mf_cont|nothing)) \ 928132718Skan | (1_0b_bs, (1_b_cont|nothing)) \ 929132718Skan | (1_0bb_bs, (1_bb_cont|nothing)) \ 930132718Skan | (1_0mb_bs, (1_mb_cont|nothing)) \ 931132718Skan | (1_1m_bs, 1_m_cont) \ 932132718Skan | (1_1mi_bs, (1_mi_cont|nothing)) \ 933132718Skan | (1_1mm_bs, 1_mm_cont) \ 934132718Skan | (1_1mf_bs, (1_mf_cont|nothing)) \ 935132718Skan | (1_1b_bs, (1_b_cont|nothing)) \ 936132718Skan | (1_1bb_bs, (1_bb_cont|nothing)) \ 937132718Skan | (1_1mb_bs, (1_mb_cont|nothing)) \ 938132718Skan | (1_m_cont_only, (1_m_cont|nothing)) \ 939132718Skan | (1_b_cont_only, (1_b_cont|nothing)) \ 940132718Skan | (1_mi_cont_only, (1_mi_cont|nothing)) \ 941132718Skan | (1_mm_cont_only, (1_mm_cont|nothing)) \ 942132718Skan | (1_mf_cont_only, (1_mf_cont|nothing)) \ 943132718Skan | (1_mb_cont_only, (1_mb_cont|nothing)) \ 944132718Skan | (1_bb_cont_only, (1_bb_cont|nothing)) \ 945132718Skan | (1_m_stop, (1_0mmi_cont|nothing)) \ 946132718Skan | (1_mi_stop, (1_0mii_cont|nothing))") 947132718Skan 948132718Skan;; Bypasses: 949132718Skan(define_bypass 1 "1_fcmp" "1_br,1_scall") 950132718Skan;; ??? I found 7 cycle delay for 1_fmac -> 1_fcmp for Itanium1 951132718Skan(define_bypass 7 "1_fmac" "1_fmisc,1_fcvtfx,1_xmpy,1_fcmp") 952132718Skan 953132718Skan;; ??? 954132718Skan(define_bypass 3 "1_frbr" "1_mmmul,1_mmshf") 955132718Skan(define_bypass 14 "1_frar_i" "1_mmmul,1_mmshf") 956132718Skan(define_bypass 7 "1_frar_m" "1_mmmul,1_mmshf") 957132718Skan 958132718Skan;; ???? 959132718Skan;; There is only one insn `mov ar.pfs =' for toar_i. 960132718Skan(define_bypass 0 "1_tobr,1_topr,1_toar_i" "1_br,1_scall") 961132718Skan 962169689Skan(define_bypass 3 "1_ialu,1_ialu_addr" "1_mmmul,1_mmshf,1_mmalua") 963132718Skan;; ??? howto describe ialu for I slot only. We use ialu_addr for that 964132718Skan;;(define_bypass 2 "1_ialu" "1_ld" "ia64_ld_address_bypass_p") 965132718Skan;; ??? howto describe ialu st/address for I slot only. We use ialu_addr 966132718Skan;; for that. 967132718Skan;;(define_bypass 2 "1_ialu" "1_st" "ia64_st_address_bypass_p") 968132718Skan 969132718Skan(define_bypass 0 "1_icmp" "1_br,1_scall") 970132718Skan 971132718Skan(define_bypass 3 "1_ilog" "1_mmmul,1_mmshf") 972132718Skan 973132718Skan(define_bypass 2 "1_ilog,1_xtd" "1_ld" "ia64_ld_address_bypass_p") 974132718Skan(define_bypass 2 "1_ilog,1_xtd" "1_st" "ia64_st_address_bypass_p") 975132718Skan 976169689Skan(define_bypass 3 "1_ld,1_ldc" "1_mmmul,1_mmshf") 977132718Skan(define_bypass 3 "1_ld" "1_ld" "ia64_ld_address_bypass_p") 978132718Skan(define_bypass 3 "1_ld" "1_st" "ia64_st_address_bypass_p") 979132718Skan 980132718Skan;; Intel docs say only LD, ST, IALU, ILOG, ISHF consumers have latency 4, 981132718Skan;; but HP engineers say any non-MM operation. 982169689Skan(define_bypass 4 "1_mmmul,1_mmshf,1_mmalua" 983169689Skan "1_br,1_fcmp,1_fcvtfx,1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,\ 984169689Skan 1_frbr,1_frfr,1_frpr,1_ialu,1_icmp,1_ilog,1_ishf,1_ld,1_ldc,1_chk_s_i,1_chk_s_f,1_chk_a,\ 985132718Skan 1_long_i,1_rse_m,1_sem,1_stf,1_st,1_syst_m0,1_syst_m,\ 986132718Skan 1_tbit,1_toar_i,1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd") 987132718Skan 988132718Skan;; ??? how to describe that if scheduled < 4 cycle then latency is 10 cycles. 989132718Skan;; (define_bypass 10 "1_mmmul,1_mmshf" "1_ialu,1_ilog,1_ishf,1_st,1_ld") 990132718Skan 991132718Skan(define_bypass 0 "1_tbit" "1_br,1_scall") 992132718Skan 993132718Skan(define_bypass 8 "1_tofr" "1_frfr,1_stf") 994132718Skan(define_bypass 7 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy" "1_frfr") 995132718Skan(define_bypass 8 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy" "1_stf") 996132718Skan 997132718Skan;; We don't use here fcmp because scall may be predicated. 998169689Skan(define_bypass 0 "1_fcvtfx,1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,\ 999132718Skan 1_frbr,1_frfr,1_frpr,1_ialu,1_ialu_addr,1_ilog,1_ishf,\ 1000169689Skan 1_ld,1_ldc,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,\ 1001169689Skan 1_toar_m,1_tofr,1_xmpy,1_xtd" "1_scall") 1002132718Skan 1003132718Skan(define_bypass 0 "1_unknown,1_ignore,1_stop_bit,1_br,1_fcmp,1_fcvtfx,\ 1004169689Skan 1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,1_frbr,1_frfr,\ 1005169689Skan 1_frpr,1_ialu,1_ialu_addr,1_icmp,1_ilog,1_ishf,1_ld,1_ldc,\ 1006169689Skan 1_chk_s_i,1_chk_s_f,1_chk_a,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,1_nop,\ 1007132718Skan 1_nop_b,1_nop_f,1_nop_i,1_nop_m,1_nop_x,1_rse_m,1_scall,\ 1008132718Skan 1_sem,1_stf,1_st,1_syst_m0,1_syst_m,1_tbit,1_toar_i,\ 1009132718Skan 1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd,1_lfetch" 1010132718Skan "1_ignore") 1011132718Skan 1012132718Skan 1013132718Skan;; Bundling 1014132718Skan 1015132718Skan(define_automaton "oneb") 1016132718Skan 1017132718Skan;; Pseudo units for quicker searching for position in two packet window. */ 1018132718Skan(define_query_cpu_unit "1_1,1_2,1_3,1_4,1_5,1_6" "oneb") 1019132718Skan 1020132718Skan;; All possible combinations of bundles/syllables 1021132718Skan(define_cpu_unit 1022132718Skan "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1023132718Skan 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx" "oneb") 1024132718Skan(define_cpu_unit 1025132718Skan "1b_0mi.i, 1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\ 1026132718Skan 1b_0mi.b, 1b_0mm.b, 1b_0mf.b" "oneb") 1027132718Skan(define_query_cpu_unit 1028132718Skan "1b_0mii., 1b_0mmi., 1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\ 1029132718Skan 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx." "oneb") 1030132718Skan 1031132718Skan(define_cpu_unit "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\ 1032132718Skan 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx" "oneb") 1033132718Skan(define_cpu_unit "1b_1mi.i, 1b_1mm.i, 1b_1mf.i, 1b_1bb.b, 1b_1mb.b,\ 1034132718Skan 1b_1mi.b, 1b_1mm.b, 1b_1mf.b" "oneb") 1035132718Skan(define_query_cpu_unit "1b_1mii., 1b_1mmi., 1b_1mfi., 1b_1bbb., 1b_1mbb.,\ 1036132718Skan 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx." "oneb") 1037132718Skan 1038132718Skan;; Slot 1 1039132718Skan(exclusion_set "1b_0m.ii" 1040132718Skan "1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1041132718Skan 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1042132718Skan(exclusion_set "1b_0m.mi" 1043132718Skan "1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb, 1b_0m.ib,\ 1044132718Skan 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1045132718Skan(exclusion_set "1b_0m.fi" 1046132718Skan "1b_0m.mf, 1b_0b.bb, 1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1047132718Skan(exclusion_set "1b_0m.mf" 1048132718Skan "1b_0b.bb, 1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1049132718Skan(exclusion_set "1b_0b.bb" "1b_0m.bb, 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1050132718Skan(exclusion_set "1b_0m.bb" "1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1051132718Skan(exclusion_set "1b_0m.ib" "1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1052132718Skan(exclusion_set "1b_0m.mb" "1b_0m.fb, 1b_0m.lx") 1053132718Skan(exclusion_set "1b_0m.fb" "1b_0m.lx") 1054132718Skan 1055132718Skan;; Slot 2 1056132718Skan(exclusion_set "1b_0mi.i" 1057132718Skan "1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\ 1058132718Skan 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1059132718Skan(exclusion_set "1b_0mm.i" 1060132718Skan "1b_0mf.i, 1b_0mm.f, 1b_0bb.b, 1b_0mb.b,\ 1061132718Skan 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1062132718Skan(exclusion_set "1b_0mf.i" 1063132718Skan "1b_0mm.f, 1b_0bb.b, 1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1064132718Skan(exclusion_set "1b_0mm.f" 1065132718Skan "1b_0bb.b, 1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1066132718Skan(exclusion_set "1b_0bb.b" "1b_0mb.b, 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1067132718Skan(exclusion_set "1b_0mb.b" "1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1068132718Skan(exclusion_set "1b_0mi.b" "1b_0mm.b, 1b_0mf.b, 1b_0mlx.") 1069132718Skan(exclusion_set "1b_0mm.b" "1b_0mf.b, 1b_0mlx.") 1070132718Skan(exclusion_set "1b_0mf.b" "1b_0mlx.") 1071132718Skan 1072132718Skan;; Slot 3 1073132718Skan(exclusion_set "1b_0mii." 1074132718Skan "1b_0mmi., 1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\ 1075132718Skan 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1076132718Skan(exclusion_set "1b_0mmi." 1077132718Skan "1b_0mfi., 1b_0mmf., 1b_0bbb., 1b_0mbb.,\ 1078132718Skan 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1079132718Skan(exclusion_set "1b_0mfi." 1080132718Skan "1b_0mmf., 1b_0bbb., 1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1081132718Skan(exclusion_set "1b_0mmf." 1082132718Skan "1b_0bbb., 1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1083132718Skan(exclusion_set "1b_0bbb." "1b_0mbb., 1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1084132718Skan(exclusion_set "1b_0mbb." "1b_0mib., 1b_0mmb., 1b_0mfb., 1b_0mlx.") 1085132718Skan(exclusion_set "1b_0mib." "1b_0mmb., 1b_0mfb., 1b_0mlx.") 1086132718Skan(exclusion_set "1b_0mmb." "1b_0mfb., 1b_0mlx.") 1087132718Skan(exclusion_set "1b_0mfb." "1b_0mlx.") 1088132718Skan 1089132718Skan;; Slot 4 1090132718Skan(exclusion_set "1b_1m.ii" 1091132718Skan "1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\ 1092132718Skan 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1093132718Skan(exclusion_set "1b_1m.mi" 1094132718Skan "1b_1m.fi, 1b_1b.bb, 1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1095132718Skan(exclusion_set "1b_1m.fi" 1096132718Skan "1b_1b.bb, 1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1097132718Skan(exclusion_set "1b_1b.bb" "1b_1m.bb, 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1098132718Skan(exclusion_set "1b_1m.bb" "1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1099132718Skan(exclusion_set "1b_1m.ib" "1b_1m.mb, 1b_1m.fb, 1b_1m.lx") 1100132718Skan(exclusion_set "1b_1m.mb" "1b_1m.fb, 1b_1m.lx") 1101132718Skan(exclusion_set "1b_1m.fb" "1b_1m.lx") 1102132718Skan 1103132718Skan;; Slot 5 1104132718Skan(exclusion_set "1b_1mi.i" 1105132718Skan "1b_1mm.i, 1b_1mf.i, 1b_1bb.b, 1b_1mb.b,\ 1106132718Skan 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1107132718Skan(exclusion_set "1b_1mm.i" 1108132718Skan "1b_1mf.i, 1b_1bb.b, 1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1109132718Skan(exclusion_set "1b_1mf.i" 1110132718Skan "1b_1bb.b, 1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1111132718Skan(exclusion_set "1b_1bb.b" "1b_1mb.b, 1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1112132718Skan(exclusion_set "1b_1mb.b" "1b_1mi.b, 1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1113132718Skan(exclusion_set "1b_1mi.b" "1b_1mm.b, 1b_1mf.b, 1b_1mlx.") 1114132718Skan(exclusion_set "1b_1mm.b" "1b_1mf.b, 1b_1mlx.") 1115132718Skan(exclusion_set "1b_1mf.b" "1b_1mlx.") 1116132718Skan 1117132718Skan;; Slot 6 1118132718Skan(exclusion_set "1b_1mii." 1119132718Skan "1b_1mmi., 1b_1mfi., 1b_1bbb., 1b_1mbb.,\ 1120132718Skan 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1121132718Skan(exclusion_set "1b_1mmi." 1122132718Skan "1b_1mfi., 1b_1bbb., 1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1123132718Skan(exclusion_set "1b_1mfi." 1124132718Skan "1b_1bbb., 1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1125132718Skan(exclusion_set "1b_1bbb." "1b_1mbb., 1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1126132718Skan(exclusion_set "1b_1mbb." "1b_1mib., 1b_1mmb., 1b_1mfb., 1b_1mlx.") 1127132718Skan(exclusion_set "1b_1mib." "1b_1mmb., 1b_1mfb., 1b_1mlx.") 1128132718Skan(exclusion_set "1b_1mmb." "1b_1mfb., 1b_1mlx.") 1129132718Skan(exclusion_set "1b_1mfb." "1b_1mlx.") 1130132718Skan 1131132718Skan(final_presence_set "1b_0mi.i" "1b_0m.ii") 1132132718Skan(final_presence_set "1b_0mii." "1b_0mi.i") 1133132718Skan(final_presence_set "1b_1mi.i" "1b_1m.ii") 1134132718Skan(final_presence_set "1b_1mii." "1b_1mi.i") 1135132718Skan 1136132718Skan(final_presence_set "1b_0mm.i" "1b_0m.mi") 1137132718Skan(final_presence_set "1b_0mmi." "1b_0mm.i") 1138132718Skan(final_presence_set "1b_1mm.i" "1b_1m.mi") 1139132718Skan(final_presence_set "1b_1mmi." "1b_1mm.i") 1140132718Skan 1141132718Skan(final_presence_set "1b_0mf.i" "1b_0m.fi") 1142132718Skan(final_presence_set "1b_0mfi." "1b_0mf.i") 1143132718Skan(final_presence_set "1b_1mf.i" "1b_1m.fi") 1144132718Skan(final_presence_set "1b_1mfi." "1b_1mf.i") 1145132718Skan 1146132718Skan(final_presence_set "1b_0mm.f" "1b_0m.mf") 1147132718Skan(final_presence_set "1b_0mmf." "1b_0mm.f") 1148132718Skan 1149132718Skan(final_presence_set "1b_0bb.b" "1b_0b.bb") 1150132718Skan(final_presence_set "1b_0bbb." "1b_0bb.b") 1151132718Skan(final_presence_set "1b_1bb.b" "1b_1b.bb") 1152132718Skan(final_presence_set "1b_1bbb." "1b_1bb.b") 1153132718Skan 1154132718Skan(final_presence_set "1b_0mb.b" "1b_0m.bb") 1155132718Skan(final_presence_set "1b_0mbb." "1b_0mb.b") 1156132718Skan(final_presence_set "1b_1mb.b" "1b_1m.bb") 1157132718Skan(final_presence_set "1b_1mbb." "1b_1mb.b") 1158132718Skan 1159132718Skan(final_presence_set "1b_0mi.b" "1b_0m.ib") 1160132718Skan(final_presence_set "1b_0mib." "1b_0mi.b") 1161132718Skan(final_presence_set "1b_1mi.b" "1b_1m.ib") 1162132718Skan(final_presence_set "1b_1mib." "1b_1mi.b") 1163132718Skan 1164132718Skan(final_presence_set "1b_0mm.b" "1b_0m.mb") 1165132718Skan(final_presence_set "1b_0mmb." "1b_0mm.b") 1166132718Skan(final_presence_set "1b_1mm.b" "1b_1m.mb") 1167132718Skan(final_presence_set "1b_1mmb." "1b_1mm.b") 1168132718Skan 1169132718Skan(final_presence_set "1b_0mf.b" "1b_0m.fb") 1170132718Skan(final_presence_set "1b_0mfb." "1b_0mf.b") 1171132718Skan(final_presence_set "1b_1mf.b" "1b_1m.fb") 1172132718Skan(final_presence_set "1b_1mfb." "1b_1mf.b") 1173132718Skan 1174132718Skan(final_presence_set "1b_0mlx." "1b_0m.lx") 1175132718Skan(final_presence_set "1b_1mlx." "1b_1m.lx") 1176132718Skan 1177132718Skan(final_presence_set 1178132718Skan "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\ 1179132718Skan 1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx" 1180132718Skan "1b_0mii.,1b_0mmi.,1b_0mfi.,1b_0mmf.,1b_0bbb.,1b_0mbb.,\ 1181132718Skan 1b_0mib.,1b_0mmb.,1b_0mfb.,1b_0mlx.") 1182132718Skan 1183132718Skan;; Microarchitecture units: 1184132718Skan(define_cpu_unit 1185132718Skan "1b_um0, 1b_um1, 1b_ui0, 1b_ui1, 1b_uf0, 1b_uf1, 1b_ub0, 1b_ub1, 1b_ub2,\ 1186132718Skan 1b_unb0, 1b_unb1, 1b_unb2" "oneb") 1187132718Skan 1188132718Skan(exclusion_set "1b_ub0" "1b_unb0") 1189132718Skan(exclusion_set "1b_ub1" "1b_unb1") 1190132718Skan(exclusion_set "1b_ub2" "1b_unb2") 1191132718Skan 1192132718Skan;; The following rules are used to decrease number of alternatives. 1193132718Skan;; They are consequences of Itanium microarchitecture. They also 1194132718Skan;; describe the following rules mentioned in Itanium 1195132718Skan;; microarchitecture: rules mentioned in Itanium microarchitecture: 1196132718Skan;; o "MMF: Always splits issue before the first M and after F regardless 1197132718Skan;; of surrounding bundles and stops". 1198132718Skan;; o "BBB/MBB: Always splits issue after either of these bundles". 1199132718Skan;; o "MIB BBB: Split issue after the first bundle in this pair". 1200132718Skan 1201132718Skan(exclusion_set "1b_0m.mf,1b_0mm.f,1b_0mmf." 1202132718Skan "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\ 1203132718Skan 1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx") 1204132718Skan(exclusion_set "1b_0b.bb,1b_0bb.b,1b_0bbb.,1b_0m.bb,1b_0mb.b,1b_0mbb." 1205132718Skan "1b_1m.ii,1b_1m.mi,1b_1m.fi,1b_1b.bb,1b_1m.bb,\ 1206132718Skan 1b_1m.ib,1b_1m.mb,1b_1m.fb,1b_1m.lx") 1207132718Skan(exclusion_set "1b_0m.ib,1b_0mi.b,1b_0mib." "1b_1b.bb") 1208132718Skan 1209132718Skan;; For exceptions of M, I, B, F insns: 1210132718Skan(define_cpu_unit "1b_not_um1, 1b_not_ui1, 1b_not_uf1" "oneb") 1211132718Skan 1212132718Skan(final_absence_set "1b_not_um1" "1b_um1") 1213132718Skan(final_absence_set "1b_not_ui1" "1b_ui1") 1214132718Skan(final_absence_set "1b_not_uf1" "1b_uf1") 1215132718Skan 1216132718Skan;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the 1217132718Skan;;; B-slot contains a nop.b or a brp instruction". 1218132718Skan;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or 1219132718Skan;;; nop.b, otherwise it disperses to B2". 1220132718Skan(final_absence_set 1221132718Skan "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1b.bb, 1b_1m.bb,\ 1222132718Skan 1b_1m.ib, 1b_1m.mb, 1b_1m.fb, 1b_1m.lx" 1223132718Skan "1b_0mib. 1b_ub2, 1b_0mfb. 1b_ub2, 1b_0mmb. 1b_ub2") 1224132718Skan 1225132718Skan;; This is necessary to start new processor cycle when we meet stop bit. 1226132718Skan(define_cpu_unit "1b_stop" "oneb") 1227132718Skan(final_absence_set 1228132718Skan "1b_0m.ii,1b_0mi.i,1b_0mii.,1b_0m.mi,1b_0mm.i,1b_0mmi.,\ 1229132718Skan 1b_0m.fi,1b_0mf.i,1b_0mfi.,\ 1230132718Skan 1b_0m.mf,1b_0mm.f,1b_0mmf.,1b_0b.bb,1b_0bb.b,1b_0bbb.,\ 1231132718Skan 1b_0m.bb,1b_0mb.b,1b_0mbb.,\ 1232132718Skan 1b_0m.ib,1b_0mi.b,1b_0mib.,1b_0m.mb,1b_0mm.b,1b_0mmb.,\ 1233132718Skan 1b_0m.fb,1b_0mf.b,1b_0mfb.,1b_0m.lx,1b_0mlx., \ 1234132718Skan 1b_1m.ii,1b_1mi.i,1b_1mii.,1b_1m.mi,1b_1mm.i,1b_1mmi.,\ 1235132718Skan 1b_1m.fi,1b_1mf.i,1b_1mfi.,\ 1236132718Skan 1b_1b.bb,1b_1bb.b,1b_1bbb.,1b_1m.bb,1b_1mb.b,1b_1mbb.,\ 1237132718Skan 1b_1m.ib,1b_1mi.b,1b_1mib.,\ 1238132718Skan 1b_1m.mb,1b_1mm.b,1b_1mmb.,1b_1m.fb,1b_1mf.b,1b_1mfb.,1b_1m.lx,1b_1mlx." 1239132718Skan "1b_stop") 1240132718Skan 1241132718Skan;; M and I instruction is dispersed to the lowest numbered M or I unit 1242132718Skan;; not already in use. An I slot in the 3rd position of 2nd bundle is 1243132718Skan;; always dispersed to I1 1244132718Skan(final_presence_set "1b_um1" "1b_um0") 1245132718Skan(final_presence_set "1b_ui1" "1b_ui0, 1b_1mii., 1b_1mmi., 1b_1mfi.") 1246132718Skan 1247132718Skan;; Insns 1248132718Skan 1249132718Skan;; M and I instruction is dispersed to the lowest numbered M or I unit 1250132718Skan;; not already in use. An I slot in the 3rd position of 2nd bundle is 1251132718Skan;; always dispersed to I1 1252132718Skan(define_reservation "1b_M" 1253132718Skan "1b_0m.ii+1_1+1b_um0|1b_0m.mi+1_1+1b_um0|1b_0mm.i+1_2+(1b_um0|1b_um1)\ 1254132718Skan |1b_0m.fi+1_1+1b_um0|1b_0m.mf+1_1+1b_um0|1b_0mm.f+1_2+1b_um1\ 1255132718Skan |1b_0m.bb+1_1+1b_um0|1b_0m.ib+1_1+1b_um0|1b_0m.mb+1_1+1b_um0\ 1256132718Skan |1b_0mm.b+1_2+1b_um1|1b_0m.fb+1_1+1b_um0|1b_0m.lx+1_1+1b_um0\ 1257132718Skan |1b_1mm.i+1_5+1b_um1|1b_1mm.b+1_5+1b_um1\ 1258132718Skan |(1b_1m.ii+1_4|1b_1m.mi+1_4|1b_1m.fi+1_4|1b_1m.bb+1_4|1b_1m.ib+1_4\ 1259132718Skan |1b_1m.mb+1_4|1b_1m.fb+1_4|1b_1m.lx+1_4)\ 1260132718Skan +(1b_um0|1b_um1)") 1261132718Skan 1262132718Skan;; Exceptions for dispersal rules. 1263132718Skan;; "An I slot in the 3rd position of 2nd bundle is always dispersed to I1". 1264132718Skan(define_reservation "1b_I" 1265132718Skan "1b_0mi.i+1_2+1b_ui0|1b_0mii.+1_3+(1b_ui0|1b_ui1)|1b_0mmi.+1_3+1b_ui0\ 1266132718Skan |1b_0mfi.+1_3+1b_ui0|1b_0mi.b+1_2+1b_ui0\ 1267132718Skan |(1b_1mi.i+1_5|1b_1mi.b+1_5)+(1b_ui0|1b_ui1)\ 1268132718Skan |1b_1mii.+1_6+1b_ui1|1b_1mmi.+1_6+1b_ui1|1b_1mfi.+1_6+1b_ui1") 1269132718Skan 1270132718Skan;; "An F slot in the 1st bundle disperses to F0". 1271132718Skan;; "An F slot in the 2st bundle disperses to F1". 1272132718Skan(define_reservation "1b_F" 1273132718Skan "1b_0mf.i+1_2+1b_uf0|1b_0mmf.+1_3+1b_uf0|1b_0mf.b+1_2+1b_uf0\ 1274132718Skan |1b_1mf.i+1_5+1b_uf1|1b_1mf.b+1_5+1b_uf1") 1275132718Skan 1276132718Skan;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B 1277132718Skan;;; unit. That is, a B slot in 1st position is dispersed to B0. In the 1278132718Skan;;; 2nd position it is dispersed to B2". 1279132718Skan(define_reservation "1b_NB" 1280132718Skan "1b_0b.bb+1_1+1b_unb0|1b_0bb.b+1_2+1b_unb1|1b_0bbb.+1_3+1b_unb2\ 1281132718Skan |1b_0mb.b+1_2+1b_unb1|1b_0mbb.+1_3+1b_unb2\ 1282132718Skan |1b_0mib.+1_3+1b_unb0|1b_0mmb.+1_3+1b_unb0|1b_0mfb.+1_3+1b_unb0\ 1283132718Skan |1b_1b.bb+1_4+1b_unb0|1b_1bb.b+1_5+1b_unb1\ 1284132718Skan |1b_1bbb.+1_6+1b_unb2|1b_1mb.b+1_5+1b_unb1|1b_1mbb.+1_6+1b_unb2\ 1285132718Skan |1b_1mib.+1_6+1b_unb0|1b_1mmb.+1_6+1b_unb0|1b_1mfb.+1_6+1b_unb0") 1286132718Skan 1287132718Skan(define_reservation "1b_B" 1288132718Skan "1b_0b.bb+1_1+1b_ub0|1b_0bb.b+1_2+1b_ub1|1b_0bbb.+1_3+1b_ub2\ 1289132718Skan |1b_0mb.b+1_2+1b_ub1|1b_0mbb.+1_3+1b_ub2|1b_0mib.+1_3+1b_ub2\ 1290132718Skan |1b_0mfb.+1_3+1b_ub2|1b_1b.bb+1_4+1b_ub0|1b_1bb.b+1_5+1b_ub1\ 1291132718Skan |1b_1bbb.+1_6+1b_ub2|1b_1mb.b+1_5+1b_ub1\ 1292132718Skan |1b_1mib.+1_6+1b_ub2|1b_1mmb.+1_6+1b_ub2|1b_1mfb.+1_6+1b_ub2") 1293132718Skan 1294132718Skan(define_reservation "1b_L" "1b_0mlx.+1_3+1b_ui0+1b_uf0\ 1295132718Skan |1b_1mlx.+1_6+(1b_ui0|1b_ui1)+1b_uf1") 1296132718Skan 1297132718Skan;; We assume that there is no insn issued on the same cycle as unknown insn. 1298132718Skan(define_cpu_unit "1b_empty" "oneb") 1299132718Skan(exclusion_set "1b_empty" 1300132718Skan "1b_0m.ii,1b_0m.mi,1b_0m.fi,1b_0m.mf,1b_0b.bb,1b_0m.bb,\ 1301132718Skan 1b_0m.ib,1b_0m.mb,1b_0m.fb,1b_0m.lx") 1302132718Skan 1303132718Skan(define_cpu_unit 1304132718Skan "1b_0m_bs, 1b_0mi_bs, 1b_0mm_bs, 1b_0mf_bs, 1b_0b_bs, 1b_0bb_bs, 1b_0mb_bs" 1305132718Skan "oneb") 1306132718Skan(define_cpu_unit 1307132718Skan "1b_1m_bs, 1b_1mi_bs, 1b_1mm_bs, 1b_1mf_bs, 1b_1b_bs, 1b_1bb_bs, 1b_1mb_bs" 1308132718Skan "oneb") 1309132718Skan 1310132718Skan(define_cpu_unit "1b_m_cont, 1b_mi_cont, 1b_mm_cont, 1b_mf_cont, 1b_mb_cont,\ 1311132718Skan 1b_b_cont, 1b_bb_cont" "oneb") 1312132718Skan 1313132718Skan;; For stop in the middle of the bundles. 1314132718Skan(define_cpu_unit "1b_m_stop, 1b_m0_stop, 1b_m1_stop, 1b_0mmi_cont" "oneb") 1315132718Skan(define_cpu_unit "1b_mi_stop, 1b_mi0_stop, 1b_mi1_stop, 1b_0mii_cont" "oneb") 1316132718Skan 1317132718Skan(final_presence_set "1b_0m_bs" 1318132718Skan "1b_0m.ii, 1b_0m.mi, 1b_0m.mf, 1b_0m.fi, 1b_0m.bb,\ 1319132718Skan 1b_0m.ib, 1b_0m.fb, 1b_0m.mb, 1b_0m.lx") 1320132718Skan(final_presence_set "1b_1m_bs" 1321132718Skan "1b_1m.ii, 1b_1m.mi, 1b_1m.fi, 1b_1m.bb, 1b_1m.ib, 1b_1m.fb, 1b_1m.mb,\ 1322132718Skan 1b_1m.lx") 1323132718Skan(final_presence_set "1b_0mi_bs" "1b_0mi.i, 1b_0mi.i") 1324132718Skan(final_presence_set "1b_1mi_bs" "1b_1mi.i, 1b_1mi.i") 1325132718Skan(final_presence_set "1b_0mm_bs" "1b_0mm.i, 1b_0mm.f, 1b_0mm.b") 1326132718Skan(final_presence_set "1b_1mm_bs" "1b_1mm.i, 1b_1mm.b") 1327132718Skan(final_presence_set "1b_0mf_bs" "1b_0mf.i, 1b_0mf.b") 1328132718Skan(final_presence_set "1b_1mf_bs" "1b_1mf.i, 1b_1mf.b") 1329132718Skan(final_presence_set "1b_0b_bs" "1b_0b.bb") 1330132718Skan(final_presence_set "1b_1b_bs" "1b_1b.bb") 1331132718Skan(final_presence_set "1b_0bb_bs" "1b_0bb.b") 1332132718Skan(final_presence_set "1b_1bb_bs" "1b_1bb.b") 1333132718Skan(final_presence_set "1b_0mb_bs" "1b_0mb.b") 1334132718Skan(final_presence_set "1b_1mb_bs" "1b_1mb.b") 1335132718Skan 1336132718Skan(exclusion_set "1b_0m_bs" 1337132718Skan "1b_0mi.i, 1b_0mm.i, 1b_0mm.f, 1b_0mf.i, 1b_0mb.b,\ 1338132718Skan 1b_0mi.b, 1b_0mf.b, 1b_0mm.b, 1b_0mlx., 1b_m0_stop") 1339132718Skan(exclusion_set "1b_1m_bs" 1340132718Skan "1b_1mi.i, 1b_1mm.i, 1b_1mf.i, 1b_1mb.b, 1b_1mi.b, 1b_1mf.b, 1b_1mm.b,\ 1341132718Skan 1b_1mlx., 1b_m1_stop") 1342132718Skan(exclusion_set "1b_0mi_bs" "1b_0mii., 1b_0mib., 1b_mi0_stop") 1343132718Skan(exclusion_set "1b_1mi_bs" "1b_1mii., 1b_1mib., 1b_mi1_stop") 1344132718Skan(exclusion_set "1b_0mm_bs" "1b_0mmi., 1b_0mmf., 1b_0mmb.") 1345132718Skan(exclusion_set "1b_1mm_bs" "1b_1mmi., 1b_1mmb.") 1346132718Skan(exclusion_set "1b_0mf_bs" "1b_0mfi., 1b_0mfb.") 1347132718Skan(exclusion_set "1b_1mf_bs" "1b_1mfi., 1b_1mfb.") 1348132718Skan(exclusion_set "1b_0b_bs" "1b_0bb.b") 1349132718Skan(exclusion_set "1b_1b_bs" "1b_1bb.b") 1350132718Skan(exclusion_set "1b_0bb_bs" "1b_0bbb.") 1351132718Skan(exclusion_set "1b_1bb_bs" "1b_1bbb.") 1352132718Skan(exclusion_set "1b_0mb_bs" "1b_0mbb.") 1353132718Skan(exclusion_set "1b_1mb_bs" "1b_1mbb.") 1354132718Skan 1355132718Skan(exclusion_set 1356132718Skan "1b_0m_bs, 1b_0mi_bs, 1b_0mm_bs, 1b_0mf_bs, 1b_0b_bs, 1b_0bb_bs, 1b_0mb_bs, 1357132718Skan 1b_1m_bs, 1b_1mi_bs, 1b_1mm_bs, 1b_1mf_bs, 1b_1b_bs, 1b_1bb_bs, 1b_1mb_bs" 1358132718Skan "1b_stop") 1359132718Skan 1360132718Skan(final_presence_set 1361132718Skan "1b_0mi.i, 1b_0mm.i, 1b_0mf.i, 1b_0mm.f, 1b_0mb.b,\ 1362132718Skan 1b_0mi.b, 1b_0mm.b, 1b_0mf.b, 1b_0mlx." 1363132718Skan "1b_m_cont") 1364132718Skan(final_presence_set "1b_0mii., 1b_0mib." "1b_mi_cont") 1365132718Skan(final_presence_set "1b_0mmi., 1b_0mmf., 1b_0mmb." "1b_mm_cont") 1366132718Skan(final_presence_set "1b_0mfi., 1b_0mfb." "1b_mf_cont") 1367132718Skan(final_presence_set "1b_0bb.b" "1b_b_cont") 1368132718Skan(final_presence_set "1b_0bbb." "1b_bb_cont") 1369132718Skan(final_presence_set "1b_0mbb." "1b_mb_cont") 1370132718Skan 1371132718Skan(exclusion_set 1372132718Skan "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1373132718Skan 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx" 1374132718Skan "1b_m_cont, 1b_mi_cont, 1b_mm_cont, 1b_mf_cont,\ 1375132718Skan 1b_mb_cont, 1b_b_cont, 1b_bb_cont") 1376132718Skan 1377132718Skan(exclusion_set "1b_empty" 1378132718Skan "1b_m_cont,1b_mi_cont,1b_mm_cont,1b_mf_cont,\ 1379132718Skan 1b_mb_cont,1b_b_cont,1b_bb_cont") 1380132718Skan 1381132718Skan;; For m;mi bundle 1382132718Skan(final_presence_set "1b_m0_stop" "1b_0m.mi") 1383132718Skan(final_presence_set "1b_0mm.i" "1b_0mmi_cont") 1384132718Skan(exclusion_set "1b_0mmi_cont" 1385132718Skan "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1386132718Skan 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1387132718Skan(exclusion_set "1b_m0_stop" "1b_0mm.i") 1388132718Skan(final_presence_set "1b_m1_stop" "1b_1m.mi") 1389132718Skan(exclusion_set "1b_m1_stop" "1b_1mm.i") 1390132718Skan(final_presence_set "1b_m_stop" "1b_m0_stop, 1b_m1_stop") 1391132718Skan 1392132718Skan;; For mi;i bundle 1393132718Skan(final_presence_set "1b_mi0_stop" "1b_0mi.i") 1394132718Skan(final_presence_set "1b_0mii." "1b_0mii_cont") 1395132718Skan(exclusion_set "1b_0mii_cont" 1396132718Skan "1b_0m.ii, 1b_0m.mi, 1b_0m.fi, 1b_0m.mf, 1b_0b.bb, 1b_0m.bb,\ 1397132718Skan 1b_0m.ib, 1b_0m.mb, 1b_0m.fb, 1b_0m.lx") 1398132718Skan(exclusion_set "1b_mi0_stop" "1b_0mii.") 1399132718Skan(final_presence_set "1b_mi1_stop" "1b_1mi.i") 1400132718Skan(exclusion_set "1b_mi1_stop" "1b_1mii.") 1401132718Skan(final_presence_set "1b_mi_stop" "1b_mi0_stop, 1b_mi1_stop") 1402132718Skan 1403132718Skan(final_absence_set 1404132718Skan "1b_0m.ii,1b_0mi.i,1b_0mii.,1b_0m.mi,1b_0mm.i,1b_0mmi.,\ 1405132718Skan 1b_0m.fi,1b_0mf.i,1b_0mfi.,1b_0m.mf,1b_0mm.f,1b_0mmf.,\ 1406132718Skan 1b_0b.bb,1b_0bb.b,1b_0bbb.,1b_0m.bb,1b_0mb.b,1b_0mbb.,\ 1407132718Skan 1b_0m.ib,1b_0mi.b,1b_0mib.,1b_0m.mb,1b_0mm.b,1b_0mmb.,\ 1408132718Skan 1b_0m.fb,1b_0mf.b,1b_0mfb.,1b_0m.lx,1b_0mlx., \ 1409132718Skan 1b_1m.ii,1b_1mi.i,1b_1mii.,1b_1m.mi,1b_1mm.i,1b_1mmi.,\ 1410132718Skan 1b_1m.fi,1b_1mf.i,1b_1mfi.,\ 1411132718Skan 1b_1b.bb,1b_1bb.b,1b_1bbb.,1b_1m.bb,1b_1mb.b,1b_1mbb.,\ 1412132718Skan 1b_1m.ib,1b_1mi.b,1b_1mib.,1b_1m.mb,1b_1mm.b,1b_1mmb.,\ 1413132718Skan 1b_1m.fb,1b_1mf.b,1b_1mfb.,1b_1m.lx,1b_1mlx." 1414132718Skan "1b_m0_stop,1b_m1_stop,1b_mi0_stop,1b_mi1_stop") 1415132718Skan 1416132718Skan(define_reservation "1b_A" "1b_M|1b_I") 1417132718Skan 1418132718Skan(define_insn_reservation "1b_stop_bit" 0 1419132718Skan (and (and (eq_attr "cpu" "itanium") 1420132718Skan (eq_attr "itanium_class" "stop_bit")) 1421132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1422132718Skan "1b_stop|1b_m0_stop|1b_m1_stop|1b_mi0_stop|1b_mi1_stop") 1423132718Skan(define_insn_reservation "1b_br" 0 1424132718Skan (and (and (eq_attr "cpu" "itanium") 1425132718Skan (eq_attr "itanium_class" "br")) 1426132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_B") 1427132718Skan(define_insn_reservation "1b_scall" 0 1428132718Skan (and (and (eq_attr "cpu" "itanium") 1429132718Skan (eq_attr "itanium_class" "scall")) 1430132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_B") 1431132718Skan(define_insn_reservation "1b_fcmp" 2 1432132718Skan (and (and (eq_attr "cpu" "itanium") 1433132718Skan (eq_attr "itanium_class" "fcmp")) 1434132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1435132718Skan "1b_F+1b_not_uf1") 1436132718Skan(define_insn_reservation "1b_fcvtfx" 7 1437132718Skan (and (and (eq_attr "cpu" "itanium") 1438132718Skan (eq_attr "itanium_class" "fcvtfx")) 1439132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F") 1440169689Skan 1441132718Skan(define_insn_reservation "1b_fld" 9 1442169689Skan (and (and (and (eq_attr "cpu" "itanium") 1443169689Skan (eq_attr "itanium_class" "fld")) 1444169689Skan (eq_attr "check_load" "no")) 1445132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1446169689Skan(define_insn_reservation "1b_fldc" 0 1447169689Skan (and (and (and (eq_attr "cpu" "itanium") 1448169689Skan (eq_attr "itanium_class" "fld")) 1449169689Skan (eq_attr "check_load" "yes")) 1450169689Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1451169689Skan 1452169689Skan(define_insn_reservation "1b_fldp" 9 1453169689Skan (and (and (and (eq_attr "cpu" "itanium") 1454169689Skan (eq_attr "itanium_class" "fldp")) 1455169689Skan (eq_attr "check_load" "no")) 1456169689Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1457169689Skan(define_insn_reservation "1b_fldpc" 0 1458169689Skan (and (and (and (eq_attr "cpu" "itanium") 1459169689Skan (eq_attr "itanium_class" "fldp")) 1460169689Skan (eq_attr "check_load" "yes")) 1461169689Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1462169689Skan 1463132718Skan(define_insn_reservation "1b_fmac" 5 1464132718Skan (and (and (eq_attr "cpu" "itanium") 1465132718Skan (eq_attr "itanium_class" "fmac")) 1466132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F") 1467132718Skan(define_insn_reservation "1b_fmisc" 5 1468132718Skan (and (and (eq_attr "cpu" "itanium") 1469132718Skan (eq_attr "itanium_class" "fmisc")) 1470132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1471132718Skan "1b_F+1b_not_uf1") 1472132718Skan(define_insn_reservation "1b_frar_i" 13 1473132718Skan (and (and (eq_attr "cpu" "itanium") 1474132718Skan (eq_attr "itanium_class" "frar_i")) 1475132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1476132718Skan "1b_I+1b_not_ui1") 1477132718Skan(define_insn_reservation "1b_frar_m" 6 1478132718Skan (and (and (eq_attr "cpu" "itanium") 1479132718Skan (eq_attr "itanium_class" "frar_m")) 1480132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1481132718Skan "1b_M+1b_not_um1") 1482132718Skan(define_insn_reservation "1b_frbr" 2 1483132718Skan (and (and (eq_attr "cpu" "itanium") 1484132718Skan (eq_attr "itanium_class" "frbr")) 1485132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1486132718Skan "1b_I+1b_not_ui1") 1487132718Skan(define_insn_reservation "1b_frfr" 2 1488132718Skan (and (and (eq_attr "cpu" "itanium") 1489132718Skan (eq_attr "itanium_class" "frfr")) 1490132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1491132718Skan "1b_M+1b_not_um1") 1492132718Skan(define_insn_reservation "1b_frpr" 2 1493132718Skan (and (and (eq_attr "cpu" "itanium") 1494132718Skan (eq_attr "itanium_class" "frpr")) 1495132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1496132718Skan "1b_I+1b_not_ui1") 1497132718Skan(define_insn_reservation "1b_ialu" 1 1498132718Skan (and (and (eq_attr "cpu" "itanium") 1499132718Skan (eq_attr "itanium_class" "ialu")) 1500132718Skan (ne (symbol_ref 1501132718Skan "bundling_p && !ia64_produce_address_p (insn)") 1502132718Skan (const_int 0))) 1503132718Skan "1b_A") 1504132718Skan(define_insn_reservation "1b_ialu_addr" 1 1505132718Skan (and (and (eq_attr "cpu" "itanium") 1506132718Skan (eq_attr "itanium_class" "ialu")) 1507132718Skan (eq (symbol_ref 1508132718Skan "bundling_p && ia64_produce_address_p (insn)") 1509132718Skan (const_int 1))) 1510132718Skan "1b_M") 1511132718Skan(define_insn_reservation "1b_icmp" 1 1512132718Skan (and (and (eq_attr "cpu" "itanium") 1513132718Skan (eq_attr "itanium_class" "icmp")) 1514132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A") 1515132718Skan(define_insn_reservation "1b_ilog" 1 1516132718Skan (and (and (eq_attr "cpu" "itanium") 1517132718Skan (eq_attr "itanium_class" "ilog")) 1518132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A") 1519169689Skan(define_insn_reservation "1b_mmalua" 2 1520169689Skan (and (and (eq_attr "cpu" "itanium") 1521169689Skan (eq_attr "itanium_class" "mmalua")) 1522169689Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A") 1523132718Skan(define_insn_reservation "1b_ishf" 1 1524132718Skan (and (and (eq_attr "cpu" "itanium") 1525132718Skan (eq_attr "itanium_class" "ishf")) 1526132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1527132718Skan "1b_I+1b_not_ui1") 1528169689Skan 1529132718Skan(define_insn_reservation "1b_ld" 2 1530169689Skan (and (and (and (eq_attr "cpu" "itanium") 1531169689Skan (eq_attr "itanium_class" "ld")) 1532169689Skan (eq_attr "check_load" "no")) 1533132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1534169689Skan(define_insn_reservation "1b_ldc" 0 1535169689Skan (and (and (and (eq_attr "cpu" "itanium") 1536169689Skan (eq_attr "itanium_class" "ld")) 1537169689Skan (eq_attr "check_load" "yes")) 1538169689Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1539169689Skan 1540132718Skan(define_insn_reservation "1b_long_i" 1 1541132718Skan (and (and (eq_attr "cpu" "itanium") 1542132718Skan (eq_attr "itanium_class" "long_i")) 1543132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_L") 1544132718Skan(define_insn_reservation "1b_mmmul" 2 1545132718Skan (and (and (eq_attr "cpu" "itanium") 1546132718Skan (eq_attr "itanium_class" "mmmul")) 1547132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1548132718Skan "1b_I+1b_not_ui1") 1549132718Skan(define_insn_reservation "1b_mmshf" 2 1550132718Skan (and (and (eq_attr "cpu" "itanium") 1551132718Skan (eq_attr "itanium_class" "mmshf")) 1552132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I") 1553132718Skan(define_insn_reservation "1b_mmshfi" 2 1554132718Skan (and (and (eq_attr "cpu" "itanium") 1555132718Skan (eq_attr "itanium_class" "mmshfi")) 1556132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I") 1557132718Skan(define_insn_reservation "1b_rse_m" 0 1558132718Skan (and (and (eq_attr "cpu" "itanium") 1559132718Skan (eq_attr "itanium_class" "rse_m")) 1560132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1561132718Skan "(1b_0m.ii|1b_0m.mi|1b_0m.fi|1b_0m.mf|1b_0b.bb|1b_0m.bb\ 1562132718Skan |1b_0m.ib|1b_0m.mb|1b_0m.fb|1b_0m.lx)+1_1+1b_um0") 1563132718Skan(define_insn_reservation "1b_sem" 0 1564132718Skan (and (and (eq_attr "cpu" "itanium") 1565132718Skan (eq_attr "itanium_class" "sem")) 1566132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1567132718Skan "1b_M+1b_not_um1") 1568132718Skan(define_insn_reservation "1b_stf" 1 1569132718Skan (and (and (eq_attr "cpu" "itanium") 1570132718Skan (eq_attr "itanium_class" "stf")) 1571132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1572132718Skan(define_insn_reservation "1b_st" 1 1573132718Skan (and (and (eq_attr "cpu" "itanium") 1574132718Skan (eq_attr "itanium_class" "st")) 1575132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1576132718Skan(define_insn_reservation "1b_syst_m0" 0 1577132718Skan (and (and (eq_attr "cpu" "itanium") 1578132718Skan (eq_attr "itanium_class" "syst_m0")) 1579132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1580132718Skan "1b_M+1b_not_um1") 1581132718Skan(define_insn_reservation "1b_syst_m" 0 1582132718Skan (and (and (eq_attr "cpu" "itanium") 1583132718Skan (eq_attr "itanium_class" "syst_m")) 1584132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1585132718Skan(define_insn_reservation "1b_tbit" 1 1586132718Skan (and (and (eq_attr "cpu" "itanium") 1587132718Skan (eq_attr "itanium_class" "tbit")) 1588132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1589132718Skan "1b_I+1b_not_ui1") 1590132718Skan(define_insn_reservation "1b_toar_i" 0 1591132718Skan (and (and (eq_attr "cpu" "itanium") 1592132718Skan (eq_attr "itanium_class" "toar_i")) 1593132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1594132718Skan "1b_I+1b_not_ui1") 1595132718Skan(define_insn_reservation "1b_toar_m" 5 1596132718Skan (and (and (eq_attr "cpu" "itanium") 1597132718Skan (eq_attr "itanium_class" "toar_m")) 1598132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1599132718Skan "1b_M+1b_not_um1") 1600132718Skan(define_insn_reservation "1b_tobr" 1 1601132718Skan (and (and (eq_attr "cpu" "itanium") 1602132718Skan (eq_attr "itanium_class" "tobr")) 1603132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1604132718Skan "1b_I+1b_not_ui1") 1605132718Skan(define_insn_reservation "1b_tofr" 9 1606132718Skan (and (and (eq_attr "cpu" "itanium") 1607132718Skan (eq_attr "itanium_class" "tofr")) 1608132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1609132718Skan(define_insn_reservation "1b_topr" 1 1610132718Skan (and (and (eq_attr "cpu" "itanium") 1611132718Skan (eq_attr "itanium_class" "topr")) 1612132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1613132718Skan "1b_I+1b_not_ui1") 1614132718Skan(define_insn_reservation "1b_xmpy" 7 1615132718Skan (and (and (eq_attr "cpu" "itanium") 1616132718Skan (eq_attr "itanium_class" "xmpy")) 1617132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F") 1618132718Skan(define_insn_reservation "1b_xtd" 1 1619132718Skan (and (and (eq_attr "cpu" "itanium") 1620132718Skan (eq_attr "itanium_class" "xtd")) 1621132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I") 1622169689Skan 1623169689Skan(define_insn_reservation "1b_chk_s_i" 0 1624132718Skan (and (and (eq_attr "cpu" "itanium") 1625169689Skan (eq_attr "itanium_class" "chk_s_i")) 1626132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A") 1627169689Skan(define_insn_reservation "1b_chk_s_f" 0 1628169689Skan (and (and (eq_attr "cpu" "itanium") 1629169689Skan (eq_attr "itanium_class" "chk_s_f")) 1630169689Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1631169689Skan(define_insn_reservation "1b_chk_a" 0 1632169689Skan (and (and (eq_attr "cpu" "itanium") 1633169689Skan (eq_attr "itanium_class" "chk_a")) 1634169689Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1635169689Skan 1636132718Skan(define_insn_reservation "1b_lfetch" 0 1637132718Skan (and (and (eq_attr "cpu" "itanium") 1638132718Skan (eq_attr "itanium_class" "lfetch")) 1639132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1640132718Skan(define_insn_reservation "1b_nop_m" 0 1641132718Skan (and (and (eq_attr "cpu" "itanium") 1642132718Skan (eq_attr "itanium_class" "nop_m")) 1643132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M") 1644132718Skan(define_insn_reservation "1b_nop_b" 0 1645132718Skan (and (and (eq_attr "cpu" "itanium") 1646132718Skan (eq_attr "itanium_class" "nop_b")) 1647132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_NB") 1648132718Skan(define_insn_reservation "1b_nop_i" 0 1649132718Skan (and (and (eq_attr "cpu" "itanium") 1650132718Skan (eq_attr "itanium_class" "nop_i")) 1651132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I") 1652132718Skan(define_insn_reservation "1b_nop_f" 0 1653132718Skan (and (and (eq_attr "cpu" "itanium") 1654132718Skan (eq_attr "itanium_class" "nop_f")) 1655132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F") 1656132718Skan(define_insn_reservation "1b_nop_x" 0 1657132718Skan (and (and (eq_attr "cpu" "itanium") 1658132718Skan (eq_attr "itanium_class" "nop_x")) 1659132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) "1b_L") 1660132718Skan(define_insn_reservation "1b_unknown" 1 1661132718Skan (and (and (eq_attr "cpu" "itanium") 1662132718Skan (eq_attr "itanium_class" "unknown")) 1663132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1664132718Skan "1b_empty") 1665132718Skan(define_insn_reservation "1b_nop" 1 1666132718Skan (and (and (eq_attr "cpu" "itanium") 1667132718Skan (eq_attr "itanium_class" "nop")) 1668132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1669132718Skan "1b_M|1b_NB|1b_I|1b_F") 1670132718Skan(define_insn_reservation "1b_ignore" 0 1671132718Skan (and (and (eq_attr "cpu" "itanium") 1672132718Skan (eq_attr "itanium_class" "ignore")) 1673132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1674132718Skan "nothing") 1675132718Skan 1676132718Skan(define_insn_reservation "1b_pre_cycle" 0 1677132718Skan (and (and (eq_attr "cpu" "itanium") 1678132718Skan (eq_attr "itanium_class" "pre_cycle")) 1679132718Skan (ne (symbol_ref "bundling_p") (const_int 0))) 1680132718Skan "(1b_0m_bs, 1b_m_cont) \ 1681132718Skan | (1b_0mi_bs, 1b_mi_cont) \ 1682132718Skan | (1b_0mm_bs, 1b_mm_cont) \ 1683132718Skan | (1b_0mf_bs, 1b_mf_cont) \ 1684132718Skan | (1b_0b_bs, 1b_b_cont) \ 1685132718Skan | (1b_0bb_bs, 1b_bb_cont) \ 1686132718Skan | (1b_0mb_bs, 1b_mb_cont) \ 1687132718Skan | (1b_1m_bs, 1b_m_cont) \ 1688132718Skan | (1b_1mi_bs, 1b_mi_cont) \ 1689132718Skan | (1b_1mm_bs, 1b_mm_cont) \ 1690132718Skan | (1b_1mf_bs, 1b_mf_cont) \ 1691132718Skan | (1b_1b_bs, 1b_b_cont) \ 1692132718Skan | (1b_1bb_bs, 1b_bb_cont) \ 1693132718Skan | (1b_1mb_bs, 1b_mb_cont) \ 1694132718Skan | (1b_m_stop, 1b_0mmi_cont) \ 1695132718Skan | (1b_mi_stop, 1b_0mii_cont)") 1696132718Skan 1697